drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_vfio.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_common.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19 #include "hns3_flow.h"
  20
  21 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  22 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  23
  24 #define HNS3VF_RESET_WAIT_MS    20
  25 #define HNS3VF_RESET_WAIT_CNT   2000
  26
  27 /* Reset related Registers */
  28 #define HNS3_GLOBAL_RESET_BIT           0
  29 #define HNS3_CORE_RESET_BIT             1
  30 #define HNS3_IMP_RESET_BIT              2
  31 #define HNS3_FUN_RST_ING_B              0
  32
  33 enum hns3vf_evt_cause {
  34         HNS3VF_VECTOR0_EVENT_RST,
  35         HNS3VF_VECTOR0_EVENT_MBX,
  36         HNS3VF_VECTOR0_EVENT_OTHER,
  37 };
  38
  39 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  40                                                     uint64_t *levels);
  41 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  42 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  43
  44 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  45                                   struct rte_ether_addr *mac_addr);
  46 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  47                                      struct rte_ether_addr *mac_addr);
  48 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
  49                                    __rte_unused int wait_to_complete);
  50
  51 /* set PCI bus mastering */
  52 static int
  53 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  54 {
  55         uint16_t reg;
  56         int ret;
  57
  58         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  59         if (ret < 0) {
  60                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  61                              PCI_COMMAND);
  62                 return ret;
  63         }
  64
  65         if (op)
  66                 /* set the master bit */
  67                 reg |= PCI_COMMAND_MASTER;
  68         else
  69                 reg &= ~(PCI_COMMAND_MASTER);
  70
  71         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  72 }
  73
  74 /**
  75  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  76  * @cap: the capability
  77  *
  78  * Return the address of the given capability within the PCI capability list.
  79  */
  80 static int
  81 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  82 {
  83 #define MAX_PCIE_CAPABILITY 48
  84         uint16_t status;
  85         uint8_t pos;
  86         uint8_t id;
  87         int ttl;
  88         int ret;
  89
  90         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  91         if (ret < 0) {
  92                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  93                 return 0;
  94         }
  95
  96         if (!(status & PCI_STATUS_CAP_LIST))
  97                 return 0;
  98
  99         ttl = MAX_PCIE_CAPABILITY;
 100         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 101                                   PCI_CAPABILITY_LIST);
 102         if (ret < 0) {
 103                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 104                              PCI_CAPABILITY_LIST);
 105                 return 0;
 106         }
 107
 108         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 109                 ret = rte_pci_read_config(device, &id, sizeof(id),
 110                                           (pos + PCI_CAP_LIST_ID));
 111                 if (ret < 0) {
 112                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 113                                      (pos + PCI_CAP_LIST_ID));
 114                         break;
 115                 }
 116
 117                 if (id == 0xFF)
 118                         break;
 119
 120                 if (id == cap)
 121                         return (int)pos;
 122
 123                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 124                                           (pos + PCI_CAP_LIST_NEXT));
 125                 if (ret < 0) {
 126                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 127                                      (pos + PCI_CAP_LIST_NEXT));
 128                         break;
 129                 }
 130         }
 131         return 0;
 132 }
 133
 134 static int
 135 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 136 {
 137         uint16_t control;
 138         int pos;
 139         int ret;
 140
 141         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 142         if (pos) {
 143                 ret = rte_pci_read_config(device, &control, sizeof(control),
 144                                           (pos + PCI_MSIX_FLAGS));
 145                 if (ret < 0) {
 146                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 147                                      (pos + PCI_MSIX_FLAGS));
 148                         return -ENXIO;
 149                 }
 150
 151                 if (op)
 152                         control |= PCI_MSIX_FLAGS_ENABLE;
 153                 else
 154                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 155                 ret = rte_pci_write_config(device, &control, sizeof(control),
 156                                            (pos + PCI_MSIX_FLAGS));
 157                 if (ret < 0) {
 158                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 159                                      (pos + PCI_MSIX_FLAGS));
 160                         return -ENXIO;
 161                 }
 162
 163                 return 0;
 164         }
 165
 166         return -ENXIO;
 167 }
 168
 169 static int
 170 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 171 {
 172         /* mac address was checked by upper level interface */
 173         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 174         int ret;
 175
 176         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 177                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 178                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 179         if (ret) {
 180                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 181                                       mac_addr);
 182                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 183                          mac_str, ret);
 184         }
 185         return ret;
 186 }
 187
 188 static int
 189 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 190 {
 191         /* mac address was checked by upper level interface */
 192         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 193         int ret;
 194
 195         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 196                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 197                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 198                                 false, NULL, 0);
 199         if (ret) {
 200                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 201                                        mac_addr);
 202                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 203                          mac_str, ret);
 204         }
 205         return ret;
 206 }
 207
 208 static int
 209 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 210                             struct rte_ether_addr *mac_addr)
 211 {
 212 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 213         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 214         struct rte_ether_addr *old_addr;
 215         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 216         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 217         int ret;
 218
 219         /*
 220          * It has been guaranteed that input parameter named mac_addr is valid
 221          * address in the rte layer of DPDK framework.
 222          */
 223         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 224         rte_spinlock_lock(&hw->lock);
 225         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 226         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 227                RTE_ETHER_ADDR_LEN);
 228
 229         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 230                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 231                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 232         if (ret) {
 233                 /*
 234                  * The hns3 VF PMD depends on the hns3 PF kernel ethdev
 235                  * driver. When user has configured a MAC address for VF device
 236                  * by "ip link set ..." command based on the PF device, the hns3
 237                  * PF kernel ethdev driver does not allow VF driver to request
 238                  * reconfiguring a different default MAC address, and return
 239                  * -EPREM to VF driver through mailbox.
 240                  */
 241                 if (ret == -EPERM) {
 242                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 243                                                old_addr);
 244                         hns3_warn(hw, "Has permanent mac addr(%s) for vf",
 245                                   mac_str);
 246                 } else {
 247                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 248                                                mac_addr);
 249                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 250                                  mac_str, ret);
 251                 }
 252         }
 253
 254         rte_ether_addr_copy(mac_addr,
 255                             (struct rte_ether_addr *)hw->mac.mac_addr);
 256         rte_spinlock_unlock(&hw->lock);
 257
 258         return ret;
 259 }
 260
 261 static int
 262 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 263                        struct rte_ether_addr *mac_addr)
 264 {
 265         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 266         int ret;
 267
 268         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 269                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 270                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 271                                 NULL, 0);
 272         if (ret) {
 273                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 274                                       mac_addr);
 275                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 276                          mac_str, ret);
 277         }
 278
 279         return ret;
 280 }
 281
 282 static int
 283 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 284                           struct rte_ether_addr *mac_addr)
 285 {
 286         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 287         int ret;
 288
 289         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 290                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 291                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 292                                 NULL, 0);
 293         if (ret) {
 294                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 295                                        mac_addr);
 296                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 297                          mac_str, ret);
 298         }
 299
 300         return ret;
 301 }
 302
 303 static int
 304 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 305                         bool en_uc_pmc, bool en_mc_pmc)
 306 {
 307         struct hns3_mbx_vf_to_pf_cmd *req;
 308         struct hns3_cmd_desc desc;
 309         int ret;
 310
 311         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 312
 313         /*
 314          * The hns3 VF PMD depends on the hns3 PF kernel ethdev driver,
 315          * so there are some features for promiscuous/allmulticast mode in hns3
 316          * VF PMD as below:
 317          * 1. The promiscuous/allmulticast mode can be configured successfully
 318          *    only based on the trusted VF device. If based on the non trusted
 319          *    VF device, configuring promiscuous/allmulticast mode will fail.
 320          *    The hns3 VF device can be configured as trusted device by hns3 PF
 321          *    kernel ethdev driver on the host by the following command:
 322          *      "ip link set <eth num> vf <vf id> turst on"
 323          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 324          *    can receive the ingress and outgoing traffic. This includes
 325          *    all the ingress packets, all the packets sent from the PF and
 326          *    other VFs on the same physical port.
 327          * 3. Note: Because of the hardware constraints, By default vlan filter
 328          *    is enabled and couldn't be turned off based on VF device, so vlan
 329          *    filter is still effective even in promiscuous mode. If upper
 330          *    applications don't call rte_eth_dev_vlan_filter API function to
 331          *    set vlan based on VF device, hns3 VF PMD will can't receive
 332          *    the packets with vlan tag in promiscuous mode.
 333          */
 334         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 335         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 336         req->msg[1] = en_bc_pmc ? 1 : 0;
 337         req->msg[2] = en_uc_pmc ? 1 : 0;
 338         req->msg[3] = en_mc_pmc ? 1 : 0;
 339         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 340
 341         ret = hns3_cmd_send(hw, &desc, 1);
 342         if (ret)
 343                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 344
 345         return ret;
 346 }
 347
 348 static int
 349 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 350 {
 351         struct hns3_adapter *hns = dev->data->dev_private;
 352         struct hns3_hw *hw = &hns->hw;
 353         int ret;
 354
 355         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 356         if (ret)
 357                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 358                         ret);
 359         return ret;
 360 }
 361
 362 static int
 363 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 364 {
 365         bool allmulti = dev->data->all_multicast ? true : false;
 366         struct hns3_adapter *hns = dev->data->dev_private;
 367         struct hns3_hw *hw = &hns->hw;
 368         int ret;
 369
 370         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 371         if (ret)
 372                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 373                         ret);
 374         return ret;
 375 }
 376
 377 static int
 378 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 379 {
 380         struct hns3_adapter *hns = dev->data->dev_private;
 381         struct hns3_hw *hw = &hns->hw;
 382         int ret;
 383
 384         if (dev->data->promiscuous)
 385                 return 0;
 386
 387         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 388         if (ret)
 389                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 390                         ret);
 391         return ret;
 392 }
 393
 394 static int
 395 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 396 {
 397         struct hns3_adapter *hns = dev->data->dev_private;
 398         struct hns3_hw *hw = &hns->hw;
 399         int ret;
 400
 401         if (dev->data->promiscuous)
 402                 return 0;
 403
 404         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 405         if (ret)
 406                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 407                         ret);
 408         return ret;
 409 }
 410
 411 static int
 412 hns3vf_restore_promisc(struct hns3_adapter *hns)
 413 {
 414         struct hns3_hw *hw = &hns->hw;
 415         bool allmulti = hw->data->all_multicast ? true : false;
 416
 417         if (hw->data->promiscuous)
 418                 return hns3vf_set_promisc_mode(hw, true, true, true);
 419
 420         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 421 }
 422
 423 static int
 424 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id,
 425                              bool mmap, enum hns3_ring_type queue_type,
 426                              uint16_t queue_id)
 427 {
 428         struct hns3_vf_bind_vector_msg bind_msg;
 429         const char *op_str;
 430         uint16_t code;
 431         int ret;
 432
 433         memset(&bind_msg, 0, sizeof(bind_msg));
 434         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 435                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 436         bind_msg.vector_id = (uint8_t)vector_id;
 437
 438         if (queue_type == HNS3_RING_TYPE_RX)
 439                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 440         else
 441                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 442
 443         bind_msg.param[0].ring_type = queue_type;
 444         bind_msg.ring_num = 1;
 445         bind_msg.param[0].tqp_index = queue_id;
 446         op_str = mmap ? "Map" : "Unmap";
 447         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 448                                 sizeof(bind_msg), false, NULL, 0);
 449         if (ret)
 450                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 451                          op_str, queue_id, bind_msg.vector_id, ret);
 452
 453         return ret;
 454 }
 455
 456 static int
 457 hns3vf_dev_configure(struct rte_eth_dev *dev)
 458 {
 459         struct hns3_adapter *hns = dev->data->dev_private;
 460         struct hns3_hw *hw = &hns->hw;
 461         struct rte_eth_conf *conf = &dev->data->dev_conf;
 462         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 463         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 464         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 465         struct rte_eth_rss_conf rss_conf;
 466         bool gro_en;
 467         int ret;
 468
 469         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 470
 471         /*
 472          * Some versions of hardware network engine does not support
 473          * individually enable/disable/reset the Tx or Rx queue. These devices
 474          * must enable/disable/reset Tx and Rx queues at the same time. When the
 475          * numbers of Tx queues allocated by upper applications are not equal to
 476          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 477          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 478          * work as usual. But these fake queues are imperceptible, and can not
 479          * be used by upper applications.
 480          */
 481         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 482         if (ret) {
 483                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
 484                 hw->cfg_max_queues = 0;
 485                 return ret;
 486         }
 487
 488         hw->adapter_state = HNS3_NIC_CONFIGURING;
 489         if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
 490                 hns3_err(hw, "setting link speed/duplex not supported");
 491                 ret = -EINVAL;
 492                 goto cfg_err;
 493         }
 494
 495         /* When RSS is not configured, redirect the packet queue 0 */
 496         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
 497                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
 498                 rss_conf = conf->rx_adv_conf.rss_conf;
 499                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 500                 if (ret)
 501                         goto cfg_err;
 502         }
 503
 504         ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
 505         if (ret != 0)
 506                 goto cfg_err;
 507
 508         ret = hns3vf_dev_configure_vlan(dev);
 509         if (ret)
 510                 goto cfg_err;
 511
 512         /* config hardware GRO */
 513         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
 514         ret = hns3_config_gro(hw, gro_en);
 515         if (ret)
 516                 goto cfg_err;
 517
 518         hns3_init_rx_ptype_tble(dev);
 519
 520         hw->adapter_state = HNS3_NIC_CONFIGURED;
 521         return 0;
 522
 523 cfg_err:
 524         hw->cfg_max_queues = 0;
 525         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 526         hw->adapter_state = HNS3_NIC_INITIALIZED;
 527
 528         return ret;
 529 }
 530
 531 static int
 532 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 533 {
 534         int ret;
 535
 536         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 537                                 sizeof(mtu), true, NULL, 0);
 538         if (ret)
 539                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 540
 541         return ret;
 542 }
 543
 544 static int
 545 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 546 {
 547         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 548         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 549         int ret;
 550
 551         /*
 552          * The hns3 PF/VF devices on the same port share the hardware MTU
 553          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 554          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD,
 555          * there is no need to stop the port for hns3 VF device, and the
 556          * MTU value issued by hns3 VF PMD must be less than or equal to
 557          * PF's MTU.
 558          */
 559         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 560                 hns3_err(hw, "Failed to set mtu during resetting");
 561                 return -EIO;
 562         }
 563
 564         /*
 565          * when Rx of scattered packets is off, we have some possibility of
 566          * using vector Rx process function or simple Rx functions in hns3 PMD.
 567          * If the input MTU is increased and the maximum length of
 568          * received packets is greater than the length of a buffer for Rx
 569          * packet, the hardware network engine needs to use multiple BDs and
 570          * buffers to store these packets. This will cause problems when still
 571          * using vector Rx process function or simple Rx function to receiving
 572          * packets. So, when Rx of scattered packets is off and device is
 573          * started, it is not permitted to increase MTU so that the maximum
 574          * length of Rx packets is greater than Rx buffer length.
 575          */
 576         if (dev->data->dev_started && !dev->data->scattered_rx &&
 577             frame_size > hw->rx_buf_len) {
 578                 hns3_err(hw, "failed to set mtu because current is "
 579                         "not scattered rx mode");
 580                 return -EOPNOTSUPP;
 581         }
 582
 583         rte_spinlock_lock(&hw->lock);
 584         ret = hns3vf_config_mtu(hw, mtu);
 585         if (ret) {
 586                 rte_spinlock_unlock(&hw->lock);
 587                 return ret;
 588         }
 589         rte_spinlock_unlock(&hw->lock);
 590
 591         return 0;
 592 }
 593
 594 static void
 595 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 596 {
 597         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 598 }
 599
 600 static void
 601 hns3vf_disable_irq0(struct hns3_hw *hw)
 602 {
 603         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 604 }
 605
 606 static void
 607 hns3vf_enable_irq0(struct hns3_hw *hw)
 608 {
 609         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 610 }
 611
 612 static enum hns3vf_evt_cause
 613 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 614 {
 615         struct hns3_hw *hw = &hns->hw;
 616         enum hns3vf_evt_cause ret;
 617         uint32_t cmdq_stat_reg;
 618         uint32_t rst_ing_reg;
 619         uint32_t val;
 620
 621         /* Fetch the events from their corresponding regs */
 622         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 623         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 624                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 625                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 626                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 627                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 628                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 629                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 630                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 631                 if (clearval) {
 632                         hw->reset.stats.global_cnt++;
 633                         hns3_warn(hw, "Global reset detected, clear reset status");
 634                 } else {
 635                         hns3_schedule_delayed_reset(hns);
 636                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 637                 }
 638
 639                 ret = HNS3VF_VECTOR0_EVENT_RST;
 640                 goto out;
 641         }
 642
 643         /* Check for vector0 mailbox(=CMDQ RX) event source */
 644         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
 645                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 646                 ret = HNS3VF_VECTOR0_EVENT_MBX;
 647                 goto out;
 648         }
 649
 650         val = 0;
 651         ret = HNS3VF_VECTOR0_EVENT_OTHER;
 652 out:
 653         if (clearval)
 654                 *clearval = val;
 655         return ret;
 656 }
 657
 658 static void
 659 hns3vf_interrupt_handler(void *param)
 660 {
 661         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 662         struct hns3_adapter *hns = dev->data->dev_private;
 663         struct hns3_hw *hw = &hns->hw;
 664         enum hns3vf_evt_cause event_cause;
 665         uint32_t clearval;
 666
 667         /* Disable interrupt */
 668         hns3vf_disable_irq0(hw);
 669
 670         /* Read out interrupt causes */
 671         event_cause = hns3vf_check_event_cause(hns, &clearval);
 672         /* Clear interrupt causes */
 673         hns3vf_clear_event_cause(hw, clearval);
 674
 675         switch (event_cause) {
 676         case HNS3VF_VECTOR0_EVENT_RST:
 677                 hns3_schedule_reset(hns);
 678                 break;
 679         case HNS3VF_VECTOR0_EVENT_MBX:
 680                 hns3_dev_handle_mbx_msg(hw);
 681                 break;
 682         default:
 683                 break;
 684         }
 685
 686         /* Enable interrupt */
 687         hns3vf_enable_irq0(hw);
 688 }
 689
 690 static void
 691 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
 692 {
 693         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
 694         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
 695         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
 696         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
 697 }
 698
 699 static void
 700 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
 701 {
 702         struct hns3_dev_specs_0_cmd *req0;
 703
 704         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
 705
 706         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
 707         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
 708         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
 709         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
 710 }
 711
 712 static int
 713 hns3vf_check_dev_specifications(struct hns3_hw *hw)
 714 {
 715         if (hw->rss_ind_tbl_size == 0 ||
 716             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
 717                 hns3_warn(hw, "the size of hash lookup table configured (%u) exceeds the maximum(%u)",
 718                           hw->rss_ind_tbl_size, HNS3_RSS_IND_TBL_SIZE_MAX);
 719                 return -EINVAL;
 720         }
 721
 722         return 0;
 723 }
 724
 725 static int
 726 hns3vf_query_dev_specifications(struct hns3_hw *hw)
 727 {
 728         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
 729         int ret;
 730         int i;
 731
 732         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
 733                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
 734                                           true);
 735                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 736         }
 737         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
 738
 739         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
 740         if (ret)
 741                 return ret;
 742
 743         hns3vf_parse_dev_specifications(hw, desc);
 744
 745         return hns3vf_check_dev_specifications(hw);
 746 }
 747
 748 void
 749 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
 750 {
 751         uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
 752                                    HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
 753         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
 754         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
 755
 756         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
 757                 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
 758                                           __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
 759 }
 760
 761 static void
 762 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
 763 {
 764 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS      500
 765
 766         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
 767         int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
 768         uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
 769         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
 770         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
 771
 772         __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
 773                          __ATOMIC_RELEASE);
 774
 775         (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
 776                                 NULL, 0);
 777
 778         while (remain_ms > 0) {
 779                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
 780                 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
 781                         HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
 782                         break;
 783                 remain_ms--;
 784         }
 785
 786         /*
 787          * When exit above loop, the pf_push_lsc_cap could be one of the three
 788          * state: unknown (means pf not ack), not_supported, supported.
 789          * Here config it as 'not_supported' when it's 'unknown' state.
 790          */
 791         __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
 792                                   __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
 793
 794         if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
 795                 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
 796                 hns3_info(hw, "detect PF support push link status change!");
 797         } else {
 798                 /*
 799                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
 800                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
 801                  * the RTE_ETH_DEV_INTR_LSC capability.
 802                  */
 803                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
 804         }
 805 }
 806
 807 static int
 808 hns3vf_get_capability(struct hns3_hw *hw)
 809 {
 810         int ret;
 811
 812         ret = hns3_get_pci_revision_id(hw, &hw->revision);
 813         if (ret)
 814                 return ret;
 815
 816         if (hw->revision < PCI_REVISION_ID_HIP09_A) {
 817                 hns3vf_set_default_dev_specifications(hw);
 818                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
 819                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
 820                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
 821                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
 822                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
 823                 hw->rss_info.ipv6_sctp_offload_supported = false;
 824                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
 825                 return 0;
 826         }
 827
 828         ret = hns3vf_query_dev_specifications(hw);
 829         if (ret) {
 830                 PMD_INIT_LOG(ERR,
 831                              "failed to query dev specifications, ret = %d",
 832                              ret);
 833                 return ret;
 834         }
 835
 836         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
 837         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
 838         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
 839         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
 840         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
 841         hw->rss_info.ipv6_sctp_offload_supported = true;
 842         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
 843
 844         return 0;
 845 }
 846
 847 static int
 848 hns3vf_check_tqp_info(struct hns3_hw *hw)
 849 {
 850         if (hw->tqps_num == 0) {
 851                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
 852                 return -EINVAL;
 853         }
 854
 855         if (hw->rss_size_max == 0) {
 856                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
 857                 return -EINVAL;
 858         }
 859
 860         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
 861
 862         return 0;
 863 }
 864
 865 static int
 866 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
 867 {
 868         uint8_t resp_msg;
 869         int ret;
 870
 871         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
 872                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
 873                                 true, &resp_msg, sizeof(resp_msg));
 874         if (ret) {
 875                 if (ret == -ETIME) {
 876                         /*
 877                          * Getting current port based VLAN state from PF driver
 878                          * will not affect VF driver's basic function. Because
 879                          * the VF driver relies on hns3 PF kernel ether driver,
 880                          * to avoid introducing compatibility issues with older
 881                          * version of PF driver, no failure will be returned
 882                          * when the return value is ETIME. This return value has
 883                          * the following scenarios:
 884                          * 1) Firmware didn't return the results in time
 885                          * 2) the result return by firmware is timeout
 886                          * 3) the older version of kernel side PF driver does
 887                          *    not support this mailbox message.
 888                          * For scenarios 1 and 2, it is most likely that a
 889                          * hardware error has occurred, or a hardware reset has
 890                          * occurred. In this case, these errors will be caught
 891                          * by other functions.
 892                          */
 893                         PMD_INIT_LOG(WARNING,
 894                                 "failed to get PVID state for timeout, maybe "
 895                                 "kernel side PF driver doesn't support this "
 896                                 "mailbox message, or firmware didn't respond.");
 897                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
 898                 } else {
 899                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
 900                                 " ret = %d", ret);
 901                         return ret;
 902                 }
 903         }
 904         hw->port_base_vlan_cfg.state = resp_msg ?
 905                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 906         return 0;
 907 }
 908
 909 static int
 910 hns3vf_get_queue_info(struct hns3_hw *hw)
 911 {
 912 #define HNS3VF_TQPS_RSS_INFO_LEN        6
 913         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
 914         int ret;
 915
 916         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
 917                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
 918         if (ret) {
 919                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
 920                 return ret;
 921         }
 922
 923         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
 924         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
 925
 926         return hns3vf_check_tqp_info(hw);
 927 }
 928
 929 static void
 930 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
 931 {
 932         if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
 933                 hns3_set_bit(hw->capability,
 934                                 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
 935 }
 936
 937 static int
 938 hns3vf_get_num_tc(struct hns3_hw *hw)
 939 {
 940         uint8_t num_tc = 0;
 941         uint32_t i;
 942
 943         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
 944                 if (hw->hw_tc_map & BIT(i))
 945                         num_tc++;
 946         }
 947         return num_tc;
 948 }
 949
 950 static int
 951 hns3vf_get_basic_info(struct hns3_hw *hw)
 952 {
 953         uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
 954         struct hns3_basic_info *basic_info;
 955         int ret;
 956
 957         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
 958                                 true, resp_msg, sizeof(resp_msg));
 959         if (ret) {
 960                 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
 961                                 ret);
 962                 return ret;
 963         }
 964
 965         basic_info = (struct hns3_basic_info *)resp_msg;
 966         hw->hw_tc_map = basic_info->hw_tc_map;
 967         hw->num_tc = hns3vf_get_num_tc(hw);
 968         hw->pf_vf_if_version = basic_info->pf_vf_if_version;
 969         hns3vf_update_caps(hw, basic_info->caps);
 970
 971         return 0;
 972 }
 973
 974 static int
 975 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
 976 {
 977         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
 978         int ret;
 979
 980         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
 981                                 true, host_mac, RTE_ETHER_ADDR_LEN);
 982         if (ret) {
 983                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
 984                 return ret;
 985         }
 986
 987         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
 988
 989         return 0;
 990 }
 991
 992 static int
 993 hns3vf_get_configuration(struct hns3_hw *hw)
 994 {
 995         int ret;
 996
 997         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
 998
 999         /* Get device capability */
1000         ret = hns3vf_get_capability(hw);
1001         if (ret) {
1002                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1003                 return ret;
1004         }
1005
1006         hns3vf_get_push_lsc_cap(hw);
1007
1008         /* Get basic info from PF */
1009         ret = hns3vf_get_basic_info(hw);
1010         if (ret)
1011                 return ret;
1012
1013         /* Get queue configuration from PF */
1014         ret = hns3vf_get_queue_info(hw);
1015         if (ret)
1016                 return ret;
1017
1018         /* Get user defined VF MAC addr from PF */
1019         ret = hns3vf_get_host_mac_addr(hw);
1020         if (ret)
1021                 return ret;
1022
1023         return hns3vf_get_port_base_vlan_filter_state(hw);
1024 }
1025
1026 static void
1027 hns3vf_request_link_info(struct hns3_hw *hw)
1028 {
1029         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1030         bool send_req;
1031         int ret;
1032
1033         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1034                 return;
1035
1036         send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1037                    vf->req_link_info_cnt > 0;
1038         if (!send_req)
1039                 return;
1040
1041         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1042                                 NULL, 0);
1043         if (ret) {
1044                 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1045                 return;
1046         }
1047
1048         if (vf->req_link_info_cnt > 0)
1049                 vf->req_link_info_cnt--;
1050 }
1051
1052 void
1053 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1054                           uint32_t link_speed, uint8_t link_duplex)
1055 {
1056         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1057         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1058         struct hns3_mac *mac = &hw->mac;
1059         int ret;
1060
1061         /*
1062          * PF kernel driver may push link status when VF driver is in resetting,
1063          * driver will stop polling job in this case, after resetting done
1064          * driver will start polling job again.
1065          * When polling job started, driver will get initial link status by
1066          * sending request to PF kernel driver, then could update link status by
1067          * process PF kernel driver's link status mailbox message.
1068          */
1069         if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1070                 return;
1071
1072         if (hw->adapter_state != HNS3_NIC_STARTED)
1073                 return;
1074
1075         mac->link_status = link_status;
1076         mac->link_speed = link_speed;
1077         mac->link_duplex = link_duplex;
1078         ret = hns3vf_dev_link_update(dev, 0);
1079         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1080                 hns3_start_report_lse(dev);
1081 }
1082
1083 static int
1084 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1085 {
1086 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1087         struct hns3_hw *hw = &hns->hw;
1088         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1089         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1090         uint8_t is_kill = on ? 0 : 1;
1091
1092         msg_data[0] = is_kill;
1093         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1094         memcpy(&msg_data[3], &proto, sizeof(proto));
1095
1096         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1097                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1098                                  0);
1099 }
1100
1101 static int
1102 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1103 {
1104         struct hns3_adapter *hns = dev->data->dev_private;
1105         struct hns3_hw *hw = &hns->hw;
1106         int ret;
1107
1108         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1109                 hns3_err(hw,
1110                          "vf set vlan id failed during resetting, vlan_id =%u",
1111                          vlan_id);
1112                 return -EIO;
1113         }
1114         rte_spinlock_lock(&hw->lock);
1115         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1116         rte_spinlock_unlock(&hw->lock);
1117         if (ret)
1118                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1119                          vlan_id, ret);
1120
1121         return ret;
1122 }
1123
1124 static int
1125 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1126 {
1127         uint8_t msg_data;
1128         int ret;
1129
1130         if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1131                 return 0;
1132
1133         msg_data = enable ? 1 : 0;
1134         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1135                         HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1136                         sizeof(msg_data), true, NULL, 0);
1137         if (ret)
1138                 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1139                                 enable ? "enable" : "disable", ret);
1140
1141         return ret;
1142 }
1143
1144 static int
1145 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1146 {
1147         uint8_t msg_data;
1148         int ret;
1149
1150         msg_data = enable ? 1 : 0;
1151         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1152                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1153         if (ret)
1154                 hns3_err(hw, "vf %s strip failed, ret = %d.",
1155                                 enable ? "enable" : "disable", ret);
1156
1157         return ret;
1158 }
1159
1160 static int
1161 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1162 {
1163         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1164         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1165         unsigned int tmp_mask;
1166         int ret = 0;
1167
1168         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1169                 hns3_err(hw, "vf set vlan offload failed during resetting, mask = 0x%x",
1170                          mask);
1171                 return -EIO;
1172         }
1173
1174         tmp_mask = (unsigned int)mask;
1175
1176         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
1177                 rte_spinlock_lock(&hw->lock);
1178                 /* Enable or disable VLAN filter */
1179                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1180                         ret = hns3vf_en_vlan_filter(hw, true);
1181                 else
1182                         ret = hns3vf_en_vlan_filter(hw, false);
1183                 rte_spinlock_unlock(&hw->lock);
1184                 if (ret)
1185                         return ret;
1186         }
1187
1188         /* Vlan stripping setting */
1189         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
1190                 rte_spinlock_lock(&hw->lock);
1191                 /* Enable or disable VLAN stripping */
1192                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1193                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1194                 else
1195                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1196                 rte_spinlock_unlock(&hw->lock);
1197         }
1198
1199         return ret;
1200 }
1201
1202 static int
1203 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1204 {
1205         struct rte_vlan_filter_conf *vfc;
1206         struct hns3_hw *hw = &hns->hw;
1207         uint16_t vlan_id;
1208         uint64_t vbit;
1209         uint64_t ids;
1210         int ret = 0;
1211         uint32_t i;
1212
1213         vfc = &hw->data->vlan_filter_conf;
1214         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1215                 if (vfc->ids[i] == 0)
1216                         continue;
1217                 ids = vfc->ids[i];
1218                 while (ids) {
1219                         /*
1220                          * 64 means the num bits of ids, one bit corresponds to
1221                          * one vlan id
1222                          */
1223                         vlan_id = 64 * i;
1224                         /* count trailing zeroes */
1225                         vbit = ~ids & (ids - 1);
1226                         /* clear least significant bit set */
1227                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1228                         for (; vbit;) {
1229                                 vbit >>= 1;
1230                                 vlan_id++;
1231                         }
1232                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1233                         if (ret) {
1234                                 hns3_err(hw,
1235                                          "VF handle vlan table failed, ret =%d, on = %d",
1236                                          ret, on);
1237                                 return ret;
1238                         }
1239                 }
1240         }
1241
1242         return ret;
1243 }
1244
1245 static int
1246 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1247 {
1248         return hns3vf_handle_all_vlan_table(hns, 0);
1249 }
1250
1251 static int
1252 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1253 {
1254         struct hns3_hw *hw = &hns->hw;
1255         struct rte_eth_conf *dev_conf;
1256         bool en;
1257         int ret;
1258
1259         dev_conf = &hw->data->dev_conf;
1260         en = dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? true
1261                                                                    : false;
1262         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1263         if (ret)
1264                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1265                          ret);
1266         return ret;
1267 }
1268
1269 static int
1270 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1271 {
1272         struct hns3_adapter *hns = dev->data->dev_private;
1273         struct rte_eth_dev_data *data = dev->data;
1274         struct hns3_hw *hw = &hns->hw;
1275         int ret;
1276
1277         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1278             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1279             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1280                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1281                               "or hw_vlan_insert_pvid is not support!");
1282         }
1283
1284         /* Apply vlan offload setting */
1285         ret = hns3vf_vlan_offload_set(dev, RTE_ETH_VLAN_STRIP_MASK |
1286                                         RTE_ETH_VLAN_FILTER_MASK);
1287         if (ret)
1288                 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1289
1290         return ret;
1291 }
1292
1293 static int
1294 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1295 {
1296         uint8_t msg_data;
1297
1298         msg_data = alive ? 1 : 0;
1299         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1300                                  sizeof(msg_data), false, NULL, 0);
1301 }
1302
1303 static void
1304 hns3vf_keep_alive_handler(void *param)
1305 {
1306         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1307         struct hns3_adapter *hns = eth_dev->data->dev_private;
1308         struct hns3_hw *hw = &hns->hw;
1309         int ret;
1310
1311         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1312                                 false, NULL, 0);
1313         if (ret)
1314                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1315                          ret);
1316
1317         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1318                           eth_dev);
1319 }
1320
1321 static void
1322 hns3vf_service_handler(void *param)
1323 {
1324         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1325         struct hns3_adapter *hns = eth_dev->data->dev_private;
1326         struct hns3_hw *hw = &hns->hw;
1327
1328         /*
1329          * The query link status and reset processing are executed in the
1330          * interrupt thread. When the IMP reset occurs, IMP will not respond,
1331          * and the query operation will timeout after 30ms. In the case of
1332          * multiple PF/VFs, each query failure timeout causes the IMP reset
1333          * interrupt to fail to respond within 100ms.
1334          * Before querying the link status, check whether there is a reset
1335          * pending, and if so, abandon the query.
1336          */
1337         if (!hns3vf_is_reset_pending(hns)) {
1338                 hns3vf_request_link_info(hw);
1339                 hns3_update_hw_stats(hw);
1340         } else {
1341                 hns3_warn(hw, "Cancel the query when reset is pending");
1342         }
1343
1344         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1345                           eth_dev);
1346 }
1347
1348 static void
1349 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1350 {
1351 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT      3
1352
1353         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1354
1355         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1356                 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1357
1358         __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1359
1360         hns3vf_service_handler(dev);
1361 }
1362
1363 static void
1364 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1365 {
1366         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1367
1368         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1369
1370         __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1371 }
1372
1373 static int
1374 hns3_query_vf_resource(struct hns3_hw *hw)
1375 {
1376         struct hns3_vf_res_cmd *req;
1377         struct hns3_cmd_desc desc;
1378         uint16_t num_msi;
1379         int ret;
1380
1381         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1382         ret = hns3_cmd_send(hw, &desc, 1);
1383         if (ret) {
1384                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1385                 return ret;
1386         }
1387
1388         req = (struct hns3_vf_res_cmd *)desc.data;
1389         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1390                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1391         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1392                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1393                          num_msi, HNS3_MIN_VECTOR_NUM);
1394                 return -EINVAL;
1395         }
1396
1397         hw->num_msi = num_msi;
1398
1399         return 0;
1400 }
1401
1402 static int
1403 hns3vf_init_hardware(struct hns3_adapter *hns)
1404 {
1405         struct hns3_hw *hw = &hns->hw;
1406         uint16_t mtu = hw->data->mtu;
1407         int ret;
1408
1409         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1410         if (ret)
1411                 return ret;
1412
1413         ret = hns3vf_config_mtu(hw, mtu);
1414         if (ret)
1415                 goto err_init_hardware;
1416
1417         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1418         if (ret) {
1419                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1420                 goto err_init_hardware;
1421         }
1422
1423         ret = hns3_config_gro(hw, false);
1424         if (ret) {
1425                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1426                 goto err_init_hardware;
1427         }
1428
1429         /*
1430          * In the initialization clearing the all hardware mapping relationship
1431          * configurations between queues and interrupt vectors is needed, so
1432          * some error caused by the residual configurations, such as the
1433          * unexpected interrupt, can be avoid.
1434          */
1435         ret = hns3_init_ring_with_vector(hw);
1436         if (ret) {
1437                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1438                 goto err_init_hardware;
1439         }
1440
1441         return 0;
1442
1443 err_init_hardware:
1444         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1445         return ret;
1446 }
1447
1448 static int
1449 hns3vf_clear_vport_list(struct hns3_hw *hw)
1450 {
1451         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1452                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1453                                  NULL, 0);
1454 }
1455
1456 static int
1457 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1458 {
1459         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1460         struct hns3_adapter *hns = eth_dev->data->dev_private;
1461         struct hns3_hw *hw = &hns->hw;
1462         int ret;
1463
1464         PMD_INIT_FUNC_TRACE();
1465
1466         /* Get hardware io base address from pcie BAR2 IO space */
1467         hw->io_base = pci_dev->mem_resource[2].addr;
1468
1469         /* Firmware command queue initialize */
1470         ret = hns3_cmd_init_queue(hw);
1471         if (ret) {
1472                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1473                 goto err_cmd_init_queue;
1474         }
1475
1476         /* Firmware command initialize */
1477         ret = hns3_cmd_init(hw);
1478         if (ret) {
1479                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1480                 goto err_cmd_init;
1481         }
1482
1483         hns3_tx_push_init(eth_dev);
1484
1485         /* Get VF resource */
1486         ret = hns3_query_vf_resource(hw);
1487         if (ret)
1488                 goto err_cmd_init;
1489
1490         rte_spinlock_init(&hw->mbx_resp.lock);
1491
1492         hns3vf_clear_event_cause(hw, 0);
1493
1494         ret = rte_intr_callback_register(pci_dev->intr_handle,
1495                                          hns3vf_interrupt_handler, eth_dev);
1496         if (ret) {
1497                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1498                 goto err_intr_callback_register;
1499         }
1500
1501         /* Enable interrupt */
1502         rte_intr_enable(pci_dev->intr_handle);
1503         hns3vf_enable_irq0(hw);
1504
1505         /* Get configuration from PF */
1506         ret = hns3vf_get_configuration(hw);
1507         if (ret) {
1508                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1509                 goto err_get_config;
1510         }
1511
1512         ret = hns3_stats_init(hw);
1513         if (ret)
1514                 goto err_get_config;
1515
1516         ret = hns3_queue_to_tc_mapping(hw, hw->tqps_num, hw->tqps_num);
1517         if (ret) {
1518                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1519                 goto err_set_tc_queue;
1520         }
1521
1522         ret = hns3vf_clear_vport_list(hw);
1523         if (ret) {
1524                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1525                 goto err_set_tc_queue;
1526         }
1527
1528         ret = hns3vf_init_hardware(hns);
1529         if (ret)
1530                 goto err_set_tc_queue;
1531
1532         hns3_rss_set_default_args(hw);
1533
1534         ret = hns3vf_set_alive(hw, true);
1535         if (ret) {
1536                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1537                 goto err_set_tc_queue;
1538         }
1539
1540         return 0;
1541
1542 err_set_tc_queue:
1543         hns3_stats_uninit(hw);
1544
1545 err_get_config:
1546         hns3vf_disable_irq0(hw);
1547         rte_intr_disable(pci_dev->intr_handle);
1548         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1549                              eth_dev);
1550 err_intr_callback_register:
1551 err_cmd_init:
1552         hns3_cmd_uninit(hw);
1553         hns3_cmd_destroy_queue(hw);
1554 err_cmd_init_queue:
1555         hw->io_base = NULL;
1556
1557         return ret;
1558 }
1559
1560 static void
1561 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1562 {
1563         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1564         struct hns3_adapter *hns = eth_dev->data->dev_private;
1565         struct hns3_hw *hw = &hns->hw;
1566
1567         PMD_INIT_FUNC_TRACE();
1568
1569         hns3_rss_uninit(hns);
1570         (void)hns3_config_gro(hw, false);
1571         (void)hns3vf_set_alive(hw, false);
1572         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1573         hns3_flow_uninit(eth_dev);
1574         hns3_stats_uninit(hw);
1575         hns3vf_disable_irq0(hw);
1576         rte_intr_disable(pci_dev->intr_handle);
1577         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1578                              eth_dev);
1579         hns3_cmd_uninit(hw);
1580         hns3_cmd_destroy_queue(hw);
1581         hw->io_base = NULL;
1582 }
1583
1584 static int
1585 hns3vf_do_stop(struct hns3_adapter *hns)
1586 {
1587         struct hns3_hw *hw = &hns->hw;
1588         int ret;
1589
1590         hw->mac.link_status = RTE_ETH_LINK_DOWN;
1591
1592         /*
1593          * The "hns3vf_do_stop" function will also be called by .stop_service to
1594          * prepare reset. At the time of global or IMP reset, the command cannot
1595          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
1596          * accessed during the reset process. So the mbuf can not be released
1597          * during reset and is required to be released after the reset is
1598          * completed.
1599          */
1600         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
1601                 hns3_dev_release_mbufs(hns);
1602
1603         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
1604                 hns3_configure_all_mac_addr(hns, true);
1605                 ret = hns3_reset_all_tqps(hns);
1606                 if (ret) {
1607                         hns3_err(hw, "failed to reset all queues ret = %d",
1608                                  ret);
1609                         return ret;
1610                 }
1611         }
1612         return 0;
1613 }
1614
1615 static int
1616 hns3vf_dev_stop(struct rte_eth_dev *dev)
1617 {
1618         struct hns3_adapter *hns = dev->data->dev_private;
1619         struct hns3_hw *hw = &hns->hw;
1620
1621         PMD_INIT_FUNC_TRACE();
1622         dev->data->dev_started = 0;
1623
1624         hw->adapter_state = HNS3_NIC_STOPPING;
1625         hns3_set_rxtx_function(dev);
1626         rte_wmb();
1627         /* Disable datapath on secondary process. */
1628         hns3_mp_req_stop_rxtx(dev);
1629         /* Prevent crashes when queues are still in use. */
1630         rte_delay_ms(hw->cfg_max_queues);
1631
1632         rte_spinlock_lock(&hw->lock);
1633         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1634                 hns3_stop_tqps(hw);
1635                 hns3vf_do_stop(hns);
1636                 hns3_unmap_rx_interrupt(dev);
1637                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1638         }
1639         hns3_rx_scattered_reset(dev);
1640         hns3vf_stop_poll_job(dev);
1641         hns3_stop_report_lse(dev);
1642         rte_spinlock_unlock(&hw->lock);
1643
1644         return 0;
1645 }
1646
1647 static int
1648 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1649 {
1650         struct hns3_adapter *hns = eth_dev->data->dev_private;
1651         struct hns3_hw *hw = &hns->hw;
1652         int ret = 0;
1653
1654         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1655                 hns3_mp_uninit(eth_dev);
1656                 return 0;
1657         }
1658
1659         if (hw->adapter_state == HNS3_NIC_STARTED)
1660                 ret = hns3vf_dev_stop(eth_dev);
1661
1662         hw->adapter_state = HNS3_NIC_CLOSING;
1663         hns3_reset_abort(hns);
1664         hw->adapter_state = HNS3_NIC_CLOSED;
1665         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1666         hns3_configure_all_mc_mac_addr(hns, true);
1667         hns3vf_remove_all_vlan_table(hns);
1668         hns3vf_uninit_vf(eth_dev);
1669         hns3_free_all_queues(eth_dev);
1670         rte_free(hw->reset.wait_data);
1671         hns3_mp_uninit(eth_dev);
1672         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
1673
1674         return ret;
1675 }
1676
1677 static int
1678 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1679                        __rte_unused int wait_to_complete)
1680 {
1681         struct hns3_adapter *hns = eth_dev->data->dev_private;
1682         struct hns3_hw *hw = &hns->hw;
1683         struct hns3_mac *mac = &hw->mac;
1684         struct rte_eth_link new_link;
1685
1686         memset(&new_link, 0, sizeof(new_link));
1687         switch (mac->link_speed) {
1688         case RTE_ETH_SPEED_NUM_10M:
1689         case RTE_ETH_SPEED_NUM_100M:
1690         case RTE_ETH_SPEED_NUM_1G:
1691         case RTE_ETH_SPEED_NUM_10G:
1692         case RTE_ETH_SPEED_NUM_25G:
1693         case RTE_ETH_SPEED_NUM_40G:
1694         case RTE_ETH_SPEED_NUM_50G:
1695         case RTE_ETH_SPEED_NUM_100G:
1696         case RTE_ETH_SPEED_NUM_200G:
1697                 if (mac->link_status)
1698                         new_link.link_speed = mac->link_speed;
1699                 break;
1700         default:
1701                 if (mac->link_status)
1702                         new_link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
1703                 break;
1704         }
1705
1706         if (!mac->link_status)
1707                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
1708
1709         new_link.link_duplex = mac->link_duplex;
1710         new_link.link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
1711         new_link.link_autoneg =
1712             !(eth_dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED);
1713
1714         return rte_eth_linkstatus_set(eth_dev, &new_link);
1715 }
1716
1717 static int
1718 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1719 {
1720         struct hns3_hw *hw = &hns->hw;
1721         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1722         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1723         int ret;
1724
1725         ret = hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1726         if (ret)
1727                 return ret;
1728
1729         hns3_enable_rxd_adv_layout(hw);
1730
1731         ret = hns3_init_queues(hns, reset_queue);
1732         if (ret)
1733                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
1734
1735         return ret;
1736 }
1737
1738 static void
1739 hns3vf_restore_filter(struct rte_eth_dev *dev)
1740 {
1741         hns3_restore_rss_filter(dev);
1742 }
1743
1744 static int
1745 hns3vf_dev_start(struct rte_eth_dev *dev)
1746 {
1747         struct hns3_adapter *hns = dev->data->dev_private;
1748         struct hns3_hw *hw = &hns->hw;
1749         int ret;
1750
1751         PMD_INIT_FUNC_TRACE();
1752         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1753                 return -EBUSY;
1754
1755         rte_spinlock_lock(&hw->lock);
1756         hw->adapter_state = HNS3_NIC_STARTING;
1757         ret = hns3vf_do_start(hns, true);
1758         if (ret) {
1759                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1760                 rte_spinlock_unlock(&hw->lock);
1761                 return ret;
1762         }
1763         ret = hns3_map_rx_interrupt(dev);
1764         if (ret)
1765                 goto map_rx_inter_err;
1766
1767         /*
1768          * There are three register used to control the status of a TQP
1769          * (contains a pair of Tx queue and Rx queue) in the new version network
1770          * engine. One is used to control the enabling of Tx queue, the other is
1771          * used to control the enabling of Rx queue, and the last is the master
1772          * switch used to control the enabling of the tqp. The Tx register and
1773          * TQP register must be enabled at the same time to enable a Tx queue.
1774          * The same applies to the Rx queue. For the older network enginem, this
1775          * function only refresh the enabled flag, and it is used to update the
1776          * status of queue in the dpdk framework.
1777          */
1778         ret = hns3_start_all_txqs(dev);
1779         if (ret)
1780                 goto map_rx_inter_err;
1781
1782         ret = hns3_start_all_rxqs(dev);
1783         if (ret)
1784                 goto start_all_rxqs_fail;
1785
1786         hw->adapter_state = HNS3_NIC_STARTED;
1787         rte_spinlock_unlock(&hw->lock);
1788
1789         hns3_rx_scattered_calc(dev);
1790         hns3_set_rxtx_function(dev);
1791         hns3_mp_req_start_rxtx(dev);
1792
1793         hns3vf_restore_filter(dev);
1794
1795         /* Enable interrupt of all rx queues before enabling queues */
1796         hns3_dev_all_rx_queue_intr_enable(hw, true);
1797         hns3_start_tqps(hw);
1798
1799         if (dev->data->dev_conf.intr_conf.lsc != 0)
1800                 hns3vf_dev_link_update(dev, 0);
1801         hns3vf_start_poll_job(dev);
1802
1803         return ret;
1804
1805 start_all_rxqs_fail:
1806         hns3_stop_all_txqs(dev);
1807 map_rx_inter_err:
1808         (void)hns3vf_do_stop(hns);
1809         hw->adapter_state = HNS3_NIC_CONFIGURED;
1810         rte_spinlock_unlock(&hw->lock);
1811
1812         return ret;
1813 }
1814
1815 static bool
1816 is_vf_reset_done(struct hns3_hw *hw)
1817 {
1818 #define HNS3_FUN_RST_ING_BITS \
1819         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
1820          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
1821          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
1822          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
1823
1824         uint32_t val;
1825
1826         if (hw->reset.level == HNS3_VF_RESET) {
1827                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1828                 if (val & HNS3_VF_RST_ING_BIT)
1829                         return false;
1830         } else {
1831                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1832                 if (val & HNS3_FUN_RST_ING_BITS)
1833                         return false;
1834         }
1835         return true;
1836 }
1837
1838 bool
1839 hns3vf_is_reset_pending(struct hns3_adapter *hns)
1840 {
1841         struct hns3_hw *hw = &hns->hw;
1842         enum hns3_reset_level reset;
1843
1844         /*
1845          * According to the protocol of PCIe, FLR to a PF device resets the PF
1846          * state as well as the SR-IOV extended capability including VF Enable
1847          * which means that VFs no longer exist.
1848          *
1849          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
1850          * is in FLR stage, the register state of VF device is not reliable,
1851          * so register states detection can not be carried out. In this case,
1852          * we just ignore the register states and return false to indicate that
1853          * there are no other reset states that need to be processed by driver.
1854          */
1855         if (hw->reset.level == HNS3_VF_FULL_RESET)
1856                 return false;
1857
1858         /* Check the registers to confirm whether there is reset pending */
1859         hns3vf_check_event_cause(hns, NULL);
1860         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
1861         if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
1862             hw->reset.level < reset) {
1863                 hns3_warn(hw, "High level reset %d is pending", reset);
1864                 return true;
1865         }
1866         return false;
1867 }
1868
1869 static int
1870 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
1871 {
1872 #define HNS3_WAIT_PF_RESET_READY_TIME 5
1873         struct hns3_hw *hw = &hns->hw;
1874         struct hns3_wait_data *wait_data = hw->reset.wait_data;
1875         struct timeval tv;
1876
1877         if (wait_data->result == HNS3_WAIT_SUCCESS) {
1878                 /*
1879                  * After vf reset is ready, the PF may not have completed
1880                  * the reset processing. The vf sending mbox to PF may fail
1881                  * during the pf reset, so it is better to add extra delay.
1882                  */
1883                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
1884                     hw->reset.level == HNS3_FLR_RESET)
1885                         return 0;
1886                 /* Reset retry process, no need to add extra delay. */
1887                 if (hw->reset.attempts)
1888                         return 0;
1889                 if (wait_data->check_completion == NULL)
1890                         return 0;
1891
1892                 wait_data->check_completion = NULL;
1893                 wait_data->interval = HNS3_WAIT_PF_RESET_READY_TIME *
1894                         MSEC_PER_SEC * USEC_PER_MSEC;
1895                 wait_data->count = 1;
1896                 wait_data->result = HNS3_WAIT_REQUEST;
1897                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
1898                                   wait_data);
1899                 hns3_warn(hw, "hardware is ready, delay %d sec for PF reset complete",
1900                                 HNS3_WAIT_PF_RESET_READY_TIME);
1901                 return -EAGAIN;
1902         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
1903                 hns3_clock_gettime(&tv);
1904                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
1905                           tv.tv_sec, tv.tv_usec);
1906                 return -ETIME;
1907         } else if (wait_data->result == HNS3_WAIT_REQUEST)
1908                 return -EAGAIN;
1909
1910         wait_data->hns = hns;
1911         wait_data->check_completion = is_vf_reset_done;
1912         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
1913                                 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
1914         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
1915         wait_data->count = HNS3VF_RESET_WAIT_CNT;
1916         wait_data->result = HNS3_WAIT_REQUEST;
1917         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
1918         return -EAGAIN;
1919 }
1920
1921 static int
1922 hns3vf_prepare_reset(struct hns3_adapter *hns)
1923 {
1924         struct hns3_hw *hw = &hns->hw;
1925         int ret;
1926
1927         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
1928                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
1929                                         0, true, NULL, 0);
1930                 if (ret)
1931                         return ret;
1932         }
1933         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
1934
1935         return 0;
1936 }
1937
1938 static int
1939 hns3vf_stop_service(struct hns3_adapter *hns)
1940 {
1941         struct hns3_hw *hw = &hns->hw;
1942         struct rte_eth_dev *eth_dev;
1943
1944         eth_dev = &rte_eth_devices[hw->data->port_id];
1945         if (hw->adapter_state == HNS3_NIC_STARTED) {
1946                 /*
1947                  * Make sure call update link status before hns3vf_stop_poll_job
1948                  * because update link status depend on polling job exist.
1949                  */
1950                 hns3vf_update_link_status(hw, RTE_ETH_LINK_DOWN, hw->mac.link_speed,
1951                                           hw->mac.link_duplex);
1952                 hns3vf_stop_poll_job(eth_dev);
1953         }
1954         hw->mac.link_status = RTE_ETH_LINK_DOWN;
1955
1956         hns3_set_rxtx_function(eth_dev);
1957         rte_wmb();
1958         /* Disable datapath on secondary process. */
1959         hns3_mp_req_stop_rxtx(eth_dev);
1960         rte_delay_ms(hw->cfg_max_queues);
1961
1962         rte_spinlock_lock(&hw->lock);
1963         if (hw->adapter_state == HNS3_NIC_STARTED ||
1964             hw->adapter_state == HNS3_NIC_STOPPING) {
1965                 hns3_enable_all_queues(hw, false);
1966                 hns3vf_do_stop(hns);
1967                 hw->reset.mbuf_deferred_free = true;
1968         } else
1969                 hw->reset.mbuf_deferred_free = false;
1970
1971         /*
1972          * It is cumbersome for hardware to pick-and-choose entries for deletion
1973          * from table space. Hence, for function reset software intervention is
1974          * required to delete the entries.
1975          */
1976         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
1977                 hns3_configure_all_mc_mac_addr(hns, true);
1978         rte_spinlock_unlock(&hw->lock);
1979
1980         return 0;
1981 }
1982
1983 static int
1984 hns3vf_start_service(struct hns3_adapter *hns)
1985 {
1986         struct hns3_hw *hw = &hns->hw;
1987         struct rte_eth_dev *eth_dev;
1988
1989         eth_dev = &rte_eth_devices[hw->data->port_id];
1990         hns3_set_rxtx_function(eth_dev);
1991         hns3_mp_req_start_rxtx(eth_dev);
1992         if (hw->adapter_state == HNS3_NIC_STARTED) {
1993                 hns3vf_start_poll_job(eth_dev);
1994
1995                 /* Enable interrupt of all rx queues before enabling queues */
1996                 hns3_dev_all_rx_queue_intr_enable(hw, true);
1997                 /*
1998                  * Enable state of each rxq and txq will be recovered after
1999                  * reset, so we need to restore them before enable all tqps;
2000                  */
2001                 hns3_restore_tqp_enable_state(hw);
2002                 /*
2003                  * When finished the initialization, enable queues to receive
2004                  * and transmit packets.
2005                  */
2006                 hns3_enable_all_queues(hw, true);
2007         }
2008
2009         return 0;
2010 }
2011
2012 static int
2013 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2014 {
2015         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2016         struct rte_ether_addr *hw_mac;
2017         int ret;
2018
2019         /*
2020          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2021          * on the host by "ip link set ..." command. If the hns3 PF kernel
2022          * ethdev driver sets the MAC address for VF device after the
2023          * initialization of the related VF device, the PF driver will notify
2024          * VF driver to reset VF device to make the new MAC address effective
2025          * immediately. The hns3 VF PMD should check whether the MAC
2026          * address has been changed by the PF kernel ethdev driver, if changed
2027          * VF driver should configure hardware using the new MAC address in the
2028          * recovering hardware configuration stage of the reset process.
2029          */
2030         ret = hns3vf_get_host_mac_addr(hw);
2031         if (ret)
2032                 return ret;
2033
2034         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2035         ret = rte_is_zero_ether_addr(hw_mac);
2036         if (ret) {
2037                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2038         } else {
2039                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2040                 if (!ret) {
2041                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2042                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2043                                               &hw->data->mac_addrs[0]);
2044                         hns3_warn(hw, "Default MAC address has been changed to:"
2045                                   " %s by the host PF kernel ethdev driver",
2046                                   mac_str);
2047                 }
2048         }
2049
2050         return 0;
2051 }
2052
2053 static int
2054 hns3vf_restore_conf(struct hns3_adapter *hns)
2055 {
2056         struct hns3_hw *hw = &hns->hw;
2057         int ret;
2058
2059         ret = hns3vf_check_default_mac_change(hw);
2060         if (ret)
2061                 return ret;
2062
2063         ret = hns3_configure_all_mac_addr(hns, false);
2064         if (ret)
2065                 return ret;
2066
2067         ret = hns3_configure_all_mc_mac_addr(hns, false);
2068         if (ret)
2069                 goto err_mc_mac;
2070
2071         ret = hns3vf_restore_promisc(hns);
2072         if (ret)
2073                 goto err_vlan_table;
2074
2075         ret = hns3vf_restore_vlan_conf(hns);
2076         if (ret)
2077                 goto err_vlan_table;
2078
2079         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2080         if (ret)
2081                 goto err_vlan_table;
2082
2083         ret = hns3_restore_rx_interrupt(hw);
2084         if (ret)
2085                 goto err_vlan_table;
2086
2087         ret = hns3_restore_gro_conf(hw);
2088         if (ret)
2089                 goto err_vlan_table;
2090
2091         if (hw->adapter_state == HNS3_NIC_STARTED) {
2092                 ret = hns3vf_do_start(hns, false);
2093                 if (ret)
2094                         goto err_vlan_table;
2095                 hns3_info(hw, "hns3vf dev restart successful!");
2096         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2097                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2098
2099         ret = hns3vf_set_alive(hw, true);
2100         if (ret) {
2101                 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2102                 goto err_vlan_table;
2103         }
2104
2105         return 0;
2106
2107 err_vlan_table:
2108         hns3_configure_all_mc_mac_addr(hns, true);
2109 err_mc_mac:
2110         hns3_configure_all_mac_addr(hns, true);
2111         return ret;
2112 }
2113
2114 static enum hns3_reset_level
2115 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2116 {
2117         enum hns3_reset_level reset_level;
2118
2119         /* return the highest priority reset level amongst all */
2120         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2121                 reset_level = HNS3_VF_RESET;
2122         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2123                 reset_level = HNS3_VF_FULL_RESET;
2124         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2125                 reset_level = HNS3_VF_PF_FUNC_RESET;
2126         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2127                 reset_level = HNS3_VF_FUNC_RESET;
2128         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2129                 reset_level = HNS3_FLR_RESET;
2130         else
2131                 reset_level = HNS3_NONE_RESET;
2132
2133         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2134                 return HNS3_NONE_RESET;
2135
2136         return reset_level;
2137 }
2138
2139 static void
2140 hns3vf_reset_service(void *param)
2141 {
2142         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2143         struct hns3_hw *hw = &hns->hw;
2144         enum hns3_reset_level reset_level;
2145         struct timeval tv_delta;
2146         struct timeval tv_start;
2147         struct timeval tv;
2148         uint64_t msec;
2149
2150         /*
2151          * The interrupt is not triggered within the delay time.
2152          * The interrupt may have been lost. It is necessary to handle
2153          * the interrupt to recover from the error.
2154          */
2155         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2156                             SCHEDULE_DEFERRED) {
2157                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2158                                  __ATOMIC_RELAXED);
2159                 hns3_err(hw, "Handling interrupts in delayed tasks");
2160                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2161                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2162                 if (reset_level == HNS3_NONE_RESET) {
2163                         hns3_err(hw, "No reset level is set, try global reset");
2164                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2165                 }
2166         }
2167         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2168
2169         /*
2170          * Hardware reset has been notified, we now have to poll & check if
2171          * hardware has actually completed the reset sequence.
2172          */
2173         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2174         if (reset_level != HNS3_NONE_RESET) {
2175                 hns3_clock_gettime(&tv_start);
2176                 hns3_reset_process(hns, reset_level);
2177                 hns3_clock_gettime(&tv);
2178                 timersub(&tv, &tv_start, &tv_delta);
2179                 msec = hns3_clock_calctime_ms(&tv_delta);
2180                 if (msec > HNS3_RESET_PROCESS_MS)
2181                         hns3_err(hw, "%d handle long time delta %" PRIu64
2182                                  " ms time=%ld.%.6ld",
2183                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2184         }
2185 }
2186
2187 static int
2188 hns3vf_reinit_dev(struct hns3_adapter *hns)
2189 {
2190         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2191         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2192         struct hns3_hw *hw = &hns->hw;
2193         int ret;
2194
2195         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2196                 rte_intr_disable(pci_dev->intr_handle);
2197                 ret = hns3vf_set_bus_master(pci_dev, true);
2198                 if (ret < 0) {
2199                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2200                         return ret;
2201                 }
2202         }
2203
2204         /* Firmware command initialize */
2205         ret = hns3_cmd_init(hw);
2206         if (ret) {
2207                 hns3_err(hw, "Failed to init cmd: %d", ret);
2208                 return ret;
2209         }
2210
2211         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2212                 /*
2213                  * UIO enables msix by writing the pcie configuration space
2214                  * vfio_pci enables msix in rte_intr_enable.
2215                  */
2216                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2217                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2218                         if (hns3vf_enable_msix(pci_dev, true))
2219                                 hns3_err(hw, "Failed to enable msix");
2220                 }
2221
2222                 rte_intr_enable(pci_dev->intr_handle);
2223         }
2224
2225         ret = hns3_reset_all_tqps(hns);
2226         if (ret) {
2227                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2228                 return ret;
2229         }
2230
2231         ret = hns3vf_init_hardware(hns);
2232         if (ret) {
2233                 hns3_err(hw, "Failed to init hardware: %d", ret);
2234                 return ret;
2235         }
2236
2237         return 0;
2238 }
2239
2240 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2241         .dev_configure      = hns3vf_dev_configure,
2242         .dev_start          = hns3vf_dev_start,
2243         .dev_stop           = hns3vf_dev_stop,
2244         .dev_close          = hns3vf_dev_close,
2245         .mtu_set            = hns3vf_dev_mtu_set,
2246         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2247         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2248         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2249         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2250         .stats_get          = hns3_stats_get,
2251         .stats_reset        = hns3_stats_reset,
2252         .xstats_get         = hns3_dev_xstats_get,
2253         .xstats_get_names   = hns3_dev_xstats_get_names,
2254         .xstats_reset       = hns3_dev_xstats_reset,
2255         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2256         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2257         .dev_infos_get      = hns3_dev_infos_get,
2258         .fw_version_get     = hns3_fw_version_get,
2259         .rx_queue_setup     = hns3_rx_queue_setup,
2260         .tx_queue_setup     = hns3_tx_queue_setup,
2261         .rx_queue_release   = hns3_dev_rx_queue_release,
2262         .tx_queue_release   = hns3_dev_tx_queue_release,
2263         .rx_queue_start     = hns3_dev_rx_queue_start,
2264         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2265         .tx_queue_start     = hns3_dev_tx_queue_start,
2266         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2267         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2268         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2269         .rxq_info_get       = hns3_rxq_info_get,
2270         .txq_info_get       = hns3_txq_info_get,
2271         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2272         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2273         .mac_addr_add       = hns3_add_mac_addr,
2274         .mac_addr_remove    = hns3_remove_mac_addr,
2275         .mac_addr_set       = hns3vf_set_default_mac_addr,
2276         .set_mc_addr_list   = hns3_set_mc_mac_addr_list,
2277         .link_update        = hns3vf_dev_link_update,
2278         .rss_hash_update    = hns3_dev_rss_hash_update,
2279         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2280         .reta_update        = hns3_dev_rss_reta_update,
2281         .reta_query         = hns3_dev_rss_reta_query,
2282         .flow_ops_get       = hns3_dev_flow_ops_get,
2283         .vlan_filter_set    = hns3vf_vlan_filter_set,
2284         .vlan_offload_set   = hns3vf_vlan_offload_set,
2285         .get_reg            = hns3_get_regs,
2286         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2287         .tx_done_cleanup    = hns3_tx_done_cleanup,
2288         .eth_dev_priv_dump  = hns3_eth_dev_priv_dump,
2289 };
2290
2291 static const struct hns3_reset_ops hns3vf_reset_ops = {
2292         .reset_service       = hns3vf_reset_service,
2293         .stop_service        = hns3vf_stop_service,
2294         .prepare_reset       = hns3vf_prepare_reset,
2295         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2296         .reinit_dev          = hns3vf_reinit_dev,
2297         .restore_conf        = hns3vf_restore_conf,
2298         .start_service       = hns3vf_start_service,
2299 };
2300
2301 static void
2302 hns3vf_init_hw_ops(struct hns3_hw *hw)
2303 {
2304         hw->ops.add_mc_mac_addr = hns3vf_add_mc_mac_addr;
2305         hw->ops.del_mc_mac_addr = hns3vf_remove_mc_mac_addr;
2306         hw->ops.add_uc_mac_addr = hns3vf_add_uc_mac_addr;
2307         hw->ops.del_uc_mac_addr = hns3vf_remove_uc_mac_addr;
2308         hw->ops.bind_ring_with_vector = hns3vf_bind_ring_with_vector;
2309 }
2310
2311 static int
2312 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2313 {
2314         struct hns3_adapter *hns = eth_dev->data->dev_private;
2315         struct hns3_hw *hw = &hns->hw;
2316         int ret;
2317
2318         PMD_INIT_FUNC_TRACE();
2319
2320         hns3_flow_init(eth_dev);
2321
2322         hns3_set_rxtx_function(eth_dev);
2323         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2324         eth_dev->rx_queue_count = hns3_rx_queue_count;
2325         ret = hns3_mp_init(eth_dev);
2326         if (ret)
2327                 goto err_mp_init;
2328
2329         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2330                 hns3_tx_push_init(eth_dev);
2331                 return 0;
2332         }
2333
2334         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2335         hns->is_vf = true;
2336         hw->data = eth_dev->data;
2337         hns3_parse_devargs(eth_dev);
2338
2339         ret = hns3_reset_init(hw);
2340         if (ret)
2341                 goto err_init_reset;
2342         hw->reset.ops = &hns3vf_reset_ops;
2343
2344         hns3vf_init_hw_ops(hw);
2345         ret = hns3vf_init_vf(eth_dev);
2346         if (ret) {
2347                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2348                 goto err_init_vf;
2349         }
2350
2351         ret = hns3_init_mac_addrs(eth_dev);
2352         if (ret != 0)
2353                 goto err_init_mac_addrs;
2354
2355         hw->adapter_state = HNS3_NIC_INITIALIZED;
2356
2357         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2358                             SCHEDULE_PENDING) {
2359                 hns3_err(hw, "Reschedule reset service after dev_init");
2360                 hns3_schedule_reset(hns);
2361         } else {
2362                 /* IMP will wait ready flag before reset */
2363                 hns3_notify_reset_ready(hw, false);
2364         }
2365         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2366                           eth_dev);
2367         return 0;
2368
2369 err_init_mac_addrs:
2370         hns3vf_uninit_vf(eth_dev);
2371
2372 err_init_vf:
2373         rte_free(hw->reset.wait_data);
2374
2375 err_init_reset:
2376         hns3_mp_uninit(eth_dev);
2377
2378 err_mp_init:
2379         eth_dev->dev_ops = NULL;
2380         eth_dev->rx_pkt_burst = NULL;
2381         eth_dev->rx_descriptor_status = NULL;
2382         eth_dev->tx_pkt_burst = NULL;
2383         eth_dev->tx_pkt_prepare = NULL;
2384         eth_dev->tx_descriptor_status = NULL;
2385
2386         return ret;
2387 }
2388
2389 static int
2390 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2391 {
2392         struct hns3_adapter *hns = eth_dev->data->dev_private;
2393         struct hns3_hw *hw = &hns->hw;
2394
2395         PMD_INIT_FUNC_TRACE();
2396
2397         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2398                 hns3_mp_uninit(eth_dev);
2399                 return 0;
2400         }
2401
2402         if (hw->adapter_state < HNS3_NIC_CLOSING)
2403                 hns3vf_dev_close(eth_dev);
2404
2405         hw->adapter_state = HNS3_NIC_REMOVED;
2406         return 0;
2407 }
2408
2409 static int
2410 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2411                      struct rte_pci_device *pci_dev)
2412 {
2413         return rte_eth_dev_pci_generic_probe(pci_dev,
2414                                              sizeof(struct hns3_adapter),
2415                                              hns3vf_dev_init);
2416 }
2417
2418 static int
2419 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2420 {
2421         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2422 }
2423
2424 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2425         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2426         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2427         { .vendor_id = 0, }, /* sentinel */
2428 };
2429
2430 static struct rte_pci_driver rte_hns3vf_pmd = {
2431         .id_table = pci_id_hns3vf_map,
2432         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2433         .probe = eth_hns3vf_pci_probe,
2434         .remove = eth_hns3vf_pci_remove,
2435 };
2436
2437 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2438 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2439 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
2440 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
2441                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
2442                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
2443                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
2444                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16_t> ");