drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static int
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71         int ret;
  72
  73         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  74         if (ret < 0) {
  75                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  76                              PCI_COMMAND);
  77                 return ret;
  78         }
  79
  80         if (op)
  81                 /* set the master bit */
  82                 reg |= PCI_COMMAND_MASTER;
  83         else
  84                 reg &= ~(PCI_COMMAND_MASTER);
  85
  86         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  87 }
  88
  89 /**
  90  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  91  * @cap: the capability
  92  *
  93  * Return the address of the given capability within the PCI capability list.
  94  */
  95 static int
  96 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  97 {
  98 #define MAX_PCIE_CAPABILITY 48
  99         uint16_t status;
 100         uint8_t pos;
 101         uint8_t id;
 102         int ttl;
 103         int ret;
 104
 105         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
 106         if (ret < 0) {
 107                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
 108                 return 0;
 109         }
 110
 111         if (!(status & PCI_STATUS_CAP_LIST))
 112                 return 0;
 113
 114         ttl = MAX_PCIE_CAPABILITY;
 115         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 116                                   PCI_CAPABILITY_LIST);
 117         if (ret < 0) {
 118                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 119                              PCI_CAPABILITY_LIST);
 120                 return 0;
 121         }
 122
 123         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 124                 ret = rte_pci_read_config(device, &id, sizeof(id),
 125                                           (pos + PCI_CAP_LIST_ID));
 126                 if (ret < 0) {
 127                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 128                                      (pos + PCI_CAP_LIST_ID));
 129                         break;
 130                 }
 131
 132                 if (id == 0xFF)
 133                         break;
 134
 135                 if (id == cap)
 136                         return (int)pos;
 137
 138                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 139                                           (pos + PCI_CAP_LIST_NEXT));
 140                 if (ret < 0) {
 141                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 142                                      (pos + PCI_CAP_LIST_NEXT));
 143                         break;
 144                 }
 145         }
 146         return 0;
 147 }
 148
 149 static int
 150 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 151 {
 152         uint16_t control;
 153         int pos;
 154         int ret;
 155
 156         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 157         if (pos) {
 158                 ret = rte_pci_read_config(device, &control, sizeof(control),
 159                                     (pos + PCI_MSIX_FLAGS));
 160                 if (ret < 0) {
 161                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 162                                      (pos + PCI_MSIX_FLAGS));
 163                         return -ENXIO;
 164                 }
 165
 166                 if (op)
 167                         control |= PCI_MSIX_FLAGS_ENABLE;
 168                 else
 169                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 170                 rte_pci_write_config(device, &control, sizeof(control),
 171                                      (pos + PCI_MSIX_FLAGS));
 172                 return 0;
 173         }
 174         return -ENXIO;
 175 }
 176
 177 static int
 178 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 179 {
 180         /* mac address was checked by upper level interface */
 181         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 182         int ret;
 183
 184         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 185                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 186                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 187         if (ret) {
 188                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 189                                       mac_addr);
 190                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 191                          mac_str, ret);
 192         }
 193         return ret;
 194 }
 195
 196 static int
 197 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 198 {
 199         /* mac address was checked by upper level interface */
 200         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 201         int ret;
 202
 203         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 204                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 205                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 206                                 false, NULL, 0);
 207         if (ret) {
 208                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 209                                       mac_addr);
 210                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 211                          mac_str, ret);
 212         }
 213         return ret;
 214 }
 215
 216 static int
 217 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 218 {
 219         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 220         struct rte_ether_addr *addr;
 221         int ret;
 222         int i;
 223
 224         for (i = 0; i < hw->mc_addrs_num; i++) {
 225                 addr = &hw->mc_addrs[i];
 226                 /* Check if there are duplicate addresses */
 227                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 228                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 229                                               addr);
 230                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 231                                  "(%s) is added by the set_mc_mac_addr_list "
 232                                  "API", mac_str);
 233                         return -EINVAL;
 234                 }
 235         }
 236
 237         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 238         if (ret) {
 239                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 240                                       mac_addr);
 241                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 242                          mac_str, ret);
 243         }
 244         return ret;
 245 }
 246
 247 static int
 248 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 249                     __rte_unused uint32_t idx,
 250                     __rte_unused uint32_t pool)
 251 {
 252         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         /*
 259          * In hns3 network engine adding UC and MC mac address with different
 260          * commands with firmware. We need to determine whether the input
 261          * address is a UC or a MC address to call different commands.
 262          * By the way, it is recommended calling the API function named
 263          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 264          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 265          * may affect the specifications of UC mac addresses.
 266          */
 267         if (rte_is_multicast_ether_addr(mac_addr))
 268                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 269         else
 270                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 271
 272         rte_spinlock_unlock(&hw->lock);
 273         if (ret) {
 274                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 275                                       mac_addr);
 276                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 277                          ret);
 278         }
 279
 280         return ret;
 281 }
 282
 283 static void
 284 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 285 {
 286         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 287         /* index will be checked by upper level rte interface */
 288         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 289         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 290         int ret;
 291
 292         rte_spinlock_lock(&hw->lock);
 293
 294         if (rte_is_multicast_ether_addr(mac_addr))
 295                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 296         else
 297                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 298
 299         rte_spinlock_unlock(&hw->lock);
 300         if (ret) {
 301                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 302                                       mac_addr);
 303                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 304                          mac_str, ret);
 305         }
 306 }
 307
 308 static int
 309 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 310                             struct rte_ether_addr *mac_addr)
 311 {
 312 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 313         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 314         struct rte_ether_addr *old_addr;
 315         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 316         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 317         int ret;
 318
 319         /*
 320          * It has been guaranteed that input parameter named mac_addr is valid
 321          * address in the rte layer of DPDK framework.
 322          */
 323         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 324         rte_spinlock_lock(&hw->lock);
 325         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 326         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 327                RTE_ETHER_ADDR_LEN);
 328
 329         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 330                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 331                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 332         if (ret) {
 333                 /*
 334                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 335                  * driver. When user has configured a MAC address for VF device
 336                  * by "ip link set ..." command based on the PF device, the hns3
 337                  * PF kernel ethdev driver does not allow VF driver to request
 338                  * reconfiguring a different default MAC address, and return
 339                  * -EPREM to VF driver through mailbox.
 340                  */
 341                 if (ret == -EPERM) {
 342                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 343                                               old_addr);
 344                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 345                                   mac_str);
 346                 } else {
 347                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 348                                               mac_addr);
 349                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 350                                  mac_str, ret);
 351                 }
 352         }
 353
 354         rte_ether_addr_copy(mac_addr,
 355                             (struct rte_ether_addr *)hw->mac.mac_addr);
 356         rte_spinlock_unlock(&hw->lock);
 357
 358         return ret;
 359 }
 360
 361 static int
 362 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 363 {
 364         struct hns3_hw *hw = &hns->hw;
 365         struct rte_ether_addr *addr;
 366         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 367         int err = 0;
 368         int ret;
 369         int i;
 370
 371         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 372                 addr = &hw->data->mac_addrs[i];
 373                 if (rte_is_zero_ether_addr(addr))
 374                         continue;
 375                 if (rte_is_multicast_ether_addr(addr))
 376                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 377                               hns3vf_add_mc_mac_addr(hw, addr);
 378                 else
 379                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 380                               hns3vf_add_uc_mac_addr(hw, addr);
 381
 382                 if (ret) {
 383                         err = ret;
 384                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 385                                               addr);
 386                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 387                                  "ret = %d.", del ? "remove" : "restore",
 388                                  mac_str, i, ret);
 389                 }
 390         }
 391         return err;
 392 }
 393
 394 static int
 395 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 396                        struct rte_ether_addr *mac_addr)
 397 {
 398         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 399         int ret;
 400
 401         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 402                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 403                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 404                                 NULL, 0);
 405         if (ret) {
 406                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 407                                       mac_addr);
 408                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 409                          mac_str, ret);
 410         }
 411
 412         return ret;
 413 }
 414
 415 static int
 416 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 417                           struct rte_ether_addr *mac_addr)
 418 {
 419         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 420         int ret;
 421
 422         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 423                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 424                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 425                                 NULL, 0);
 426         if (ret) {
 427                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 428                                       mac_addr);
 429                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 430                          mac_str, ret);
 431         }
 432
 433         return ret;
 434 }
 435
 436 static int
 437 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 438                              struct rte_ether_addr *mc_addr_set,
 439                              uint32_t nb_mc_addr)
 440 {
 441         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 442         struct rte_ether_addr *addr;
 443         uint32_t i;
 444         uint32_t j;
 445
 446         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 447                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 448                          "invalid. valid range: 0~%d",
 449                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 450                 return -EINVAL;
 451         }
 452
 453         /* Check if input mac addresses are valid */
 454         for (i = 0; i < nb_mc_addr; i++) {
 455                 addr = &mc_addr_set[i];
 456                 if (!rte_is_multicast_ether_addr(addr)) {
 457                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 458                                               addr);
 459                         hns3_err(hw,
 460                                  "failed to set mc mac addr, addr(%s) invalid.",
 461                                  mac_str);
 462                         return -EINVAL;
 463                 }
 464
 465                 /* Check if there are duplicate addresses */
 466                 for (j = i + 1; j < nb_mc_addr; j++) {
 467                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 468                                 rte_ether_format_addr(mac_str,
 469                                                       RTE_ETHER_ADDR_FMT_SIZE,
 470                                                       addr);
 471                                 hns3_err(hw, "failed to set mc mac addr, "
 472                                          "addrs invalid. two same addrs(%s).",
 473                                          mac_str);
 474                                 return -EINVAL;
 475                         }
 476                 }
 477
 478                 /*
 479                  * Check if there are duplicate addresses between mac_addrs
 480                  * and mc_addr_set
 481                  */
 482                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 483                         if (rte_is_same_ether_addr(addr,
 484                                                    &hw->data->mac_addrs[j])) {
 485                                 rte_ether_format_addr(mac_str,
 486                                                       RTE_ETHER_ADDR_FMT_SIZE,
 487                                                       addr);
 488                                 hns3_err(hw, "failed to set mc mac addr, "
 489                                          "addrs invalid. addrs(%s) has already "
 490                                          "configured in mac_addr add API",
 491                                          mac_str);
 492                                 return -EINVAL;
 493                         }
 494                 }
 495         }
 496
 497         return 0;
 498 }
 499
 500 static int
 501 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 502                             struct rte_ether_addr *mc_addr_set,
 503                             uint32_t nb_mc_addr)
 504 {
 505         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 506         struct rte_ether_addr *addr;
 507         int cur_addr_num;
 508         int set_addr_num;
 509         int num;
 510         int ret;
 511         int i;
 512
 513         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 514         if (ret)
 515                 return ret;
 516
 517         rte_spinlock_lock(&hw->lock);
 518         cur_addr_num = hw->mc_addrs_num;
 519         for (i = 0; i < cur_addr_num; i++) {
 520                 num = cur_addr_num - i - 1;
 521                 addr = &hw->mc_addrs[num];
 522                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 523                 if (ret) {
 524                         rte_spinlock_unlock(&hw->lock);
 525                         return ret;
 526                 }
 527
 528                 hw->mc_addrs_num--;
 529         }
 530
 531         set_addr_num = (int)nb_mc_addr;
 532         for (i = 0; i < set_addr_num; i++) {
 533                 addr = &mc_addr_set[i];
 534                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 535                 if (ret) {
 536                         rte_spinlock_unlock(&hw->lock);
 537                         return ret;
 538                 }
 539
 540                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 541                 hw->mc_addrs_num++;
 542         }
 543         rte_spinlock_unlock(&hw->lock);
 544
 545         return 0;
 546 }
 547
 548 static int
 549 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 550 {
 551         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 552         struct hns3_hw *hw = &hns->hw;
 553         struct rte_ether_addr *addr;
 554         int err = 0;
 555         int ret;
 556         int i;
 557
 558         for (i = 0; i < hw->mc_addrs_num; i++) {
 559                 addr = &hw->mc_addrs[i];
 560                 if (!rte_is_multicast_ether_addr(addr))
 561                         continue;
 562                 if (del)
 563                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 564                 else
 565                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 566                 if (ret) {
 567                         err = ret;
 568                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 569                                               addr);
 570                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 571                                  del ? "Remove" : "Restore", mac_str, ret);
 572                 }
 573         }
 574         return err;
 575 }
 576
 577 static int
 578 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 579                         bool en_uc_pmc, bool en_mc_pmc)
 580 {
 581         struct hns3_mbx_vf_to_pf_cmd *req;
 582         struct hns3_cmd_desc desc;
 583         int ret;
 584
 585         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 586
 587         /*
 588          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 589          * so there are some features for promiscuous/allmulticast mode in hns3
 590          * VF PMD driver as below:
 591          * 1. The promiscuous/allmulticast mode can be configured successfully
 592          *    only based on the trusted VF device. If based on the non trusted
 593          *    VF device, configuring promiscuous/allmulticast mode will fail.
 594          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 595          *    kernel ethdev driver on the host by the following command:
 596          *      "ip link set <eth num> vf <vf id> turst on"
 597          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 598          *    driver can receive the ingress and outgoing traffic. In the words,
 599          *    all the ingress packets, all the packets sent from the PF and
 600          *    other VFs on the same physical port.
 601          * 3. Note: Because of the hardware constraints, By default vlan filter
 602          *    is enabled and couldn't be turned off based on VF device, so vlan
 603          *    filter is still effective even in promiscuous mode. If upper
 604          *    applications don't call rte_eth_dev_vlan_filter API function to
 605          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 606          *    the packets with vlan tag in promiscuoue mode.
 607          */
 608         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 609         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 610         req->msg[1] = en_bc_pmc ? 1 : 0;
 611         req->msg[2] = en_uc_pmc ? 1 : 0;
 612         req->msg[3] = en_mc_pmc ? 1 : 0;
 613         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 614
 615         ret = hns3_cmd_send(hw, &desc, 1);
 616         if (ret)
 617                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 618
 619         return ret;
 620 }
 621
 622 static int
 623 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 624 {
 625         struct hns3_adapter *hns = dev->data->dev_private;
 626         struct hns3_hw *hw = &hns->hw;
 627         int ret;
 628
 629         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 630         if (ret)
 631                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 632                         ret);
 633         return ret;
 634 }
 635
 636 static int
 637 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 638 {
 639         bool allmulti = dev->data->all_multicast ? true : false;
 640         struct hns3_adapter *hns = dev->data->dev_private;
 641         struct hns3_hw *hw = &hns->hw;
 642         int ret;
 643
 644         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 645         if (ret)
 646                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 647                         ret);
 648         return ret;
 649 }
 650
 651 static int
 652 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 653 {
 654         struct hns3_adapter *hns = dev->data->dev_private;
 655         struct hns3_hw *hw = &hns->hw;
 656         int ret;
 657
 658         if (dev->data->promiscuous)
 659                 return 0;
 660
 661         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 662         if (ret)
 663                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 664                         ret);
 665         return ret;
 666 }
 667
 668 static int
 669 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 670 {
 671         struct hns3_adapter *hns = dev->data->dev_private;
 672         struct hns3_hw *hw = &hns->hw;
 673         int ret;
 674
 675         if (dev->data->promiscuous)
 676                 return 0;
 677
 678         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 679         if (ret)
 680                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 681                         ret);
 682         return ret;
 683 }
 684
 685 static int
 686 hns3vf_restore_promisc(struct hns3_adapter *hns)
 687 {
 688         struct hns3_hw *hw = &hns->hw;
 689         bool allmulti = hw->data->all_multicast ? true : false;
 690
 691         if (hw->data->promiscuous)
 692                 return hns3vf_set_promisc_mode(hw, true, true, true);
 693
 694         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 695 }
 696
 697 static int
 698 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 699                              bool mmap, enum hns3_ring_type queue_type,
 700                              uint16_t queue_id)
 701 {
 702         struct hns3_vf_bind_vector_msg bind_msg;
 703         const char *op_str;
 704         uint16_t code;
 705         int ret;
 706
 707         memset(&bind_msg, 0, sizeof(bind_msg));
 708         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 709                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 710         bind_msg.vector_id = vector_id;
 711
 712         if (queue_type == HNS3_RING_TYPE_RX)
 713                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 714         else
 715                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 716
 717         bind_msg.param[0].ring_type = queue_type;
 718         bind_msg.ring_num = 1;
 719         bind_msg.param[0].tqp_index = queue_id;
 720         op_str = mmap ? "Map" : "Unmap";
 721         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 722                                 sizeof(bind_msg), false, NULL, 0);
 723         if (ret)
 724                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 725                          op_str, queue_id, bind_msg.vector_id, ret);
 726
 727         return ret;
 728 }
 729
 730 static int
 731 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 732 {
 733         uint16_t vec;
 734         int ret;
 735         int i;
 736
 737         /*
 738          * In hns3 network engine, vector 0 is always the misc interrupt of this
 739          * function, vector 1~N can be used respectively for the queues of the
 740          * function. Tx and Rx queues with the same number share the interrupt
 741          * vector. In the initialization clearing the all hardware mapping
 742          * relationship configurations between queues and interrupt vectors is
 743          * needed, so some error caused by the residual configurations, such as
 744          * the unexpected Tx interrupt, can be avoid.
 745          */
 746         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 747         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 748                 vec = vec - 1; /* the last interrupt is reserved */
 749         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 750         for (i = 0; i < hw->intr_tqps_num; i++) {
 751                 /*
 752                  * Set gap limiter/rate limiter/quanity limiter algorithm
 753                  * configuration for interrupt coalesce of queue's interrupt.
 754                  */
 755                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 756                                        HNS3_TQP_INTR_GL_DEFAULT);
 757                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 758                                        HNS3_TQP_INTR_GL_DEFAULT);
 759                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 760                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 761
 762                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 763                                                    HNS3_RING_TYPE_TX, i);
 764                 if (ret) {
 765                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 766                                           "vector: %d, ret=%d", i, vec, ret);
 767                         return ret;
 768                 }
 769
 770                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 771                                                    HNS3_RING_TYPE_RX, i);
 772                 if (ret) {
 773                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 774                                           "vector: %d, ret=%d", i, vec, ret);
 775                         return ret;
 776                 }
 777         }
 778
 779         return 0;
 780 }
 781
 782 static int
 783 hns3vf_dev_configure(struct rte_eth_dev *dev)
 784 {
 785         struct hns3_adapter *hns = dev->data->dev_private;
 786         struct hns3_hw *hw = &hns->hw;
 787         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 788         struct rte_eth_conf *conf = &dev->data->dev_conf;
 789         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 790         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 791         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 792         struct rte_eth_rss_conf rss_conf;
 793         uint16_t mtu;
 794         bool gro_en;
 795         int ret;
 796
 797         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 798
 799         /*
 800          * Some versions of hardware network engine does not support
 801          * individually enable/disable/reset the Tx or Rx queue. These devices
 802          * must enable/disable/reset Tx and Rx queues at the same time. When the
 803          * numbers of Tx queues allocated by upper applications are not equal to
 804          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 805          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 806          * work as usual. But these fake queues are imperceptible, and can not
 807          * be used by upper applications.
 808          */
 809         if (!hns3_dev_indep_txrx_supported(hw)) {
 810                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 811                 if (ret) {
 812                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
 813                                  ret);
 814                         return ret;
 815                 }
 816         }
 817
 818         hw->adapter_state = HNS3_NIC_CONFIGURING;
 819         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 820                 hns3_err(hw, "setting link speed/duplex not supported");
 821                 ret = -EINVAL;
 822                 goto cfg_err;
 823         }
 824
 825         /* When RSS is not configured, redirect the packet queue 0 */
 826         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 827                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 828                 hw->rss_dis_flag = false;
 829                 rss_conf = conf->rx_adv_conf.rss_conf;
 830                 if (rss_conf.rss_key == NULL) {
 831                         rss_conf.rss_key = rss_cfg->key;
 832                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 833                 }
 834
 835                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 836                 if (ret)
 837                         goto cfg_err;
 838         }
 839
 840         /*
 841          * If jumbo frames are enabled, MTU needs to be refreshed
 842          * according to the maximum RX packet length.
 843          */
 844         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 845                 /*
 846                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 847                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 848                  * can safely assign to "uint16_t" type variable.
 849                  */
 850                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 851                 ret = hns3vf_dev_mtu_set(dev, mtu);
 852                 if (ret)
 853                         goto cfg_err;
 854                 dev->data->mtu = mtu;
 855         }
 856
 857         ret = hns3vf_dev_configure_vlan(dev);
 858         if (ret)
 859                 goto cfg_err;
 860
 861         /* config hardware GRO */
 862         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 863         ret = hns3_config_gro(hw, gro_en);
 864         if (ret)
 865                 goto cfg_err;
 866
 867         hns->rx_simple_allowed = true;
 868         hns->rx_vec_allowed = true;
 869         hns->tx_simple_allowed = true;
 870         hns->tx_vec_allowed = true;
 871
 872         hns3_init_rx_ptype_tble(dev);
 873
 874         hw->adapter_state = HNS3_NIC_CONFIGURED;
 875         return 0;
 876
 877 cfg_err:
 878         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 879         hw->adapter_state = HNS3_NIC_INITIALIZED;
 880
 881         return ret;
 882 }
 883
 884 static int
 885 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 886 {
 887         int ret;
 888
 889         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 890                                 sizeof(mtu), true, NULL, 0);
 891         if (ret)
 892                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 893
 894         return ret;
 895 }
 896
 897 static int
 898 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 899 {
 900         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 901         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 902         int ret;
 903
 904         /*
 905          * The hns3 PF/VF devices on the same port share the hardware MTU
 906          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 907          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 908          * driver, there is no need to stop the port for hns3 VF device, and the
 909          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 910          * PF's MTU.
 911          */
 912         if (rte_atomic16_read(&hw->reset.resetting)) {
 913                 hns3_err(hw, "Failed to set mtu during resetting");
 914                 return -EIO;
 915         }
 916
 917         /*
 918          * when Rx of scattered packets is off, we have some possibility of
 919          * using vector Rx process function or simple Rx functions in hns3 PMD
 920          * driver. If the input MTU is increased and the maximum length of
 921          * received packets is greater than the length of a buffer for Rx
 922          * packet, the hardware network engine needs to use multiple BDs and
 923          * buffers to store these packets. This will cause problems when still
 924          * using vector Rx process function or simple Rx function to receiving
 925          * packets. So, when Rx of scattered packets is off and device is
 926          * started, it is not permitted to increase MTU so that the maximum
 927          * length of Rx packets is greater than Rx buffer length.
 928          */
 929         if (dev->data->dev_started && !dev->data->scattered_rx &&
 930             frame_size > hw->rx_buf_len) {
 931                 hns3_err(hw, "failed to set mtu because current is "
 932                         "not scattered rx mode");
 933                 return -EOPNOTSUPP;
 934         }
 935
 936         rte_spinlock_lock(&hw->lock);
 937         ret = hns3vf_config_mtu(hw, mtu);
 938         if (ret) {
 939                 rte_spinlock_unlock(&hw->lock);
 940                 return ret;
 941         }
 942         if (frame_size > RTE_ETHER_MAX_LEN)
 943                 dev->data->dev_conf.rxmode.offloads |=
 944                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 945         else
 946                 dev->data->dev_conf.rxmode.offloads &=
 947                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 948         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 949         rte_spinlock_unlock(&hw->lock);
 950
 951         return 0;
 952 }
 953
 954 static int
 955 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 956 {
 957         struct hns3_adapter *hns = eth_dev->data->dev_private;
 958         struct hns3_hw *hw = &hns->hw;
 959         uint16_t q_num = hw->tqps_num;
 960
 961         /*
 962          * In interrupt mode, 'max_rx_queues' is set based on the number of
 963          * MSI-X interrupt resources of the hardware.
 964          */
 965         if (hw->data->dev_conf.intr_conf.rxq == 1)
 966                 q_num = hw->intr_tqps_num;
 967
 968         info->max_rx_queues = q_num;
 969         info->max_tx_queues = hw->tqps_num;
 970         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 971         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 972         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 973         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 974         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 975
 976         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 977                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 978                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 979                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 980                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 981                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 982                                  DEV_RX_OFFLOAD_SCATTER |
 983                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 984                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 985                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 986                                  DEV_RX_OFFLOAD_RSS_HASH |
 987                                  DEV_RX_OFFLOAD_TCP_LRO);
 988         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 989                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 990                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 991                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 992                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 993                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 994                                  DEV_TX_OFFLOAD_TCP_TSO |
 995                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 996                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 997                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 998                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 999                                  hns3_txvlan_cap_get(hw));
1000
1001         if (hns3_dev_indep_txrx_supported(hw))
1002                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
1003                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
1004
1005         info->rx_desc_lim = (struct rte_eth_desc_lim) {
1006                 .nb_max = HNS3_MAX_RING_DESC,
1007                 .nb_min = HNS3_MIN_RING_DESC,
1008                 .nb_align = HNS3_ALIGN_RING_DESC,
1009         };
1010
1011         info->tx_desc_lim = (struct rte_eth_desc_lim) {
1012                 .nb_max = HNS3_MAX_RING_DESC,
1013                 .nb_min = HNS3_MIN_RING_DESC,
1014                 .nb_align = HNS3_ALIGN_RING_DESC,
1015                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
1016                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
1017         };
1018
1019         info->default_rxconf = (struct rte_eth_rxconf) {
1020                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
1021                 /*
1022                  * If there are no available Rx buffer descriptors, incoming
1023                  * packets are always dropped by hardware based on hns3 network
1024                  * engine.
1025                  */
1026                 .rx_drop_en = 1,
1027                 .offloads = 0,
1028         };
1029         info->default_txconf = (struct rte_eth_txconf) {
1030                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
1031                 .offloads = 0,
1032         };
1033
1034         info->vmdq_queue_num = 0;
1035
1036         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
1037         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1038         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1039         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1040         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1041
1042         return 0;
1043 }
1044
1045 static void
1046 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1047 {
1048         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1049 }
1050
1051 static void
1052 hns3vf_disable_irq0(struct hns3_hw *hw)
1053 {
1054         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1055 }
1056
1057 static void
1058 hns3vf_enable_irq0(struct hns3_hw *hw)
1059 {
1060         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1061 }
1062
1063 static enum hns3vf_evt_cause
1064 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1065 {
1066         struct hns3_hw *hw = &hns->hw;
1067         enum hns3vf_evt_cause ret;
1068         uint32_t cmdq_stat_reg;
1069         uint32_t rst_ing_reg;
1070         uint32_t val;
1071
1072         /* Fetch the events from their corresponding regs */
1073         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1074
1075         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1076                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1077                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1078                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1079                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1080                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1081                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1082                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1083                 if (clearval) {
1084                         hw->reset.stats.global_cnt++;
1085                         hns3_warn(hw, "Global reset detected, clear reset status");
1086                 } else {
1087                         hns3_schedule_delayed_reset(hns);
1088                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1089                 }
1090
1091                 ret = HNS3VF_VECTOR0_EVENT_RST;
1092                 goto out;
1093         }
1094
1095         /* Check for vector0 mailbox(=CMDQ RX) event source */
1096         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1097                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1098                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1099                 goto out;
1100         }
1101
1102         val = 0;
1103         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1104 out:
1105         if (clearval)
1106                 *clearval = val;
1107         return ret;
1108 }
1109
1110 static void
1111 hns3vf_interrupt_handler(void *param)
1112 {
1113         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1114         struct hns3_adapter *hns = dev->data->dev_private;
1115         struct hns3_hw *hw = &hns->hw;
1116         enum hns3vf_evt_cause event_cause;
1117         uint32_t clearval;
1118
1119         if (hw->irq_thread_id == 0)
1120                 hw->irq_thread_id = pthread_self();
1121
1122         /* Disable interrupt */
1123         hns3vf_disable_irq0(hw);
1124
1125         /* Read out interrupt causes */
1126         event_cause = hns3vf_check_event_cause(hns, &clearval);
1127
1128         switch (event_cause) {
1129         case HNS3VF_VECTOR0_EVENT_RST:
1130                 hns3_schedule_reset(hns);
1131                 break;
1132         case HNS3VF_VECTOR0_EVENT_MBX:
1133                 hns3_dev_handle_mbx_msg(hw);
1134                 break;
1135         default:
1136                 break;
1137         }
1138
1139         /* Clear interrupt causes */
1140         hns3vf_clear_event_cause(hw, clearval);
1141
1142         /* Enable interrupt */
1143         hns3vf_enable_irq0(hw);
1144 }
1145
1146 static void
1147 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1148 {
1149         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1150         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1151         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1152 }
1153
1154 static void
1155 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1156 {
1157         struct hns3_dev_specs_0_cmd *req0;
1158
1159         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1160
1161         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1162         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1163         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1164 }
1165
1166 static int
1167 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1168 {
1169         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1170         int ret;
1171         int i;
1172
1173         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1174                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1175                                           true);
1176                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1177         }
1178         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1179
1180         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1181         if (ret)
1182                 return ret;
1183
1184         hns3vf_parse_dev_specifications(hw, desc);
1185
1186         return 0;
1187 }
1188
1189 static int
1190 hns3vf_get_capability(struct hns3_hw *hw)
1191 {
1192         struct rte_pci_device *pci_dev;
1193         struct rte_eth_dev *eth_dev;
1194         uint8_t revision;
1195         int ret;
1196
1197         eth_dev = &rte_eth_devices[hw->data->port_id];
1198         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1199
1200         /* Get PCI revision id */
1201         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1202                                   HNS3_PCI_REVISION_ID);
1203         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1204                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1205                              ret);
1206                 return -EIO;
1207         }
1208         hw->revision = revision;
1209
1210         if (revision < PCI_REVISION_ID_HIP09_A) {
1211                 hns3vf_set_default_dev_specifications(hw);
1212                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1213                 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
1214                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1215                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1216                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1217                 hw->rss_info.ipv6_sctp_offload_supported = false;
1218                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1219                 return 0;
1220         }
1221
1222         ret = hns3vf_query_dev_specifications(hw);
1223         if (ret) {
1224                 PMD_INIT_LOG(ERR,
1225                              "failed to query dev specifications, ret = %d",
1226                              ret);
1227                 return ret;
1228         }
1229
1230         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1231         hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
1232         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1233         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1234         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1235         hw->rss_info.ipv6_sctp_offload_supported = true;
1236         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1237
1238         return 0;
1239 }
1240
1241 static int
1242 hns3vf_check_tqp_info(struct hns3_hw *hw)
1243 {
1244         if (hw->tqps_num == 0) {
1245                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1246                 return -EINVAL;
1247         }
1248
1249         if (hw->rss_size_max == 0) {
1250                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1251                 return -EINVAL;
1252         }
1253
1254         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1255
1256         return 0;
1257 }
1258
1259 static int
1260 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1261 {
1262         uint8_t resp_msg;
1263         int ret;
1264
1265         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1266                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1267                                 true, &resp_msg, sizeof(resp_msg));
1268         if (ret) {
1269                 if (ret == -ETIME) {
1270                         /*
1271                          * Getting current port based VLAN state from PF driver
1272                          * will not affect VF driver's basic function. Because
1273                          * the VF driver relies on hns3 PF kernel ether driver,
1274                          * to avoid introducing compatibility issues with older
1275                          * version of PF driver, no failure will be returned
1276                          * when the return value is ETIME. This return value has
1277                          * the following scenarios:
1278                          * 1) Firmware didn't return the results in time
1279                          * 2) the result return by firmware is timeout
1280                          * 3) the older version of kernel side PF driver does
1281                          *    not support this mailbox message.
1282                          * For scenarios 1 and 2, it is most likely that a
1283                          * hardware error has occurred, or a hardware reset has
1284                          * occurred. In this case, these errors will be caught
1285                          * by other functions.
1286                          */
1287                         PMD_INIT_LOG(WARNING,
1288                                 "failed to get PVID state for timeout, maybe "
1289                                 "kernel side PF driver doesn't support this "
1290                                 "mailbox message, or firmware didn't respond.");
1291                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1292                 } else {
1293                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1294                                 " ret = %d", ret);
1295                         return ret;
1296                 }
1297         }
1298         hw->port_base_vlan_cfg.state = resp_msg ?
1299                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1300         return 0;
1301 }
1302
1303 static int
1304 hns3vf_get_queue_info(struct hns3_hw *hw)
1305 {
1306 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1307         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1308         int ret;
1309
1310         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1311                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1312         if (ret) {
1313                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1314                 return ret;
1315         }
1316
1317         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1318         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1319
1320         return hns3vf_check_tqp_info(hw);
1321 }
1322
1323 static int
1324 hns3vf_get_queue_depth(struct hns3_hw *hw)
1325 {
1326 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1327         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1328         int ret;
1329
1330         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1331                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1332         if (ret) {
1333                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1334                              ret);
1335                 return ret;
1336         }
1337
1338         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1339         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1340
1341         return 0;
1342 }
1343
1344 static int
1345 hns3vf_get_tc_info(struct hns3_hw *hw)
1346 {
1347         uint8_t resp_msg;
1348         int ret;
1349         int i;
1350
1351         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1352                                 true, &resp_msg, sizeof(resp_msg));
1353         if (ret) {
1354                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1355                          ret);
1356                 return ret;
1357         }
1358
1359         hw->hw_tc_map = resp_msg;
1360
1361         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1362                 if (hw->hw_tc_map & BIT(i))
1363                         hw->num_tc++;
1364         }
1365
1366         return 0;
1367 }
1368
1369 static int
1370 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1371 {
1372         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1373         int ret;
1374
1375         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1376                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1377         if (ret) {
1378                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1379                 return ret;
1380         }
1381
1382         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1383
1384         return 0;
1385 }
1386
1387 static int
1388 hns3vf_get_configuration(struct hns3_hw *hw)
1389 {
1390         int ret;
1391
1392         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1393         hw->rss_dis_flag = false;
1394
1395         /* Get device capability */
1396         ret = hns3vf_get_capability(hw);
1397         if (ret) {
1398                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1399                 return ret;
1400         }
1401
1402         /* Get queue configuration from PF */
1403         ret = hns3vf_get_queue_info(hw);
1404         if (ret)
1405                 return ret;
1406
1407         /* Get queue depth info from PF */
1408         ret = hns3vf_get_queue_depth(hw);
1409         if (ret)
1410                 return ret;
1411
1412         /* Get user defined VF MAC addr from PF */
1413         ret = hns3vf_get_host_mac_addr(hw);
1414         if (ret)
1415                 return ret;
1416
1417         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1418         if (ret)
1419                 return ret;
1420
1421         /* Get tc configuration from PF */
1422         return hns3vf_get_tc_info(hw);
1423 }
1424
1425 static int
1426 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1427                             uint16_t nb_tx_q)
1428 {
1429         struct hns3_hw *hw = &hns->hw;
1430
1431         if (nb_rx_q < hw->num_tc) {
1432                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1433                          nb_rx_q, hw->num_tc);
1434                 return -EINVAL;
1435         }
1436
1437         if (nb_tx_q < hw->num_tc) {
1438                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1439                          nb_tx_q, hw->num_tc);
1440                 return -EINVAL;
1441         }
1442
1443         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1444 }
1445
1446 static void
1447 hns3vf_request_link_info(struct hns3_hw *hw)
1448 {
1449         uint8_t resp_msg;
1450         int ret;
1451
1452         if (rte_atomic16_read(&hw->reset.resetting))
1453                 return;
1454         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1455                                 &resp_msg, sizeof(resp_msg));
1456         if (ret)
1457                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1458 }
1459
1460 static int
1461 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1462 {
1463 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1464         struct hns3_hw *hw = &hns->hw;
1465         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1466         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1467         uint8_t is_kill = on ? 0 : 1;
1468
1469         msg_data[0] = is_kill;
1470         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1471         memcpy(&msg_data[3], &proto, sizeof(proto));
1472
1473         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1474                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1475                                  0);
1476 }
1477
1478 static int
1479 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1480 {
1481         struct hns3_adapter *hns = dev->data->dev_private;
1482         struct hns3_hw *hw = &hns->hw;
1483         int ret;
1484
1485         if (rte_atomic16_read(&hw->reset.resetting)) {
1486                 hns3_err(hw,
1487                          "vf set vlan id failed during resetting, vlan_id =%u",
1488                          vlan_id);
1489                 return -EIO;
1490         }
1491         rte_spinlock_lock(&hw->lock);
1492         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1493         rte_spinlock_unlock(&hw->lock);
1494         if (ret)
1495                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1496                          vlan_id, ret);
1497
1498         return ret;
1499 }
1500
1501 static int
1502 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1503 {
1504         uint8_t msg_data;
1505         int ret;
1506
1507         msg_data = enable ? 1 : 0;
1508         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1509                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1510         if (ret)
1511                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1512
1513         return ret;
1514 }
1515
1516 static int
1517 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1518 {
1519         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1520         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1521         unsigned int tmp_mask;
1522         int ret = 0;
1523
1524         if (rte_atomic16_read(&hw->reset.resetting)) {
1525                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1526                              "mask = 0x%x", mask);
1527                 return -EIO;
1528         }
1529
1530         tmp_mask = (unsigned int)mask;
1531         /* Vlan stripping setting */
1532         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1533                 rte_spinlock_lock(&hw->lock);
1534                 /* Enable or disable VLAN stripping */
1535                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1536                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1537                 else
1538                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1539                 rte_spinlock_unlock(&hw->lock);
1540         }
1541
1542         return ret;
1543 }
1544
1545 static int
1546 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1547 {
1548         struct rte_vlan_filter_conf *vfc;
1549         struct hns3_hw *hw = &hns->hw;
1550         uint16_t vlan_id;
1551         uint64_t vbit;
1552         uint64_t ids;
1553         int ret = 0;
1554         uint32_t i;
1555
1556         vfc = &hw->data->vlan_filter_conf;
1557         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1558                 if (vfc->ids[i] == 0)
1559                         continue;
1560                 ids = vfc->ids[i];
1561                 while (ids) {
1562                         /*
1563                          * 64 means the num bits of ids, one bit corresponds to
1564                          * one vlan id
1565                          */
1566                         vlan_id = 64 * i;
1567                         /* count trailing zeroes */
1568                         vbit = ~ids & (ids - 1);
1569                         /* clear least significant bit set */
1570                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1571                         for (; vbit;) {
1572                                 vbit >>= 1;
1573                                 vlan_id++;
1574                         }
1575                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1576                         if (ret) {
1577                                 hns3_err(hw,
1578                                          "VF handle vlan table failed, ret =%d, on = %d",
1579                                          ret, on);
1580                                 return ret;
1581                         }
1582                 }
1583         }
1584
1585         return ret;
1586 }
1587
1588 static int
1589 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1590 {
1591         return hns3vf_handle_all_vlan_table(hns, 0);
1592 }
1593
1594 static int
1595 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1596 {
1597         struct hns3_hw *hw = &hns->hw;
1598         struct rte_eth_conf *dev_conf;
1599         bool en;
1600         int ret;
1601
1602         dev_conf = &hw->data->dev_conf;
1603         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1604                                                                    : false;
1605         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1606         if (ret)
1607                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1608                          ret);
1609         return ret;
1610 }
1611
1612 static int
1613 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1614 {
1615         struct hns3_adapter *hns = dev->data->dev_private;
1616         struct rte_eth_dev_data *data = dev->data;
1617         struct hns3_hw *hw = &hns->hw;
1618         int ret;
1619
1620         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1621             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1622             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1623                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1624                               "or hw_vlan_insert_pvid is not support!");
1625         }
1626
1627         /* Apply vlan offload setting */
1628         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1629         if (ret)
1630                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1631
1632         return ret;
1633 }
1634
1635 static int
1636 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1637 {
1638         uint8_t msg_data;
1639
1640         msg_data = alive ? 1 : 0;
1641         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1642                                  sizeof(msg_data), false, NULL, 0);
1643 }
1644
1645 static void
1646 hns3vf_keep_alive_handler(void *param)
1647 {
1648         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1649         struct hns3_adapter *hns = eth_dev->data->dev_private;
1650         struct hns3_hw *hw = &hns->hw;
1651         uint8_t respmsg;
1652         int ret;
1653
1654         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1655                                 false, &respmsg, sizeof(uint8_t));
1656         if (ret)
1657                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1658                          ret);
1659
1660         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1661                           eth_dev);
1662 }
1663
1664 static void
1665 hns3vf_service_handler(void *param)
1666 {
1667         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1668         struct hns3_adapter *hns = eth_dev->data->dev_private;
1669         struct hns3_hw *hw = &hns->hw;
1670
1671         /*
1672          * The query link status and reset processing are executed in the
1673          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1674          * and the query operation will time out after 30ms. In the case of
1675          * multiple PF/VFs, each query failure timeout causes the IMP reset
1676          * interrupt to fail to respond within 100ms.
1677          * Before querying the link status, check whether there is a reset
1678          * pending, and if so, abandon the query.
1679          */
1680         if (!hns3vf_is_reset_pending(hns))
1681                 hns3vf_request_link_info(hw);
1682         else
1683                 hns3_warn(hw, "Cancel the query when reset is pending");
1684
1685         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1686                           eth_dev);
1687 }
1688
1689 static int
1690 hns3_query_vf_resource(struct hns3_hw *hw)
1691 {
1692         struct hns3_vf_res_cmd *req;
1693         struct hns3_cmd_desc desc;
1694         uint16_t num_msi;
1695         int ret;
1696
1697         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1698         ret = hns3_cmd_send(hw, &desc, 1);
1699         if (ret) {
1700                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1701                 return ret;
1702         }
1703
1704         req = (struct hns3_vf_res_cmd *)desc.data;
1705         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1706                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1707         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1708                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1709                          num_msi, HNS3_MIN_VECTOR_NUM);
1710                 return -EINVAL;
1711         }
1712
1713         hw->num_msi = num_msi;
1714
1715         return 0;
1716 }
1717
1718 static int
1719 hns3vf_init_hardware(struct hns3_adapter *hns)
1720 {
1721         struct hns3_hw *hw = &hns->hw;
1722         uint16_t mtu = hw->data->mtu;
1723         int ret;
1724
1725         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1726         if (ret)
1727                 return ret;
1728
1729         ret = hns3vf_config_mtu(hw, mtu);
1730         if (ret)
1731                 goto err_init_hardware;
1732
1733         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1734         if (ret) {
1735                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1736                 goto err_init_hardware;
1737         }
1738
1739         ret = hns3_config_gro(hw, false);
1740         if (ret) {
1741                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1742                 goto err_init_hardware;
1743         }
1744
1745         /*
1746          * In the initialization clearing the all hardware mapping relationship
1747          * configurations between queues and interrupt vectors is needed, so
1748          * some error caused by the residual configurations, such as the
1749          * unexpected interrupt, can be avoid.
1750          */
1751         ret = hns3vf_init_ring_with_vector(hw);
1752         if (ret) {
1753                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1754                 goto err_init_hardware;
1755         }
1756
1757         ret = hns3vf_set_alive(hw, true);
1758         if (ret) {
1759                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1760                 goto err_init_hardware;
1761         }
1762
1763         hns3vf_request_link_info(hw);
1764         return 0;
1765
1766 err_init_hardware:
1767         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1768         return ret;
1769 }
1770
1771 static int
1772 hns3vf_clear_vport_list(struct hns3_hw *hw)
1773 {
1774         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1775                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1776                                  NULL, 0);
1777 }
1778
1779 static int
1780 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1781 {
1782         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1783         struct hns3_adapter *hns = eth_dev->data->dev_private;
1784         struct hns3_hw *hw = &hns->hw;
1785         int ret;
1786
1787         PMD_INIT_FUNC_TRACE();
1788
1789         /* Get hardware io base address from pcie BAR2 IO space */
1790         hw->io_base = pci_dev->mem_resource[2].addr;
1791
1792         /* Firmware command queue initialize */
1793         ret = hns3_cmd_init_queue(hw);
1794         if (ret) {
1795                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1796                 goto err_cmd_init_queue;
1797         }
1798
1799         /* Firmware command initialize */
1800         ret = hns3_cmd_init(hw);
1801         if (ret) {
1802                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1803                 goto err_cmd_init;
1804         }
1805
1806         /* Get VF resource */
1807         ret = hns3_query_vf_resource(hw);
1808         if (ret)
1809                 goto err_cmd_init;
1810
1811         rte_spinlock_init(&hw->mbx_resp.lock);
1812
1813         hns3vf_clear_event_cause(hw, 0);
1814
1815         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1816                                          hns3vf_interrupt_handler, eth_dev);
1817         if (ret) {
1818                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1819                 goto err_intr_callback_register;
1820         }
1821
1822         /* Enable interrupt */
1823         rte_intr_enable(&pci_dev->intr_handle);
1824         hns3vf_enable_irq0(hw);
1825
1826         /* Get configuration from PF */
1827         ret = hns3vf_get_configuration(hw);
1828         if (ret) {
1829                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1830                 goto err_get_config;
1831         }
1832
1833         ret = hns3_tqp_stats_init(hw);
1834         if (ret)
1835                 goto err_get_config;
1836
1837         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1838         if (ret) {
1839                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1840                 goto err_set_tc_queue;
1841         }
1842
1843         ret = hns3vf_clear_vport_list(hw);
1844         if (ret) {
1845                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1846                 goto err_set_tc_queue;
1847         }
1848
1849         ret = hns3vf_init_hardware(hns);
1850         if (ret)
1851                 goto err_set_tc_queue;
1852
1853         hns3_set_default_rss_args(hw);
1854
1855         return 0;
1856
1857 err_set_tc_queue:
1858         hns3_tqp_stats_uninit(hw);
1859
1860 err_get_config:
1861         hns3vf_disable_irq0(hw);
1862         rte_intr_disable(&pci_dev->intr_handle);
1863         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1864                              eth_dev);
1865 err_intr_callback_register:
1866 err_cmd_init:
1867         hns3_cmd_uninit(hw);
1868         hns3_cmd_destroy_queue(hw);
1869 err_cmd_init_queue:
1870         hw->io_base = NULL;
1871
1872         return ret;
1873 }
1874
1875 static void
1876 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1877 {
1878         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1879         struct hns3_adapter *hns = eth_dev->data->dev_private;
1880         struct hns3_hw *hw = &hns->hw;
1881
1882         PMD_INIT_FUNC_TRACE();
1883
1884         hns3_rss_uninit(hns);
1885         (void)hns3_config_gro(hw, false);
1886         (void)hns3vf_set_alive(hw, false);
1887         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1888         hns3_tqp_stats_uninit(hw);
1889         hns3vf_disable_irq0(hw);
1890         rte_intr_disable(&pci_dev->intr_handle);
1891         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1892                              eth_dev);
1893         hns3_cmd_uninit(hw);
1894         hns3_cmd_destroy_queue(hw);
1895         hw->io_base = NULL;
1896 }
1897
1898 static int
1899 hns3vf_do_stop(struct hns3_adapter *hns)
1900 {
1901         struct hns3_hw *hw = &hns->hw;
1902         int ret;
1903
1904         hw->mac.link_status = ETH_LINK_DOWN;
1905
1906         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1907                 hns3vf_configure_mac_addr(hns, true);
1908                 ret = hns3_reset_all_tqps(hns);
1909                 if (ret) {
1910                         hns3_err(hw, "failed to reset all queues ret = %d",
1911                                  ret);
1912                         return ret;
1913                 }
1914         }
1915         return 0;
1916 }
1917
1918 static void
1919 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1920 {
1921         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1923         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1924         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1925         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1926         uint16_t q_id;
1927
1928         if (dev->data->dev_conf.intr_conf.rxq == 0)
1929                 return;
1930
1931         /* unmap the ring with vector */
1932         if (rte_intr_allow_others(intr_handle)) {
1933                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1934                 base = RTE_INTR_VEC_RXTX_OFFSET;
1935         }
1936         if (rte_intr_dp_is_en(intr_handle)) {
1937                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1938                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1939                                                            HNS3_RING_TYPE_RX,
1940                                                            q_id);
1941                         if (vec < base + intr_handle->nb_efd - 1)
1942                                 vec++;
1943                 }
1944         }
1945         /* Clean datapath event and queue/vec mapping */
1946         rte_intr_efd_disable(intr_handle);
1947         if (intr_handle->intr_vec) {
1948                 rte_free(intr_handle->intr_vec);
1949                 intr_handle->intr_vec = NULL;
1950         }
1951 }
1952
1953 static int
1954 hns3vf_dev_stop(struct rte_eth_dev *dev)
1955 {
1956         struct hns3_adapter *hns = dev->data->dev_private;
1957         struct hns3_hw *hw = &hns->hw;
1958
1959         PMD_INIT_FUNC_TRACE();
1960         dev->data->dev_started = 0;
1961
1962         hw->adapter_state = HNS3_NIC_STOPPING;
1963         hns3_set_rxtx_function(dev);
1964         rte_wmb();
1965         /* Disable datapath on secondary process. */
1966         hns3_mp_req_stop_rxtx(dev);
1967         /* Prevent crashes when queues are still in use. */
1968         rte_delay_ms(hw->tqps_num);
1969
1970         rte_spinlock_lock(&hw->lock);
1971         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1972                 hns3_stop_tqps(hw);
1973                 hns3vf_do_stop(hns);
1974                 hns3vf_unmap_rx_interrupt(dev);
1975                 hns3_dev_release_mbufs(hns);
1976                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1977         }
1978         hns3_rx_scattered_reset(dev);
1979         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1980         rte_spinlock_unlock(&hw->lock);
1981
1982         return 0;
1983 }
1984
1985 static int
1986 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1987 {
1988         struct hns3_adapter *hns = eth_dev->data->dev_private;
1989         struct hns3_hw *hw = &hns->hw;
1990         int ret = 0;
1991
1992         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1993                 return 0;
1994
1995         if (hw->adapter_state == HNS3_NIC_STARTED)
1996                 ret = hns3vf_dev_stop(eth_dev);
1997
1998         hw->adapter_state = HNS3_NIC_CLOSING;
1999         hns3_reset_abort(hns);
2000         hw->adapter_state = HNS3_NIC_CLOSED;
2001         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
2002         hns3vf_configure_all_mc_mac_addr(hns, true);
2003         hns3vf_remove_all_vlan_table(hns);
2004         hns3vf_uninit_vf(eth_dev);
2005         hns3_free_all_queues(eth_dev);
2006         rte_free(hw->reset.wait_data);
2007         rte_free(eth_dev->process_private);
2008         eth_dev->process_private = NULL;
2009         hns3_mp_uninit_primary();
2010         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
2011
2012         return ret;
2013 }
2014
2015 static int
2016 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2017                       size_t fw_size)
2018 {
2019         struct hns3_adapter *hns = eth_dev->data->dev_private;
2020         struct hns3_hw *hw = &hns->hw;
2021         uint32_t version = hw->fw_version;
2022         int ret;
2023
2024         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2025                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2026                                       HNS3_FW_VERSION_BYTE3_S),
2027                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2028                                       HNS3_FW_VERSION_BYTE2_S),
2029                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2030                                       HNS3_FW_VERSION_BYTE1_S),
2031                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2032                                       HNS3_FW_VERSION_BYTE0_S));
2033         ret += 1; /* add the size of '\0' */
2034         if (fw_size < (uint32_t)ret)
2035                 return ret;
2036         else
2037                 return 0;
2038 }
2039
2040 static int
2041 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2042                        __rte_unused int wait_to_complete)
2043 {
2044         struct hns3_adapter *hns = eth_dev->data->dev_private;
2045         struct hns3_hw *hw = &hns->hw;
2046         struct hns3_mac *mac = &hw->mac;
2047         struct rte_eth_link new_link;
2048
2049         memset(&new_link, 0, sizeof(new_link));
2050         switch (mac->link_speed) {
2051         case ETH_SPEED_NUM_10M:
2052         case ETH_SPEED_NUM_100M:
2053         case ETH_SPEED_NUM_1G:
2054         case ETH_SPEED_NUM_10G:
2055         case ETH_SPEED_NUM_25G:
2056         case ETH_SPEED_NUM_40G:
2057         case ETH_SPEED_NUM_50G:
2058         case ETH_SPEED_NUM_100G:
2059         case ETH_SPEED_NUM_200G:
2060                 new_link.link_speed = mac->link_speed;
2061                 break;
2062         default:
2063                 new_link.link_speed = ETH_SPEED_NUM_100M;
2064                 break;
2065         }
2066
2067         new_link.link_duplex = mac->link_duplex;
2068         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2069         new_link.link_autoneg =
2070             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2071
2072         return rte_eth_linkstatus_set(eth_dev, &new_link);
2073 }
2074
2075 static int
2076 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2077 {
2078         struct hns3_hw *hw = &hns->hw;
2079         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2080         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2081         int ret;
2082
2083         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2084         if (ret)
2085                 return ret;
2086
2087         ret = hns3_init_queues(hns, reset_queue);
2088         if (ret)
2089                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2090
2091         return ret;
2092 }
2093
2094 static int
2095 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2096 {
2097         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2098         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2099         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2101         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2102         uint32_t intr_vector;
2103         uint16_t q_id;
2104         int ret;
2105
2106         if (dev->data->dev_conf.intr_conf.rxq == 0)
2107                 return 0;
2108
2109         /* disable uio/vfio intr/eventfd mapping */
2110         rte_intr_disable(intr_handle);
2111
2112         /* check and configure queue intr-vector mapping */
2113         if (rte_intr_cap_multiple(intr_handle) ||
2114             !RTE_ETH_DEV_SRIOV(dev).active) {
2115                 intr_vector = hw->used_rx_queues;
2116                 /* It creates event fd for each intr vector when MSIX is used */
2117                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2118                         return -EINVAL;
2119         }
2120         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2121                 intr_handle->intr_vec =
2122                         rte_zmalloc("intr_vec",
2123                                     hw->used_rx_queues * sizeof(int), 0);
2124                 if (intr_handle->intr_vec == NULL) {
2125                         hns3_err(hw, "Failed to allocate %d rx_queues"
2126                                      " intr_vec", hw->used_rx_queues);
2127                         ret = -ENOMEM;
2128                         goto vf_alloc_intr_vec_error;
2129                 }
2130         }
2131
2132         if (rte_intr_allow_others(intr_handle)) {
2133                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2134                 base = RTE_INTR_VEC_RXTX_OFFSET;
2135         }
2136         if (rte_intr_dp_is_en(intr_handle)) {
2137                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2138                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2139                                                            HNS3_RING_TYPE_RX,
2140                                                            q_id);
2141                         if (ret)
2142                                 goto vf_bind_vector_error;
2143                         intr_handle->intr_vec[q_id] = vec;
2144                         if (vec < base + intr_handle->nb_efd - 1)
2145                                 vec++;
2146                 }
2147         }
2148         rte_intr_enable(intr_handle);
2149         return 0;
2150
2151 vf_bind_vector_error:
2152         rte_intr_efd_disable(intr_handle);
2153         if (intr_handle->intr_vec) {
2154                 free(intr_handle->intr_vec);
2155                 intr_handle->intr_vec = NULL;
2156         }
2157         return ret;
2158 vf_alloc_intr_vec_error:
2159         rte_intr_efd_disable(intr_handle);
2160         return ret;
2161 }
2162
2163 static int
2164 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2165 {
2166         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2167         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2168         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2169         uint16_t q_id;
2170         int ret;
2171
2172         if (dev->data->dev_conf.intr_conf.rxq == 0)
2173                 return 0;
2174
2175         if (rte_intr_dp_is_en(intr_handle)) {
2176                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2177                         ret = hns3vf_bind_ring_with_vector(hw,
2178                                         intr_handle->intr_vec[q_id], true,
2179                                         HNS3_RING_TYPE_RX, q_id);
2180                         if (ret)
2181                                 return ret;
2182                 }
2183         }
2184
2185         return 0;
2186 }
2187
2188 static void
2189 hns3vf_restore_filter(struct rte_eth_dev *dev)
2190 {
2191         hns3_restore_rss_filter(dev);
2192 }
2193
2194 static int
2195 hns3vf_dev_start(struct rte_eth_dev *dev)
2196 {
2197         struct hns3_adapter *hns = dev->data->dev_private;
2198         struct hns3_hw *hw = &hns->hw;
2199         int ret;
2200
2201         PMD_INIT_FUNC_TRACE();
2202         if (rte_atomic16_read(&hw->reset.resetting))
2203                 return -EBUSY;
2204
2205         rte_spinlock_lock(&hw->lock);
2206         hw->adapter_state = HNS3_NIC_STARTING;
2207         ret = hns3vf_do_start(hns, true);
2208         if (ret) {
2209                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2210                 rte_spinlock_unlock(&hw->lock);
2211                 return ret;
2212         }
2213         ret = hns3vf_map_rx_interrupt(dev);
2214         if (ret) {
2215                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2216                 rte_spinlock_unlock(&hw->lock);
2217                 return ret;
2218         }
2219
2220         /*
2221          * There are three register used to control the status of a TQP
2222          * (contains a pair of Tx queue and Rx queue) in the new version network
2223          * engine. One is used to control the enabling of Tx queue, the other is
2224          * used to control the enabling of Rx queue, and the last is the master
2225          * switch used to control the enabling of the tqp. The Tx register and
2226          * TQP register must be enabled at the same time to enable a Tx queue.
2227          * The same applies to the Rx queue. For the older network enginem, this
2228          * function only refresh the enabled flag, and it is used to update the
2229          * status of queue in the dpdk framework.
2230          */
2231         ret = hns3_start_all_txqs(dev);
2232         if (ret) {
2233                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2234                 rte_spinlock_unlock(&hw->lock);
2235                 return ret;
2236         }
2237
2238         ret = hns3_start_all_rxqs(dev);
2239         if (ret) {
2240                 hns3_stop_all_txqs(dev);
2241                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2242                 rte_spinlock_unlock(&hw->lock);
2243                 return ret;
2244         }
2245
2246         hw->adapter_state = HNS3_NIC_STARTED;
2247         rte_spinlock_unlock(&hw->lock);
2248
2249         hns3_rx_scattered_calc(dev);
2250         hns3_set_rxtx_function(dev);
2251         hns3_mp_req_start_rxtx(dev);
2252         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2253
2254         hns3vf_restore_filter(dev);
2255
2256         /* Enable interrupt of all rx queues before enabling queues */
2257         hns3_dev_all_rx_queue_intr_enable(hw, true);
2258
2259         /*
2260          * After finished the initialization, start all tqps to receive/transmit
2261          * packets and refresh all queue status.
2262          */
2263         hns3_start_tqps(hw);
2264
2265         return ret;
2266 }
2267
2268 static bool
2269 is_vf_reset_done(struct hns3_hw *hw)
2270 {
2271 #define HNS3_FUN_RST_ING_BITS \
2272         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2273          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2274          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2275          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2276
2277         uint32_t val;
2278
2279         if (hw->reset.level == HNS3_VF_RESET) {
2280                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2281                 if (val & HNS3_VF_RST_ING_BIT)
2282                         return false;
2283         } else {
2284                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2285                 if (val & HNS3_FUN_RST_ING_BITS)
2286                         return false;
2287         }
2288         return true;
2289 }
2290
2291 bool
2292 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2293 {
2294         struct hns3_hw *hw = &hns->hw;
2295         enum hns3_reset_level reset;
2296
2297         /*
2298          * According to the protocol of PCIe, FLR to a PF device resets the PF
2299          * state as well as the SR-IOV extended capability including VF Enable
2300          * which means that VFs no longer exist.
2301          *
2302          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2303          * is in FLR stage, the register state of VF device is not reliable,
2304          * so register states detection can not be carried out. In this case,
2305          * we just ignore the register states and return false to indicate that
2306          * there are no other reset states that need to be processed by driver.
2307          */
2308         if (hw->reset.level == HNS3_VF_FULL_RESET)
2309                 return false;
2310
2311         /* Check the registers to confirm whether there is reset pending */
2312         hns3vf_check_event_cause(hns, NULL);
2313         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2314         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2315                 hns3_warn(hw, "High level reset %d is pending", reset);
2316                 return true;
2317         }
2318         return false;
2319 }
2320
2321 static int
2322 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2323 {
2324         struct hns3_hw *hw = &hns->hw;
2325         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2326         struct timeval tv;
2327
2328         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2329                 /*
2330                  * After vf reset is ready, the PF may not have completed
2331                  * the reset processing. The vf sending mbox to PF may fail
2332                  * during the pf reset, so it is better to add extra delay.
2333                  */
2334                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2335                     hw->reset.level == HNS3_FLR_RESET)
2336                         return 0;
2337                 /* Reset retry process, no need to add extra delay. */
2338                 if (hw->reset.attempts)
2339                         return 0;
2340                 if (wait_data->check_completion == NULL)
2341                         return 0;
2342
2343                 wait_data->check_completion = NULL;
2344                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2345                 wait_data->count = 1;
2346                 wait_data->result = HNS3_WAIT_REQUEST;
2347                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2348                                   wait_data);
2349                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2350                 return -EAGAIN;
2351         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2352                 gettimeofday(&tv, NULL);
2353                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2354                           tv.tv_sec, tv.tv_usec);
2355                 return -ETIME;
2356         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2357                 return -EAGAIN;
2358
2359         wait_data->hns = hns;
2360         wait_data->check_completion = is_vf_reset_done;
2361         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2362                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2363         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2364         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2365         wait_data->result = HNS3_WAIT_REQUEST;
2366         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2367         return -EAGAIN;
2368 }
2369
2370 static int
2371 hns3vf_prepare_reset(struct hns3_adapter *hns)
2372 {
2373         struct hns3_hw *hw = &hns->hw;
2374         int ret = 0;
2375
2376         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2377                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2378                                         0, true, NULL, 0);
2379         }
2380         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2381
2382         return ret;
2383 }
2384
2385 static int
2386 hns3vf_stop_service(struct hns3_adapter *hns)
2387 {
2388         struct hns3_hw *hw = &hns->hw;
2389         struct rte_eth_dev *eth_dev;
2390
2391         eth_dev = &rte_eth_devices[hw->data->port_id];
2392         if (hw->adapter_state == HNS3_NIC_STARTED)
2393                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2394         hw->mac.link_status = ETH_LINK_DOWN;
2395
2396         hns3_set_rxtx_function(eth_dev);
2397         rte_wmb();
2398         /* Disable datapath on secondary process. */
2399         hns3_mp_req_stop_rxtx(eth_dev);
2400         rte_delay_ms(hw->tqps_num);
2401
2402         rte_spinlock_lock(&hw->lock);
2403         if (hw->adapter_state == HNS3_NIC_STARTED ||
2404             hw->adapter_state == HNS3_NIC_STOPPING) {
2405                 hns3_enable_all_queues(hw, false);
2406                 hns3vf_do_stop(hns);
2407                 hw->reset.mbuf_deferred_free = true;
2408         } else
2409                 hw->reset.mbuf_deferred_free = false;
2410
2411         /*
2412          * It is cumbersome for hardware to pick-and-choose entries for deletion
2413          * from table space. Hence, for function reset software intervention is
2414          * required to delete the entries.
2415          */
2416         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2417                 hns3vf_configure_all_mc_mac_addr(hns, true);
2418         rte_spinlock_unlock(&hw->lock);
2419
2420         return 0;
2421 }
2422
2423 static int
2424 hns3vf_start_service(struct hns3_adapter *hns)
2425 {
2426         struct hns3_hw *hw = &hns->hw;
2427         struct rte_eth_dev *eth_dev;
2428
2429         eth_dev = &rte_eth_devices[hw->data->port_id];
2430         hns3_set_rxtx_function(eth_dev);
2431         hns3_mp_req_start_rxtx(eth_dev);
2432         if (hw->adapter_state == HNS3_NIC_STARTED) {
2433                 hns3vf_service_handler(eth_dev);
2434
2435                 /* Enable interrupt of all rx queues before enabling queues */
2436                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2437                 /*
2438                  * When finished the initialization, enable queues to receive
2439                  * and transmit packets.
2440                  */
2441                 hns3_enable_all_queues(hw, true);
2442         }
2443
2444         return 0;
2445 }
2446
2447 static int
2448 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2449 {
2450         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2451         struct rte_ether_addr *hw_mac;
2452         int ret;
2453
2454         /*
2455          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2456          * on the host by "ip link set ..." command. If the hns3 PF kernel
2457          * ethdev driver sets the MAC address for VF device after the
2458          * initialization of the related VF device, the PF driver will notify
2459          * VF driver to reset VF device to make the new MAC address effective
2460          * immediately. The hns3 VF PMD driver should check whether the MAC
2461          * address has been changed by the PF kernel ethdev driver, if changed
2462          * VF driver should configure hardware using the new MAC address in the
2463          * recovering hardware configuration stage of the reset process.
2464          */
2465         ret = hns3vf_get_host_mac_addr(hw);
2466         if (ret)
2467                 return ret;
2468
2469         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2470         ret = rte_is_zero_ether_addr(hw_mac);
2471         if (ret) {
2472                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2473         } else {
2474                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2475                 if (!ret) {
2476                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2477                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2478                                               &hw->data->mac_addrs[0]);
2479                         hns3_warn(hw, "Default MAC address has been changed to:"
2480                                   " %s by the host PF kernel ethdev driver",
2481                                   mac_str);
2482                 }
2483         }
2484
2485         return 0;
2486 }
2487
2488 static int
2489 hns3vf_restore_conf(struct hns3_adapter *hns)
2490 {
2491         struct hns3_hw *hw = &hns->hw;
2492         int ret;
2493
2494         ret = hns3vf_check_default_mac_change(hw);
2495         if (ret)
2496                 return ret;
2497
2498         ret = hns3vf_configure_mac_addr(hns, false);
2499         if (ret)
2500                 return ret;
2501
2502         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2503         if (ret)
2504                 goto err_mc_mac;
2505
2506         ret = hns3vf_restore_promisc(hns);
2507         if (ret)
2508                 goto err_vlan_table;
2509
2510         ret = hns3vf_restore_vlan_conf(hns);
2511         if (ret)
2512                 goto err_vlan_table;
2513
2514         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2515         if (ret)
2516                 goto err_vlan_table;
2517
2518         ret = hns3vf_restore_rx_interrupt(hw);
2519         if (ret)
2520                 goto err_vlan_table;
2521
2522         ret = hns3_restore_gro_conf(hw);
2523         if (ret)
2524                 goto err_vlan_table;
2525
2526         if (hw->adapter_state == HNS3_NIC_STARTED) {
2527                 ret = hns3vf_do_start(hns, false);
2528                 if (ret)
2529                         goto err_vlan_table;
2530                 hns3_info(hw, "hns3vf dev restart successful!");
2531         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2532                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2533         return 0;
2534
2535 err_vlan_table:
2536         hns3vf_configure_all_mc_mac_addr(hns, true);
2537 err_mc_mac:
2538         hns3vf_configure_mac_addr(hns, true);
2539         return ret;
2540 }
2541
2542 static enum hns3_reset_level
2543 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2544 {
2545         enum hns3_reset_level reset_level;
2546
2547         /* return the highest priority reset level amongst all */
2548         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2549                 reset_level = HNS3_VF_RESET;
2550         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2551                 reset_level = HNS3_VF_FULL_RESET;
2552         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2553                 reset_level = HNS3_VF_PF_FUNC_RESET;
2554         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2555                 reset_level = HNS3_VF_FUNC_RESET;
2556         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2557                 reset_level = HNS3_FLR_RESET;
2558         else
2559                 reset_level = HNS3_NONE_RESET;
2560
2561         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2562                 return HNS3_NONE_RESET;
2563
2564         return reset_level;
2565 }
2566
2567 static void
2568 hns3vf_reset_service(void *param)
2569 {
2570         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2571         struct hns3_hw *hw = &hns->hw;
2572         enum hns3_reset_level reset_level;
2573         struct timeval tv_delta;
2574         struct timeval tv_start;
2575         struct timeval tv;
2576         uint64_t msec;
2577
2578         /*
2579          * The interrupt is not triggered within the delay time.
2580          * The interrupt may have been lost. It is necessary to handle
2581          * the interrupt to recover from the error.
2582          */
2583         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2584                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2585                 hns3_err(hw, "Handling interrupts in delayed tasks");
2586                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2587                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2588                 if (reset_level == HNS3_NONE_RESET) {
2589                         hns3_err(hw, "No reset level is set, try global reset");
2590                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2591                 }
2592         }
2593         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2594
2595         /*
2596          * Hardware reset has been notified, we now have to poll & check if
2597          * hardware has actually completed the reset sequence.
2598          */
2599         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2600         if (reset_level != HNS3_NONE_RESET) {
2601                 gettimeofday(&tv_start, NULL);
2602                 hns3_reset_process(hns, reset_level);
2603                 gettimeofday(&tv, NULL);
2604                 timersub(&tv, &tv_start, &tv_delta);
2605                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2606                        tv_delta.tv_usec / USEC_PER_MSEC;
2607                 if (msec > HNS3_RESET_PROCESS_MS)
2608                         hns3_err(hw, "%d handle long time delta %" PRIx64
2609                                  " ms time=%ld.%.6ld",
2610                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2611         }
2612 }
2613
2614 static int
2615 hns3vf_reinit_dev(struct hns3_adapter *hns)
2616 {
2617         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2618         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2619         struct hns3_hw *hw = &hns->hw;
2620         int ret;
2621
2622         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2623                 rte_intr_disable(&pci_dev->intr_handle);
2624                 ret = hns3vf_set_bus_master(pci_dev, true);
2625                 if (ret < 0) {
2626                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2627                         return ret;
2628                 }
2629         }
2630
2631         /* Firmware command initialize */
2632         ret = hns3_cmd_init(hw);
2633         if (ret) {
2634                 hns3_err(hw, "Failed to init cmd: %d", ret);
2635                 return ret;
2636         }
2637
2638         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2639                 /*
2640                  * UIO enables msix by writing the pcie configuration space
2641                  * vfio_pci enables msix in rte_intr_enable.
2642                  */
2643                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2644                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2645                         if (hns3vf_enable_msix(pci_dev, true))
2646                                 hns3_err(hw, "Failed to enable msix");
2647                 }
2648
2649                 rte_intr_enable(&pci_dev->intr_handle);
2650         }
2651
2652         ret = hns3_reset_all_tqps(hns);
2653         if (ret) {
2654                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2655                 return ret;
2656         }
2657
2658         ret = hns3vf_init_hardware(hns);
2659         if (ret) {
2660                 hns3_err(hw, "Failed to init hardware: %d", ret);
2661                 return ret;
2662         }
2663
2664         return 0;
2665 }
2666
2667 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2668         .dev_configure      = hns3vf_dev_configure,
2669         .dev_start          = hns3vf_dev_start,
2670         .dev_stop           = hns3vf_dev_stop,
2671         .dev_close          = hns3vf_dev_close,
2672         .mtu_set            = hns3vf_dev_mtu_set,
2673         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2674         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2675         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2676         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2677         .stats_get          = hns3_stats_get,
2678         .stats_reset        = hns3_stats_reset,
2679         .xstats_get         = hns3_dev_xstats_get,
2680         .xstats_get_names   = hns3_dev_xstats_get_names,
2681         .xstats_reset       = hns3_dev_xstats_reset,
2682         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2683         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2684         .dev_infos_get      = hns3vf_dev_infos_get,
2685         .fw_version_get     = hns3vf_fw_version_get,
2686         .rx_queue_setup     = hns3_rx_queue_setup,
2687         .tx_queue_setup     = hns3_tx_queue_setup,
2688         .rx_queue_release   = hns3_dev_rx_queue_release,
2689         .tx_queue_release   = hns3_dev_tx_queue_release,
2690         .rx_queue_start     = hns3_dev_rx_queue_start,
2691         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2692         .tx_queue_start     = hns3_dev_tx_queue_start,
2693         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2694         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2695         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2696         .rxq_info_get       = hns3_rxq_info_get,
2697         .txq_info_get       = hns3_txq_info_get,
2698         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2699         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2700         .mac_addr_add       = hns3vf_add_mac_addr,
2701         .mac_addr_remove    = hns3vf_remove_mac_addr,
2702         .mac_addr_set       = hns3vf_set_default_mac_addr,
2703         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2704         .link_update        = hns3vf_dev_link_update,
2705         .rss_hash_update    = hns3_dev_rss_hash_update,
2706         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2707         .reta_update        = hns3_dev_rss_reta_update,
2708         .reta_query         = hns3_dev_rss_reta_query,
2709         .filter_ctrl        = hns3_dev_filter_ctrl,
2710         .vlan_filter_set    = hns3vf_vlan_filter_set,
2711         .vlan_offload_set   = hns3vf_vlan_offload_set,
2712         .get_reg            = hns3_get_regs,
2713         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2714 };
2715
2716 static const struct hns3_reset_ops hns3vf_reset_ops = {
2717         .reset_service       = hns3vf_reset_service,
2718         .stop_service        = hns3vf_stop_service,
2719         .prepare_reset       = hns3vf_prepare_reset,
2720         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2721         .reinit_dev          = hns3vf_reinit_dev,
2722         .restore_conf        = hns3vf_restore_conf,
2723         .start_service       = hns3vf_start_service,
2724 };
2725
2726 static int
2727 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2728 {
2729         struct hns3_adapter *hns = eth_dev->data->dev_private;
2730         struct hns3_hw *hw = &hns->hw;
2731         int ret;
2732
2733         PMD_INIT_FUNC_TRACE();
2734
2735         eth_dev->process_private = (struct hns3_process_private *)
2736             rte_zmalloc_socket("hns3_filter_list",
2737                                sizeof(struct hns3_process_private),
2738                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2739         if (eth_dev->process_private == NULL) {
2740                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2741                 return -ENOMEM;
2742         }
2743
2744         /* initialize flow filter lists */
2745         hns3_filterlist_init(eth_dev);
2746
2747         hns3_set_rxtx_function(eth_dev);
2748         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2749         eth_dev->rx_queue_count = hns3_rx_queue_count;
2750         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2751                 ret = hns3_mp_init_secondary();
2752                 if (ret) {
2753                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2754                                           "process, ret = %d", ret);
2755                         goto err_mp_init_secondary;
2756                 }
2757
2758                 hw->secondary_cnt++;
2759                 return 0;
2760         }
2761
2762         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2763
2764         ret = hns3_mp_init_primary();
2765         if (ret) {
2766                 PMD_INIT_LOG(ERR,
2767                              "Failed to init for primary process, ret = %d",
2768                              ret);
2769                 goto err_mp_init_primary;
2770         }
2771
2772         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2773         hns->is_vf = true;
2774         hw->data = eth_dev->data;
2775
2776         ret = hns3_reset_init(hw);
2777         if (ret)
2778                 goto err_init_reset;
2779         hw->reset.ops = &hns3vf_reset_ops;
2780
2781         ret = hns3vf_init_vf(eth_dev);
2782         if (ret) {
2783                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2784                 goto err_init_vf;
2785         }
2786
2787         /* Allocate memory for storing MAC addresses */
2788         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2789                                                sizeof(struct rte_ether_addr) *
2790                                                HNS3_VF_UC_MACADDR_NUM, 0);
2791         if (eth_dev->data->mac_addrs == NULL) {
2792                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2793                              "to store MAC addresses",
2794                              sizeof(struct rte_ether_addr) *
2795                              HNS3_VF_UC_MACADDR_NUM);
2796                 ret = -ENOMEM;
2797                 goto err_rte_zmalloc;
2798         }
2799
2800         /*
2801          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2802          * on the host by "ip link set ..." command. To avoid some incorrect
2803          * scenes, for example, hns3 VF PMD driver fails to receive and send
2804          * packets after user configure the MAC address by using the
2805          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2806          * address strategy as the hns3 kernel ethdev driver in the
2807          * initialization. If user configure a MAC address by the ip command
2808          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2809          * start with a random MAC address in the initialization.
2810          */
2811         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2812                 rte_eth_random_addr(hw->mac.mac_addr);
2813         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2814                             &eth_dev->data->mac_addrs[0]);
2815
2816         hw->adapter_state = HNS3_NIC_INITIALIZED;
2817
2818         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2819                 hns3_err(hw, "Reschedule reset service after dev_init");
2820                 hns3_schedule_reset(hns);
2821         } else {
2822                 /* IMP will wait ready flag before reset */
2823                 hns3_notify_reset_ready(hw, false);
2824         }
2825         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2826                           eth_dev);
2827         return 0;
2828
2829 err_rte_zmalloc:
2830         hns3vf_uninit_vf(eth_dev);
2831
2832 err_init_vf:
2833         rte_free(hw->reset.wait_data);
2834
2835 err_init_reset:
2836         hns3_mp_uninit_primary();
2837
2838 err_mp_init_primary:
2839 err_mp_init_secondary:
2840         eth_dev->dev_ops = NULL;
2841         eth_dev->rx_pkt_burst = NULL;
2842         eth_dev->tx_pkt_burst = NULL;
2843         eth_dev->tx_pkt_prepare = NULL;
2844         rte_free(eth_dev->process_private);
2845         eth_dev->process_private = NULL;
2846
2847         return ret;
2848 }
2849
2850 static int
2851 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2852 {
2853         struct hns3_adapter *hns = eth_dev->data->dev_private;
2854         struct hns3_hw *hw = &hns->hw;
2855
2856         PMD_INIT_FUNC_TRACE();
2857
2858         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2859                 return -EPERM;
2860
2861         if (hw->adapter_state < HNS3_NIC_CLOSING)
2862                 hns3vf_dev_close(eth_dev);
2863
2864         hw->adapter_state = HNS3_NIC_REMOVED;
2865         return 0;
2866 }
2867
2868 static int
2869 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2870                      struct rte_pci_device *pci_dev)
2871 {
2872         return rte_eth_dev_pci_generic_probe(pci_dev,
2873                                              sizeof(struct hns3_adapter),
2874                                              hns3vf_dev_init);
2875 }
2876
2877 static int
2878 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2879 {
2880         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2881 }
2882
2883 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2884         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2885         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2886         { .vendor_id = 0, /* sentinel */ },
2887 };
2888
2889 static struct rte_pci_driver rte_hns3vf_pmd = {
2890         .id_table = pci_id_hns3vf_map,
2891         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2892         .probe = eth_hns3vf_pci_probe,
2893         .remove = eth_hns3vf_pci_remove,
2894 };
2895
2896 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2897 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2898 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");