1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #include <linux/pci_regs.h>
7 #include <ethdev_pci.h>
12 #include "hns3_ethdev.h"
13 #include "hns3_logs.h"
14 #include "hns3_rxtx.h"
15 #include "hns3_regs.h"
16 #include "hns3_intr.h"
20 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */
21 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */
23 #define HNS3VF_RESET_WAIT_MS 20
24 #define HNS3VF_RESET_WAIT_CNT 2000
26 /* Reset related Registers */
27 #define HNS3_GLOBAL_RESET_BIT 0
28 #define HNS3_CORE_RESET_BIT 1
29 #define HNS3_IMP_RESET_BIT 2
30 #define HNS3_FUN_RST_ING_B 0
32 enum hns3vf_evt_cause {
33 HNS3VF_VECTOR0_EVENT_RST,
34 HNS3VF_VECTOR0_EVENT_MBX,
35 HNS3VF_VECTOR0_EVENT_OTHER,
38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
44 struct rte_ether_addr *mac_addr);
45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
46 struct rte_ether_addr *mac_addr);
47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
48 __rte_unused int wait_to_complete);
50 /* set PCI bus mastering */
52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
57 ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND);
59 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
65 /* set the master bit */
66 reg |= PCI_COMMAND_MASTER;
68 reg &= ~(PCI_COMMAND_MASTER);
70 return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND);
74 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
75 * @cap: the capability
77 * Return the address of the given capability within the PCI capability list.
80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
82 #define MAX_PCIE_CAPABILITY 48
89 ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
91 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
95 if (!(status & PCI_STATUS_CAP_LIST))
98 ttl = MAX_PCIE_CAPABILITY;
99 ret = rte_pci_read_config(device, &pos, sizeof(pos),
100 PCI_CAPABILITY_LIST);
102 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
103 PCI_CAPABILITY_LIST);
107 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
108 ret = rte_pci_read_config(device, &id, sizeof(id),
109 (pos + PCI_CAP_LIST_ID));
111 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
112 (pos + PCI_CAP_LIST_ID));
122 ret = rte_pci_read_config(device, &pos, sizeof(pos),
123 (pos + PCI_CAP_LIST_NEXT));
125 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
126 (pos + PCI_CAP_LIST_NEXT));
134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
140 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
142 ret = rte_pci_read_config(device, &control, sizeof(control),
143 (pos + PCI_MSIX_FLAGS));
145 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
146 (pos + PCI_MSIX_FLAGS));
151 control |= PCI_MSIX_FLAGS_ENABLE;
153 control &= ~PCI_MSIX_FLAGS_ENABLE;
154 ret = rte_pci_write_config(device, &control, sizeof(control),
155 (pos + PCI_MSIX_FLAGS));
157 PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
158 (pos + PCI_MSIX_FLAGS));
169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
171 /* mac address was checked by upper level interface */
172 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
175 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
176 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
177 RTE_ETHER_ADDR_LEN, false, NULL, 0);
179 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
181 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
190 /* mac address was checked by upper level interface */
191 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
194 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
195 HNS3_MBX_MAC_VLAN_UC_REMOVE,
196 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
199 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
201 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
208 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
209 __rte_unused uint32_t idx,
210 __rte_unused uint32_t pool)
212 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
213 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
216 rte_spinlock_lock(&hw->lock);
219 * In hns3 network engine adding UC and MC mac address with different
220 * commands with firmware. We need to determine whether the input
221 * address is a UC or a MC address to call different commands.
222 * By the way, it is recommended calling the API function named
223 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
224 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
225 * may affect the specifications of UC mac addresses.
227 if (rte_is_multicast_ether_addr(mac_addr)) {
228 if (hns3_find_duplicate_mc_addr(hw, mac_addr)) {
229 rte_spinlock_unlock(&hw->lock);
232 ret = hw->ops.add_mc_mac_addr(hw, mac_addr);
234 ret = hw->ops.add_uc_mac_addr(hw, mac_addr);
237 rte_spinlock_unlock(&hw->lock);
239 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
241 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
249 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
251 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
252 /* index will be checked by upper level rte interface */
253 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
254 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
257 rte_spinlock_lock(&hw->lock);
259 if (rte_is_multicast_ether_addr(mac_addr))
260 ret = hw->ops.del_mc_mac_addr(hw, mac_addr);
262 ret = hw->ops.del_uc_mac_addr(hw, mac_addr);
264 rte_spinlock_unlock(&hw->lock);
266 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
268 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
274 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
275 struct rte_ether_addr *mac_addr)
277 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
278 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
279 struct rte_ether_addr *old_addr;
280 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
281 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
285 * It has been guaranteed that input parameter named mac_addr is valid
286 * address in the rte layer of DPDK framework.
288 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
289 rte_spinlock_lock(&hw->lock);
290 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
291 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
294 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
295 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
296 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
299 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
300 * driver. When user has configured a MAC address for VF device
301 * by "ip link set ..." command based on the PF device, the hns3
302 * PF kernel ethdev driver does not allow VF driver to request
303 * reconfiguring a different default MAC address, and return
304 * -EPREM to VF driver through mailbox.
307 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
309 hns3_warn(hw, "Has permanet mac addr(%s) for vf",
312 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
314 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
319 rte_ether_addr_copy(mac_addr,
320 (struct rte_ether_addr *)hw->mac.mac_addr);
321 rte_spinlock_unlock(&hw->lock);
327 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
329 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
330 struct hns3_hw *hw = &hns->hw;
331 struct hns3_hw_ops *ops = &hw->ops;
332 struct rte_ether_addr *addr;
337 for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
338 addr = &hw->data->mac_addrs[i];
339 if (rte_is_zero_ether_addr(addr))
341 if (rte_is_multicast_ether_addr(addr))
342 ret = del ? ops->del_mc_mac_addr(hw, addr) :
343 ops->add_mc_mac_addr(hw, addr);
345 ret = del ? ops->del_uc_mac_addr(hw, addr) :
346 ops->add_uc_mac_addr(hw, addr);
350 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
352 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
353 "ret = %d.", del ? "remove" : "restore",
361 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
362 struct rte_ether_addr *mac_addr)
364 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
367 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
368 HNS3_MBX_MAC_VLAN_MC_ADD,
369 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
372 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
374 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
382 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
383 struct rte_ether_addr *mac_addr)
385 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
388 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
389 HNS3_MBX_MAC_VLAN_MC_REMOVE,
390 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
393 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
395 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
403 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
404 struct rte_ether_addr *mc_addr_set,
407 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
408 struct rte_ether_addr *addr;
412 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
413 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
414 "invalid. valid range: 0~%d",
415 nb_mc_addr, HNS3_MC_MACADDR_NUM);
419 /* Check if input mac addresses are valid */
420 for (i = 0; i < nb_mc_addr; i++) {
421 addr = &mc_addr_set[i];
422 if (!rte_is_multicast_ether_addr(addr)) {
423 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
426 "failed to set mc mac addr, addr(%s) invalid.",
431 /* Check if there are duplicate addresses */
432 for (j = i + 1; j < nb_mc_addr; j++) {
433 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
434 hns3_ether_format_addr(mac_str,
435 RTE_ETHER_ADDR_FMT_SIZE,
437 hns3_err(hw, "failed to set mc mac addr, "
438 "addrs invalid. two same addrs(%s).",
445 * Check if there are duplicate addresses between mac_addrs
448 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
449 if (rte_is_same_ether_addr(addr,
450 &hw->data->mac_addrs[j])) {
451 hns3_ether_format_addr(mac_str,
452 RTE_ETHER_ADDR_FMT_SIZE,
454 hns3_err(hw, "failed to set mc mac addr, "
455 "addrs invalid. addrs(%s) has already "
456 "configured in mac_addr add API",
467 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
468 struct rte_ether_addr *mc_addr_set,
471 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
472 struct rte_ether_addr *addr;
479 ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
483 rte_spinlock_lock(&hw->lock);
484 cur_addr_num = hw->mc_addrs_num;
485 for (i = 0; i < cur_addr_num; i++) {
486 num = cur_addr_num - i - 1;
487 addr = &hw->mc_addrs[num];
488 ret = hw->ops.del_mc_mac_addr(hw, addr);
490 rte_spinlock_unlock(&hw->lock);
497 set_addr_num = (int)nb_mc_addr;
498 for (i = 0; i < set_addr_num; i++) {
499 addr = &mc_addr_set[i];
500 ret = hw->ops.add_mc_mac_addr(hw, addr);
502 rte_spinlock_unlock(&hw->lock);
506 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
509 rte_spinlock_unlock(&hw->lock);
515 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
517 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
518 struct hns3_hw *hw = &hns->hw;
519 struct rte_ether_addr *addr;
524 for (i = 0; i < hw->mc_addrs_num; i++) {
525 addr = &hw->mc_addrs[i];
526 if (!rte_is_multicast_ether_addr(addr))
529 ret = hw->ops.del_mc_mac_addr(hw, addr);
531 ret = hw->ops.add_mc_mac_addr(hw, addr);
534 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
536 hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
537 del ? "Remove" : "Restore", mac_str, ret);
544 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
545 bool en_uc_pmc, bool en_mc_pmc)
547 struct hns3_mbx_vf_to_pf_cmd *req;
548 struct hns3_cmd_desc desc;
551 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
554 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
555 * so there are some features for promiscuous/allmulticast mode in hns3
556 * VF PMD driver as below:
557 * 1. The promiscuous/allmulticast mode can be configured successfully
558 * only based on the trusted VF device. If based on the non trusted
559 * VF device, configuring promiscuous/allmulticast mode will fail.
560 * The hns3 VF device can be confiruged as trusted device by hns3 PF
561 * kernel ethdev driver on the host by the following command:
562 * "ip link set <eth num> vf <vf id> turst on"
563 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
564 * driver can receive the ingress and outgoing traffic. In the words,
565 * all the ingress packets, all the packets sent from the PF and
566 * other VFs on the same physical port.
567 * 3. Note: Because of the hardware constraints, By default vlan filter
568 * is enabled and couldn't be turned off based on VF device, so vlan
569 * filter is still effective even in promiscuous mode. If upper
570 * applications don't call rte_eth_dev_vlan_filter API function to
571 * set vlan based on VF device, hns3 VF PMD driver will can't receive
572 * the packets with vlan tag in promiscuoue mode.
574 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
575 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
576 req->msg[1] = en_bc_pmc ? 1 : 0;
577 req->msg[2] = en_uc_pmc ? 1 : 0;
578 req->msg[3] = en_mc_pmc ? 1 : 0;
579 req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
581 ret = hns3_cmd_send(hw, &desc, 1);
583 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
589 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
591 struct hns3_adapter *hns = dev->data->dev_private;
592 struct hns3_hw *hw = &hns->hw;
595 ret = hns3vf_set_promisc_mode(hw, true, true, true);
597 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
603 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
605 bool allmulti = dev->data->all_multicast ? true : false;
606 struct hns3_adapter *hns = dev->data->dev_private;
607 struct hns3_hw *hw = &hns->hw;
610 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
612 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
618 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
620 struct hns3_adapter *hns = dev->data->dev_private;
621 struct hns3_hw *hw = &hns->hw;
624 if (dev->data->promiscuous)
627 ret = hns3vf_set_promisc_mode(hw, true, false, true);
629 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
635 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
637 struct hns3_adapter *hns = dev->data->dev_private;
638 struct hns3_hw *hw = &hns->hw;
641 if (dev->data->promiscuous)
644 ret = hns3vf_set_promisc_mode(hw, true, false, false);
646 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
652 hns3vf_restore_promisc(struct hns3_adapter *hns)
654 struct hns3_hw *hw = &hns->hw;
655 bool allmulti = hw->data->all_multicast ? true : false;
657 if (hw->data->promiscuous)
658 return hns3vf_set_promisc_mode(hw, true, true, true);
660 return hns3vf_set_promisc_mode(hw, true, false, allmulti);
664 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
665 bool mmap, enum hns3_ring_type queue_type,
668 struct hns3_vf_bind_vector_msg bind_msg;
673 memset(&bind_msg, 0, sizeof(bind_msg));
674 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
675 HNS3_MBX_UNMAP_RING_TO_VECTOR;
676 bind_msg.vector_id = vector_id;
678 if (queue_type == HNS3_RING_TYPE_RX)
679 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
681 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
683 bind_msg.param[0].ring_type = queue_type;
684 bind_msg.ring_num = 1;
685 bind_msg.param[0].tqp_index = queue_id;
686 op_str = mmap ? "Map" : "Unmap";
687 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
688 sizeof(bind_msg), false, NULL, 0);
690 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
691 op_str, queue_id, bind_msg.vector_id, ret);
697 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
704 * In hns3 network engine, vector 0 is always the misc interrupt of this
705 * function, vector 1~N can be used respectively for the queues of the
706 * function. Tx and Rx queues with the same number share the interrupt
707 * vector. In the initialization clearing the all hardware mapping
708 * relationship configurations between queues and interrupt vectors is
709 * needed, so some error caused by the residual configurations, such as
710 * the unexpected Tx interrupt, can be avoid.
712 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
713 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
714 vec = vec - 1; /* the last interrupt is reserved */
715 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
716 for (i = 0; i < hw->intr_tqps_num; i++) {
718 * Set gap limiter/rate limiter/quanity limiter algorithm
719 * configuration for interrupt coalesce of queue's interrupt.
721 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
722 HNS3_TQP_INTR_GL_DEFAULT);
723 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
724 HNS3_TQP_INTR_GL_DEFAULT);
725 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
727 * QL(quantity limiter) is not used currently, just set 0 to
730 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
732 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
733 HNS3_RING_TYPE_TX, i);
735 PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
736 "vector: %u, ret=%d", i, vec, ret);
740 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
741 HNS3_RING_TYPE_RX, i);
743 PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
744 "vector: %u, ret=%d", i, vec, ret);
753 hns3vf_dev_configure(struct rte_eth_dev *dev)
755 struct hns3_adapter *hns = dev->data->dev_private;
756 struct hns3_hw *hw = &hns->hw;
757 struct rte_eth_conf *conf = &dev->data->dev_conf;
758 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
759 uint16_t nb_rx_q = dev->data->nb_rx_queues;
760 uint16_t nb_tx_q = dev->data->nb_tx_queues;
761 struct rte_eth_rss_conf rss_conf;
765 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
768 * Some versions of hardware network engine does not support
769 * individually enable/disable/reset the Tx or Rx queue. These devices
770 * must enable/disable/reset Tx and Rx queues at the same time. When the
771 * numbers of Tx queues allocated by upper applications are not equal to
772 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
773 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
774 * work as usual. But these fake queues are imperceptible, and can not
775 * be used by upper applications.
777 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
779 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
780 hw->cfg_max_queues = 0;
784 hw->adapter_state = HNS3_NIC_CONFIGURING;
785 if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
786 hns3_err(hw, "setting link speed/duplex not supported");
791 /* When RSS is not configured, redirect the packet queue 0 */
792 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
793 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
794 hw->rss_dis_flag = false;
795 rss_conf = conf->rx_adv_conf.rss_conf;
796 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
801 ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
805 ret = hns3vf_dev_configure_vlan(dev);
809 /* config hardware GRO */
810 gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
811 ret = hns3_config_gro(hw, gro_en);
815 hns3_init_rx_ptype_tble(dev);
817 hw->adapter_state = HNS3_NIC_CONFIGURED;
821 hw->cfg_max_queues = 0;
822 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
823 hw->adapter_state = HNS3_NIC_INITIALIZED;
829 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
833 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
834 sizeof(mtu), true, NULL, 0);
836 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
842 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
844 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
845 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
849 * The hns3 PF/VF devices on the same port share the hardware MTU
850 * configuration. Currently, we send mailbox to inform hns3 PF kernel
851 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
852 * driver, there is no need to stop the port for hns3 VF device, and the
853 * MTU value issued by hns3 VF PMD driver must be less than or equal to
856 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
857 hns3_err(hw, "Failed to set mtu during resetting");
862 * when Rx of scattered packets is off, we have some possibility of
863 * using vector Rx process function or simple Rx functions in hns3 PMD
864 * driver. If the input MTU is increased and the maximum length of
865 * received packets is greater than the length of a buffer for Rx
866 * packet, the hardware network engine needs to use multiple BDs and
867 * buffers to store these packets. This will cause problems when still
868 * using vector Rx process function or simple Rx function to receiving
869 * packets. So, when Rx of scattered packets is off and device is
870 * started, it is not permitted to increase MTU so that the maximum
871 * length of Rx packets is greater than Rx buffer length.
873 if (dev->data->dev_started && !dev->data->scattered_rx &&
874 frame_size > hw->rx_buf_len) {
875 hns3_err(hw, "failed to set mtu because current is "
876 "not scattered rx mode");
880 rte_spinlock_lock(&hw->lock);
881 ret = hns3vf_config_mtu(hw, mtu);
883 rte_spinlock_unlock(&hw->lock);
886 rte_spinlock_unlock(&hw->lock);
892 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
894 struct hns3_adapter *hns = eth_dev->data->dev_private;
895 struct hns3_hw *hw = &hns->hw;
896 uint16_t q_num = hw->tqps_num;
899 * In interrupt mode, 'max_rx_queues' is set based on the number of
900 * MSI-X interrupt resources of the hardware.
902 if (hw->data->dev_conf.intr_conf.rxq == 1)
903 q_num = hw->intr_tqps_num;
905 info->max_rx_queues = q_num;
906 info->max_tx_queues = hw->tqps_num;
907 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
908 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
909 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
910 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
911 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
913 info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
914 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
915 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
916 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
917 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
918 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
919 RTE_ETH_RX_OFFLOAD_SCATTER |
920 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
921 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
922 RTE_ETH_RX_OFFLOAD_RSS_HASH |
923 RTE_ETH_RX_OFFLOAD_TCP_LRO);
924 info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
925 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
926 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
927 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
928 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
929 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
930 RTE_ETH_TX_OFFLOAD_TCP_TSO |
931 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
932 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
933 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
934 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
935 hns3_txvlan_cap_get(hw));
937 if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
938 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
940 if (hns3_dev_get_support(hw, INDEP_TXRX))
941 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
942 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
944 info->rx_desc_lim = (struct rte_eth_desc_lim) {
945 .nb_max = HNS3_MAX_RING_DESC,
946 .nb_min = HNS3_MIN_RING_DESC,
947 .nb_align = HNS3_ALIGN_RING_DESC,
950 info->tx_desc_lim = (struct rte_eth_desc_lim) {
951 .nb_max = HNS3_MAX_RING_DESC,
952 .nb_min = HNS3_MIN_RING_DESC,
953 .nb_align = HNS3_ALIGN_RING_DESC,
954 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
955 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
958 info->default_rxconf = (struct rte_eth_rxconf) {
959 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
961 * If there are no available Rx buffer descriptors, incoming
962 * packets are always dropped by hardware based on hns3 network
968 info->default_txconf = (struct rte_eth_txconf) {
969 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
973 info->reta_size = hw->rss_ind_tbl_size;
974 info->hash_key_size = HNS3_RSS_KEY_SIZE;
975 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
977 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
978 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
979 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
980 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
981 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
982 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
988 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
990 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
994 hns3vf_disable_irq0(struct hns3_hw *hw)
996 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1000 hns3vf_enable_irq0(struct hns3_hw *hw)
1002 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1005 static enum hns3vf_evt_cause
1006 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1008 struct hns3_hw *hw = &hns->hw;
1009 enum hns3vf_evt_cause ret;
1010 uint32_t cmdq_stat_reg;
1011 uint32_t rst_ing_reg;
1014 /* Fetch the events from their corresponding regs */
1015 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1016 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1017 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1018 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1019 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1020 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
1021 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1022 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1023 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1025 hw->reset.stats.global_cnt++;
1026 hns3_warn(hw, "Global reset detected, clear reset status");
1028 hns3_schedule_delayed_reset(hns);
1029 hns3_warn(hw, "Global reset detected, don't clear reset status");
1032 ret = HNS3VF_VECTOR0_EVENT_RST;
1036 /* Check for vector0 mailbox(=CMDQ RX) event source */
1037 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1038 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1039 ret = HNS3VF_VECTOR0_EVENT_MBX;
1044 ret = HNS3VF_VECTOR0_EVENT_OTHER;
1052 hns3vf_interrupt_handler(void *param)
1054 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1055 struct hns3_adapter *hns = dev->data->dev_private;
1056 struct hns3_hw *hw = &hns->hw;
1057 enum hns3vf_evt_cause event_cause;
1060 /* Disable interrupt */
1061 hns3vf_disable_irq0(hw);
1063 /* Read out interrupt causes */
1064 event_cause = hns3vf_check_event_cause(hns, &clearval);
1065 /* Clear interrupt causes */
1066 hns3vf_clear_event_cause(hw, clearval);
1068 switch (event_cause) {
1069 case HNS3VF_VECTOR0_EVENT_RST:
1070 hns3_schedule_reset(hns);
1072 case HNS3VF_VECTOR0_EVENT_MBX:
1073 hns3_dev_handle_mbx_msg(hw);
1079 /* Enable interrupt */
1080 hns3vf_enable_irq0(hw);
1084 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1086 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1087 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1088 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1089 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1093 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1095 struct hns3_dev_specs_0_cmd *req0;
1097 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1099 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1100 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1101 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1102 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1106 hns3vf_check_dev_specifications(struct hns3_hw *hw)
1108 if (hw->rss_ind_tbl_size == 0 ||
1109 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
1110 hns3_warn(hw, "the size of hash lookup table configured (%u)"
1111 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
1112 HNS3_RSS_IND_TBL_SIZE_MAX);
1120 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1122 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1126 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1127 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1129 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1131 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1133 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1137 hns3vf_parse_dev_specifications(hw, desc);
1139 return hns3vf_check_dev_specifications(hw);
1143 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
1145 uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
1146 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1147 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1148 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1150 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1151 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1152 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1156 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
1158 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS 500
1160 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1161 int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
1162 uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1163 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1164 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1166 __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
1169 (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1172 while (remain_ms > 0) {
1173 rte_delay_ms(HNS3_POLL_RESPONE_MS);
1174 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
1175 HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1181 * When exit above loop, the pf_push_lsc_cap could be one of the three
1182 * state: unknown (means pf not ack), not_supported, supported.
1183 * Here config it as 'not_supported' when it's 'unknown' state.
1185 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1186 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1188 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
1189 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
1190 hns3_info(hw, "detect PF support push link status change!");
1193 * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
1194 * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
1195 * the RTE_ETH_DEV_INTR_LSC capability.
1197 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1202 hns3vf_get_capability(struct hns3_hw *hw)
1204 struct rte_pci_device *pci_dev;
1205 struct rte_eth_dev *eth_dev;
1209 eth_dev = &rte_eth_devices[hw->data->port_id];
1210 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1212 /* Get PCI revision id */
1213 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1214 HNS3_PCI_REVISION_ID);
1215 if (ret != HNS3_PCI_REVISION_ID_LEN) {
1216 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1220 hw->revision = revision;
1222 if (revision < PCI_REVISION_ID_HIP09_A) {
1223 hns3vf_set_default_dev_specifications(hw);
1224 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1225 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1226 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1227 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
1228 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1229 hw->rss_info.ipv6_sctp_offload_supported = false;
1230 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1234 ret = hns3vf_query_dev_specifications(hw);
1237 "failed to query dev specifications, ret = %d",
1242 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1243 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1244 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1245 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1246 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1247 hw->rss_info.ipv6_sctp_offload_supported = true;
1248 hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1254 hns3vf_check_tqp_info(struct hns3_hw *hw)
1256 if (hw->tqps_num == 0) {
1257 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1261 if (hw->rss_size_max == 0) {
1262 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1266 hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1272 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1277 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1278 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1279 true, &resp_msg, sizeof(resp_msg));
1281 if (ret == -ETIME) {
1283 * Getting current port based VLAN state from PF driver
1284 * will not affect VF driver's basic function. Because
1285 * the VF driver relies on hns3 PF kernel ether driver,
1286 * to avoid introducing compatibility issues with older
1287 * version of PF driver, no failure will be returned
1288 * when the return value is ETIME. This return value has
1289 * the following scenarios:
1290 * 1) Firmware didn't return the results in time
1291 * 2) the result return by firmware is timeout
1292 * 3) the older version of kernel side PF driver does
1293 * not support this mailbox message.
1294 * For scenarios 1 and 2, it is most likely that a
1295 * hardware error has occurred, or a hardware reset has
1296 * occurred. In this case, these errors will be caught
1297 * by other functions.
1299 PMD_INIT_LOG(WARNING,
1300 "failed to get PVID state for timeout, maybe "
1301 "kernel side PF driver doesn't support this "
1302 "mailbox message, or firmware didn't respond.");
1303 resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1305 PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1310 hw->port_base_vlan_cfg.state = resp_msg ?
1311 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1316 hns3vf_get_queue_info(struct hns3_hw *hw)
1318 #define HNS3VF_TQPS_RSS_INFO_LEN 6
1319 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1322 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1323 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1325 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1329 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1330 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1332 return hns3vf_check_tqp_info(hw);
1336 hns3vf_get_queue_depth(struct hns3_hw *hw)
1338 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4
1339 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1342 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1343 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1345 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1350 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1351 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1357 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1359 if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1360 hns3_set_bit(hw->capability,
1361 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1365 hns3vf_get_num_tc(struct hns3_hw *hw)
1370 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1371 if (hw->hw_tc_map & BIT(i))
1378 hns3vf_get_basic_info(struct hns3_hw *hw)
1380 uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1381 struct hns3_basic_info *basic_info;
1384 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1385 true, resp_msg, sizeof(resp_msg));
1387 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1392 basic_info = (struct hns3_basic_info *)resp_msg;
1393 hw->hw_tc_map = basic_info->hw_tc_map;
1394 hw->num_tc = hns3vf_get_num_tc(hw);
1395 hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1396 hns3vf_update_caps(hw, basic_info->caps);
1402 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1404 uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1407 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1408 true, host_mac, RTE_ETHER_ADDR_LEN);
1410 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1414 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1420 hns3vf_get_configuration(struct hns3_hw *hw)
1424 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1425 hw->rss_dis_flag = false;
1427 /* Get device capability */
1428 ret = hns3vf_get_capability(hw);
1430 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1434 hns3vf_get_push_lsc_cap(hw);
1436 /* Get basic info from PF */
1437 ret = hns3vf_get_basic_info(hw);
1441 /* Get queue configuration from PF */
1442 ret = hns3vf_get_queue_info(hw);
1446 /* Get queue depth info from PF */
1447 ret = hns3vf_get_queue_depth(hw);
1451 /* Get user defined VF MAC addr from PF */
1452 ret = hns3vf_get_host_mac_addr(hw);
1456 return hns3vf_get_port_base_vlan_filter_state(hw);
1460 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1463 struct hns3_hw *hw = &hns->hw;
1465 return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1469 hns3vf_request_link_info(struct hns3_hw *hw)
1471 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1475 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1478 send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1479 vf->req_link_info_cnt > 0;
1483 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1486 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1490 if (vf->req_link_info_cnt > 0)
1491 vf->req_link_info_cnt--;
1495 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1496 uint32_t link_speed, uint8_t link_duplex)
1498 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1499 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1500 struct hns3_mac *mac = &hw->mac;
1504 * PF kernel driver may push link status when VF driver is in resetting,
1505 * driver will stop polling job in this case, after resetting done
1506 * driver will start polling job again.
1507 * When polling job started, driver will get initial link status by
1508 * sending request to PF kernel driver, then could update link status by
1509 * process PF kernel driver's link status mailbox message.
1511 if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1514 if (hw->adapter_state != HNS3_NIC_STARTED)
1517 mac->link_status = link_status;
1518 mac->link_speed = link_speed;
1519 mac->link_duplex = link_duplex;
1520 ret = hns3vf_dev_link_update(dev, 0);
1521 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1522 hns3_start_report_lse(dev);
1526 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1528 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1529 struct hns3_hw *hw = &hns->hw;
1530 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1531 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1532 uint8_t is_kill = on ? 0 : 1;
1534 msg_data[0] = is_kill;
1535 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1536 memcpy(&msg_data[3], &proto, sizeof(proto));
1538 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1539 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1544 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1546 struct hns3_adapter *hns = dev->data->dev_private;
1547 struct hns3_hw *hw = &hns->hw;
1550 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1552 "vf set vlan id failed during resetting, vlan_id =%u",
1556 rte_spinlock_lock(&hw->lock);
1557 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1558 rte_spinlock_unlock(&hw->lock);
1560 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1567 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1572 if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1575 msg_data = enable ? 1 : 0;
1576 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1577 HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1578 sizeof(msg_data), true, NULL, 0);
1580 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1581 enable ? "enable" : "disable", ret);
1587 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1592 msg_data = enable ? 1 : 0;
1593 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1594 &msg_data, sizeof(msg_data), false, NULL, 0);
1596 hns3_err(hw, "vf %s strip failed, ret = %d.",
1597 enable ? "enable" : "disable", ret);
1603 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1605 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1607 unsigned int tmp_mask;
1610 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1611 hns3_err(hw, "vf set vlan offload failed during resetting, "
1612 "mask = 0x%x", mask);
1616 tmp_mask = (unsigned int)mask;
1618 if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
1619 rte_spinlock_lock(&hw->lock);
1620 /* Enable or disable VLAN filter */
1621 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1622 ret = hns3vf_en_vlan_filter(hw, true);
1624 ret = hns3vf_en_vlan_filter(hw, false);
1625 rte_spinlock_unlock(&hw->lock);
1630 /* Vlan stripping setting */
1631 if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
1632 rte_spinlock_lock(&hw->lock);
1633 /* Enable or disable VLAN stripping */
1634 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1635 ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1637 ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1638 rte_spinlock_unlock(&hw->lock);
1645 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1647 struct rte_vlan_filter_conf *vfc;
1648 struct hns3_hw *hw = &hns->hw;
1655 vfc = &hw->data->vlan_filter_conf;
1656 for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1657 if (vfc->ids[i] == 0)
1662 * 64 means the num bits of ids, one bit corresponds to
1666 /* count trailing zeroes */
1667 vbit = ~ids & (ids - 1);
1668 /* clear least significant bit set */
1669 ids ^= (ids ^ (ids - 1)) ^ vbit;
1674 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1677 "VF handle vlan table failed, ret =%d, on = %d",
1688 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1690 return hns3vf_handle_all_vlan_table(hns, 0);
1694 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1696 struct hns3_hw *hw = &hns->hw;
1697 struct rte_eth_conf *dev_conf;
1701 dev_conf = &hw->data->dev_conf;
1702 en = dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? true
1704 ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1706 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1712 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1714 struct hns3_adapter *hns = dev->data->dev_private;
1715 struct rte_eth_dev_data *data = dev->data;
1716 struct hns3_hw *hw = &hns->hw;
1719 if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1720 data->dev_conf.txmode.hw_vlan_reject_untagged ||
1721 data->dev_conf.txmode.hw_vlan_insert_pvid) {
1722 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1723 "or hw_vlan_insert_pvid is not support!");
1726 /* Apply vlan offload setting */
1727 ret = hns3vf_vlan_offload_set(dev, RTE_ETH_VLAN_STRIP_MASK |
1728 RTE_ETH_VLAN_FILTER_MASK);
1730 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1736 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1740 msg_data = alive ? 1 : 0;
1741 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1742 sizeof(msg_data), false, NULL, 0);
1746 hns3vf_keep_alive_handler(void *param)
1748 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1749 struct hns3_adapter *hns = eth_dev->data->dev_private;
1750 struct hns3_hw *hw = &hns->hw;
1753 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1756 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1759 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1764 hns3vf_service_handler(void *param)
1766 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1767 struct hns3_adapter *hns = eth_dev->data->dev_private;
1768 struct hns3_hw *hw = &hns->hw;
1771 * The query link status and reset processing are executed in the
1772 * interrupt thread. When the IMP reset occurs, IMP will not respond,
1773 * and the query operation will timeout after 30ms. In the case of
1774 * multiple PF/VFs, each query failure timeout causes the IMP reset
1775 * interrupt to fail to respond within 100ms.
1776 * Before querying the link status, check whether there is a reset
1777 * pending, and if so, abandon the query.
1779 if (!hns3vf_is_reset_pending(hns))
1780 hns3vf_request_link_info(hw);
1782 hns3_warn(hw, "Cancel the query when reset is pending");
1784 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1789 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1791 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT 3
1793 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1795 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1796 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1798 __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1800 hns3vf_service_handler(dev);
1804 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1806 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1808 rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1810 __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1814 hns3_query_vf_resource(struct hns3_hw *hw)
1816 struct hns3_vf_res_cmd *req;
1817 struct hns3_cmd_desc desc;
1821 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1822 ret = hns3_cmd_send(hw, &desc, 1);
1824 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1828 req = (struct hns3_vf_res_cmd *)desc.data;
1829 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1830 HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1831 if (num_msi < HNS3_MIN_VECTOR_NUM) {
1832 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1833 num_msi, HNS3_MIN_VECTOR_NUM);
1837 hw->num_msi = num_msi;
1843 hns3vf_init_hardware(struct hns3_adapter *hns)
1845 struct hns3_hw *hw = &hns->hw;
1846 uint16_t mtu = hw->data->mtu;
1849 ret = hns3vf_set_promisc_mode(hw, true, false, false);
1853 ret = hns3vf_config_mtu(hw, mtu);
1855 goto err_init_hardware;
1857 ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1859 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1860 goto err_init_hardware;
1863 ret = hns3_config_gro(hw, false);
1865 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1866 goto err_init_hardware;
1870 * In the initialization clearing the all hardware mapping relationship
1871 * configurations between queues and interrupt vectors is needed, so
1872 * some error caused by the residual configurations, such as the
1873 * unexpected interrupt, can be avoid.
1875 ret = hns3vf_init_ring_with_vector(hw);
1877 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1878 goto err_init_hardware;
1884 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1889 hns3vf_clear_vport_list(struct hns3_hw *hw)
1891 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1892 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1897 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1899 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1900 struct hns3_adapter *hns = eth_dev->data->dev_private;
1901 struct hns3_hw *hw = &hns->hw;
1904 PMD_INIT_FUNC_TRACE();
1906 /* Get hardware io base address from pcie BAR2 IO space */
1907 hw->io_base = pci_dev->mem_resource[2].addr;
1909 /* Firmware command queue initialize */
1910 ret = hns3_cmd_init_queue(hw);
1912 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1913 goto err_cmd_init_queue;
1916 /* Firmware command initialize */
1917 ret = hns3_cmd_init(hw);
1919 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1923 hns3_tx_push_init(eth_dev);
1925 /* Get VF resource */
1926 ret = hns3_query_vf_resource(hw);
1930 rte_spinlock_init(&hw->mbx_resp.lock);
1932 hns3vf_clear_event_cause(hw, 0);
1934 ret = rte_intr_callback_register(pci_dev->intr_handle,
1935 hns3vf_interrupt_handler, eth_dev);
1937 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1938 goto err_intr_callback_register;
1941 /* Enable interrupt */
1942 rte_intr_enable(pci_dev->intr_handle);
1943 hns3vf_enable_irq0(hw);
1945 /* Get configuration from PF */
1946 ret = hns3vf_get_configuration(hw);
1948 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1949 goto err_get_config;
1952 ret = hns3_tqp_stats_init(hw);
1954 goto err_get_config;
1956 /* Hardware statistics of imissed registers cleared. */
1957 ret = hns3_update_imissed_stats(hw, true);
1959 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1960 goto err_set_tc_queue;
1963 ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1965 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1966 goto err_set_tc_queue;
1969 ret = hns3vf_clear_vport_list(hw);
1971 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1972 goto err_set_tc_queue;
1975 ret = hns3vf_init_hardware(hns);
1977 goto err_set_tc_queue;
1979 hns3_rss_set_default_args(hw);
1981 ret = hns3vf_set_alive(hw, true);
1983 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1984 goto err_set_tc_queue;
1990 hns3_tqp_stats_uninit(hw);
1993 hns3vf_disable_irq0(hw);
1994 rte_intr_disable(pci_dev->intr_handle);
1995 hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1997 err_intr_callback_register:
1999 hns3_cmd_uninit(hw);
2000 hns3_cmd_destroy_queue(hw);
2008 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
2010 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2011 struct hns3_adapter *hns = eth_dev->data->dev_private;
2012 struct hns3_hw *hw = &hns->hw;
2014 PMD_INIT_FUNC_TRACE();
2016 hns3_rss_uninit(hns);
2017 (void)hns3_config_gro(hw, false);
2018 (void)hns3vf_set_alive(hw, false);
2019 (void)hns3vf_set_promisc_mode(hw, false, false, false);
2020 hns3_flow_uninit(eth_dev);
2021 hns3_tqp_stats_uninit(hw);
2022 hns3vf_disable_irq0(hw);
2023 rte_intr_disable(pci_dev->intr_handle);
2024 hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
2026 hns3_cmd_uninit(hw);
2027 hns3_cmd_destroy_queue(hw);
2032 hns3vf_do_stop(struct hns3_adapter *hns)
2034 struct hns3_hw *hw = &hns->hw;
2037 hw->mac.link_status = RTE_ETH_LINK_DOWN;
2040 * The "hns3vf_do_stop" function will also be called by .stop_service to
2041 * prepare reset. At the time of global or IMP reset, the command cannot
2042 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
2043 * accessed during the reset process. So the mbuf can not be released
2044 * during reset and is required to be released after the reset is
2047 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)
2048 hns3_dev_release_mbufs(hns);
2050 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
2051 hns3vf_configure_mac_addr(hns, true);
2052 ret = hns3_reset_all_tqps(hns);
2054 hns3_err(hw, "failed to reset all queues ret = %d",
2063 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
2065 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2066 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2067 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2068 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2069 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2072 if (dev->data->dev_conf.intr_conf.rxq == 0)
2075 /* unmap the ring with vector */
2076 if (rte_intr_allow_others(intr_handle)) {
2077 vec = RTE_INTR_VEC_RXTX_OFFSET;
2078 base = RTE_INTR_VEC_RXTX_OFFSET;
2080 if (rte_intr_dp_is_en(intr_handle)) {
2081 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2082 (void)hns3vf_bind_ring_with_vector(hw, vec, false,
2085 if (vec < base + rte_intr_nb_efd_get(intr_handle)
2090 /* Clean datapath event and queue/vec mapping */
2091 rte_intr_efd_disable(intr_handle);
2093 /* Cleanup vector list */
2094 rte_intr_vec_list_free(intr_handle);
2098 hns3vf_dev_stop(struct rte_eth_dev *dev)
2100 struct hns3_adapter *hns = dev->data->dev_private;
2101 struct hns3_hw *hw = &hns->hw;
2103 PMD_INIT_FUNC_TRACE();
2104 dev->data->dev_started = 0;
2106 hw->adapter_state = HNS3_NIC_STOPPING;
2107 hns3_set_rxtx_function(dev);
2109 /* Disable datapath on secondary process. */
2110 hns3_mp_req_stop_rxtx(dev);
2111 /* Prevent crashes when queues are still in use. */
2112 rte_delay_ms(hw->cfg_max_queues);
2114 rte_spinlock_lock(&hw->lock);
2115 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
2117 hns3vf_do_stop(hns);
2118 hns3vf_unmap_rx_interrupt(dev);
2119 hw->adapter_state = HNS3_NIC_CONFIGURED;
2121 hns3_rx_scattered_reset(dev);
2122 hns3vf_stop_poll_job(dev);
2123 hns3_stop_report_lse(dev);
2124 rte_spinlock_unlock(&hw->lock);
2130 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
2132 struct hns3_adapter *hns = eth_dev->data->dev_private;
2133 struct hns3_hw *hw = &hns->hw;
2136 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2139 if (hw->adapter_state == HNS3_NIC_STARTED)
2140 ret = hns3vf_dev_stop(eth_dev);
2142 hw->adapter_state = HNS3_NIC_CLOSING;
2143 hns3_reset_abort(hns);
2144 hw->adapter_state = HNS3_NIC_CLOSED;
2145 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
2146 hns3vf_configure_all_mc_mac_addr(hns, true);
2147 hns3vf_remove_all_vlan_table(hns);
2148 hns3vf_uninit_vf(eth_dev);
2149 hns3_free_all_queues(eth_dev);
2150 rte_free(hw->reset.wait_data);
2151 hns3_mp_uninit_primary();
2152 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
2158 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2161 struct hns3_adapter *hns = eth_dev->data->dev_private;
2162 struct hns3_hw *hw = &hns->hw;
2163 uint32_t version = hw->fw_version;
2166 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2167 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2168 HNS3_FW_VERSION_BYTE3_S),
2169 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2170 HNS3_FW_VERSION_BYTE2_S),
2171 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2172 HNS3_FW_VERSION_BYTE1_S),
2173 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2174 HNS3_FW_VERSION_BYTE0_S));
2178 ret += 1; /* add the size of '\0' */
2179 if (fw_size < (size_t)ret)
2186 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2187 __rte_unused int wait_to_complete)
2189 struct hns3_adapter *hns = eth_dev->data->dev_private;
2190 struct hns3_hw *hw = &hns->hw;
2191 struct hns3_mac *mac = &hw->mac;
2192 struct rte_eth_link new_link;
2194 memset(&new_link, 0, sizeof(new_link));
2195 switch (mac->link_speed) {
2196 case RTE_ETH_SPEED_NUM_10M:
2197 case RTE_ETH_SPEED_NUM_100M:
2198 case RTE_ETH_SPEED_NUM_1G:
2199 case RTE_ETH_SPEED_NUM_10G:
2200 case RTE_ETH_SPEED_NUM_25G:
2201 case RTE_ETH_SPEED_NUM_40G:
2202 case RTE_ETH_SPEED_NUM_50G:
2203 case RTE_ETH_SPEED_NUM_100G:
2204 case RTE_ETH_SPEED_NUM_200G:
2205 if (mac->link_status)
2206 new_link.link_speed = mac->link_speed;
2209 if (mac->link_status)
2210 new_link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2214 if (!mac->link_status)
2215 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2217 new_link.link_duplex = mac->link_duplex;
2218 new_link.link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2219 new_link.link_autoneg =
2220 !(eth_dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED);
2222 return rte_eth_linkstatus_set(eth_dev, &new_link);
2226 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2228 struct hns3_hw *hw = &hns->hw;
2229 uint16_t nb_rx_q = hw->data->nb_rx_queues;
2230 uint16_t nb_tx_q = hw->data->nb_tx_queues;
2233 ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2237 hns3_enable_rxd_adv_layout(hw);
2239 ret = hns3_init_queues(hns, reset_queue);
2241 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2247 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2249 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2250 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2251 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2252 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2253 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2254 uint32_t intr_vector;
2259 * hns3 needs a separate interrupt to be used as event interrupt which
2260 * could not be shared with task queue pair, so KERNEL drivers need
2261 * support multiple interrupt vectors.
2263 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2264 !rte_intr_cap_multiple(intr_handle))
2267 rte_intr_disable(intr_handle);
2268 intr_vector = hw->used_rx_queues;
2269 /* It creates event fd for each intr vector when MSIX is used */
2270 if (rte_intr_efd_enable(intr_handle, intr_vector))
2273 /* Allocate vector list */
2274 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
2275 hw->used_rx_queues)) {
2276 hns3_err(hw, "Failed to allocate %u rx_queues"
2277 " intr_vec", hw->used_rx_queues);
2279 goto vf_alloc_intr_vec_error;
2282 if (rte_intr_allow_others(intr_handle)) {
2283 vec = RTE_INTR_VEC_RXTX_OFFSET;
2284 base = RTE_INTR_VEC_RXTX_OFFSET;
2287 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2288 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2289 HNS3_RING_TYPE_RX, q_id);
2291 goto vf_bind_vector_error;
2293 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
2294 goto vf_bind_vector_error;
2297 * If there are not enough efds (e.g. not enough interrupt),
2298 * remaining queues will be bond to the last interrupt.
2300 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
2303 rte_intr_enable(intr_handle);
2306 vf_bind_vector_error:
2307 rte_intr_vec_list_free(intr_handle);
2308 vf_alloc_intr_vec_error:
2309 rte_intr_efd_disable(intr_handle);
2314 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2316 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2317 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2318 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2322 if (dev->data->dev_conf.intr_conf.rxq == 0)
2325 if (rte_intr_dp_is_en(intr_handle)) {
2326 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2327 ret = hns3vf_bind_ring_with_vector(hw,
2328 rte_intr_vec_list_index_get(intr_handle,
2330 true, HNS3_RING_TYPE_RX, q_id);
2340 hns3vf_restore_filter(struct rte_eth_dev *dev)
2342 hns3_restore_rss_filter(dev);
2346 hns3vf_dev_start(struct rte_eth_dev *dev)
2348 struct hns3_adapter *hns = dev->data->dev_private;
2349 struct hns3_hw *hw = &hns->hw;
2352 PMD_INIT_FUNC_TRACE();
2353 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2356 rte_spinlock_lock(&hw->lock);
2357 hw->adapter_state = HNS3_NIC_STARTING;
2358 ret = hns3vf_do_start(hns, true);
2360 hw->adapter_state = HNS3_NIC_CONFIGURED;
2361 rte_spinlock_unlock(&hw->lock);
2364 ret = hns3vf_map_rx_interrupt(dev);
2366 goto map_rx_inter_err;
2369 * There are three register used to control the status of a TQP
2370 * (contains a pair of Tx queue and Rx queue) in the new version network
2371 * engine. One is used to control the enabling of Tx queue, the other is
2372 * used to control the enabling of Rx queue, and the last is the master
2373 * switch used to control the enabling of the tqp. The Tx register and
2374 * TQP register must be enabled at the same time to enable a Tx queue.
2375 * The same applies to the Rx queue. For the older network enginem, this
2376 * function only refresh the enabled flag, and it is used to update the
2377 * status of queue in the dpdk framework.
2379 ret = hns3_start_all_txqs(dev);
2381 goto map_rx_inter_err;
2383 ret = hns3_start_all_rxqs(dev);
2385 goto start_all_rxqs_fail;
2387 hw->adapter_state = HNS3_NIC_STARTED;
2388 rte_spinlock_unlock(&hw->lock);
2390 hns3_rx_scattered_calc(dev);
2391 hns3_set_rxtx_function(dev);
2392 hns3_mp_req_start_rxtx(dev);
2394 hns3vf_restore_filter(dev);
2396 /* Enable interrupt of all rx queues before enabling queues */
2397 hns3_dev_all_rx_queue_intr_enable(hw, true);
2398 hns3_start_tqps(hw);
2400 if (dev->data->dev_conf.intr_conf.lsc != 0)
2401 hns3vf_dev_link_update(dev, 0);
2402 hns3vf_start_poll_job(dev);
2406 start_all_rxqs_fail:
2407 hns3_stop_all_txqs(dev);
2409 (void)hns3vf_do_stop(hns);
2410 hw->adapter_state = HNS3_NIC_CONFIGURED;
2411 rte_spinlock_unlock(&hw->lock);
2417 is_vf_reset_done(struct hns3_hw *hw)
2419 #define HNS3_FUN_RST_ING_BITS \
2420 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2421 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2422 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2423 BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2427 if (hw->reset.level == HNS3_VF_RESET) {
2428 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2429 if (val & HNS3_VF_RST_ING_BIT)
2432 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2433 if (val & HNS3_FUN_RST_ING_BITS)
2440 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2442 struct hns3_hw *hw = &hns->hw;
2443 enum hns3_reset_level reset;
2446 * According to the protocol of PCIe, FLR to a PF device resets the PF
2447 * state as well as the SR-IOV extended capability including VF Enable
2448 * which means that VFs no longer exist.
2450 * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2451 * is in FLR stage, the register state of VF device is not reliable,
2452 * so register states detection can not be carried out. In this case,
2453 * we just ignore the register states and return false to indicate that
2454 * there are no other reset states that need to be processed by driver.
2456 if (hw->reset.level == HNS3_VF_FULL_RESET)
2459 /* Check the registers to confirm whether there is reset pending */
2460 hns3vf_check_event_cause(hns, NULL);
2461 reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2462 if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2463 hw->reset.level < reset) {
2464 hns3_warn(hw, "High level reset %d is pending", reset);
2471 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2473 struct hns3_hw *hw = &hns->hw;
2474 struct hns3_wait_data *wait_data = hw->reset.wait_data;
2477 if (wait_data->result == HNS3_WAIT_SUCCESS) {
2479 * After vf reset is ready, the PF may not have completed
2480 * the reset processing. The vf sending mbox to PF may fail
2481 * during the pf reset, so it is better to add extra delay.
2483 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2484 hw->reset.level == HNS3_FLR_RESET)
2486 /* Reset retry process, no need to add extra delay. */
2487 if (hw->reset.attempts)
2489 if (wait_data->check_completion == NULL)
2492 wait_data->check_completion = NULL;
2493 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2494 wait_data->count = 1;
2495 wait_data->result = HNS3_WAIT_REQUEST;
2496 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2498 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2500 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2501 hns3_clock_gettime(&tv);
2502 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2503 tv.tv_sec, tv.tv_usec);
2505 } else if (wait_data->result == HNS3_WAIT_REQUEST)
2508 wait_data->hns = hns;
2509 wait_data->check_completion = is_vf_reset_done;
2510 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2511 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2512 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2513 wait_data->count = HNS3VF_RESET_WAIT_CNT;
2514 wait_data->result = HNS3_WAIT_REQUEST;
2515 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2520 hns3vf_prepare_reset(struct hns3_adapter *hns)
2522 struct hns3_hw *hw = &hns->hw;
2525 if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2526 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2531 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2537 hns3vf_stop_service(struct hns3_adapter *hns)
2539 struct hns3_hw *hw = &hns->hw;
2540 struct rte_eth_dev *eth_dev;
2542 eth_dev = &rte_eth_devices[hw->data->port_id];
2543 if (hw->adapter_state == HNS3_NIC_STARTED) {
2545 * Make sure call update link status before hns3vf_stop_poll_job
2546 * because update link status depend on polling job exist.
2548 hns3vf_update_link_status(hw, RTE_ETH_LINK_DOWN, hw->mac.link_speed,
2549 hw->mac.link_duplex);
2550 hns3vf_stop_poll_job(eth_dev);
2552 hw->mac.link_status = RTE_ETH_LINK_DOWN;
2554 hns3_set_rxtx_function(eth_dev);
2556 /* Disable datapath on secondary process. */
2557 hns3_mp_req_stop_rxtx(eth_dev);
2558 rte_delay_ms(hw->cfg_max_queues);
2560 rte_spinlock_lock(&hw->lock);
2561 if (hw->adapter_state == HNS3_NIC_STARTED ||
2562 hw->adapter_state == HNS3_NIC_STOPPING) {
2563 hns3_enable_all_queues(hw, false);
2564 hns3vf_do_stop(hns);
2565 hw->reset.mbuf_deferred_free = true;
2567 hw->reset.mbuf_deferred_free = false;
2570 * It is cumbersome for hardware to pick-and-choose entries for deletion
2571 * from table space. Hence, for function reset software intervention is
2572 * required to delete the entries.
2574 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2575 hns3vf_configure_all_mc_mac_addr(hns, true);
2576 rte_spinlock_unlock(&hw->lock);
2582 hns3vf_start_service(struct hns3_adapter *hns)
2584 struct hns3_hw *hw = &hns->hw;
2585 struct rte_eth_dev *eth_dev;
2587 eth_dev = &rte_eth_devices[hw->data->port_id];
2588 hns3_set_rxtx_function(eth_dev);
2589 hns3_mp_req_start_rxtx(eth_dev);
2590 if (hw->adapter_state == HNS3_NIC_STARTED) {
2591 hns3vf_start_poll_job(eth_dev);
2593 /* Enable interrupt of all rx queues before enabling queues */
2594 hns3_dev_all_rx_queue_intr_enable(hw, true);
2596 * Enable state of each rxq and txq will be recovered after
2597 * reset, so we need to restore them before enable all tqps;
2599 hns3_restore_tqp_enable_state(hw);
2601 * When finished the initialization, enable queues to receive
2602 * and transmit packets.
2604 hns3_enable_all_queues(hw, true);
2611 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2613 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2614 struct rte_ether_addr *hw_mac;
2618 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2619 * on the host by "ip link set ..." command. If the hns3 PF kernel
2620 * ethdev driver sets the MAC address for VF device after the
2621 * initialization of the related VF device, the PF driver will notify
2622 * VF driver to reset VF device to make the new MAC address effective
2623 * immediately. The hns3 VF PMD driver should check whether the MAC
2624 * address has been changed by the PF kernel ethdev driver, if changed
2625 * VF driver should configure hardware using the new MAC address in the
2626 * recovering hardware configuration stage of the reset process.
2628 ret = hns3vf_get_host_mac_addr(hw);
2632 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2633 ret = rte_is_zero_ether_addr(hw_mac);
2635 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2637 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2639 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2640 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2641 &hw->data->mac_addrs[0]);
2642 hns3_warn(hw, "Default MAC address has been changed to:"
2643 " %s by the host PF kernel ethdev driver",
2652 hns3vf_restore_conf(struct hns3_adapter *hns)
2654 struct hns3_hw *hw = &hns->hw;
2657 ret = hns3vf_check_default_mac_change(hw);
2661 ret = hns3vf_configure_mac_addr(hns, false);
2665 ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2669 ret = hns3vf_restore_promisc(hns);
2671 goto err_vlan_table;
2673 ret = hns3vf_restore_vlan_conf(hns);
2675 goto err_vlan_table;
2677 ret = hns3vf_get_port_base_vlan_filter_state(hw);
2679 goto err_vlan_table;
2681 ret = hns3vf_restore_rx_interrupt(hw);
2683 goto err_vlan_table;
2685 ret = hns3_restore_gro_conf(hw);
2687 goto err_vlan_table;
2689 if (hw->adapter_state == HNS3_NIC_STARTED) {
2690 ret = hns3vf_do_start(hns, false);
2692 goto err_vlan_table;
2693 hns3_info(hw, "hns3vf dev restart successful!");
2694 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2695 hw->adapter_state = HNS3_NIC_CONFIGURED;
2697 ret = hns3vf_set_alive(hw, true);
2699 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2700 goto err_vlan_table;
2706 hns3vf_configure_all_mc_mac_addr(hns, true);
2708 hns3vf_configure_mac_addr(hns, true);
2712 static enum hns3_reset_level
2713 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2715 enum hns3_reset_level reset_level;
2717 /* return the highest priority reset level amongst all */
2718 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2719 reset_level = HNS3_VF_RESET;
2720 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2721 reset_level = HNS3_VF_FULL_RESET;
2722 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2723 reset_level = HNS3_VF_PF_FUNC_RESET;
2724 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2725 reset_level = HNS3_VF_FUNC_RESET;
2726 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2727 reset_level = HNS3_FLR_RESET;
2729 reset_level = HNS3_NONE_RESET;
2731 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2732 return HNS3_NONE_RESET;
2738 hns3vf_reset_service(void *param)
2740 struct hns3_adapter *hns = (struct hns3_adapter *)param;
2741 struct hns3_hw *hw = &hns->hw;
2742 enum hns3_reset_level reset_level;
2743 struct timeval tv_delta;
2744 struct timeval tv_start;
2749 * The interrupt is not triggered within the delay time.
2750 * The interrupt may have been lost. It is necessary to handle
2751 * the interrupt to recover from the error.
2753 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2754 SCHEDULE_DEFERRED) {
2755 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2757 hns3_err(hw, "Handling interrupts in delayed tasks");
2758 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2759 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2760 if (reset_level == HNS3_NONE_RESET) {
2761 hns3_err(hw, "No reset level is set, try global reset");
2762 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2765 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2768 * Hardware reset has been notified, we now have to poll & check if
2769 * hardware has actually completed the reset sequence.
2771 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2772 if (reset_level != HNS3_NONE_RESET) {
2773 hns3_clock_gettime(&tv_start);
2774 hns3_reset_process(hns, reset_level);
2775 hns3_clock_gettime(&tv);
2776 timersub(&tv, &tv_start, &tv_delta);
2777 msec = hns3_clock_calctime_ms(&tv_delta);
2778 if (msec > HNS3_RESET_PROCESS_MS)
2779 hns3_err(hw, "%d handle long time delta %" PRIu64
2780 " ms time=%ld.%.6ld",
2781 hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2786 hns3vf_reinit_dev(struct hns3_adapter *hns)
2788 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2789 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2790 struct hns3_hw *hw = &hns->hw;
2793 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2794 rte_intr_disable(pci_dev->intr_handle);
2795 ret = hns3vf_set_bus_master(pci_dev, true);
2797 hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2802 /* Firmware command initialize */
2803 ret = hns3_cmd_init(hw);
2805 hns3_err(hw, "Failed to init cmd: %d", ret);
2809 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2811 * UIO enables msix by writing the pcie configuration space
2812 * vfio_pci enables msix in rte_intr_enable.
2814 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2815 pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2816 if (hns3vf_enable_msix(pci_dev, true))
2817 hns3_err(hw, "Failed to enable msix");
2820 rte_intr_enable(pci_dev->intr_handle);
2823 ret = hns3_reset_all_tqps(hns);
2825 hns3_err(hw, "Failed to reset all queues: %d", ret);
2829 ret = hns3vf_init_hardware(hns);
2831 hns3_err(hw, "Failed to init hardware: %d", ret);
2838 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2839 .dev_configure = hns3vf_dev_configure,
2840 .dev_start = hns3vf_dev_start,
2841 .dev_stop = hns3vf_dev_stop,
2842 .dev_close = hns3vf_dev_close,
2843 .mtu_set = hns3vf_dev_mtu_set,
2844 .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2845 .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2846 .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2847 .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2848 .stats_get = hns3_stats_get,
2849 .stats_reset = hns3_stats_reset,
2850 .xstats_get = hns3_dev_xstats_get,
2851 .xstats_get_names = hns3_dev_xstats_get_names,
2852 .xstats_reset = hns3_dev_xstats_reset,
2853 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
2854 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2855 .dev_infos_get = hns3vf_dev_infos_get,
2856 .fw_version_get = hns3vf_fw_version_get,
2857 .rx_queue_setup = hns3_rx_queue_setup,
2858 .tx_queue_setup = hns3_tx_queue_setup,
2859 .rx_queue_release = hns3_dev_rx_queue_release,
2860 .tx_queue_release = hns3_dev_tx_queue_release,
2861 .rx_queue_start = hns3_dev_rx_queue_start,
2862 .rx_queue_stop = hns3_dev_rx_queue_stop,
2863 .tx_queue_start = hns3_dev_tx_queue_start,
2864 .tx_queue_stop = hns3_dev_tx_queue_stop,
2865 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
2866 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
2867 .rxq_info_get = hns3_rxq_info_get,
2868 .txq_info_get = hns3_txq_info_get,
2869 .rx_burst_mode_get = hns3_rx_burst_mode_get,
2870 .tx_burst_mode_get = hns3_tx_burst_mode_get,
2871 .mac_addr_add = hns3vf_add_mac_addr,
2872 .mac_addr_remove = hns3vf_remove_mac_addr,
2873 .mac_addr_set = hns3vf_set_default_mac_addr,
2874 .set_mc_addr_list = hns3vf_set_mc_mac_addr_list,
2875 .link_update = hns3vf_dev_link_update,
2876 .rss_hash_update = hns3_dev_rss_hash_update,
2877 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
2878 .reta_update = hns3_dev_rss_reta_update,
2879 .reta_query = hns3_dev_rss_reta_query,
2880 .flow_ops_get = hns3_dev_flow_ops_get,
2881 .vlan_filter_set = hns3vf_vlan_filter_set,
2882 .vlan_offload_set = hns3vf_vlan_offload_set,
2883 .get_reg = hns3_get_regs,
2884 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2885 .tx_done_cleanup = hns3_tx_done_cleanup,
2888 static const struct hns3_reset_ops hns3vf_reset_ops = {
2889 .reset_service = hns3vf_reset_service,
2890 .stop_service = hns3vf_stop_service,
2891 .prepare_reset = hns3vf_prepare_reset,
2892 .wait_hardware_ready = hns3vf_wait_hardware_ready,
2893 .reinit_dev = hns3vf_reinit_dev,
2894 .restore_conf = hns3vf_restore_conf,
2895 .start_service = hns3vf_start_service,
2899 hns3vf_init_hw_ops(struct hns3_hw *hw)
2901 hw->ops.add_mc_mac_addr = hns3vf_add_mc_mac_addr;
2902 hw->ops.del_mc_mac_addr = hns3vf_remove_mc_mac_addr;
2903 hw->ops.add_uc_mac_addr = hns3vf_add_uc_mac_addr;
2904 hw->ops.del_uc_mac_addr = hns3vf_remove_uc_mac_addr;
2908 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2910 struct hns3_adapter *hns = eth_dev->data->dev_private;
2911 struct hns3_hw *hw = &hns->hw;
2914 PMD_INIT_FUNC_TRACE();
2916 hns3_flow_init(eth_dev);
2918 hns3_set_rxtx_function(eth_dev);
2919 eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2920 eth_dev->rx_queue_count = hns3_rx_queue_count;
2921 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2922 ret = hns3_mp_init_secondary();
2924 PMD_INIT_LOG(ERR, "Failed to init for secondary "
2925 "process, ret = %d", ret);
2926 goto err_mp_init_secondary;
2928 hw->secondary_cnt++;
2929 hns3_tx_push_init(eth_dev);
2933 ret = hns3_mp_init_primary();
2936 "Failed to init for primary process, ret = %d",
2938 goto err_mp_init_primary;
2941 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2943 hw->data = eth_dev->data;
2944 hns3_parse_devargs(eth_dev);
2946 ret = hns3_reset_init(hw);
2948 goto err_init_reset;
2949 hw->reset.ops = &hns3vf_reset_ops;
2951 hns3vf_init_hw_ops(hw);
2952 ret = hns3vf_init_vf(eth_dev);
2954 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2958 /* Allocate memory for storing MAC addresses */
2959 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2960 sizeof(struct rte_ether_addr) *
2961 HNS3_VF_UC_MACADDR_NUM, 0);
2962 if (eth_dev->data->mac_addrs == NULL) {
2963 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2964 "to store MAC addresses",
2965 sizeof(struct rte_ether_addr) *
2966 HNS3_VF_UC_MACADDR_NUM);
2968 goto err_rte_zmalloc;
2972 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2973 * on the host by "ip link set ..." command. To avoid some incorrect
2974 * scenes, for example, hns3 VF PMD driver fails to receive and send
2975 * packets after user configure the MAC address by using the
2976 * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2977 * address strategy as the hns3 kernel ethdev driver in the
2978 * initialization. If user configure a MAC address by the ip command
2979 * for VF device, then hns3 VF PMD driver will start with it, otherwise
2980 * start with a random MAC address in the initialization.
2982 if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2983 rte_eth_random_addr(hw->mac.mac_addr);
2984 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2985 ð_dev->data->mac_addrs[0]);
2987 hw->adapter_state = HNS3_NIC_INITIALIZED;
2989 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2991 hns3_err(hw, "Reschedule reset service after dev_init");
2992 hns3_schedule_reset(hns);
2994 /* IMP will wait ready flag before reset */
2995 hns3_notify_reset_ready(hw, false);
2997 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
3002 hns3vf_uninit_vf(eth_dev);
3005 rte_free(hw->reset.wait_data);
3008 hns3_mp_uninit_primary();
3010 err_mp_init_primary:
3011 err_mp_init_secondary:
3012 eth_dev->dev_ops = NULL;
3013 eth_dev->rx_pkt_burst = NULL;
3014 eth_dev->rx_descriptor_status = NULL;
3015 eth_dev->tx_pkt_burst = NULL;
3016 eth_dev->tx_pkt_prepare = NULL;
3017 eth_dev->tx_descriptor_status = NULL;
3023 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
3025 struct hns3_adapter *hns = eth_dev->data->dev_private;
3026 struct hns3_hw *hw = &hns->hw;
3028 PMD_INIT_FUNC_TRACE();
3030 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3033 if (hw->adapter_state < HNS3_NIC_CLOSING)
3034 hns3vf_dev_close(eth_dev);
3036 hw->adapter_state = HNS3_NIC_REMOVED;
3041 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3042 struct rte_pci_device *pci_dev)
3044 return rte_eth_dev_pci_generic_probe(pci_dev,
3045 sizeof(struct hns3_adapter),
3050 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
3052 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
3055 static const struct rte_pci_id pci_id_hns3vf_map[] = {
3056 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
3057 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
3058 { .vendor_id = 0, }, /* sentinel */
3061 static struct rte_pci_driver rte_hns3vf_pmd = {
3062 .id_table = pci_id_hns3vf_map,
3063 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3064 .probe = eth_hns3vf_pci_probe,
3065 .remove = eth_hns3vf_pci_remove,
3068 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
3069 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
3070 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
3071 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
3072 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
3073 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
3074 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
3075 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16_t> ");