drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
  48                                    __rte_unused int wait_to_complete);
  49
  50 /* set PCI bus mastering */
  51 static int
  52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  53 {
  54         uint16_t reg;
  55         int ret;
  56
  57         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  58         if (ret < 0) {
  59                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  60                              PCI_COMMAND);
  61                 return ret;
  62         }
  63
  64         if (op)
  65                 /* set the master bit */
  66                 reg |= PCI_COMMAND_MASTER;
  67         else
  68                 reg &= ~(PCI_COMMAND_MASTER);
  69
  70         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  71 }
  72
  73 /**
  74  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  75  * @cap: the capability
  76  *
  77  * Return the address of the given capability within the PCI capability list.
  78  */
  79 static int
  80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  81 {
  82 #define MAX_PCIE_CAPABILITY 48
  83         uint16_t status;
  84         uint8_t pos;
  85         uint8_t id;
  86         int ttl;
  87         int ret;
  88
  89         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  90         if (ret < 0) {
  91                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  92                 return 0;
  93         }
  94
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 100                                   PCI_CAPABILITY_LIST);
 101         if (ret < 0) {
 102                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 103                              PCI_CAPABILITY_LIST);
 104                 return 0;
 105         }
 106
 107         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 108                 ret = rte_pci_read_config(device, &id, sizeof(id),
 109                                           (pos + PCI_CAP_LIST_ID));
 110                 if (ret < 0) {
 111                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 112                                      (pos + PCI_CAP_LIST_ID));
 113                         break;
 114                 }
 115
 116                 if (id == 0xFF)
 117                         break;
 118
 119                 if (id == cap)
 120                         return (int)pos;
 121
 122                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 123                                           (pos + PCI_CAP_LIST_NEXT));
 124                 if (ret < 0) {
 125                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 126                                      (pos + PCI_CAP_LIST_NEXT));
 127                         break;
 128                 }
 129         }
 130         return 0;
 131 }
 132
 133 static int
 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 135 {
 136         uint16_t control;
 137         int pos;
 138         int ret;
 139
 140         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 141         if (pos) {
 142                 ret = rte_pci_read_config(device, &control, sizeof(control),
 143                                     (pos + PCI_MSIX_FLAGS));
 144                 if (ret < 0) {
 145                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 146                                      (pos + PCI_MSIX_FLAGS));
 147                         return -ENXIO;
 148                 }
 149
 150                 if (op)
 151                         control |= PCI_MSIX_FLAGS_ENABLE;
 152                 else
 153                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 154                 ret = rte_pci_write_config(device, &control, sizeof(control),
 155                                           (pos + PCI_MSIX_FLAGS));
 156                 if (ret < 0) {
 157                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 158                                     (pos + PCI_MSIX_FLAGS));
 159                         return -ENXIO;
 160                 }
 161
 162                 return 0;
 163         }
 164
 165         return -ENXIO;
 166 }
 167
 168 static int
 169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 170 {
 171         /* mac address was checked by upper level interface */
 172         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 173         int ret;
 174
 175         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 176                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 177                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 178         if (ret) {
 179                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 180                                       mac_addr);
 181                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 182                          mac_str, ret);
 183         }
 184         return ret;
 185 }
 186
 187 static int
 188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 189 {
 190         /* mac address was checked by upper level interface */
 191         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 192         int ret;
 193
 194         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 195                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 196                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 197                                 false, NULL, 0);
 198         if (ret) {
 199                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 200                                       mac_addr);
 201                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 202                          mac_str, ret);
 203         }
 204         return ret;
 205 }
 206
 207 static int
 208 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 209                     __rte_unused uint32_t idx,
 210                     __rte_unused uint32_t pool)
 211 {
 212         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 213         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 214         int ret;
 215
 216         rte_spinlock_lock(&hw->lock);
 217
 218         /*
 219          * In hns3 network engine adding UC and MC mac address with different
 220          * commands with firmware. We need to determine whether the input
 221          * address is a UC or a MC address to call different commands.
 222          * By the way, it is recommended calling the API function named
 223          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 224          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 225          * may affect the specifications of UC mac addresses.
 226          */
 227         if (rte_is_multicast_ether_addr(mac_addr)) {
 228                 if (hns3_find_duplicate_mc_addr(hw, mac_addr)) {
 229                         rte_spinlock_unlock(&hw->lock);
 230                         return -EINVAL;
 231                 }
 232                 ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 233         } else {
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235         }
 236
 237         rte_spinlock_unlock(&hw->lock);
 238         if (ret) {
 239                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 240                                       mac_addr);
 241                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 242                          ret);
 243         }
 244
 245         return ret;
 246 }
 247
 248 static void
 249 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 250 {
 251         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 252         /* index will be checked by upper level rte interface */
 253         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 254         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 255         int ret;
 256
 257         rte_spinlock_lock(&hw->lock);
 258
 259         if (rte_is_multicast_ether_addr(mac_addr))
 260                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 261         else
 262                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 263
 264         rte_spinlock_unlock(&hw->lock);
 265         if (ret) {
 266                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 267                                       mac_addr);
 268                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 269                          mac_str, ret);
 270         }
 271 }
 272
 273 static int
 274 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 275                             struct rte_ether_addr *mac_addr)
 276 {
 277 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 278         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 279         struct rte_ether_addr *old_addr;
 280         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 281         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 282         int ret;
 283
 284         /*
 285          * It has been guaranteed that input parameter named mac_addr is valid
 286          * address in the rte layer of DPDK framework.
 287          */
 288         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 289         rte_spinlock_lock(&hw->lock);
 290         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 291         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 292                RTE_ETHER_ADDR_LEN);
 293
 294         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 295                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 296                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 297         if (ret) {
 298                 /*
 299                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 300                  * driver. When user has configured a MAC address for VF device
 301                  * by "ip link set ..." command based on the PF device, the hns3
 302                  * PF kernel ethdev driver does not allow VF driver to request
 303                  * reconfiguring a different default MAC address, and return
 304                  * -EPREM to VF driver through mailbox.
 305                  */
 306                 if (ret == -EPERM) {
 307                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 308                                               old_addr);
 309                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 310                                   mac_str);
 311                 } else {
 312                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 313                                               mac_addr);
 314                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 315                                  mac_str, ret);
 316                 }
 317         }
 318
 319         rte_ether_addr_copy(mac_addr,
 320                             (struct rte_ether_addr *)hw->mac.mac_addr);
 321         rte_spinlock_unlock(&hw->lock);
 322
 323         return ret;
 324 }
 325
 326 static int
 327 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 328 {
 329         struct hns3_hw *hw = &hns->hw;
 330         struct rte_ether_addr *addr;
 331         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 332         int err = 0;
 333         int ret;
 334         int i;
 335
 336         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 337                 addr = &hw->data->mac_addrs[i];
 338                 if (rte_is_zero_ether_addr(addr))
 339                         continue;
 340                 if (rte_is_multicast_ether_addr(addr))
 341                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 342                               hns3vf_add_mc_mac_addr(hw, addr);
 343                 else
 344                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 345                               hns3vf_add_uc_mac_addr(hw, addr);
 346
 347                 if (ret) {
 348                         err = ret;
 349                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 350                                               addr);
 351                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 352                                  "ret = %d.", del ? "remove" : "restore",
 353                                  mac_str, i, ret);
 354                 }
 355         }
 356         return err;
 357 }
 358
 359 static int
 360 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 361                        struct rte_ether_addr *mac_addr)
 362 {
 363         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 364         int ret;
 365
 366         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 367                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 368                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 369                                 NULL, 0);
 370         if (ret) {
 371                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 372                                       mac_addr);
 373                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 374                          mac_str, ret);
 375         }
 376
 377         return ret;
 378 }
 379
 380 static int
 381 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 382                           struct rte_ether_addr *mac_addr)
 383 {
 384         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 385         int ret;
 386
 387         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 388                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 389                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 390                                 NULL, 0);
 391         if (ret) {
 392                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 393                                       mac_addr);
 394                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 395                          mac_str, ret);
 396         }
 397
 398         return ret;
 399 }
 400
 401 static int
 402 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 403                              struct rte_ether_addr *mc_addr_set,
 404                              uint32_t nb_mc_addr)
 405 {
 406         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 407         struct rte_ether_addr *addr;
 408         uint32_t i;
 409         uint32_t j;
 410
 411         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 412                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
 413                          "invalid. valid range: 0~%d",
 414                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 415                 return -EINVAL;
 416         }
 417
 418         /* Check if input mac addresses are valid */
 419         for (i = 0; i < nb_mc_addr; i++) {
 420                 addr = &mc_addr_set[i];
 421                 if (!rte_is_multicast_ether_addr(addr)) {
 422                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 423                                               addr);
 424                         hns3_err(hw,
 425                                  "failed to set mc mac addr, addr(%s) invalid.",
 426                                  mac_str);
 427                         return -EINVAL;
 428                 }
 429
 430                 /* Check if there are duplicate addresses */
 431                 for (j = i + 1; j < nb_mc_addr; j++) {
 432                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 433                                 hns3_ether_format_addr(mac_str,
 434                                                       RTE_ETHER_ADDR_FMT_SIZE,
 435                                                       addr);
 436                                 hns3_err(hw, "failed to set mc mac addr, "
 437                                          "addrs invalid. two same addrs(%s).",
 438                                          mac_str);
 439                                 return -EINVAL;
 440                         }
 441                 }
 442
 443                 /*
 444                  * Check if there are duplicate addresses between mac_addrs
 445                  * and mc_addr_set
 446                  */
 447                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 448                         if (rte_is_same_ether_addr(addr,
 449                                                    &hw->data->mac_addrs[j])) {
 450                                 hns3_ether_format_addr(mac_str,
 451                                                       RTE_ETHER_ADDR_FMT_SIZE,
 452                                                       addr);
 453                                 hns3_err(hw, "failed to set mc mac addr, "
 454                                          "addrs invalid. addrs(%s) has already "
 455                                          "configured in mac_addr add API",
 456                                          mac_str);
 457                                 return -EINVAL;
 458                         }
 459                 }
 460         }
 461
 462         return 0;
 463 }
 464
 465 static int
 466 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 467                             struct rte_ether_addr *mc_addr_set,
 468                             uint32_t nb_mc_addr)
 469 {
 470         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 471         struct rte_ether_addr *addr;
 472         int cur_addr_num;
 473         int set_addr_num;
 474         int num;
 475         int ret;
 476         int i;
 477
 478         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 479         if (ret)
 480                 return ret;
 481
 482         rte_spinlock_lock(&hw->lock);
 483         cur_addr_num = hw->mc_addrs_num;
 484         for (i = 0; i < cur_addr_num; i++) {
 485                 num = cur_addr_num - i - 1;
 486                 addr = &hw->mc_addrs[num];
 487                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 488                 if (ret) {
 489                         rte_spinlock_unlock(&hw->lock);
 490                         return ret;
 491                 }
 492
 493                 hw->mc_addrs_num--;
 494         }
 495
 496         set_addr_num = (int)nb_mc_addr;
 497         for (i = 0; i < set_addr_num; i++) {
 498                 addr = &mc_addr_set[i];
 499                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 500                 if (ret) {
 501                         rte_spinlock_unlock(&hw->lock);
 502                         return ret;
 503                 }
 504
 505                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 506                 hw->mc_addrs_num++;
 507         }
 508         rte_spinlock_unlock(&hw->lock);
 509
 510         return 0;
 511 }
 512
 513 static int
 514 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 515 {
 516         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 517         struct hns3_hw *hw = &hns->hw;
 518         struct rte_ether_addr *addr;
 519         int err = 0;
 520         int ret;
 521         int i;
 522
 523         for (i = 0; i < hw->mc_addrs_num; i++) {
 524                 addr = &hw->mc_addrs[i];
 525                 if (!rte_is_multicast_ether_addr(addr))
 526                         continue;
 527                 if (del)
 528                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 529                 else
 530                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 531                 if (ret) {
 532                         err = ret;
 533                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 534                                               addr);
 535                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 536                                  del ? "Remove" : "Restore", mac_str, ret);
 537                 }
 538         }
 539         return err;
 540 }
 541
 542 static int
 543 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 544                         bool en_uc_pmc, bool en_mc_pmc)
 545 {
 546         struct hns3_mbx_vf_to_pf_cmd *req;
 547         struct hns3_cmd_desc desc;
 548         int ret;
 549
 550         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 551
 552         /*
 553          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 554          * so there are some features for promiscuous/allmulticast mode in hns3
 555          * VF PMD driver as below:
 556          * 1. The promiscuous/allmulticast mode can be configured successfully
 557          *    only based on the trusted VF device. If based on the non trusted
 558          *    VF device, configuring promiscuous/allmulticast mode will fail.
 559          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 560          *    kernel ethdev driver on the host by the following command:
 561          *      "ip link set <eth num> vf <vf id> turst on"
 562          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 563          *    driver can receive the ingress and outgoing traffic. In the words,
 564          *    all the ingress packets, all the packets sent from the PF and
 565          *    other VFs on the same physical port.
 566          * 3. Note: Because of the hardware constraints, By default vlan filter
 567          *    is enabled and couldn't be turned off based on VF device, so vlan
 568          *    filter is still effective even in promiscuous mode. If upper
 569          *    applications don't call rte_eth_dev_vlan_filter API function to
 570          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 571          *    the packets with vlan tag in promiscuoue mode.
 572          */
 573         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 574         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 575         req->msg[1] = en_bc_pmc ? 1 : 0;
 576         req->msg[2] = en_uc_pmc ? 1 : 0;
 577         req->msg[3] = en_mc_pmc ? 1 : 0;
 578         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 579
 580         ret = hns3_cmd_send(hw, &desc, 1);
 581         if (ret)
 582                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 583
 584         return ret;
 585 }
 586
 587 static int
 588 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 589 {
 590         struct hns3_adapter *hns = dev->data->dev_private;
 591         struct hns3_hw *hw = &hns->hw;
 592         int ret;
 593
 594         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 595         if (ret)
 596                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 597                         ret);
 598         return ret;
 599 }
 600
 601 static int
 602 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 603 {
 604         bool allmulti = dev->data->all_multicast ? true : false;
 605         struct hns3_adapter *hns = dev->data->dev_private;
 606         struct hns3_hw *hw = &hns->hw;
 607         int ret;
 608
 609         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 610         if (ret)
 611                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 612                         ret);
 613         return ret;
 614 }
 615
 616 static int
 617 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 618 {
 619         struct hns3_adapter *hns = dev->data->dev_private;
 620         struct hns3_hw *hw = &hns->hw;
 621         int ret;
 622
 623         if (dev->data->promiscuous)
 624                 return 0;
 625
 626         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 627         if (ret)
 628                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 629                         ret);
 630         return ret;
 631 }
 632
 633 static int
 634 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 635 {
 636         struct hns3_adapter *hns = dev->data->dev_private;
 637         struct hns3_hw *hw = &hns->hw;
 638         int ret;
 639
 640         if (dev->data->promiscuous)
 641                 return 0;
 642
 643         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 644         if (ret)
 645                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 646                         ret);
 647         return ret;
 648 }
 649
 650 static int
 651 hns3vf_restore_promisc(struct hns3_adapter *hns)
 652 {
 653         struct hns3_hw *hw = &hns->hw;
 654         bool allmulti = hw->data->all_multicast ? true : false;
 655
 656         if (hw->data->promiscuous)
 657                 return hns3vf_set_promisc_mode(hw, true, true, true);
 658
 659         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 660 }
 661
 662 static int
 663 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 664                              bool mmap, enum hns3_ring_type queue_type,
 665                              uint16_t queue_id)
 666 {
 667         struct hns3_vf_bind_vector_msg bind_msg;
 668         const char *op_str;
 669         uint16_t code;
 670         int ret;
 671
 672         memset(&bind_msg, 0, sizeof(bind_msg));
 673         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 674                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 675         bind_msg.vector_id = vector_id;
 676
 677         if (queue_type == HNS3_RING_TYPE_RX)
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 679         else
 680                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 681
 682         bind_msg.param[0].ring_type = queue_type;
 683         bind_msg.ring_num = 1;
 684         bind_msg.param[0].tqp_index = queue_id;
 685         op_str = mmap ? "Map" : "Unmap";
 686         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 687                                 sizeof(bind_msg), false, NULL, 0);
 688         if (ret)
 689                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 690                          op_str, queue_id, bind_msg.vector_id, ret);
 691
 692         return ret;
 693 }
 694
 695 static int
 696 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 697 {
 698         uint16_t vec;
 699         int ret;
 700         int i;
 701
 702         /*
 703          * In hns3 network engine, vector 0 is always the misc interrupt of this
 704          * function, vector 1~N can be used respectively for the queues of the
 705          * function. Tx and Rx queues with the same number share the interrupt
 706          * vector. In the initialization clearing the all hardware mapping
 707          * relationship configurations between queues and interrupt vectors is
 708          * needed, so some error caused by the residual configurations, such as
 709          * the unexpected Tx interrupt, can be avoid.
 710          */
 711         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 712         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 713                 vec = vec - 1; /* the last interrupt is reserved */
 714         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 715         for (i = 0; i < hw->intr_tqps_num; i++) {
 716                 /*
 717                  * Set gap limiter/rate limiter/quanity limiter algorithm
 718                  * configuration for interrupt coalesce of queue's interrupt.
 719                  */
 720                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 721                                        HNS3_TQP_INTR_GL_DEFAULT);
 722                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 723                                        HNS3_TQP_INTR_GL_DEFAULT);
 724                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 725                 /*
 726                  * QL(quantity limiter) is not used currently, just set 0 to
 727                  * close it.
 728                  */
 729                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 730
 731                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 732                                                    HNS3_RING_TYPE_TX, i);
 733                 if (ret) {
 734                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 735                                           "vector: %u, ret=%d", i, vec, ret);
 736                         return ret;
 737                 }
 738
 739                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 740                                                    HNS3_RING_TYPE_RX, i);
 741                 if (ret) {
 742                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 743                                           "vector: %u, ret=%d", i, vec, ret);
 744                         return ret;
 745                 }
 746         }
 747
 748         return 0;
 749 }
 750
 751 static int
 752 hns3vf_dev_configure(struct rte_eth_dev *dev)
 753 {
 754         struct hns3_adapter *hns = dev->data->dev_private;
 755         struct hns3_hw *hw = &hns->hw;
 756         struct rte_eth_conf *conf = &dev->data->dev_conf;
 757         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 758         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 759         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 760         struct rte_eth_rss_conf rss_conf;
 761         bool gro_en;
 762         int ret;
 763
 764         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 765
 766         /*
 767          * Some versions of hardware network engine does not support
 768          * individually enable/disable/reset the Tx or Rx queue. These devices
 769          * must enable/disable/reset Tx and Rx queues at the same time. When the
 770          * numbers of Tx queues allocated by upper applications are not equal to
 771          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 772          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 773          * work as usual. But these fake queues are imperceptible, and can not
 774          * be used by upper applications.
 775          */
 776         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 777         if (ret) {
 778                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
 779                 hw->cfg_max_queues = 0;
 780                 return ret;
 781         }
 782
 783         hw->adapter_state = HNS3_NIC_CONFIGURING;
 784         if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
 785                 hns3_err(hw, "setting link speed/duplex not supported");
 786                 ret = -EINVAL;
 787                 goto cfg_err;
 788         }
 789
 790         /* When RSS is not configured, redirect the packet queue 0 */
 791         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
 792                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
 793                 hw->rss_dis_flag = false;
 794                 rss_conf = conf->rx_adv_conf.rss_conf;
 795                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 796                 if (ret)
 797                         goto cfg_err;
 798         }
 799
 800         ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
 801         if (ret != 0)
 802                 goto cfg_err;
 803
 804         ret = hns3vf_dev_configure_vlan(dev);
 805         if (ret)
 806                 goto cfg_err;
 807
 808         /* config hardware GRO */
 809         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
 810         ret = hns3_config_gro(hw, gro_en);
 811         if (ret)
 812                 goto cfg_err;
 813
 814         hns3_init_rx_ptype_tble(dev);
 815
 816         hw->adapter_state = HNS3_NIC_CONFIGURED;
 817         return 0;
 818
 819 cfg_err:
 820         hw->cfg_max_queues = 0;
 821         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 822         hw->adapter_state = HNS3_NIC_INITIALIZED;
 823
 824         return ret;
 825 }
 826
 827 static int
 828 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 829 {
 830         int ret;
 831
 832         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 833                                 sizeof(mtu), true, NULL, 0);
 834         if (ret)
 835                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 836
 837         return ret;
 838 }
 839
 840 static int
 841 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 842 {
 843         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 844         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 845         int ret;
 846
 847         /*
 848          * The hns3 PF/VF devices on the same port share the hardware MTU
 849          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 850          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 851          * driver, there is no need to stop the port for hns3 VF device, and the
 852          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 853          * PF's MTU.
 854          */
 855         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 856                 hns3_err(hw, "Failed to set mtu during resetting");
 857                 return -EIO;
 858         }
 859
 860         /*
 861          * when Rx of scattered packets is off, we have some possibility of
 862          * using vector Rx process function or simple Rx functions in hns3 PMD
 863          * driver. If the input MTU is increased and the maximum length of
 864          * received packets is greater than the length of a buffer for Rx
 865          * packet, the hardware network engine needs to use multiple BDs and
 866          * buffers to store these packets. This will cause problems when still
 867          * using vector Rx process function or simple Rx function to receiving
 868          * packets. So, when Rx of scattered packets is off and device is
 869          * started, it is not permitted to increase MTU so that the maximum
 870          * length of Rx packets is greater than Rx buffer length.
 871          */
 872         if (dev->data->dev_started && !dev->data->scattered_rx &&
 873             frame_size > hw->rx_buf_len) {
 874                 hns3_err(hw, "failed to set mtu because current is "
 875                         "not scattered rx mode");
 876                 return -EOPNOTSUPP;
 877         }
 878
 879         rte_spinlock_lock(&hw->lock);
 880         ret = hns3vf_config_mtu(hw, mtu);
 881         if (ret) {
 882                 rte_spinlock_unlock(&hw->lock);
 883                 return ret;
 884         }
 885         rte_spinlock_unlock(&hw->lock);
 886
 887         return 0;
 888 }
 889
 890 static int
 891 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 892 {
 893         struct hns3_adapter *hns = eth_dev->data->dev_private;
 894         struct hns3_hw *hw = &hns->hw;
 895         uint16_t q_num = hw->tqps_num;
 896
 897         /*
 898          * In interrupt mode, 'max_rx_queues' is set based on the number of
 899          * MSI-X interrupt resources of the hardware.
 900          */
 901         if (hw->data->dev_conf.intr_conf.rxq == 1)
 902                 q_num = hw->intr_tqps_num;
 903
 904         info->max_rx_queues = q_num;
 905         info->max_tx_queues = hw->tqps_num;
 906         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 907         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 908         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 909         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 910         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 911
 912         info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
 913                                  RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
 914                                  RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
 915                                  RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
 916                                  RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 917                                  RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
 918                                  RTE_ETH_RX_OFFLOAD_SCATTER |
 919                                  RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
 920                                  RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
 921                                  RTE_ETH_RX_OFFLOAD_RSS_HASH |
 922                                  RTE_ETH_RX_OFFLOAD_TCP_LRO);
 923         info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 924                                  RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
 925                                  RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
 926                                  RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
 927                                  RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
 928                                  RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
 929                                  RTE_ETH_TX_OFFLOAD_TCP_TSO |
 930                                  RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
 931                                  RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
 932                                  RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
 933                                  RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
 934                                  hns3_txvlan_cap_get(hw));
 935
 936         if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
 937                 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
 938
 939         if (hns3_dev_get_support(hw, INDEP_TXRX))
 940                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 941                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 942
 943         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 944                 .nb_max = HNS3_MAX_RING_DESC,
 945                 .nb_min = HNS3_MIN_RING_DESC,
 946                 .nb_align = HNS3_ALIGN_RING_DESC,
 947         };
 948
 949         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 950                 .nb_max = HNS3_MAX_RING_DESC,
 951                 .nb_min = HNS3_MIN_RING_DESC,
 952                 .nb_align = HNS3_ALIGN_RING_DESC,
 953                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 954                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
 955         };
 956
 957         info->default_rxconf = (struct rte_eth_rxconf) {
 958                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 959                 /*
 960                  * If there are no available Rx buffer descriptors, incoming
 961                  * packets are always dropped by hardware based on hns3 network
 962                  * engine.
 963                  */
 964                 .rx_drop_en = 1,
 965                 .offloads = 0,
 966         };
 967         info->default_txconf = (struct rte_eth_txconf) {
 968                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 969                 .offloads = 0,
 970         };
 971
 972         info->reta_size = hw->rss_ind_tbl_size;
 973         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 974         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 975
 976         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 977         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 978         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 979         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 980         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 981         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 982
 983         return 0;
 984 }
 985
 986 static void
 987 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 988 {
 989         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 990 }
 991
 992 static void
 993 hns3vf_disable_irq0(struct hns3_hw *hw)
 994 {
 995         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 996 }
 997
 998 static void
 999 hns3vf_enable_irq0(struct hns3_hw *hw)
1000 {
1001         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1002 }
1003
1004 static enum hns3vf_evt_cause
1005 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1006 {
1007         struct hns3_hw *hw = &hns->hw;
1008         enum hns3vf_evt_cause ret;
1009         uint32_t cmdq_stat_reg;
1010         uint32_t rst_ing_reg;
1011         uint32_t val;
1012
1013         /* Fetch the events from their corresponding regs */
1014         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1015         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1016                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1017                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1018                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1019                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
1020                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1021                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1022                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1023                 if (clearval) {
1024                         hw->reset.stats.global_cnt++;
1025                         hns3_warn(hw, "Global reset detected, clear reset status");
1026                 } else {
1027                         hns3_schedule_delayed_reset(hns);
1028                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1029                 }
1030
1031                 ret = HNS3VF_VECTOR0_EVENT_RST;
1032                 goto out;
1033         }
1034
1035         /* Check for vector0 mailbox(=CMDQ RX) event source */
1036         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1037                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1038                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1039                 goto out;
1040         }
1041
1042         val = 0;
1043         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1044 out:
1045         if (clearval)
1046                 *clearval = val;
1047         return ret;
1048 }
1049
1050 static void
1051 hns3vf_interrupt_handler(void *param)
1052 {
1053         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1054         struct hns3_adapter *hns = dev->data->dev_private;
1055         struct hns3_hw *hw = &hns->hw;
1056         enum hns3vf_evt_cause event_cause;
1057         uint32_t clearval;
1058
1059         /* Disable interrupt */
1060         hns3vf_disable_irq0(hw);
1061
1062         /* Read out interrupt causes */
1063         event_cause = hns3vf_check_event_cause(hns, &clearval);
1064         /* Clear interrupt causes */
1065         hns3vf_clear_event_cause(hw, clearval);
1066
1067         switch (event_cause) {
1068         case HNS3VF_VECTOR0_EVENT_RST:
1069                 hns3_schedule_reset(hns);
1070                 break;
1071         case HNS3VF_VECTOR0_EVENT_MBX:
1072                 hns3_dev_handle_mbx_msg(hw);
1073                 break;
1074         default:
1075                 break;
1076         }
1077
1078         /* Enable interrupt */
1079         hns3vf_enable_irq0(hw);
1080 }
1081
1082 static void
1083 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1084 {
1085         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1086         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1087         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1088         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1089 }
1090
1091 static void
1092 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1093 {
1094         struct hns3_dev_specs_0_cmd *req0;
1095
1096         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1097
1098         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1099         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1100         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1101         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1102 }
1103
1104 static int
1105 hns3vf_check_dev_specifications(struct hns3_hw *hw)
1106 {
1107         if (hw->rss_ind_tbl_size == 0 ||
1108             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
1109                 hns3_warn(hw, "the size of hash lookup table configured (%u)"
1110                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
1111                               HNS3_RSS_IND_TBL_SIZE_MAX);
1112                 return -EINVAL;
1113         }
1114
1115         return 0;
1116 }
1117
1118 static int
1119 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1120 {
1121         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1122         int ret;
1123         int i;
1124
1125         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1126                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1127                                           true);
1128                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1129         }
1130         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1131
1132         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1133         if (ret)
1134                 return ret;
1135
1136         hns3vf_parse_dev_specifications(hw, desc);
1137
1138         return hns3vf_check_dev_specifications(hw);
1139 }
1140
1141 void
1142 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
1143 {
1144         uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
1145                                    HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1146         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1147         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1148
1149         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1150                 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1151                                           __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1152 }
1153
1154 static void
1155 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
1156 {
1157 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS      500
1158
1159         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1160         int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
1161         uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1162         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1163         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1164
1165         __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
1166                          __ATOMIC_RELEASE);
1167
1168         (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1169                                 NULL, 0);
1170
1171         while (remain_ms > 0) {
1172                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
1173                 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
1174                         HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1175                         break;
1176                 remain_ms--;
1177         }
1178
1179         /*
1180          * When exit above loop, the pf_push_lsc_cap could be one of the three
1181          * state: unknown (means pf not ack), not_supported, supported.
1182          * Here config it as 'not_supported' when it's 'unknown' state.
1183          */
1184         __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1185                                   __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1186
1187         if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
1188                 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
1189                 hns3_info(hw, "detect PF support push link status change!");
1190         } else {
1191                 /*
1192                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
1193                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
1194                  * the RTE_ETH_DEV_INTR_LSC capability.
1195                  */
1196                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1197         }
1198 }
1199
1200 static int
1201 hns3vf_get_capability(struct hns3_hw *hw)
1202 {
1203         struct rte_pci_device *pci_dev;
1204         struct rte_eth_dev *eth_dev;
1205         uint8_t revision;
1206         int ret;
1207
1208         eth_dev = &rte_eth_devices[hw->data->port_id];
1209         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1210
1211         /* Get PCI revision id */
1212         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1213                                   HNS3_PCI_REVISION_ID);
1214         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1215                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1216                              ret);
1217                 return -EIO;
1218         }
1219         hw->revision = revision;
1220
1221         if (revision < PCI_REVISION_ID_HIP09_A) {
1222                 hns3vf_set_default_dev_specifications(hw);
1223                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1224                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1225                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1226                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
1227                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1228                 hw->rss_info.ipv6_sctp_offload_supported = false;
1229                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1230                 return 0;
1231         }
1232
1233         ret = hns3vf_query_dev_specifications(hw);
1234         if (ret) {
1235                 PMD_INIT_LOG(ERR,
1236                              "failed to query dev specifications, ret = %d",
1237                              ret);
1238                 return ret;
1239         }
1240
1241         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1242         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1243         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1244         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1245         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1246         hw->rss_info.ipv6_sctp_offload_supported = true;
1247         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1248
1249         return 0;
1250 }
1251
1252 static int
1253 hns3vf_check_tqp_info(struct hns3_hw *hw)
1254 {
1255         if (hw->tqps_num == 0) {
1256                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1257                 return -EINVAL;
1258         }
1259
1260         if (hw->rss_size_max == 0) {
1261                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1262                 return -EINVAL;
1263         }
1264
1265         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1266
1267         return 0;
1268 }
1269
1270 static int
1271 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1272 {
1273         uint8_t resp_msg;
1274         int ret;
1275
1276         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1277                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1278                                 true, &resp_msg, sizeof(resp_msg));
1279         if (ret) {
1280                 if (ret == -ETIME) {
1281                         /*
1282                          * Getting current port based VLAN state from PF driver
1283                          * will not affect VF driver's basic function. Because
1284                          * the VF driver relies on hns3 PF kernel ether driver,
1285                          * to avoid introducing compatibility issues with older
1286                          * version of PF driver, no failure will be returned
1287                          * when the return value is ETIME. This return value has
1288                          * the following scenarios:
1289                          * 1) Firmware didn't return the results in time
1290                          * 2) the result return by firmware is timeout
1291                          * 3) the older version of kernel side PF driver does
1292                          *    not support this mailbox message.
1293                          * For scenarios 1 and 2, it is most likely that a
1294                          * hardware error has occurred, or a hardware reset has
1295                          * occurred. In this case, these errors will be caught
1296                          * by other functions.
1297                          */
1298                         PMD_INIT_LOG(WARNING,
1299                                 "failed to get PVID state for timeout, maybe "
1300                                 "kernel side PF driver doesn't support this "
1301                                 "mailbox message, or firmware didn't respond.");
1302                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1303                 } else {
1304                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1305                                 " ret = %d", ret);
1306                         return ret;
1307                 }
1308         }
1309         hw->port_base_vlan_cfg.state = resp_msg ?
1310                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1311         return 0;
1312 }
1313
1314 static int
1315 hns3vf_get_queue_info(struct hns3_hw *hw)
1316 {
1317 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1318         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1319         int ret;
1320
1321         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1322                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1323         if (ret) {
1324                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1325                 return ret;
1326         }
1327
1328         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1329         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1330
1331         return hns3vf_check_tqp_info(hw);
1332 }
1333
1334 static int
1335 hns3vf_get_queue_depth(struct hns3_hw *hw)
1336 {
1337 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1338         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1339         int ret;
1340
1341         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1342                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1343         if (ret) {
1344                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1345                              ret);
1346                 return ret;
1347         }
1348
1349         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1350         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1351
1352         return 0;
1353 }
1354
1355 static void
1356 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1357 {
1358         if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1359                 hns3_set_bit(hw->capability,
1360                                 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1361 }
1362
1363 static int
1364 hns3vf_get_num_tc(struct hns3_hw *hw)
1365 {
1366         uint8_t num_tc = 0;
1367         uint32_t i;
1368
1369         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1370                 if (hw->hw_tc_map & BIT(i))
1371                         num_tc++;
1372         }
1373         return num_tc;
1374 }
1375
1376 static int
1377 hns3vf_get_basic_info(struct hns3_hw *hw)
1378 {
1379         uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1380         struct hns3_basic_info *basic_info;
1381         int ret;
1382
1383         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1384                                 true, resp_msg, sizeof(resp_msg));
1385         if (ret) {
1386                 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1387                                 ret);
1388                 return ret;
1389         }
1390
1391         basic_info = (struct hns3_basic_info *)resp_msg;
1392         hw->hw_tc_map = basic_info->hw_tc_map;
1393         hw->num_tc = hns3vf_get_num_tc(hw);
1394         hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1395         hns3vf_update_caps(hw, basic_info->caps);
1396
1397         return 0;
1398 }
1399
1400 static int
1401 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1402 {
1403         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1404         int ret;
1405
1406         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1407                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1408         if (ret) {
1409                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1410                 return ret;
1411         }
1412
1413         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1414
1415         return 0;
1416 }
1417
1418 static int
1419 hns3vf_get_configuration(struct hns3_hw *hw)
1420 {
1421         int ret;
1422
1423         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1424         hw->rss_dis_flag = false;
1425
1426         /* Get device capability */
1427         ret = hns3vf_get_capability(hw);
1428         if (ret) {
1429                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1430                 return ret;
1431         }
1432
1433         hns3vf_get_push_lsc_cap(hw);
1434
1435         /* Get basic info from PF */
1436         ret = hns3vf_get_basic_info(hw);
1437         if (ret)
1438                 return ret;
1439
1440         /* Get queue configuration from PF */
1441         ret = hns3vf_get_queue_info(hw);
1442         if (ret)
1443                 return ret;
1444
1445         /* Get queue depth info from PF */
1446         ret = hns3vf_get_queue_depth(hw);
1447         if (ret)
1448                 return ret;
1449
1450         /* Get user defined VF MAC addr from PF */
1451         ret = hns3vf_get_host_mac_addr(hw);
1452         if (ret)
1453                 return ret;
1454
1455         return hns3vf_get_port_base_vlan_filter_state(hw);
1456 }
1457
1458 static int
1459 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1460                             uint16_t nb_tx_q)
1461 {
1462         struct hns3_hw *hw = &hns->hw;
1463
1464         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1465 }
1466
1467 static void
1468 hns3vf_request_link_info(struct hns3_hw *hw)
1469 {
1470         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1471         bool send_req;
1472         int ret;
1473
1474         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1475                 return;
1476
1477         send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1478                    vf->req_link_info_cnt > 0;
1479         if (!send_req)
1480                 return;
1481
1482         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1483                                 NULL, 0);
1484         if (ret) {
1485                 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1486                 return;
1487         }
1488
1489         if (vf->req_link_info_cnt > 0)
1490                 vf->req_link_info_cnt--;
1491 }
1492
1493 void
1494 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1495                           uint32_t link_speed, uint8_t link_duplex)
1496 {
1497         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1498         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1499         struct hns3_mac *mac = &hw->mac;
1500         int ret;
1501
1502         /*
1503          * PF kernel driver may push link status when VF driver is in resetting,
1504          * driver will stop polling job in this case, after resetting done
1505          * driver will start polling job again.
1506          * When polling job started, driver will get initial link status by
1507          * sending request to PF kernel driver, then could update link status by
1508          * process PF kernel driver's link status mailbox message.
1509          */
1510         if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1511                 return;
1512
1513         if (hw->adapter_state != HNS3_NIC_STARTED)
1514                 return;
1515
1516         mac->link_status = link_status;
1517         mac->link_speed = link_speed;
1518         mac->link_duplex = link_duplex;
1519         ret = hns3vf_dev_link_update(dev, 0);
1520         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1521                 hns3_start_report_lse(dev);
1522 }
1523
1524 static int
1525 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1526 {
1527 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1528         struct hns3_hw *hw = &hns->hw;
1529         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1530         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1531         uint8_t is_kill = on ? 0 : 1;
1532
1533         msg_data[0] = is_kill;
1534         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1535         memcpy(&msg_data[3], &proto, sizeof(proto));
1536
1537         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1538                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1539                                  0);
1540 }
1541
1542 static int
1543 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1544 {
1545         struct hns3_adapter *hns = dev->data->dev_private;
1546         struct hns3_hw *hw = &hns->hw;
1547         int ret;
1548
1549         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1550                 hns3_err(hw,
1551                          "vf set vlan id failed during resetting, vlan_id =%u",
1552                          vlan_id);
1553                 return -EIO;
1554         }
1555         rte_spinlock_lock(&hw->lock);
1556         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1557         rte_spinlock_unlock(&hw->lock);
1558         if (ret)
1559                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1560                          vlan_id, ret);
1561
1562         return ret;
1563 }
1564
1565 static int
1566 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1567 {
1568         uint8_t msg_data;
1569         int ret;
1570
1571         if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1572                 return 0;
1573
1574         msg_data = enable ? 1 : 0;
1575         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1576                         HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1577                         sizeof(msg_data), true, NULL, 0);
1578         if (ret)
1579                 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1580                                 enable ? "enable" : "disable", ret);
1581
1582         return ret;
1583 }
1584
1585 static int
1586 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1587 {
1588         uint8_t msg_data;
1589         int ret;
1590
1591         msg_data = enable ? 1 : 0;
1592         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1593                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1594         if (ret)
1595                 hns3_err(hw, "vf %s strip failed, ret = %d.",
1596                                 enable ? "enable" : "disable", ret);
1597
1598         return ret;
1599 }
1600
1601 static int
1602 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1603 {
1604         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1605         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1606         unsigned int tmp_mask;
1607         int ret = 0;
1608
1609         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1610                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1611                              "mask = 0x%x", mask);
1612                 return -EIO;
1613         }
1614
1615         tmp_mask = (unsigned int)mask;
1616
1617         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
1618                 rte_spinlock_lock(&hw->lock);
1619                 /* Enable or disable VLAN filter */
1620                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1621                         ret = hns3vf_en_vlan_filter(hw, true);
1622                 else
1623                         ret = hns3vf_en_vlan_filter(hw, false);
1624                 rte_spinlock_unlock(&hw->lock);
1625                 if (ret)
1626                         return ret;
1627         }
1628
1629         /* Vlan stripping setting */
1630         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
1631                 rte_spinlock_lock(&hw->lock);
1632                 /* Enable or disable VLAN stripping */
1633                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1634                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1635                 else
1636                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1637                 rte_spinlock_unlock(&hw->lock);
1638         }
1639
1640         return ret;
1641 }
1642
1643 static int
1644 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1645 {
1646         struct rte_vlan_filter_conf *vfc;
1647         struct hns3_hw *hw = &hns->hw;
1648         uint16_t vlan_id;
1649         uint64_t vbit;
1650         uint64_t ids;
1651         int ret = 0;
1652         uint32_t i;
1653
1654         vfc = &hw->data->vlan_filter_conf;
1655         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1656                 if (vfc->ids[i] == 0)
1657                         continue;
1658                 ids = vfc->ids[i];
1659                 while (ids) {
1660                         /*
1661                          * 64 means the num bits of ids, one bit corresponds to
1662                          * one vlan id
1663                          */
1664                         vlan_id = 64 * i;
1665                         /* count trailing zeroes */
1666                         vbit = ~ids & (ids - 1);
1667                         /* clear least significant bit set */
1668                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1669                         for (; vbit;) {
1670                                 vbit >>= 1;
1671                                 vlan_id++;
1672                         }
1673                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1674                         if (ret) {
1675                                 hns3_err(hw,
1676                                          "VF handle vlan table failed, ret =%d, on = %d",
1677                                          ret, on);
1678                                 return ret;
1679                         }
1680                 }
1681         }
1682
1683         return ret;
1684 }
1685
1686 static int
1687 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1688 {
1689         return hns3vf_handle_all_vlan_table(hns, 0);
1690 }
1691
1692 static int
1693 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1694 {
1695         struct hns3_hw *hw = &hns->hw;
1696         struct rte_eth_conf *dev_conf;
1697         bool en;
1698         int ret;
1699
1700         dev_conf = &hw->data->dev_conf;
1701         en = dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? true
1702                                                                    : false;
1703         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1704         if (ret)
1705                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1706                          ret);
1707         return ret;
1708 }
1709
1710 static int
1711 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1712 {
1713         struct hns3_adapter *hns = dev->data->dev_private;
1714         struct rte_eth_dev_data *data = dev->data;
1715         struct hns3_hw *hw = &hns->hw;
1716         int ret;
1717
1718         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1719             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1720             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1721                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1722                               "or hw_vlan_insert_pvid is not support!");
1723         }
1724
1725         /* Apply vlan offload setting */
1726         ret = hns3vf_vlan_offload_set(dev, RTE_ETH_VLAN_STRIP_MASK |
1727                                         RTE_ETH_VLAN_FILTER_MASK);
1728         if (ret)
1729                 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1730
1731         return ret;
1732 }
1733
1734 static int
1735 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1736 {
1737         uint8_t msg_data;
1738
1739         msg_data = alive ? 1 : 0;
1740         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1741                                  sizeof(msg_data), false, NULL, 0);
1742 }
1743
1744 static void
1745 hns3vf_keep_alive_handler(void *param)
1746 {
1747         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1748         struct hns3_adapter *hns = eth_dev->data->dev_private;
1749         struct hns3_hw *hw = &hns->hw;
1750         int ret;
1751
1752         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1753                                 false, NULL, 0);
1754         if (ret)
1755                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1756                          ret);
1757
1758         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1759                           eth_dev);
1760 }
1761
1762 static void
1763 hns3vf_service_handler(void *param)
1764 {
1765         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1766         struct hns3_adapter *hns = eth_dev->data->dev_private;
1767         struct hns3_hw *hw = &hns->hw;
1768
1769         /*
1770          * The query link status and reset processing are executed in the
1771          * interrupt thread. When the IMP reset occurs, IMP will not respond,
1772          * and the query operation will timeout after 30ms. In the case of
1773          * multiple PF/VFs, each query failure timeout causes the IMP reset
1774          * interrupt to fail to respond within 100ms.
1775          * Before querying the link status, check whether there is a reset
1776          * pending, and if so, abandon the query.
1777          */
1778         if (!hns3vf_is_reset_pending(hns))
1779                 hns3vf_request_link_info(hw);
1780         else
1781                 hns3_warn(hw, "Cancel the query when reset is pending");
1782
1783         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1784                           eth_dev);
1785 }
1786
1787 static void
1788 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1789 {
1790 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT      3
1791
1792         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1793
1794         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1795                 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1796
1797         __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1798
1799         hns3vf_service_handler(dev);
1800 }
1801
1802 static void
1803 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1804 {
1805         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1806
1807         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1808
1809         __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1810 }
1811
1812 static int
1813 hns3_query_vf_resource(struct hns3_hw *hw)
1814 {
1815         struct hns3_vf_res_cmd *req;
1816         struct hns3_cmd_desc desc;
1817         uint16_t num_msi;
1818         int ret;
1819
1820         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1821         ret = hns3_cmd_send(hw, &desc, 1);
1822         if (ret) {
1823                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1824                 return ret;
1825         }
1826
1827         req = (struct hns3_vf_res_cmd *)desc.data;
1828         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1829                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1830         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1831                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1832                          num_msi, HNS3_MIN_VECTOR_NUM);
1833                 return -EINVAL;
1834         }
1835
1836         hw->num_msi = num_msi;
1837
1838         return 0;
1839 }
1840
1841 static int
1842 hns3vf_init_hardware(struct hns3_adapter *hns)
1843 {
1844         struct hns3_hw *hw = &hns->hw;
1845         uint16_t mtu = hw->data->mtu;
1846         int ret;
1847
1848         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1849         if (ret)
1850                 return ret;
1851
1852         ret = hns3vf_config_mtu(hw, mtu);
1853         if (ret)
1854                 goto err_init_hardware;
1855
1856         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1857         if (ret) {
1858                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1859                 goto err_init_hardware;
1860         }
1861
1862         ret = hns3_config_gro(hw, false);
1863         if (ret) {
1864                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1865                 goto err_init_hardware;
1866         }
1867
1868         /*
1869          * In the initialization clearing the all hardware mapping relationship
1870          * configurations between queues and interrupt vectors is needed, so
1871          * some error caused by the residual configurations, such as the
1872          * unexpected interrupt, can be avoid.
1873          */
1874         ret = hns3vf_init_ring_with_vector(hw);
1875         if (ret) {
1876                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1877                 goto err_init_hardware;
1878         }
1879
1880         return 0;
1881
1882 err_init_hardware:
1883         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1884         return ret;
1885 }
1886
1887 static int
1888 hns3vf_clear_vport_list(struct hns3_hw *hw)
1889 {
1890         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1891                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1892                                  NULL, 0);
1893 }
1894
1895 static int
1896 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1897 {
1898         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1899         struct hns3_adapter *hns = eth_dev->data->dev_private;
1900         struct hns3_hw *hw = &hns->hw;
1901         int ret;
1902
1903         PMD_INIT_FUNC_TRACE();
1904
1905         /* Get hardware io base address from pcie BAR2 IO space */
1906         hw->io_base = pci_dev->mem_resource[2].addr;
1907
1908         /* Firmware command queue initialize */
1909         ret = hns3_cmd_init_queue(hw);
1910         if (ret) {
1911                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1912                 goto err_cmd_init_queue;
1913         }
1914
1915         /* Firmware command initialize */
1916         ret = hns3_cmd_init(hw);
1917         if (ret) {
1918                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1919                 goto err_cmd_init;
1920         }
1921
1922         hns3_tx_push_init(eth_dev);
1923
1924         /* Get VF resource */
1925         ret = hns3_query_vf_resource(hw);
1926         if (ret)
1927                 goto err_cmd_init;
1928
1929         rte_spinlock_init(&hw->mbx_resp.lock);
1930
1931         hns3vf_clear_event_cause(hw, 0);
1932
1933         ret = rte_intr_callback_register(pci_dev->intr_handle,
1934                                          hns3vf_interrupt_handler, eth_dev);
1935         if (ret) {
1936                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1937                 goto err_intr_callback_register;
1938         }
1939
1940         /* Enable interrupt */
1941         rte_intr_enable(pci_dev->intr_handle);
1942         hns3vf_enable_irq0(hw);
1943
1944         /* Get configuration from PF */
1945         ret = hns3vf_get_configuration(hw);
1946         if (ret) {
1947                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1948                 goto err_get_config;
1949         }
1950
1951         ret = hns3_tqp_stats_init(hw);
1952         if (ret)
1953                 goto err_get_config;
1954
1955         /* Hardware statistics of imissed registers cleared. */
1956         ret = hns3_update_imissed_stats(hw, true);
1957         if (ret) {
1958                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1959                 goto err_set_tc_queue;
1960         }
1961
1962         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1963         if (ret) {
1964                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1965                 goto err_set_tc_queue;
1966         }
1967
1968         ret = hns3vf_clear_vport_list(hw);
1969         if (ret) {
1970                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1971                 goto err_set_tc_queue;
1972         }
1973
1974         ret = hns3vf_init_hardware(hns);
1975         if (ret)
1976                 goto err_set_tc_queue;
1977
1978         hns3_rss_set_default_args(hw);
1979
1980         ret = hns3vf_set_alive(hw, true);
1981         if (ret) {
1982                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1983                 goto err_set_tc_queue;
1984         }
1985
1986         return 0;
1987
1988 err_set_tc_queue:
1989         hns3_tqp_stats_uninit(hw);
1990
1991 err_get_config:
1992         hns3vf_disable_irq0(hw);
1993         rte_intr_disable(pci_dev->intr_handle);
1994         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1995                              eth_dev);
1996 err_intr_callback_register:
1997 err_cmd_init:
1998         hns3_cmd_uninit(hw);
1999         hns3_cmd_destroy_queue(hw);
2000 err_cmd_init_queue:
2001         hw->io_base = NULL;
2002
2003         return ret;
2004 }
2005
2006 static void
2007 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
2008 {
2009         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2010         struct hns3_adapter *hns = eth_dev->data->dev_private;
2011         struct hns3_hw *hw = &hns->hw;
2012
2013         PMD_INIT_FUNC_TRACE();
2014
2015         hns3_rss_uninit(hns);
2016         (void)hns3_config_gro(hw, false);
2017         (void)hns3vf_set_alive(hw, false);
2018         (void)hns3vf_set_promisc_mode(hw, false, false, false);
2019         hns3_flow_uninit(eth_dev);
2020         hns3_tqp_stats_uninit(hw);
2021         hns3vf_disable_irq0(hw);
2022         rte_intr_disable(pci_dev->intr_handle);
2023         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
2024                              eth_dev);
2025         hns3_cmd_uninit(hw);
2026         hns3_cmd_destroy_queue(hw);
2027         hw->io_base = NULL;
2028 }
2029
2030 static int
2031 hns3vf_do_stop(struct hns3_adapter *hns)
2032 {
2033         struct hns3_hw *hw = &hns->hw;
2034         int ret;
2035
2036         hw->mac.link_status = RTE_ETH_LINK_DOWN;
2037
2038         /*
2039          * The "hns3vf_do_stop" function will also be called by .stop_service to
2040          * prepare reset. At the time of global or IMP reset, the command cannot
2041          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
2042          * accessed during the reset process. So the mbuf can not be released
2043          * during reset and is required to be released after the reset is
2044          * completed.
2045          */
2046         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
2047                 hns3_dev_release_mbufs(hns);
2048
2049         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
2050                 hns3vf_configure_mac_addr(hns, true);
2051                 ret = hns3_reset_all_tqps(hns);
2052                 if (ret) {
2053                         hns3_err(hw, "failed to reset all queues ret = %d",
2054                                  ret);
2055                         return ret;
2056                 }
2057         }
2058         return 0;
2059 }
2060
2061 static void
2062 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
2063 {
2064         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2066         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2067         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2068         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2069         uint16_t q_id;
2070
2071         if (dev->data->dev_conf.intr_conf.rxq == 0)
2072                 return;
2073
2074         /* unmap the ring with vector */
2075         if (rte_intr_allow_others(intr_handle)) {
2076                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2077                 base = RTE_INTR_VEC_RXTX_OFFSET;
2078         }
2079         if (rte_intr_dp_is_en(intr_handle)) {
2080                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2081                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
2082                                                            HNS3_RING_TYPE_RX,
2083                                                            q_id);
2084                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
2085                             - 1)
2086                                 vec++;
2087                 }
2088         }
2089         /* Clean datapath event and queue/vec mapping */
2090         rte_intr_efd_disable(intr_handle);
2091
2092         /* Cleanup vector list */
2093         rte_intr_vec_list_free(intr_handle);
2094 }
2095
2096 static int
2097 hns3vf_dev_stop(struct rte_eth_dev *dev)
2098 {
2099         struct hns3_adapter *hns = dev->data->dev_private;
2100         struct hns3_hw *hw = &hns->hw;
2101
2102         PMD_INIT_FUNC_TRACE();
2103         dev->data->dev_started = 0;
2104
2105         hw->adapter_state = HNS3_NIC_STOPPING;
2106         hns3_set_rxtx_function(dev);
2107         rte_wmb();
2108         /* Disable datapath on secondary process. */
2109         hns3_mp_req_stop_rxtx(dev);
2110         /* Prevent crashes when queues are still in use. */
2111         rte_delay_ms(hw->cfg_max_queues);
2112
2113         rte_spinlock_lock(&hw->lock);
2114         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
2115                 hns3_stop_tqps(hw);
2116                 hns3vf_do_stop(hns);
2117                 hns3vf_unmap_rx_interrupt(dev);
2118                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2119         }
2120         hns3_rx_scattered_reset(dev);
2121         hns3vf_stop_poll_job(dev);
2122         hns3_stop_report_lse(dev);
2123         rte_spinlock_unlock(&hw->lock);
2124
2125         return 0;
2126 }
2127
2128 static int
2129 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
2130 {
2131         struct hns3_adapter *hns = eth_dev->data->dev_private;
2132         struct hns3_hw *hw = &hns->hw;
2133         int ret = 0;
2134
2135         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2136                 return 0;
2137
2138         if (hw->adapter_state == HNS3_NIC_STARTED)
2139                 ret = hns3vf_dev_stop(eth_dev);
2140
2141         hw->adapter_state = HNS3_NIC_CLOSING;
2142         hns3_reset_abort(hns);
2143         hw->adapter_state = HNS3_NIC_CLOSED;
2144         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
2145         hns3vf_configure_all_mc_mac_addr(hns, true);
2146         hns3vf_remove_all_vlan_table(hns);
2147         hns3vf_uninit_vf(eth_dev);
2148         hns3_free_all_queues(eth_dev);
2149         rte_free(hw->reset.wait_data);
2150         hns3_mp_uninit_primary();
2151         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
2152
2153         return ret;
2154 }
2155
2156 static int
2157 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2158                       size_t fw_size)
2159 {
2160         struct hns3_adapter *hns = eth_dev->data->dev_private;
2161         struct hns3_hw *hw = &hns->hw;
2162         uint32_t version = hw->fw_version;
2163         int ret;
2164
2165         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2166                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2167                                       HNS3_FW_VERSION_BYTE3_S),
2168                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2169                                       HNS3_FW_VERSION_BYTE2_S),
2170                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2171                                       HNS3_FW_VERSION_BYTE1_S),
2172                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2173                                       HNS3_FW_VERSION_BYTE0_S));
2174         if (ret < 0)
2175                 return -EINVAL;
2176
2177         ret += 1; /* add the size of '\0' */
2178         if (fw_size < (size_t)ret)
2179                 return ret;
2180         else
2181                 return 0;
2182 }
2183
2184 static int
2185 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2186                        __rte_unused int wait_to_complete)
2187 {
2188         struct hns3_adapter *hns = eth_dev->data->dev_private;
2189         struct hns3_hw *hw = &hns->hw;
2190         struct hns3_mac *mac = &hw->mac;
2191         struct rte_eth_link new_link;
2192
2193         memset(&new_link, 0, sizeof(new_link));
2194         switch (mac->link_speed) {
2195         case RTE_ETH_SPEED_NUM_10M:
2196         case RTE_ETH_SPEED_NUM_100M:
2197         case RTE_ETH_SPEED_NUM_1G:
2198         case RTE_ETH_SPEED_NUM_10G:
2199         case RTE_ETH_SPEED_NUM_25G:
2200         case RTE_ETH_SPEED_NUM_40G:
2201         case RTE_ETH_SPEED_NUM_50G:
2202         case RTE_ETH_SPEED_NUM_100G:
2203         case RTE_ETH_SPEED_NUM_200G:
2204                 if (mac->link_status)
2205                         new_link.link_speed = mac->link_speed;
2206                 break;
2207         default:
2208                 if (mac->link_status)
2209                         new_link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2210                 break;
2211         }
2212
2213         if (!mac->link_status)
2214                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2215
2216         new_link.link_duplex = mac->link_duplex;
2217         new_link.link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2218         new_link.link_autoneg =
2219             !(eth_dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED);
2220
2221         return rte_eth_linkstatus_set(eth_dev, &new_link);
2222 }
2223
2224 static int
2225 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2226 {
2227         struct hns3_hw *hw = &hns->hw;
2228         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2229         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2230         int ret;
2231
2232         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2233         if (ret)
2234                 return ret;
2235
2236         hns3_enable_rxd_adv_layout(hw);
2237
2238         ret = hns3_init_queues(hns, reset_queue);
2239         if (ret)
2240                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2241
2242         return ret;
2243 }
2244
2245 static int
2246 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2247 {
2248         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2249         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2251         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2252         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2253         uint32_t intr_vector;
2254         uint16_t q_id;
2255         int ret;
2256
2257         /*
2258          * hns3 needs a separate interrupt to be used as event interrupt which
2259          * could not be shared with task queue pair, so KERNEL drivers need
2260          * support multiple interrupt vectors.
2261          */
2262         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2263             !rte_intr_cap_multiple(intr_handle))
2264                 return 0;
2265
2266         rte_intr_disable(intr_handle);
2267         intr_vector = hw->used_rx_queues;
2268         /* It creates event fd for each intr vector when MSIX is used */
2269         if (rte_intr_efd_enable(intr_handle, intr_vector))
2270                 return -EINVAL;
2271
2272         /* Allocate vector list */
2273         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
2274                                     hw->used_rx_queues)) {
2275                 hns3_err(hw, "Failed to allocate %u rx_queues"
2276                          " intr_vec", hw->used_rx_queues);
2277                 ret = -ENOMEM;
2278                 goto vf_alloc_intr_vec_error;
2279         }
2280
2281         if (rte_intr_allow_others(intr_handle)) {
2282                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2283                 base = RTE_INTR_VEC_RXTX_OFFSET;
2284         }
2285
2286         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2287                 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2288                                                    HNS3_RING_TYPE_RX, q_id);
2289                 if (ret)
2290                         goto vf_bind_vector_error;
2291
2292                 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
2293                         goto vf_bind_vector_error;
2294
2295                 /*
2296                  * If there are not enough efds (e.g. not enough interrupt),
2297                  * remaining queues will be bond to the last interrupt.
2298                  */
2299                 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
2300                         vec++;
2301         }
2302         rte_intr_enable(intr_handle);
2303         return 0;
2304
2305 vf_bind_vector_error:
2306         rte_intr_vec_list_free(intr_handle);
2307 vf_alloc_intr_vec_error:
2308         rte_intr_efd_disable(intr_handle);
2309         return ret;
2310 }
2311
2312 static int
2313 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2314 {
2315         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2316         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2317         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2318         uint16_t q_id;
2319         int ret;
2320
2321         if (dev->data->dev_conf.intr_conf.rxq == 0)
2322                 return 0;
2323
2324         if (rte_intr_dp_is_en(intr_handle)) {
2325                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2326                         ret = hns3vf_bind_ring_with_vector(hw,
2327                                 rte_intr_vec_list_index_get(intr_handle,
2328                                                                    q_id),
2329                                 true, HNS3_RING_TYPE_RX, q_id);
2330                         if (ret)
2331                                 return ret;
2332                 }
2333         }
2334
2335         return 0;
2336 }
2337
2338 static void
2339 hns3vf_restore_filter(struct rte_eth_dev *dev)
2340 {
2341         hns3_restore_rss_filter(dev);
2342 }
2343
2344 static int
2345 hns3vf_dev_start(struct rte_eth_dev *dev)
2346 {
2347         struct hns3_adapter *hns = dev->data->dev_private;
2348         struct hns3_hw *hw = &hns->hw;
2349         int ret;
2350
2351         PMD_INIT_FUNC_TRACE();
2352         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2353                 return -EBUSY;
2354
2355         rte_spinlock_lock(&hw->lock);
2356         hw->adapter_state = HNS3_NIC_STARTING;
2357         ret = hns3vf_do_start(hns, true);
2358         if (ret) {
2359                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2360                 rte_spinlock_unlock(&hw->lock);
2361                 return ret;
2362         }
2363         ret = hns3vf_map_rx_interrupt(dev);
2364         if (ret)
2365                 goto map_rx_inter_err;
2366
2367         /*
2368          * There are three register used to control the status of a TQP
2369          * (contains a pair of Tx queue and Rx queue) in the new version network
2370          * engine. One is used to control the enabling of Tx queue, the other is
2371          * used to control the enabling of Rx queue, and the last is the master
2372          * switch used to control the enabling of the tqp. The Tx register and
2373          * TQP register must be enabled at the same time to enable a Tx queue.
2374          * The same applies to the Rx queue. For the older network enginem, this
2375          * function only refresh the enabled flag, and it is used to update the
2376          * status of queue in the dpdk framework.
2377          */
2378         ret = hns3_start_all_txqs(dev);
2379         if (ret)
2380                 goto map_rx_inter_err;
2381
2382         ret = hns3_start_all_rxqs(dev);
2383         if (ret)
2384                 goto start_all_rxqs_fail;
2385
2386         hw->adapter_state = HNS3_NIC_STARTED;
2387         rte_spinlock_unlock(&hw->lock);
2388
2389         hns3_rx_scattered_calc(dev);
2390         hns3_set_rxtx_function(dev);
2391         hns3_mp_req_start_rxtx(dev);
2392
2393         hns3vf_restore_filter(dev);
2394
2395         /* Enable interrupt of all rx queues before enabling queues */
2396         hns3_dev_all_rx_queue_intr_enable(hw, true);
2397         hns3_start_tqps(hw);
2398
2399         if (dev->data->dev_conf.intr_conf.lsc != 0)
2400                 hns3vf_dev_link_update(dev, 0);
2401         hns3vf_start_poll_job(dev);
2402
2403         return ret;
2404
2405 start_all_rxqs_fail:
2406         hns3_stop_all_txqs(dev);
2407 map_rx_inter_err:
2408         (void)hns3vf_do_stop(hns);
2409         hw->adapter_state = HNS3_NIC_CONFIGURED;
2410         rte_spinlock_unlock(&hw->lock);
2411
2412         return ret;
2413 }
2414
2415 static bool
2416 is_vf_reset_done(struct hns3_hw *hw)
2417 {
2418 #define HNS3_FUN_RST_ING_BITS \
2419         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2420          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2421          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2422          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2423
2424         uint32_t val;
2425
2426         if (hw->reset.level == HNS3_VF_RESET) {
2427                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2428                 if (val & HNS3_VF_RST_ING_BIT)
2429                         return false;
2430         } else {
2431                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2432                 if (val & HNS3_FUN_RST_ING_BITS)
2433                         return false;
2434         }
2435         return true;
2436 }
2437
2438 bool
2439 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2440 {
2441         struct hns3_hw *hw = &hns->hw;
2442         enum hns3_reset_level reset;
2443
2444         /*
2445          * According to the protocol of PCIe, FLR to a PF device resets the PF
2446          * state as well as the SR-IOV extended capability including VF Enable
2447          * which means that VFs no longer exist.
2448          *
2449          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2450          * is in FLR stage, the register state of VF device is not reliable,
2451          * so register states detection can not be carried out. In this case,
2452          * we just ignore the register states and return false to indicate that
2453          * there are no other reset states that need to be processed by driver.
2454          */
2455         if (hw->reset.level == HNS3_VF_FULL_RESET)
2456                 return false;
2457
2458         /* Check the registers to confirm whether there is reset pending */
2459         hns3vf_check_event_cause(hns, NULL);
2460         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2461         if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2462             hw->reset.level < reset) {
2463                 hns3_warn(hw, "High level reset %d is pending", reset);
2464                 return true;
2465         }
2466         return false;
2467 }
2468
2469 static int
2470 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2471 {
2472         struct hns3_hw *hw = &hns->hw;
2473         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2474         struct timeval tv;
2475
2476         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2477                 /*
2478                  * After vf reset is ready, the PF may not have completed
2479                  * the reset processing. The vf sending mbox to PF may fail
2480                  * during the pf reset, so it is better to add extra delay.
2481                  */
2482                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2483                     hw->reset.level == HNS3_FLR_RESET)
2484                         return 0;
2485                 /* Reset retry process, no need to add extra delay. */
2486                 if (hw->reset.attempts)
2487                         return 0;
2488                 if (wait_data->check_completion == NULL)
2489                         return 0;
2490
2491                 wait_data->check_completion = NULL;
2492                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2493                 wait_data->count = 1;
2494                 wait_data->result = HNS3_WAIT_REQUEST;
2495                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2496                                   wait_data);
2497                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2498                 return -EAGAIN;
2499         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2500                 hns3_clock_gettime(&tv);
2501                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2502                           tv.tv_sec, tv.tv_usec);
2503                 return -ETIME;
2504         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2505                 return -EAGAIN;
2506
2507         wait_data->hns = hns;
2508         wait_data->check_completion = is_vf_reset_done;
2509         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2510                                 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2511         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2512         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2513         wait_data->result = HNS3_WAIT_REQUEST;
2514         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2515         return -EAGAIN;
2516 }
2517
2518 static int
2519 hns3vf_prepare_reset(struct hns3_adapter *hns)
2520 {
2521         struct hns3_hw *hw = &hns->hw;
2522         int ret;
2523
2524         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2525                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2526                                         0, true, NULL, 0);
2527                 if (ret)
2528                         return ret;
2529         }
2530         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2531
2532         return 0;
2533 }
2534
2535 static int
2536 hns3vf_stop_service(struct hns3_adapter *hns)
2537 {
2538         struct hns3_hw *hw = &hns->hw;
2539         struct rte_eth_dev *eth_dev;
2540
2541         eth_dev = &rte_eth_devices[hw->data->port_id];
2542         if (hw->adapter_state == HNS3_NIC_STARTED) {
2543                 /*
2544                  * Make sure call update link status before hns3vf_stop_poll_job
2545                  * because update link status depend on polling job exist.
2546                  */
2547                 hns3vf_update_link_status(hw, RTE_ETH_LINK_DOWN, hw->mac.link_speed,
2548                                           hw->mac.link_duplex);
2549                 hns3vf_stop_poll_job(eth_dev);
2550         }
2551         hw->mac.link_status = RTE_ETH_LINK_DOWN;
2552
2553         hns3_set_rxtx_function(eth_dev);
2554         rte_wmb();
2555         /* Disable datapath on secondary process. */
2556         hns3_mp_req_stop_rxtx(eth_dev);
2557         rte_delay_ms(hw->cfg_max_queues);
2558
2559         rte_spinlock_lock(&hw->lock);
2560         if (hw->adapter_state == HNS3_NIC_STARTED ||
2561             hw->adapter_state == HNS3_NIC_STOPPING) {
2562                 hns3_enable_all_queues(hw, false);
2563                 hns3vf_do_stop(hns);
2564                 hw->reset.mbuf_deferred_free = true;
2565         } else
2566                 hw->reset.mbuf_deferred_free = false;
2567
2568         /*
2569          * It is cumbersome for hardware to pick-and-choose entries for deletion
2570          * from table space. Hence, for function reset software intervention is
2571          * required to delete the entries.
2572          */
2573         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2574                 hns3vf_configure_all_mc_mac_addr(hns, true);
2575         rte_spinlock_unlock(&hw->lock);
2576
2577         return 0;
2578 }
2579
2580 static int
2581 hns3vf_start_service(struct hns3_adapter *hns)
2582 {
2583         struct hns3_hw *hw = &hns->hw;
2584         struct rte_eth_dev *eth_dev;
2585
2586         eth_dev = &rte_eth_devices[hw->data->port_id];
2587         hns3_set_rxtx_function(eth_dev);
2588         hns3_mp_req_start_rxtx(eth_dev);
2589         if (hw->adapter_state == HNS3_NIC_STARTED) {
2590                 hns3vf_start_poll_job(eth_dev);
2591
2592                 /* Enable interrupt of all rx queues before enabling queues */
2593                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2594                 /*
2595                  * Enable state of each rxq and txq will be recovered after
2596                  * reset, so we need to restore them before enable all tqps;
2597                  */
2598                 hns3_restore_tqp_enable_state(hw);
2599                 /*
2600                  * When finished the initialization, enable queues to receive
2601                  * and transmit packets.
2602                  */
2603                 hns3_enable_all_queues(hw, true);
2604         }
2605
2606         return 0;
2607 }
2608
2609 static int
2610 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2611 {
2612         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2613         struct rte_ether_addr *hw_mac;
2614         int ret;
2615
2616         /*
2617          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2618          * on the host by "ip link set ..." command. If the hns3 PF kernel
2619          * ethdev driver sets the MAC address for VF device after the
2620          * initialization of the related VF device, the PF driver will notify
2621          * VF driver to reset VF device to make the new MAC address effective
2622          * immediately. The hns3 VF PMD driver should check whether the MAC
2623          * address has been changed by the PF kernel ethdev driver, if changed
2624          * VF driver should configure hardware using the new MAC address in the
2625          * recovering hardware configuration stage of the reset process.
2626          */
2627         ret = hns3vf_get_host_mac_addr(hw);
2628         if (ret)
2629                 return ret;
2630
2631         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2632         ret = rte_is_zero_ether_addr(hw_mac);
2633         if (ret) {
2634                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2635         } else {
2636                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2637                 if (!ret) {
2638                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2639                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2640                                               &hw->data->mac_addrs[0]);
2641                         hns3_warn(hw, "Default MAC address has been changed to:"
2642                                   " %s by the host PF kernel ethdev driver",
2643                                   mac_str);
2644                 }
2645         }
2646
2647         return 0;
2648 }
2649
2650 static int
2651 hns3vf_restore_conf(struct hns3_adapter *hns)
2652 {
2653         struct hns3_hw *hw = &hns->hw;
2654         int ret;
2655
2656         ret = hns3vf_check_default_mac_change(hw);
2657         if (ret)
2658                 return ret;
2659
2660         ret = hns3vf_configure_mac_addr(hns, false);
2661         if (ret)
2662                 return ret;
2663
2664         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2665         if (ret)
2666                 goto err_mc_mac;
2667
2668         ret = hns3vf_restore_promisc(hns);
2669         if (ret)
2670                 goto err_vlan_table;
2671
2672         ret = hns3vf_restore_vlan_conf(hns);
2673         if (ret)
2674                 goto err_vlan_table;
2675
2676         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2677         if (ret)
2678                 goto err_vlan_table;
2679
2680         ret = hns3vf_restore_rx_interrupt(hw);
2681         if (ret)
2682                 goto err_vlan_table;
2683
2684         ret = hns3_restore_gro_conf(hw);
2685         if (ret)
2686                 goto err_vlan_table;
2687
2688         if (hw->adapter_state == HNS3_NIC_STARTED) {
2689                 ret = hns3vf_do_start(hns, false);
2690                 if (ret)
2691                         goto err_vlan_table;
2692                 hns3_info(hw, "hns3vf dev restart successful!");
2693         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2694                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2695
2696         ret = hns3vf_set_alive(hw, true);
2697         if (ret) {
2698                 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2699                 goto err_vlan_table;
2700         }
2701
2702         return 0;
2703
2704 err_vlan_table:
2705         hns3vf_configure_all_mc_mac_addr(hns, true);
2706 err_mc_mac:
2707         hns3vf_configure_mac_addr(hns, true);
2708         return ret;
2709 }
2710
2711 static enum hns3_reset_level
2712 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2713 {
2714         enum hns3_reset_level reset_level;
2715
2716         /* return the highest priority reset level amongst all */
2717         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2718                 reset_level = HNS3_VF_RESET;
2719         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2720                 reset_level = HNS3_VF_FULL_RESET;
2721         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2722                 reset_level = HNS3_VF_PF_FUNC_RESET;
2723         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2724                 reset_level = HNS3_VF_FUNC_RESET;
2725         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2726                 reset_level = HNS3_FLR_RESET;
2727         else
2728                 reset_level = HNS3_NONE_RESET;
2729
2730         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2731                 return HNS3_NONE_RESET;
2732
2733         return reset_level;
2734 }
2735
2736 static void
2737 hns3vf_reset_service(void *param)
2738 {
2739         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2740         struct hns3_hw *hw = &hns->hw;
2741         enum hns3_reset_level reset_level;
2742         struct timeval tv_delta;
2743         struct timeval tv_start;
2744         struct timeval tv;
2745         uint64_t msec;
2746
2747         /*
2748          * The interrupt is not triggered within the delay time.
2749          * The interrupt may have been lost. It is necessary to handle
2750          * the interrupt to recover from the error.
2751          */
2752         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2753                             SCHEDULE_DEFERRED) {
2754                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2755                                  __ATOMIC_RELAXED);
2756                 hns3_err(hw, "Handling interrupts in delayed tasks");
2757                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2758                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2759                 if (reset_level == HNS3_NONE_RESET) {
2760                         hns3_err(hw, "No reset level is set, try global reset");
2761                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2762                 }
2763         }
2764         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2765
2766         /*
2767          * Hardware reset has been notified, we now have to poll & check if
2768          * hardware has actually completed the reset sequence.
2769          */
2770         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2771         if (reset_level != HNS3_NONE_RESET) {
2772                 hns3_clock_gettime(&tv_start);
2773                 hns3_reset_process(hns, reset_level);
2774                 hns3_clock_gettime(&tv);
2775                 timersub(&tv, &tv_start, &tv_delta);
2776                 msec = hns3_clock_calctime_ms(&tv_delta);
2777                 if (msec > HNS3_RESET_PROCESS_MS)
2778                         hns3_err(hw, "%d handle long time delta %" PRIu64
2779                                  " ms time=%ld.%.6ld",
2780                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2781         }
2782 }
2783
2784 static int
2785 hns3vf_reinit_dev(struct hns3_adapter *hns)
2786 {
2787         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2788         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2789         struct hns3_hw *hw = &hns->hw;
2790         int ret;
2791
2792         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2793                 rte_intr_disable(pci_dev->intr_handle);
2794                 ret = hns3vf_set_bus_master(pci_dev, true);
2795                 if (ret < 0) {
2796                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2797                         return ret;
2798                 }
2799         }
2800
2801         /* Firmware command initialize */
2802         ret = hns3_cmd_init(hw);
2803         if (ret) {
2804                 hns3_err(hw, "Failed to init cmd: %d", ret);
2805                 return ret;
2806         }
2807
2808         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2809                 /*
2810                  * UIO enables msix by writing the pcie configuration space
2811                  * vfio_pci enables msix in rte_intr_enable.
2812                  */
2813                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2814                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2815                         if (hns3vf_enable_msix(pci_dev, true))
2816                                 hns3_err(hw, "Failed to enable msix");
2817                 }
2818
2819                 rte_intr_enable(pci_dev->intr_handle);
2820         }
2821
2822         ret = hns3_reset_all_tqps(hns);
2823         if (ret) {
2824                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2825                 return ret;
2826         }
2827
2828         ret = hns3vf_init_hardware(hns);
2829         if (ret) {
2830                 hns3_err(hw, "Failed to init hardware: %d", ret);
2831                 return ret;
2832         }
2833
2834         return 0;
2835 }
2836
2837 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2838         .dev_configure      = hns3vf_dev_configure,
2839         .dev_start          = hns3vf_dev_start,
2840         .dev_stop           = hns3vf_dev_stop,
2841         .dev_close          = hns3vf_dev_close,
2842         .mtu_set            = hns3vf_dev_mtu_set,
2843         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2844         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2845         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2846         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2847         .stats_get          = hns3_stats_get,
2848         .stats_reset        = hns3_stats_reset,
2849         .xstats_get         = hns3_dev_xstats_get,
2850         .xstats_get_names   = hns3_dev_xstats_get_names,
2851         .xstats_reset       = hns3_dev_xstats_reset,
2852         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2853         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2854         .dev_infos_get      = hns3vf_dev_infos_get,
2855         .fw_version_get     = hns3vf_fw_version_get,
2856         .rx_queue_setup     = hns3_rx_queue_setup,
2857         .tx_queue_setup     = hns3_tx_queue_setup,
2858         .rx_queue_release   = hns3_dev_rx_queue_release,
2859         .tx_queue_release   = hns3_dev_tx_queue_release,
2860         .rx_queue_start     = hns3_dev_rx_queue_start,
2861         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2862         .tx_queue_start     = hns3_dev_tx_queue_start,
2863         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2864         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2865         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2866         .rxq_info_get       = hns3_rxq_info_get,
2867         .txq_info_get       = hns3_txq_info_get,
2868         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2869         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2870         .mac_addr_add       = hns3vf_add_mac_addr,
2871         .mac_addr_remove    = hns3vf_remove_mac_addr,
2872         .mac_addr_set       = hns3vf_set_default_mac_addr,
2873         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2874         .link_update        = hns3vf_dev_link_update,
2875         .rss_hash_update    = hns3_dev_rss_hash_update,
2876         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2877         .reta_update        = hns3_dev_rss_reta_update,
2878         .reta_query         = hns3_dev_rss_reta_query,
2879         .flow_ops_get       = hns3_dev_flow_ops_get,
2880         .vlan_filter_set    = hns3vf_vlan_filter_set,
2881         .vlan_offload_set   = hns3vf_vlan_offload_set,
2882         .get_reg            = hns3_get_regs,
2883         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2884         .tx_done_cleanup    = hns3_tx_done_cleanup,
2885 };
2886
2887 static const struct hns3_reset_ops hns3vf_reset_ops = {
2888         .reset_service       = hns3vf_reset_service,
2889         .stop_service        = hns3vf_stop_service,
2890         .prepare_reset       = hns3vf_prepare_reset,
2891         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2892         .reinit_dev          = hns3vf_reinit_dev,
2893         .restore_conf        = hns3vf_restore_conf,
2894         .start_service       = hns3vf_start_service,
2895 };
2896
2897 static int
2898 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2899 {
2900         struct hns3_adapter *hns = eth_dev->data->dev_private;
2901         struct hns3_hw *hw = &hns->hw;
2902         int ret;
2903
2904         PMD_INIT_FUNC_TRACE();
2905
2906         hns3_flow_init(eth_dev);
2907
2908         hns3_set_rxtx_function(eth_dev);
2909         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2910         eth_dev->rx_queue_count = hns3_rx_queue_count;
2911         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2912                 ret = hns3_mp_init_secondary();
2913                 if (ret) {
2914                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2915                                           "process, ret = %d", ret);
2916                         goto err_mp_init_secondary;
2917                 }
2918                 hw->secondary_cnt++;
2919                 hns3_tx_push_init(eth_dev);
2920                 return 0;
2921         }
2922
2923         ret = hns3_mp_init_primary();
2924         if (ret) {
2925                 PMD_INIT_LOG(ERR,
2926                              "Failed to init for primary process, ret = %d",
2927                              ret);
2928                 goto err_mp_init_primary;
2929         }
2930
2931         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2932         hns->is_vf = true;
2933         hw->data = eth_dev->data;
2934         hns3_parse_devargs(eth_dev);
2935
2936         ret = hns3_reset_init(hw);
2937         if (ret)
2938                 goto err_init_reset;
2939         hw->reset.ops = &hns3vf_reset_ops;
2940
2941         ret = hns3vf_init_vf(eth_dev);
2942         if (ret) {
2943                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2944                 goto err_init_vf;
2945         }
2946
2947         /* Allocate memory for storing MAC addresses */
2948         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2949                                                sizeof(struct rte_ether_addr) *
2950                                                HNS3_VF_UC_MACADDR_NUM, 0);
2951         if (eth_dev->data->mac_addrs == NULL) {
2952                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2953                              "to store MAC addresses",
2954                              sizeof(struct rte_ether_addr) *
2955                              HNS3_VF_UC_MACADDR_NUM);
2956                 ret = -ENOMEM;
2957                 goto err_rte_zmalloc;
2958         }
2959
2960         /*
2961          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2962          * on the host by "ip link set ..." command. To avoid some incorrect
2963          * scenes, for example, hns3 VF PMD driver fails to receive and send
2964          * packets after user configure the MAC address by using the
2965          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2966          * address strategy as the hns3 kernel ethdev driver in the
2967          * initialization. If user configure a MAC address by the ip command
2968          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2969          * start with a random MAC address in the initialization.
2970          */
2971         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2972                 rte_eth_random_addr(hw->mac.mac_addr);
2973         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2974                             &eth_dev->data->mac_addrs[0]);
2975
2976         hw->adapter_state = HNS3_NIC_INITIALIZED;
2977
2978         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2979                             SCHEDULE_PENDING) {
2980                 hns3_err(hw, "Reschedule reset service after dev_init");
2981                 hns3_schedule_reset(hns);
2982         } else {
2983                 /* IMP will wait ready flag before reset */
2984                 hns3_notify_reset_ready(hw, false);
2985         }
2986         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2987                           eth_dev);
2988         return 0;
2989
2990 err_rte_zmalloc:
2991         hns3vf_uninit_vf(eth_dev);
2992
2993 err_init_vf:
2994         rte_free(hw->reset.wait_data);
2995
2996 err_init_reset:
2997         hns3_mp_uninit_primary();
2998
2999 err_mp_init_primary:
3000 err_mp_init_secondary:
3001         eth_dev->dev_ops = NULL;
3002         eth_dev->rx_pkt_burst = NULL;
3003         eth_dev->rx_descriptor_status = NULL;
3004         eth_dev->tx_pkt_burst = NULL;
3005         eth_dev->tx_pkt_prepare = NULL;
3006         eth_dev->tx_descriptor_status = NULL;
3007
3008         return ret;
3009 }
3010
3011 static int
3012 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
3013 {
3014         struct hns3_adapter *hns = eth_dev->data->dev_private;
3015         struct hns3_hw *hw = &hns->hw;
3016
3017         PMD_INIT_FUNC_TRACE();
3018
3019         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3020                 return 0;
3021
3022         if (hw->adapter_state < HNS3_NIC_CLOSING)
3023                 hns3vf_dev_close(eth_dev);
3024
3025         hw->adapter_state = HNS3_NIC_REMOVED;
3026         return 0;
3027 }
3028
3029 static int
3030 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3031                      struct rte_pci_device *pci_dev)
3032 {
3033         return rte_eth_dev_pci_generic_probe(pci_dev,
3034                                              sizeof(struct hns3_adapter),
3035                                              hns3vf_dev_init);
3036 }
3037
3038 static int
3039 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
3040 {
3041         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
3042 }
3043
3044 static const struct rte_pci_id pci_id_hns3vf_map[] = {
3045         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
3046         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
3047         { .vendor_id = 0, }, /* sentinel */
3048 };
3049
3050 static struct rte_pci_driver rte_hns3vf_pmd = {
3051         .id_table = pci_id_hns3vf_map,
3052         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3053         .probe = eth_hns3vf_pci_probe,
3054         .remove = eth_hns3vf_pci_remove,
3055 };
3056
3057 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
3058 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
3059 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
3060 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
3061                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
3062                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
3063                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
3064                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16_t> ");