drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
  48                                    __rte_unused int wait_to_complete);
  49
  50 /* set PCI bus mastering */
  51 static int
  52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  53 {
  54         uint16_t reg;
  55         int ret;
  56
  57         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  58         if (ret < 0) {
  59                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  60                              PCI_COMMAND);
  61                 return ret;
  62         }
  63
  64         if (op)
  65                 /* set the master bit */
  66                 reg |= PCI_COMMAND_MASTER;
  67         else
  68                 reg &= ~(PCI_COMMAND_MASTER);
  69
  70         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  71 }
  72
  73 /**
  74  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  75  * @cap: the capability
  76  *
  77  * Return the address of the given capability within the PCI capability list.
  78  */
  79 static int
  80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  81 {
  82 #define MAX_PCIE_CAPABILITY 48
  83         uint16_t status;
  84         uint8_t pos;
  85         uint8_t id;
  86         int ttl;
  87         int ret;
  88
  89         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  90         if (ret < 0) {
  91                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  92                 return 0;
  93         }
  94
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 100                                   PCI_CAPABILITY_LIST);
 101         if (ret < 0) {
 102                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 103                              PCI_CAPABILITY_LIST);
 104                 return 0;
 105         }
 106
 107         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 108                 ret = rte_pci_read_config(device, &id, sizeof(id),
 109                                           (pos + PCI_CAP_LIST_ID));
 110                 if (ret < 0) {
 111                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 112                                      (pos + PCI_CAP_LIST_ID));
 113                         break;
 114                 }
 115
 116                 if (id == 0xFF)
 117                         break;
 118
 119                 if (id == cap)
 120                         return (int)pos;
 121
 122                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 123                                           (pos + PCI_CAP_LIST_NEXT));
 124                 if (ret < 0) {
 125                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 126                                      (pos + PCI_CAP_LIST_NEXT));
 127                         break;
 128                 }
 129         }
 130         return 0;
 131 }
 132
 133 static int
 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 135 {
 136         uint16_t control;
 137         int pos;
 138         int ret;
 139
 140         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 141         if (pos) {
 142                 ret = rte_pci_read_config(device, &control, sizeof(control),
 143                                     (pos + PCI_MSIX_FLAGS));
 144                 if (ret < 0) {
 145                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 146                                      (pos + PCI_MSIX_FLAGS));
 147                         return -ENXIO;
 148                 }
 149
 150                 if (op)
 151                         control |= PCI_MSIX_FLAGS_ENABLE;
 152                 else
 153                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 154                 ret = rte_pci_write_config(device, &control, sizeof(control),
 155                                           (pos + PCI_MSIX_FLAGS));
 156                 if (ret < 0) {
 157                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 158                                     (pos + PCI_MSIX_FLAGS));
 159                         return -ENXIO;
 160                 }
 161
 162                 return 0;
 163         }
 164
 165         return -ENXIO;
 166 }
 167
 168 static int
 169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 170 {
 171         /* mac address was checked by upper level interface */
 172         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 173         int ret;
 174
 175         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 176                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 177                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 178         if (ret) {
 179                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 180                                       mac_addr);
 181                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 182                          mac_str, ret);
 183         }
 184         return ret;
 185 }
 186
 187 static int
 188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 189 {
 190         /* mac address was checked by upper level interface */
 191         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 192         int ret;
 193
 194         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 195                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 196                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 197                                 false, NULL, 0);
 198         if (ret) {
 199                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 200                                       mac_addr);
 201                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 202                          mac_str, ret);
 203         }
 204         return ret;
 205 }
 206
 207 static int
 208 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 209                     __rte_unused uint32_t idx,
 210                     __rte_unused uint32_t pool)
 211 {
 212         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 213         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 214         int ret;
 215
 216         rte_spinlock_lock(&hw->lock);
 217
 218         /*
 219          * In hns3 network engine adding UC and MC mac address with different
 220          * commands with firmware. We need to determine whether the input
 221          * address is a UC or a MC address to call different commands.
 222          * By the way, it is recommended calling the API function named
 223          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 224          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 225          * may affect the specifications of UC mac addresses.
 226          */
 227         if (rte_is_multicast_ether_addr(mac_addr)) {
 228                 if (hns3_find_duplicate_mc_addr(hw, mac_addr)) {
 229                         rte_spinlock_unlock(&hw->lock);
 230                         return -EINVAL;
 231                 }
 232                 ret = hw->ops.add_mc_mac_addr(hw, mac_addr);
 233         } else {
 234                 ret = hw->ops.add_uc_mac_addr(hw, mac_addr);
 235         }
 236
 237         rte_spinlock_unlock(&hw->lock);
 238         if (ret) {
 239                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 240                                       mac_addr);
 241                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 242                          ret);
 243         }
 244
 245         return ret;
 246 }
 247
 248 static void
 249 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 250 {
 251         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 252         /* index will be checked by upper level rte interface */
 253         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 254         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 255         int ret;
 256
 257         rte_spinlock_lock(&hw->lock);
 258
 259         if (rte_is_multicast_ether_addr(mac_addr))
 260                 ret = hw->ops.del_mc_mac_addr(hw, mac_addr);
 261         else
 262                 ret = hw->ops.del_uc_mac_addr(hw, mac_addr);
 263
 264         rte_spinlock_unlock(&hw->lock);
 265         if (ret) {
 266                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 267                                       mac_addr);
 268                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 269                          mac_str, ret);
 270         }
 271 }
 272
 273 static int
 274 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 275                             struct rte_ether_addr *mac_addr)
 276 {
 277 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 278         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 279         struct rte_ether_addr *old_addr;
 280         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 281         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 282         int ret;
 283
 284         /*
 285          * It has been guaranteed that input parameter named mac_addr is valid
 286          * address in the rte layer of DPDK framework.
 287          */
 288         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 289         rte_spinlock_lock(&hw->lock);
 290         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 291         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 292                RTE_ETHER_ADDR_LEN);
 293
 294         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 295                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 296                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 297         if (ret) {
 298                 /*
 299                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 300                  * driver. When user has configured a MAC address for VF device
 301                  * by "ip link set ..." command based on the PF device, the hns3
 302                  * PF kernel ethdev driver does not allow VF driver to request
 303                  * reconfiguring a different default MAC address, and return
 304                  * -EPREM to VF driver through mailbox.
 305                  */
 306                 if (ret == -EPERM) {
 307                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 308                                               old_addr);
 309                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 310                                   mac_str);
 311                 } else {
 312                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 313                                               mac_addr);
 314                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 315                                  mac_str, ret);
 316                 }
 317         }
 318
 319         rte_ether_addr_copy(mac_addr,
 320                             (struct rte_ether_addr *)hw->mac.mac_addr);
 321         rte_spinlock_unlock(&hw->lock);
 322
 323         return ret;
 324 }
 325
 326 static int
 327 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 328                        struct rte_ether_addr *mac_addr)
 329 {
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int ret;
 332
 333         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 334                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 335                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 336                                 NULL, 0);
 337         if (ret) {
 338                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 339                                       mac_addr);
 340                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 341                          mac_str, ret);
 342         }
 343
 344         return ret;
 345 }
 346
 347 static int
 348 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 349                           struct rte_ether_addr *mac_addr)
 350 {
 351         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 352         int ret;
 353
 354         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 355                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 356                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 357                                 NULL, 0);
 358         if (ret) {
 359                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 360                                       mac_addr);
 361                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 362                          mac_str, ret);
 363         }
 364
 365         return ret;
 366 }
 367
 368 static int
 369 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 370                              struct rte_ether_addr *mc_addr_set,
 371                              uint32_t nb_mc_addr)
 372 {
 373         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 374         struct rte_ether_addr *addr;
 375         uint32_t i;
 376         uint32_t j;
 377
 378         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 379                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
 380                          "invalid. valid range: 0~%d",
 381                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 382                 return -EINVAL;
 383         }
 384
 385         /* Check if input mac addresses are valid */
 386         for (i = 0; i < nb_mc_addr; i++) {
 387                 addr = &mc_addr_set[i];
 388                 if (!rte_is_multicast_ether_addr(addr)) {
 389                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 390                                               addr);
 391                         hns3_err(hw,
 392                                  "failed to set mc mac addr, addr(%s) invalid.",
 393                                  mac_str);
 394                         return -EINVAL;
 395                 }
 396
 397                 /* Check if there are duplicate addresses */
 398                 for (j = i + 1; j < nb_mc_addr; j++) {
 399                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 400                                 hns3_ether_format_addr(mac_str,
 401                                                       RTE_ETHER_ADDR_FMT_SIZE,
 402                                                       addr);
 403                                 hns3_err(hw, "failed to set mc mac addr, "
 404                                          "addrs invalid. two same addrs(%s).",
 405                                          mac_str);
 406                                 return -EINVAL;
 407                         }
 408                 }
 409
 410                 /*
 411                  * Check if there are duplicate addresses between mac_addrs
 412                  * and mc_addr_set
 413                  */
 414                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 415                         if (rte_is_same_ether_addr(addr,
 416                                                    &hw->data->mac_addrs[j])) {
 417                                 hns3_ether_format_addr(mac_str,
 418                                                       RTE_ETHER_ADDR_FMT_SIZE,
 419                                                       addr);
 420                                 hns3_err(hw, "failed to set mc mac addr, "
 421                                          "addrs invalid. addrs(%s) has already "
 422                                          "configured in mac_addr add API",
 423                                          mac_str);
 424                                 return -EINVAL;
 425                         }
 426                 }
 427         }
 428
 429         return 0;
 430 }
 431
 432 static int
 433 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 434                             struct rte_ether_addr *mc_addr_set,
 435                             uint32_t nb_mc_addr)
 436 {
 437         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 438         struct rte_ether_addr *addr;
 439         int cur_addr_num;
 440         int set_addr_num;
 441         int num;
 442         int ret;
 443         int i;
 444
 445         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 446         if (ret)
 447                 return ret;
 448
 449         rte_spinlock_lock(&hw->lock);
 450         cur_addr_num = hw->mc_addrs_num;
 451         for (i = 0; i < cur_addr_num; i++) {
 452                 num = cur_addr_num - i - 1;
 453                 addr = &hw->mc_addrs[num];
 454                 ret = hw->ops.del_mc_mac_addr(hw, addr);
 455                 if (ret) {
 456                         rte_spinlock_unlock(&hw->lock);
 457                         return ret;
 458                 }
 459
 460                 hw->mc_addrs_num--;
 461         }
 462
 463         set_addr_num = (int)nb_mc_addr;
 464         for (i = 0; i < set_addr_num; i++) {
 465                 addr = &mc_addr_set[i];
 466                 ret = hw->ops.add_mc_mac_addr(hw, addr);
 467                 if (ret) {
 468                         rte_spinlock_unlock(&hw->lock);
 469                         return ret;
 470                 }
 471
 472                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 473                 hw->mc_addrs_num++;
 474         }
 475         rte_spinlock_unlock(&hw->lock);
 476
 477         return 0;
 478 }
 479
 480 static int
 481 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 482                         bool en_uc_pmc, bool en_mc_pmc)
 483 {
 484         struct hns3_mbx_vf_to_pf_cmd *req;
 485         struct hns3_cmd_desc desc;
 486         int ret;
 487
 488         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 489
 490         /*
 491          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 492          * so there are some features for promiscuous/allmulticast mode in hns3
 493          * VF PMD driver as below:
 494          * 1. The promiscuous/allmulticast mode can be configured successfully
 495          *    only based on the trusted VF device. If based on the non trusted
 496          *    VF device, configuring promiscuous/allmulticast mode will fail.
 497          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 498          *    kernel ethdev driver on the host by the following command:
 499          *      "ip link set <eth num> vf <vf id> turst on"
 500          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 501          *    driver can receive the ingress and outgoing traffic. In the words,
 502          *    all the ingress packets, all the packets sent from the PF and
 503          *    other VFs on the same physical port.
 504          * 3. Note: Because of the hardware constraints, By default vlan filter
 505          *    is enabled and couldn't be turned off based on VF device, so vlan
 506          *    filter is still effective even in promiscuous mode. If upper
 507          *    applications don't call rte_eth_dev_vlan_filter API function to
 508          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 509          *    the packets with vlan tag in promiscuoue mode.
 510          */
 511         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 512         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 513         req->msg[1] = en_bc_pmc ? 1 : 0;
 514         req->msg[2] = en_uc_pmc ? 1 : 0;
 515         req->msg[3] = en_mc_pmc ? 1 : 0;
 516         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 517
 518         ret = hns3_cmd_send(hw, &desc, 1);
 519         if (ret)
 520                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 521
 522         return ret;
 523 }
 524
 525 static int
 526 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 527 {
 528         struct hns3_adapter *hns = dev->data->dev_private;
 529         struct hns3_hw *hw = &hns->hw;
 530         int ret;
 531
 532         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 533         if (ret)
 534                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 535                         ret);
 536         return ret;
 537 }
 538
 539 static int
 540 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 541 {
 542         bool allmulti = dev->data->all_multicast ? true : false;
 543         struct hns3_adapter *hns = dev->data->dev_private;
 544         struct hns3_hw *hw = &hns->hw;
 545         int ret;
 546
 547         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 548         if (ret)
 549                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 550                         ret);
 551         return ret;
 552 }
 553
 554 static int
 555 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 556 {
 557         struct hns3_adapter *hns = dev->data->dev_private;
 558         struct hns3_hw *hw = &hns->hw;
 559         int ret;
 560
 561         if (dev->data->promiscuous)
 562                 return 0;
 563
 564         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 565         if (ret)
 566                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 567                         ret);
 568         return ret;
 569 }
 570
 571 static int
 572 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 573 {
 574         struct hns3_adapter *hns = dev->data->dev_private;
 575         struct hns3_hw *hw = &hns->hw;
 576         int ret;
 577
 578         if (dev->data->promiscuous)
 579                 return 0;
 580
 581         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 582         if (ret)
 583                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 584                         ret);
 585         return ret;
 586 }
 587
 588 static int
 589 hns3vf_restore_promisc(struct hns3_adapter *hns)
 590 {
 591         struct hns3_hw *hw = &hns->hw;
 592         bool allmulti = hw->data->all_multicast ? true : false;
 593
 594         if (hw->data->promiscuous)
 595                 return hns3vf_set_promisc_mode(hw, true, true, true);
 596
 597         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 598 }
 599
 600 static int
 601 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 602                              bool mmap, enum hns3_ring_type queue_type,
 603                              uint16_t queue_id)
 604 {
 605         struct hns3_vf_bind_vector_msg bind_msg;
 606         const char *op_str;
 607         uint16_t code;
 608         int ret;
 609
 610         memset(&bind_msg, 0, sizeof(bind_msg));
 611         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 612                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 613         bind_msg.vector_id = vector_id;
 614
 615         if (queue_type == HNS3_RING_TYPE_RX)
 616                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 617         else
 618                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 619
 620         bind_msg.param[0].ring_type = queue_type;
 621         bind_msg.ring_num = 1;
 622         bind_msg.param[0].tqp_index = queue_id;
 623         op_str = mmap ? "Map" : "Unmap";
 624         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 625                                 sizeof(bind_msg), false, NULL, 0);
 626         if (ret)
 627                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 628                          op_str, queue_id, bind_msg.vector_id, ret);
 629
 630         return ret;
 631 }
 632
 633 static int
 634 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 635 {
 636         uint16_t vec;
 637         int ret;
 638         int i;
 639
 640         /*
 641          * In hns3 network engine, vector 0 is always the misc interrupt of this
 642          * function, vector 1~N can be used respectively for the queues of the
 643          * function. Tx and Rx queues with the same number share the interrupt
 644          * vector. In the initialization clearing the all hardware mapping
 645          * relationship configurations between queues and interrupt vectors is
 646          * needed, so some error caused by the residual configurations, such as
 647          * the unexpected Tx interrupt, can be avoid.
 648          */
 649         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 650         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 651                 vec = vec - 1; /* the last interrupt is reserved */
 652         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 653         for (i = 0; i < hw->intr_tqps_num; i++) {
 654                 /*
 655                  * Set gap limiter/rate limiter/quanity limiter algorithm
 656                  * configuration for interrupt coalesce of queue's interrupt.
 657                  */
 658                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 659                                        HNS3_TQP_INTR_GL_DEFAULT);
 660                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 661                                        HNS3_TQP_INTR_GL_DEFAULT);
 662                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 663                 /*
 664                  * QL(quantity limiter) is not used currently, just set 0 to
 665                  * close it.
 666                  */
 667                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 668
 669                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 670                                                    HNS3_RING_TYPE_TX, i);
 671                 if (ret) {
 672                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 673                                           "vector: %u, ret=%d", i, vec, ret);
 674                         return ret;
 675                 }
 676
 677                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 678                                                    HNS3_RING_TYPE_RX, i);
 679                 if (ret) {
 680                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 681                                           "vector: %u, ret=%d", i, vec, ret);
 682                         return ret;
 683                 }
 684         }
 685
 686         return 0;
 687 }
 688
 689 static int
 690 hns3vf_dev_configure(struct rte_eth_dev *dev)
 691 {
 692         struct hns3_adapter *hns = dev->data->dev_private;
 693         struct hns3_hw *hw = &hns->hw;
 694         struct rte_eth_conf *conf = &dev->data->dev_conf;
 695         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 696         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 697         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 698         struct rte_eth_rss_conf rss_conf;
 699         bool gro_en;
 700         int ret;
 701
 702         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 703
 704         /*
 705          * Some versions of hardware network engine does not support
 706          * individually enable/disable/reset the Tx or Rx queue. These devices
 707          * must enable/disable/reset Tx and Rx queues at the same time. When the
 708          * numbers of Tx queues allocated by upper applications are not equal to
 709          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 710          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 711          * work as usual. But these fake queues are imperceptible, and can not
 712          * be used by upper applications.
 713          */
 714         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 715         if (ret) {
 716                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
 717                 hw->cfg_max_queues = 0;
 718                 return ret;
 719         }
 720
 721         hw->adapter_state = HNS3_NIC_CONFIGURING;
 722         if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
 723                 hns3_err(hw, "setting link speed/duplex not supported");
 724                 ret = -EINVAL;
 725                 goto cfg_err;
 726         }
 727
 728         /* When RSS is not configured, redirect the packet queue 0 */
 729         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
 730                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
 731                 hw->rss_dis_flag = false;
 732                 rss_conf = conf->rx_adv_conf.rss_conf;
 733                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 734                 if (ret)
 735                         goto cfg_err;
 736         }
 737
 738         ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
 739         if (ret != 0)
 740                 goto cfg_err;
 741
 742         ret = hns3vf_dev_configure_vlan(dev);
 743         if (ret)
 744                 goto cfg_err;
 745
 746         /* config hardware GRO */
 747         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
 748         ret = hns3_config_gro(hw, gro_en);
 749         if (ret)
 750                 goto cfg_err;
 751
 752         hns3_init_rx_ptype_tble(dev);
 753
 754         hw->adapter_state = HNS3_NIC_CONFIGURED;
 755         return 0;
 756
 757 cfg_err:
 758         hw->cfg_max_queues = 0;
 759         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 760         hw->adapter_state = HNS3_NIC_INITIALIZED;
 761
 762         return ret;
 763 }
 764
 765 static int
 766 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 767 {
 768         int ret;
 769
 770         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 771                                 sizeof(mtu), true, NULL, 0);
 772         if (ret)
 773                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 774
 775         return ret;
 776 }
 777
 778 static int
 779 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 780 {
 781         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 782         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 783         int ret;
 784
 785         /*
 786          * The hns3 PF/VF devices on the same port share the hardware MTU
 787          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 788          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 789          * driver, there is no need to stop the port for hns3 VF device, and the
 790          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 791          * PF's MTU.
 792          */
 793         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 794                 hns3_err(hw, "Failed to set mtu during resetting");
 795                 return -EIO;
 796         }
 797
 798         /*
 799          * when Rx of scattered packets is off, we have some possibility of
 800          * using vector Rx process function or simple Rx functions in hns3 PMD
 801          * driver. If the input MTU is increased and the maximum length of
 802          * received packets is greater than the length of a buffer for Rx
 803          * packet, the hardware network engine needs to use multiple BDs and
 804          * buffers to store these packets. This will cause problems when still
 805          * using vector Rx process function or simple Rx function to receiving
 806          * packets. So, when Rx of scattered packets is off and device is
 807          * started, it is not permitted to increase MTU so that the maximum
 808          * length of Rx packets is greater than Rx buffer length.
 809          */
 810         if (dev->data->dev_started && !dev->data->scattered_rx &&
 811             frame_size > hw->rx_buf_len) {
 812                 hns3_err(hw, "failed to set mtu because current is "
 813                         "not scattered rx mode");
 814                 return -EOPNOTSUPP;
 815         }
 816
 817         rte_spinlock_lock(&hw->lock);
 818         ret = hns3vf_config_mtu(hw, mtu);
 819         if (ret) {
 820                 rte_spinlock_unlock(&hw->lock);
 821                 return ret;
 822         }
 823         rte_spinlock_unlock(&hw->lock);
 824
 825         return 0;
 826 }
 827
 828 static int
 829 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 830 {
 831         struct hns3_adapter *hns = eth_dev->data->dev_private;
 832         struct hns3_hw *hw = &hns->hw;
 833         uint16_t q_num = hw->tqps_num;
 834
 835         /*
 836          * In interrupt mode, 'max_rx_queues' is set based on the number of
 837          * MSI-X interrupt resources of the hardware.
 838          */
 839         if (hw->data->dev_conf.intr_conf.rxq == 1)
 840                 q_num = hw->intr_tqps_num;
 841
 842         info->max_rx_queues = q_num;
 843         info->max_tx_queues = hw->tqps_num;
 844         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 845         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 846         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 847         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 848         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 849
 850         info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
 851                                  RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
 852                                  RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
 853                                  RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
 854                                  RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 855                                  RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
 856                                  RTE_ETH_RX_OFFLOAD_SCATTER |
 857                                  RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
 858                                  RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
 859                                  RTE_ETH_RX_OFFLOAD_RSS_HASH |
 860                                  RTE_ETH_RX_OFFLOAD_TCP_LRO);
 861         info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 862                                  RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
 863                                  RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
 864                                  RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
 865                                  RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
 866                                  RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
 867                                  RTE_ETH_TX_OFFLOAD_TCP_TSO |
 868                                  RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
 869                                  RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
 870                                  RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
 871                                  RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
 872                                  hns3_txvlan_cap_get(hw));
 873
 874         if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
 875                 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
 876
 877         if (hns3_dev_get_support(hw, INDEP_TXRX))
 878                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 879                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 880
 881         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 882                 .nb_max = HNS3_MAX_RING_DESC,
 883                 .nb_min = HNS3_MIN_RING_DESC,
 884                 .nb_align = HNS3_ALIGN_RING_DESC,
 885         };
 886
 887         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 888                 .nb_max = HNS3_MAX_RING_DESC,
 889                 .nb_min = HNS3_MIN_RING_DESC,
 890                 .nb_align = HNS3_ALIGN_RING_DESC,
 891                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 892                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
 893         };
 894
 895         info->default_rxconf = (struct rte_eth_rxconf) {
 896                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 897                 /*
 898                  * If there are no available Rx buffer descriptors, incoming
 899                  * packets are always dropped by hardware based on hns3 network
 900                  * engine.
 901                  */
 902                 .rx_drop_en = 1,
 903                 .offloads = 0,
 904         };
 905         info->default_txconf = (struct rte_eth_txconf) {
 906                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 907                 .offloads = 0,
 908         };
 909
 910         info->reta_size = hw->rss_ind_tbl_size;
 911         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 912         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 913
 914         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 915         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 916         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 917         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 918         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 919         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 920
 921         return 0;
 922 }
 923
 924 static void
 925 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 926 {
 927         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 928 }
 929
 930 static void
 931 hns3vf_disable_irq0(struct hns3_hw *hw)
 932 {
 933         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 934 }
 935
 936 static void
 937 hns3vf_enable_irq0(struct hns3_hw *hw)
 938 {
 939         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 940 }
 941
 942 static enum hns3vf_evt_cause
 943 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 944 {
 945         struct hns3_hw *hw = &hns->hw;
 946         enum hns3vf_evt_cause ret;
 947         uint32_t cmdq_stat_reg;
 948         uint32_t rst_ing_reg;
 949         uint32_t val;
 950
 951         /* Fetch the events from their corresponding regs */
 952         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 953         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 954                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 955                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 956                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 957                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 958                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 959                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 960                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 961                 if (clearval) {
 962                         hw->reset.stats.global_cnt++;
 963                         hns3_warn(hw, "Global reset detected, clear reset status");
 964                 } else {
 965                         hns3_schedule_delayed_reset(hns);
 966                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 967                 }
 968
 969                 ret = HNS3VF_VECTOR0_EVENT_RST;
 970                 goto out;
 971         }
 972
 973         /* Check for vector0 mailbox(=CMDQ RX) event source */
 974         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
 975                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 976                 ret = HNS3VF_VECTOR0_EVENT_MBX;
 977                 goto out;
 978         }
 979
 980         val = 0;
 981         ret = HNS3VF_VECTOR0_EVENT_OTHER;
 982 out:
 983         if (clearval)
 984                 *clearval = val;
 985         return ret;
 986 }
 987
 988 static void
 989 hns3vf_interrupt_handler(void *param)
 990 {
 991         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 992         struct hns3_adapter *hns = dev->data->dev_private;
 993         struct hns3_hw *hw = &hns->hw;
 994         enum hns3vf_evt_cause event_cause;
 995         uint32_t clearval;
 996
 997         /* Disable interrupt */
 998         hns3vf_disable_irq0(hw);
 999
1000         /* Read out interrupt causes */
1001         event_cause = hns3vf_check_event_cause(hns, &clearval);
1002         /* Clear interrupt causes */
1003         hns3vf_clear_event_cause(hw, clearval);
1004
1005         switch (event_cause) {
1006         case HNS3VF_VECTOR0_EVENT_RST:
1007                 hns3_schedule_reset(hns);
1008                 break;
1009         case HNS3VF_VECTOR0_EVENT_MBX:
1010                 hns3_dev_handle_mbx_msg(hw);
1011                 break;
1012         default:
1013                 break;
1014         }
1015
1016         /* Enable interrupt */
1017         hns3vf_enable_irq0(hw);
1018 }
1019
1020 static void
1021 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1022 {
1023         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1024         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1025         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1026         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1027 }
1028
1029 static void
1030 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1031 {
1032         struct hns3_dev_specs_0_cmd *req0;
1033
1034         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1035
1036         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1037         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1038         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1039         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1040 }
1041
1042 static int
1043 hns3vf_check_dev_specifications(struct hns3_hw *hw)
1044 {
1045         if (hw->rss_ind_tbl_size == 0 ||
1046             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
1047                 hns3_warn(hw, "the size of hash lookup table configured (%u)"
1048                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
1049                               HNS3_RSS_IND_TBL_SIZE_MAX);
1050                 return -EINVAL;
1051         }
1052
1053         return 0;
1054 }
1055
1056 static int
1057 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1058 {
1059         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1060         int ret;
1061         int i;
1062
1063         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1064                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1065                                           true);
1066                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1067         }
1068         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1069
1070         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1071         if (ret)
1072                 return ret;
1073
1074         hns3vf_parse_dev_specifications(hw, desc);
1075
1076         return hns3vf_check_dev_specifications(hw);
1077 }
1078
1079 void
1080 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
1081 {
1082         uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
1083                                    HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1084         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1085         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1086
1087         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1088                 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1089                                           __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1090 }
1091
1092 static void
1093 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
1094 {
1095 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS      500
1096
1097         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1098         int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
1099         uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1100         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1101         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1102
1103         __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
1104                          __ATOMIC_RELEASE);
1105
1106         (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1107                                 NULL, 0);
1108
1109         while (remain_ms > 0) {
1110                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
1111                 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
1112                         HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1113                         break;
1114                 remain_ms--;
1115         }
1116
1117         /*
1118          * When exit above loop, the pf_push_lsc_cap could be one of the three
1119          * state: unknown (means pf not ack), not_supported, supported.
1120          * Here config it as 'not_supported' when it's 'unknown' state.
1121          */
1122         __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1123                                   __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1124
1125         if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
1126                 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
1127                 hns3_info(hw, "detect PF support push link status change!");
1128         } else {
1129                 /*
1130                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
1131                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
1132                  * the RTE_ETH_DEV_INTR_LSC capability.
1133                  */
1134                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1135         }
1136 }
1137
1138 static int
1139 hns3vf_get_capability(struct hns3_hw *hw)
1140 {
1141         struct rte_pci_device *pci_dev;
1142         struct rte_eth_dev *eth_dev;
1143         uint8_t revision;
1144         int ret;
1145
1146         eth_dev = &rte_eth_devices[hw->data->port_id];
1147         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1148
1149         /* Get PCI revision id */
1150         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1151                                   HNS3_PCI_REVISION_ID);
1152         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1153                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1154                              ret);
1155                 return -EIO;
1156         }
1157         hw->revision = revision;
1158
1159         if (revision < PCI_REVISION_ID_HIP09_A) {
1160                 hns3vf_set_default_dev_specifications(hw);
1161                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1162                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1163                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1164                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
1165                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1166                 hw->rss_info.ipv6_sctp_offload_supported = false;
1167                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1168                 return 0;
1169         }
1170
1171         ret = hns3vf_query_dev_specifications(hw);
1172         if (ret) {
1173                 PMD_INIT_LOG(ERR,
1174                              "failed to query dev specifications, ret = %d",
1175                              ret);
1176                 return ret;
1177         }
1178
1179         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1180         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1181         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1182         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1183         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1184         hw->rss_info.ipv6_sctp_offload_supported = true;
1185         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1186
1187         return 0;
1188 }
1189
1190 static int
1191 hns3vf_check_tqp_info(struct hns3_hw *hw)
1192 {
1193         if (hw->tqps_num == 0) {
1194                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1195                 return -EINVAL;
1196         }
1197
1198         if (hw->rss_size_max == 0) {
1199                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1200                 return -EINVAL;
1201         }
1202
1203         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1204
1205         return 0;
1206 }
1207
1208 static int
1209 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1210 {
1211         uint8_t resp_msg;
1212         int ret;
1213
1214         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1215                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1216                                 true, &resp_msg, sizeof(resp_msg));
1217         if (ret) {
1218                 if (ret == -ETIME) {
1219                         /*
1220                          * Getting current port based VLAN state from PF driver
1221                          * will not affect VF driver's basic function. Because
1222                          * the VF driver relies on hns3 PF kernel ether driver,
1223                          * to avoid introducing compatibility issues with older
1224                          * version of PF driver, no failure will be returned
1225                          * when the return value is ETIME. This return value has
1226                          * the following scenarios:
1227                          * 1) Firmware didn't return the results in time
1228                          * 2) the result return by firmware is timeout
1229                          * 3) the older version of kernel side PF driver does
1230                          *    not support this mailbox message.
1231                          * For scenarios 1 and 2, it is most likely that a
1232                          * hardware error has occurred, or a hardware reset has
1233                          * occurred. In this case, these errors will be caught
1234                          * by other functions.
1235                          */
1236                         PMD_INIT_LOG(WARNING,
1237                                 "failed to get PVID state for timeout, maybe "
1238                                 "kernel side PF driver doesn't support this "
1239                                 "mailbox message, or firmware didn't respond.");
1240                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1241                 } else {
1242                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1243                                 " ret = %d", ret);
1244                         return ret;
1245                 }
1246         }
1247         hw->port_base_vlan_cfg.state = resp_msg ?
1248                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1249         return 0;
1250 }
1251
1252 static int
1253 hns3vf_get_queue_info(struct hns3_hw *hw)
1254 {
1255 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1256         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1257         int ret;
1258
1259         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1260                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1261         if (ret) {
1262                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1263                 return ret;
1264         }
1265
1266         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1267         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1268
1269         return hns3vf_check_tqp_info(hw);
1270 }
1271
1272 static int
1273 hns3vf_get_queue_depth(struct hns3_hw *hw)
1274 {
1275 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1276         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1277         int ret;
1278
1279         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1280                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1281         if (ret) {
1282                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1283                              ret);
1284                 return ret;
1285         }
1286
1287         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1288         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1289
1290         return 0;
1291 }
1292
1293 static void
1294 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1295 {
1296         if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1297                 hns3_set_bit(hw->capability,
1298                                 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1299 }
1300
1301 static int
1302 hns3vf_get_num_tc(struct hns3_hw *hw)
1303 {
1304         uint8_t num_tc = 0;
1305         uint32_t i;
1306
1307         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1308                 if (hw->hw_tc_map & BIT(i))
1309                         num_tc++;
1310         }
1311         return num_tc;
1312 }
1313
1314 static int
1315 hns3vf_get_basic_info(struct hns3_hw *hw)
1316 {
1317         uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1318         struct hns3_basic_info *basic_info;
1319         int ret;
1320
1321         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1322                                 true, resp_msg, sizeof(resp_msg));
1323         if (ret) {
1324                 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1325                                 ret);
1326                 return ret;
1327         }
1328
1329         basic_info = (struct hns3_basic_info *)resp_msg;
1330         hw->hw_tc_map = basic_info->hw_tc_map;
1331         hw->num_tc = hns3vf_get_num_tc(hw);
1332         hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1333         hns3vf_update_caps(hw, basic_info->caps);
1334
1335         return 0;
1336 }
1337
1338 static int
1339 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1340 {
1341         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1342         int ret;
1343
1344         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1345                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1346         if (ret) {
1347                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1348                 return ret;
1349         }
1350
1351         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1352
1353         return 0;
1354 }
1355
1356 static int
1357 hns3vf_get_configuration(struct hns3_hw *hw)
1358 {
1359         int ret;
1360
1361         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1362         hw->rss_dis_flag = false;
1363
1364         /* Get device capability */
1365         ret = hns3vf_get_capability(hw);
1366         if (ret) {
1367                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1368                 return ret;
1369         }
1370
1371         hns3vf_get_push_lsc_cap(hw);
1372
1373         /* Get basic info from PF */
1374         ret = hns3vf_get_basic_info(hw);
1375         if (ret)
1376                 return ret;
1377
1378         /* Get queue configuration from PF */
1379         ret = hns3vf_get_queue_info(hw);
1380         if (ret)
1381                 return ret;
1382
1383         /* Get queue depth info from PF */
1384         ret = hns3vf_get_queue_depth(hw);
1385         if (ret)
1386                 return ret;
1387
1388         /* Get user defined VF MAC addr from PF */
1389         ret = hns3vf_get_host_mac_addr(hw);
1390         if (ret)
1391                 return ret;
1392
1393         return hns3vf_get_port_base_vlan_filter_state(hw);
1394 }
1395
1396 static int
1397 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1398                             uint16_t nb_tx_q)
1399 {
1400         struct hns3_hw *hw = &hns->hw;
1401
1402         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1403 }
1404
1405 static void
1406 hns3vf_request_link_info(struct hns3_hw *hw)
1407 {
1408         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1409         bool send_req;
1410         int ret;
1411
1412         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1413                 return;
1414
1415         send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1416                    vf->req_link_info_cnt > 0;
1417         if (!send_req)
1418                 return;
1419
1420         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1421                                 NULL, 0);
1422         if (ret) {
1423                 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1424                 return;
1425         }
1426
1427         if (vf->req_link_info_cnt > 0)
1428                 vf->req_link_info_cnt--;
1429 }
1430
1431 void
1432 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1433                           uint32_t link_speed, uint8_t link_duplex)
1434 {
1435         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1436         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1437         struct hns3_mac *mac = &hw->mac;
1438         int ret;
1439
1440         /*
1441          * PF kernel driver may push link status when VF driver is in resetting,
1442          * driver will stop polling job in this case, after resetting done
1443          * driver will start polling job again.
1444          * When polling job started, driver will get initial link status by
1445          * sending request to PF kernel driver, then could update link status by
1446          * process PF kernel driver's link status mailbox message.
1447          */
1448         if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1449                 return;
1450
1451         if (hw->adapter_state != HNS3_NIC_STARTED)
1452                 return;
1453
1454         mac->link_status = link_status;
1455         mac->link_speed = link_speed;
1456         mac->link_duplex = link_duplex;
1457         ret = hns3vf_dev_link_update(dev, 0);
1458         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1459                 hns3_start_report_lse(dev);
1460 }
1461
1462 static int
1463 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1464 {
1465 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1466         struct hns3_hw *hw = &hns->hw;
1467         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1468         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1469         uint8_t is_kill = on ? 0 : 1;
1470
1471         msg_data[0] = is_kill;
1472         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1473         memcpy(&msg_data[3], &proto, sizeof(proto));
1474
1475         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1476                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1477                                  0);
1478 }
1479
1480 static int
1481 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1482 {
1483         struct hns3_adapter *hns = dev->data->dev_private;
1484         struct hns3_hw *hw = &hns->hw;
1485         int ret;
1486
1487         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1488                 hns3_err(hw,
1489                          "vf set vlan id failed during resetting, vlan_id =%u",
1490                          vlan_id);
1491                 return -EIO;
1492         }
1493         rte_spinlock_lock(&hw->lock);
1494         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1495         rte_spinlock_unlock(&hw->lock);
1496         if (ret)
1497                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1498                          vlan_id, ret);
1499
1500         return ret;
1501 }
1502
1503 static int
1504 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1505 {
1506         uint8_t msg_data;
1507         int ret;
1508
1509         if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1510                 return 0;
1511
1512         msg_data = enable ? 1 : 0;
1513         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1514                         HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1515                         sizeof(msg_data), true, NULL, 0);
1516         if (ret)
1517                 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1518                                 enable ? "enable" : "disable", ret);
1519
1520         return ret;
1521 }
1522
1523 static int
1524 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1525 {
1526         uint8_t msg_data;
1527         int ret;
1528
1529         msg_data = enable ? 1 : 0;
1530         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1531                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1532         if (ret)
1533                 hns3_err(hw, "vf %s strip failed, ret = %d.",
1534                                 enable ? "enable" : "disable", ret);
1535
1536         return ret;
1537 }
1538
1539 static int
1540 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1541 {
1542         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1543         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1544         unsigned int tmp_mask;
1545         int ret = 0;
1546
1547         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1548                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1549                              "mask = 0x%x", mask);
1550                 return -EIO;
1551         }
1552
1553         tmp_mask = (unsigned int)mask;
1554
1555         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
1556                 rte_spinlock_lock(&hw->lock);
1557                 /* Enable or disable VLAN filter */
1558                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1559                         ret = hns3vf_en_vlan_filter(hw, true);
1560                 else
1561                         ret = hns3vf_en_vlan_filter(hw, false);
1562                 rte_spinlock_unlock(&hw->lock);
1563                 if (ret)
1564                         return ret;
1565         }
1566
1567         /* Vlan stripping setting */
1568         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
1569                 rte_spinlock_lock(&hw->lock);
1570                 /* Enable or disable VLAN stripping */
1571                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1572                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1573                 else
1574                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1575                 rte_spinlock_unlock(&hw->lock);
1576         }
1577
1578         return ret;
1579 }
1580
1581 static int
1582 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1583 {
1584         struct rte_vlan_filter_conf *vfc;
1585         struct hns3_hw *hw = &hns->hw;
1586         uint16_t vlan_id;
1587         uint64_t vbit;
1588         uint64_t ids;
1589         int ret = 0;
1590         uint32_t i;
1591
1592         vfc = &hw->data->vlan_filter_conf;
1593         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1594                 if (vfc->ids[i] == 0)
1595                         continue;
1596                 ids = vfc->ids[i];
1597                 while (ids) {
1598                         /*
1599                          * 64 means the num bits of ids, one bit corresponds to
1600                          * one vlan id
1601                          */
1602                         vlan_id = 64 * i;
1603                         /* count trailing zeroes */
1604                         vbit = ~ids & (ids - 1);
1605                         /* clear least significant bit set */
1606                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1607                         for (; vbit;) {
1608                                 vbit >>= 1;
1609                                 vlan_id++;
1610                         }
1611                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1612                         if (ret) {
1613                                 hns3_err(hw,
1614                                          "VF handle vlan table failed, ret =%d, on = %d",
1615                                          ret, on);
1616                                 return ret;
1617                         }
1618                 }
1619         }
1620
1621         return ret;
1622 }
1623
1624 static int
1625 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1626 {
1627         return hns3vf_handle_all_vlan_table(hns, 0);
1628 }
1629
1630 static int
1631 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1632 {
1633         struct hns3_hw *hw = &hns->hw;
1634         struct rte_eth_conf *dev_conf;
1635         bool en;
1636         int ret;
1637
1638         dev_conf = &hw->data->dev_conf;
1639         en = dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? true
1640                                                                    : false;
1641         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1642         if (ret)
1643                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1644                          ret);
1645         return ret;
1646 }
1647
1648 static int
1649 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1650 {
1651         struct hns3_adapter *hns = dev->data->dev_private;
1652         struct rte_eth_dev_data *data = dev->data;
1653         struct hns3_hw *hw = &hns->hw;
1654         int ret;
1655
1656         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1657             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1658             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1659                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1660                               "or hw_vlan_insert_pvid is not support!");
1661         }
1662
1663         /* Apply vlan offload setting */
1664         ret = hns3vf_vlan_offload_set(dev, RTE_ETH_VLAN_STRIP_MASK |
1665                                         RTE_ETH_VLAN_FILTER_MASK);
1666         if (ret)
1667                 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1668
1669         return ret;
1670 }
1671
1672 static int
1673 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1674 {
1675         uint8_t msg_data;
1676
1677         msg_data = alive ? 1 : 0;
1678         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1679                                  sizeof(msg_data), false, NULL, 0);
1680 }
1681
1682 static void
1683 hns3vf_keep_alive_handler(void *param)
1684 {
1685         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1686         struct hns3_adapter *hns = eth_dev->data->dev_private;
1687         struct hns3_hw *hw = &hns->hw;
1688         int ret;
1689
1690         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1691                                 false, NULL, 0);
1692         if (ret)
1693                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1694                          ret);
1695
1696         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1697                           eth_dev);
1698 }
1699
1700 static void
1701 hns3vf_service_handler(void *param)
1702 {
1703         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1704         struct hns3_adapter *hns = eth_dev->data->dev_private;
1705         struct hns3_hw *hw = &hns->hw;
1706
1707         /*
1708          * The query link status and reset processing are executed in the
1709          * interrupt thread. When the IMP reset occurs, IMP will not respond,
1710          * and the query operation will timeout after 30ms. In the case of
1711          * multiple PF/VFs, each query failure timeout causes the IMP reset
1712          * interrupt to fail to respond within 100ms.
1713          * Before querying the link status, check whether there is a reset
1714          * pending, and if so, abandon the query.
1715          */
1716         if (!hns3vf_is_reset_pending(hns))
1717                 hns3vf_request_link_info(hw);
1718         else
1719                 hns3_warn(hw, "Cancel the query when reset is pending");
1720
1721         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1722                           eth_dev);
1723 }
1724
1725 static void
1726 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1727 {
1728 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT      3
1729
1730         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1731
1732         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1733                 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1734
1735         __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1736
1737         hns3vf_service_handler(dev);
1738 }
1739
1740 static void
1741 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1742 {
1743         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1744
1745         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1746
1747         __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1748 }
1749
1750 static int
1751 hns3_query_vf_resource(struct hns3_hw *hw)
1752 {
1753         struct hns3_vf_res_cmd *req;
1754         struct hns3_cmd_desc desc;
1755         uint16_t num_msi;
1756         int ret;
1757
1758         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1759         ret = hns3_cmd_send(hw, &desc, 1);
1760         if (ret) {
1761                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1762                 return ret;
1763         }
1764
1765         req = (struct hns3_vf_res_cmd *)desc.data;
1766         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1767                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1768         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1769                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1770                          num_msi, HNS3_MIN_VECTOR_NUM);
1771                 return -EINVAL;
1772         }
1773
1774         hw->num_msi = num_msi;
1775
1776         return 0;
1777 }
1778
1779 static int
1780 hns3vf_init_hardware(struct hns3_adapter *hns)
1781 {
1782         struct hns3_hw *hw = &hns->hw;
1783         uint16_t mtu = hw->data->mtu;
1784         int ret;
1785
1786         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1787         if (ret)
1788                 return ret;
1789
1790         ret = hns3vf_config_mtu(hw, mtu);
1791         if (ret)
1792                 goto err_init_hardware;
1793
1794         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1795         if (ret) {
1796                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1797                 goto err_init_hardware;
1798         }
1799
1800         ret = hns3_config_gro(hw, false);
1801         if (ret) {
1802                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1803                 goto err_init_hardware;
1804         }
1805
1806         /*
1807          * In the initialization clearing the all hardware mapping relationship
1808          * configurations between queues and interrupt vectors is needed, so
1809          * some error caused by the residual configurations, such as the
1810          * unexpected interrupt, can be avoid.
1811          */
1812         ret = hns3vf_init_ring_with_vector(hw);
1813         if (ret) {
1814                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1815                 goto err_init_hardware;
1816         }
1817
1818         return 0;
1819
1820 err_init_hardware:
1821         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1822         return ret;
1823 }
1824
1825 static int
1826 hns3vf_clear_vport_list(struct hns3_hw *hw)
1827 {
1828         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1829                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1830                                  NULL, 0);
1831 }
1832
1833 static int
1834 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1835 {
1836         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1837         struct hns3_adapter *hns = eth_dev->data->dev_private;
1838         struct hns3_hw *hw = &hns->hw;
1839         int ret;
1840
1841         PMD_INIT_FUNC_TRACE();
1842
1843         /* Get hardware io base address from pcie BAR2 IO space */
1844         hw->io_base = pci_dev->mem_resource[2].addr;
1845
1846         /* Firmware command queue initialize */
1847         ret = hns3_cmd_init_queue(hw);
1848         if (ret) {
1849                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1850                 goto err_cmd_init_queue;
1851         }
1852
1853         /* Firmware command initialize */
1854         ret = hns3_cmd_init(hw);
1855         if (ret) {
1856                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1857                 goto err_cmd_init;
1858         }
1859
1860         hns3_tx_push_init(eth_dev);
1861
1862         /* Get VF resource */
1863         ret = hns3_query_vf_resource(hw);
1864         if (ret)
1865                 goto err_cmd_init;
1866
1867         rte_spinlock_init(&hw->mbx_resp.lock);
1868
1869         hns3vf_clear_event_cause(hw, 0);
1870
1871         ret = rte_intr_callback_register(pci_dev->intr_handle,
1872                                          hns3vf_interrupt_handler, eth_dev);
1873         if (ret) {
1874                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1875                 goto err_intr_callback_register;
1876         }
1877
1878         /* Enable interrupt */
1879         rte_intr_enable(pci_dev->intr_handle);
1880         hns3vf_enable_irq0(hw);
1881
1882         /* Get configuration from PF */
1883         ret = hns3vf_get_configuration(hw);
1884         if (ret) {
1885                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1886                 goto err_get_config;
1887         }
1888
1889         ret = hns3_tqp_stats_init(hw);
1890         if (ret)
1891                 goto err_get_config;
1892
1893         /* Hardware statistics of imissed registers cleared. */
1894         ret = hns3_update_imissed_stats(hw, true);
1895         if (ret) {
1896                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1897                 goto err_set_tc_queue;
1898         }
1899
1900         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1901         if (ret) {
1902                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1903                 goto err_set_tc_queue;
1904         }
1905
1906         ret = hns3vf_clear_vport_list(hw);
1907         if (ret) {
1908                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1909                 goto err_set_tc_queue;
1910         }
1911
1912         ret = hns3vf_init_hardware(hns);
1913         if (ret)
1914                 goto err_set_tc_queue;
1915
1916         hns3_rss_set_default_args(hw);
1917
1918         ret = hns3vf_set_alive(hw, true);
1919         if (ret) {
1920                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1921                 goto err_set_tc_queue;
1922         }
1923
1924         return 0;
1925
1926 err_set_tc_queue:
1927         hns3_tqp_stats_uninit(hw);
1928
1929 err_get_config:
1930         hns3vf_disable_irq0(hw);
1931         rte_intr_disable(pci_dev->intr_handle);
1932         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1933                              eth_dev);
1934 err_intr_callback_register:
1935 err_cmd_init:
1936         hns3_cmd_uninit(hw);
1937         hns3_cmd_destroy_queue(hw);
1938 err_cmd_init_queue:
1939         hw->io_base = NULL;
1940
1941         return ret;
1942 }
1943
1944 static void
1945 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1946 {
1947         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1948         struct hns3_adapter *hns = eth_dev->data->dev_private;
1949         struct hns3_hw *hw = &hns->hw;
1950
1951         PMD_INIT_FUNC_TRACE();
1952
1953         hns3_rss_uninit(hns);
1954         (void)hns3_config_gro(hw, false);
1955         (void)hns3vf_set_alive(hw, false);
1956         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1957         hns3_flow_uninit(eth_dev);
1958         hns3_tqp_stats_uninit(hw);
1959         hns3vf_disable_irq0(hw);
1960         rte_intr_disable(pci_dev->intr_handle);
1961         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1962                              eth_dev);
1963         hns3_cmd_uninit(hw);
1964         hns3_cmd_destroy_queue(hw);
1965         hw->io_base = NULL;
1966 }
1967
1968 static int
1969 hns3vf_do_stop(struct hns3_adapter *hns)
1970 {
1971         struct hns3_hw *hw = &hns->hw;
1972         int ret;
1973
1974         hw->mac.link_status = RTE_ETH_LINK_DOWN;
1975
1976         /*
1977          * The "hns3vf_do_stop" function will also be called by .stop_service to
1978          * prepare reset. At the time of global or IMP reset, the command cannot
1979          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
1980          * accessed during the reset process. So the mbuf can not be released
1981          * during reset and is required to be released after the reset is
1982          * completed.
1983          */
1984         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
1985                 hns3_dev_release_mbufs(hns);
1986
1987         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
1988                 hns3_configure_all_mac_addr(hns, true);
1989                 ret = hns3_reset_all_tqps(hns);
1990                 if (ret) {
1991                         hns3_err(hw, "failed to reset all queues ret = %d",
1992                                  ret);
1993                         return ret;
1994                 }
1995         }
1996         return 0;
1997 }
1998
1999 static void
2000 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
2001 {
2002         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2003         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2004         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2005         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2006         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2007         uint16_t q_id;
2008
2009         if (dev->data->dev_conf.intr_conf.rxq == 0)
2010                 return;
2011
2012         /* unmap the ring with vector */
2013         if (rte_intr_allow_others(intr_handle)) {
2014                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2015                 base = RTE_INTR_VEC_RXTX_OFFSET;
2016         }
2017         if (rte_intr_dp_is_en(intr_handle)) {
2018                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2019                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
2020                                                            HNS3_RING_TYPE_RX,
2021                                                            q_id);
2022                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
2023                             - 1)
2024                                 vec++;
2025                 }
2026         }
2027         /* Clean datapath event and queue/vec mapping */
2028         rte_intr_efd_disable(intr_handle);
2029
2030         /* Cleanup vector list */
2031         rte_intr_vec_list_free(intr_handle);
2032 }
2033
2034 static int
2035 hns3vf_dev_stop(struct rte_eth_dev *dev)
2036 {
2037         struct hns3_adapter *hns = dev->data->dev_private;
2038         struct hns3_hw *hw = &hns->hw;
2039
2040         PMD_INIT_FUNC_TRACE();
2041         dev->data->dev_started = 0;
2042
2043         hw->adapter_state = HNS3_NIC_STOPPING;
2044         hns3_set_rxtx_function(dev);
2045         rte_wmb();
2046         /* Disable datapath on secondary process. */
2047         hns3_mp_req_stop_rxtx(dev);
2048         /* Prevent crashes when queues are still in use. */
2049         rte_delay_ms(hw->cfg_max_queues);
2050
2051         rte_spinlock_lock(&hw->lock);
2052         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
2053                 hns3_stop_tqps(hw);
2054                 hns3vf_do_stop(hns);
2055                 hns3vf_unmap_rx_interrupt(dev);
2056                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2057         }
2058         hns3_rx_scattered_reset(dev);
2059         hns3vf_stop_poll_job(dev);
2060         hns3_stop_report_lse(dev);
2061         rte_spinlock_unlock(&hw->lock);
2062
2063         return 0;
2064 }
2065
2066 static int
2067 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
2068 {
2069         struct hns3_adapter *hns = eth_dev->data->dev_private;
2070         struct hns3_hw *hw = &hns->hw;
2071         int ret = 0;
2072
2073         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2074                 return 0;
2075
2076         if (hw->adapter_state == HNS3_NIC_STARTED)
2077                 ret = hns3vf_dev_stop(eth_dev);
2078
2079         hw->adapter_state = HNS3_NIC_CLOSING;
2080         hns3_reset_abort(hns);
2081         hw->adapter_state = HNS3_NIC_CLOSED;
2082         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
2083         hns3_configure_all_mc_mac_addr(hns, true);
2084         hns3vf_remove_all_vlan_table(hns);
2085         hns3vf_uninit_vf(eth_dev);
2086         hns3_free_all_queues(eth_dev);
2087         rte_free(hw->reset.wait_data);
2088         hns3_mp_uninit_primary();
2089         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
2090
2091         return ret;
2092 }
2093
2094 static int
2095 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2096                       size_t fw_size)
2097 {
2098         struct hns3_adapter *hns = eth_dev->data->dev_private;
2099         struct hns3_hw *hw = &hns->hw;
2100         uint32_t version = hw->fw_version;
2101         int ret;
2102
2103         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2104                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2105                                       HNS3_FW_VERSION_BYTE3_S),
2106                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2107                                       HNS3_FW_VERSION_BYTE2_S),
2108                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2109                                       HNS3_FW_VERSION_BYTE1_S),
2110                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2111                                       HNS3_FW_VERSION_BYTE0_S));
2112         if (ret < 0)
2113                 return -EINVAL;
2114
2115         ret += 1; /* add the size of '\0' */
2116         if (fw_size < (size_t)ret)
2117                 return ret;
2118         else
2119                 return 0;
2120 }
2121
2122 static int
2123 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2124                        __rte_unused int wait_to_complete)
2125 {
2126         struct hns3_adapter *hns = eth_dev->data->dev_private;
2127         struct hns3_hw *hw = &hns->hw;
2128         struct hns3_mac *mac = &hw->mac;
2129         struct rte_eth_link new_link;
2130
2131         memset(&new_link, 0, sizeof(new_link));
2132         switch (mac->link_speed) {
2133         case RTE_ETH_SPEED_NUM_10M:
2134         case RTE_ETH_SPEED_NUM_100M:
2135         case RTE_ETH_SPEED_NUM_1G:
2136         case RTE_ETH_SPEED_NUM_10G:
2137         case RTE_ETH_SPEED_NUM_25G:
2138         case RTE_ETH_SPEED_NUM_40G:
2139         case RTE_ETH_SPEED_NUM_50G:
2140         case RTE_ETH_SPEED_NUM_100G:
2141         case RTE_ETH_SPEED_NUM_200G:
2142                 if (mac->link_status)
2143                         new_link.link_speed = mac->link_speed;
2144                 break;
2145         default:
2146                 if (mac->link_status)
2147                         new_link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2148                 break;
2149         }
2150
2151         if (!mac->link_status)
2152                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2153
2154         new_link.link_duplex = mac->link_duplex;
2155         new_link.link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2156         new_link.link_autoneg =
2157             !(eth_dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED);
2158
2159         return rte_eth_linkstatus_set(eth_dev, &new_link);
2160 }
2161
2162 static int
2163 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2164 {
2165         struct hns3_hw *hw = &hns->hw;
2166         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2167         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2168         int ret;
2169
2170         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2171         if (ret)
2172                 return ret;
2173
2174         hns3_enable_rxd_adv_layout(hw);
2175
2176         ret = hns3_init_queues(hns, reset_queue);
2177         if (ret)
2178                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2179
2180         return ret;
2181 }
2182
2183 static int
2184 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2185 {
2186         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2187         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2188         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2190         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2191         uint32_t intr_vector;
2192         uint16_t q_id;
2193         int ret;
2194
2195         /*
2196          * hns3 needs a separate interrupt to be used as event interrupt which
2197          * could not be shared with task queue pair, so KERNEL drivers need
2198          * support multiple interrupt vectors.
2199          */
2200         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2201             !rte_intr_cap_multiple(intr_handle))
2202                 return 0;
2203
2204         rte_intr_disable(intr_handle);
2205         intr_vector = hw->used_rx_queues;
2206         /* It creates event fd for each intr vector when MSIX is used */
2207         if (rte_intr_efd_enable(intr_handle, intr_vector))
2208                 return -EINVAL;
2209
2210         /* Allocate vector list */
2211         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
2212                                     hw->used_rx_queues)) {
2213                 hns3_err(hw, "Failed to allocate %u rx_queues"
2214                          " intr_vec", hw->used_rx_queues);
2215                 ret = -ENOMEM;
2216                 goto vf_alloc_intr_vec_error;
2217         }
2218
2219         if (rte_intr_allow_others(intr_handle)) {
2220                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2221                 base = RTE_INTR_VEC_RXTX_OFFSET;
2222         }
2223
2224         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2225                 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2226                                                    HNS3_RING_TYPE_RX, q_id);
2227                 if (ret)
2228                         goto vf_bind_vector_error;
2229
2230                 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
2231                         goto vf_bind_vector_error;
2232
2233                 /*
2234                  * If there are not enough efds (e.g. not enough interrupt),
2235                  * remaining queues will be bond to the last interrupt.
2236                  */
2237                 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
2238                         vec++;
2239         }
2240         rte_intr_enable(intr_handle);
2241         return 0;
2242
2243 vf_bind_vector_error:
2244         rte_intr_vec_list_free(intr_handle);
2245 vf_alloc_intr_vec_error:
2246         rte_intr_efd_disable(intr_handle);
2247         return ret;
2248 }
2249
2250 static int
2251 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2252 {
2253         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2254         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2255         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2256         uint16_t q_id;
2257         int ret;
2258
2259         if (dev->data->dev_conf.intr_conf.rxq == 0)
2260                 return 0;
2261
2262         if (rte_intr_dp_is_en(intr_handle)) {
2263                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2264                         ret = hns3vf_bind_ring_with_vector(hw,
2265                                 rte_intr_vec_list_index_get(intr_handle,
2266                                                                    q_id),
2267                                 true, HNS3_RING_TYPE_RX, q_id);
2268                         if (ret)
2269                                 return ret;
2270                 }
2271         }
2272
2273         return 0;
2274 }
2275
2276 static void
2277 hns3vf_restore_filter(struct rte_eth_dev *dev)
2278 {
2279         hns3_restore_rss_filter(dev);
2280 }
2281
2282 static int
2283 hns3vf_dev_start(struct rte_eth_dev *dev)
2284 {
2285         struct hns3_adapter *hns = dev->data->dev_private;
2286         struct hns3_hw *hw = &hns->hw;
2287         int ret;
2288
2289         PMD_INIT_FUNC_TRACE();
2290         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2291                 return -EBUSY;
2292
2293         rte_spinlock_lock(&hw->lock);
2294         hw->adapter_state = HNS3_NIC_STARTING;
2295         ret = hns3vf_do_start(hns, true);
2296         if (ret) {
2297                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2298                 rte_spinlock_unlock(&hw->lock);
2299                 return ret;
2300         }
2301         ret = hns3vf_map_rx_interrupt(dev);
2302         if (ret)
2303                 goto map_rx_inter_err;
2304
2305         /*
2306          * There are three register used to control the status of a TQP
2307          * (contains a pair of Tx queue and Rx queue) in the new version network
2308          * engine. One is used to control the enabling of Tx queue, the other is
2309          * used to control the enabling of Rx queue, and the last is the master
2310          * switch used to control the enabling of the tqp. The Tx register and
2311          * TQP register must be enabled at the same time to enable a Tx queue.
2312          * The same applies to the Rx queue. For the older network enginem, this
2313          * function only refresh the enabled flag, and it is used to update the
2314          * status of queue in the dpdk framework.
2315          */
2316         ret = hns3_start_all_txqs(dev);
2317         if (ret)
2318                 goto map_rx_inter_err;
2319
2320         ret = hns3_start_all_rxqs(dev);
2321         if (ret)
2322                 goto start_all_rxqs_fail;
2323
2324         hw->adapter_state = HNS3_NIC_STARTED;
2325         rte_spinlock_unlock(&hw->lock);
2326
2327         hns3_rx_scattered_calc(dev);
2328         hns3_set_rxtx_function(dev);
2329         hns3_mp_req_start_rxtx(dev);
2330
2331         hns3vf_restore_filter(dev);
2332
2333         /* Enable interrupt of all rx queues before enabling queues */
2334         hns3_dev_all_rx_queue_intr_enable(hw, true);
2335         hns3_start_tqps(hw);
2336
2337         if (dev->data->dev_conf.intr_conf.lsc != 0)
2338                 hns3vf_dev_link_update(dev, 0);
2339         hns3vf_start_poll_job(dev);
2340
2341         return ret;
2342
2343 start_all_rxqs_fail:
2344         hns3_stop_all_txqs(dev);
2345 map_rx_inter_err:
2346         (void)hns3vf_do_stop(hns);
2347         hw->adapter_state = HNS3_NIC_CONFIGURED;
2348         rte_spinlock_unlock(&hw->lock);
2349
2350         return ret;
2351 }
2352
2353 static bool
2354 is_vf_reset_done(struct hns3_hw *hw)
2355 {
2356 #define HNS3_FUN_RST_ING_BITS \
2357         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2358          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2359          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2360          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2361
2362         uint32_t val;
2363
2364         if (hw->reset.level == HNS3_VF_RESET) {
2365                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2366                 if (val & HNS3_VF_RST_ING_BIT)
2367                         return false;
2368         } else {
2369                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2370                 if (val & HNS3_FUN_RST_ING_BITS)
2371                         return false;
2372         }
2373         return true;
2374 }
2375
2376 bool
2377 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2378 {
2379         struct hns3_hw *hw = &hns->hw;
2380         enum hns3_reset_level reset;
2381
2382         /*
2383          * According to the protocol of PCIe, FLR to a PF device resets the PF
2384          * state as well as the SR-IOV extended capability including VF Enable
2385          * which means that VFs no longer exist.
2386          *
2387          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2388          * is in FLR stage, the register state of VF device is not reliable,
2389          * so register states detection can not be carried out. In this case,
2390          * we just ignore the register states and return false to indicate that
2391          * there are no other reset states that need to be processed by driver.
2392          */
2393         if (hw->reset.level == HNS3_VF_FULL_RESET)
2394                 return false;
2395
2396         /* Check the registers to confirm whether there is reset pending */
2397         hns3vf_check_event_cause(hns, NULL);
2398         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2399         if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2400             hw->reset.level < reset) {
2401                 hns3_warn(hw, "High level reset %d is pending", reset);
2402                 return true;
2403         }
2404         return false;
2405 }
2406
2407 static int
2408 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2409 {
2410         struct hns3_hw *hw = &hns->hw;
2411         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2412         struct timeval tv;
2413
2414         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2415                 /*
2416                  * After vf reset is ready, the PF may not have completed
2417                  * the reset processing. The vf sending mbox to PF may fail
2418                  * during the pf reset, so it is better to add extra delay.
2419                  */
2420                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2421                     hw->reset.level == HNS3_FLR_RESET)
2422                         return 0;
2423                 /* Reset retry process, no need to add extra delay. */
2424                 if (hw->reset.attempts)
2425                         return 0;
2426                 if (wait_data->check_completion == NULL)
2427                         return 0;
2428
2429                 wait_data->check_completion = NULL;
2430                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2431                 wait_data->count = 1;
2432                 wait_data->result = HNS3_WAIT_REQUEST;
2433                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2434                                   wait_data);
2435                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2436                 return -EAGAIN;
2437         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2438                 hns3_clock_gettime(&tv);
2439                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2440                           tv.tv_sec, tv.tv_usec);
2441                 return -ETIME;
2442         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2443                 return -EAGAIN;
2444
2445         wait_data->hns = hns;
2446         wait_data->check_completion = is_vf_reset_done;
2447         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2448                                 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2449         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2450         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2451         wait_data->result = HNS3_WAIT_REQUEST;
2452         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2453         return -EAGAIN;
2454 }
2455
2456 static int
2457 hns3vf_prepare_reset(struct hns3_adapter *hns)
2458 {
2459         struct hns3_hw *hw = &hns->hw;
2460         int ret;
2461
2462         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2463                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2464                                         0, true, NULL, 0);
2465                 if (ret)
2466                         return ret;
2467         }
2468         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2469
2470         return 0;
2471 }
2472
2473 static int
2474 hns3vf_stop_service(struct hns3_adapter *hns)
2475 {
2476         struct hns3_hw *hw = &hns->hw;
2477         struct rte_eth_dev *eth_dev;
2478
2479         eth_dev = &rte_eth_devices[hw->data->port_id];
2480         if (hw->adapter_state == HNS3_NIC_STARTED) {
2481                 /*
2482                  * Make sure call update link status before hns3vf_stop_poll_job
2483                  * because update link status depend on polling job exist.
2484                  */
2485                 hns3vf_update_link_status(hw, RTE_ETH_LINK_DOWN, hw->mac.link_speed,
2486                                           hw->mac.link_duplex);
2487                 hns3vf_stop_poll_job(eth_dev);
2488         }
2489         hw->mac.link_status = RTE_ETH_LINK_DOWN;
2490
2491         hns3_set_rxtx_function(eth_dev);
2492         rte_wmb();
2493         /* Disable datapath on secondary process. */
2494         hns3_mp_req_stop_rxtx(eth_dev);
2495         rte_delay_ms(hw->cfg_max_queues);
2496
2497         rte_spinlock_lock(&hw->lock);
2498         if (hw->adapter_state == HNS3_NIC_STARTED ||
2499             hw->adapter_state == HNS3_NIC_STOPPING) {
2500                 hns3_enable_all_queues(hw, false);
2501                 hns3vf_do_stop(hns);
2502                 hw->reset.mbuf_deferred_free = true;
2503         } else
2504                 hw->reset.mbuf_deferred_free = false;
2505
2506         /*
2507          * It is cumbersome for hardware to pick-and-choose entries for deletion
2508          * from table space. Hence, for function reset software intervention is
2509          * required to delete the entries.
2510          */
2511         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2512                 hns3_configure_all_mc_mac_addr(hns, true);
2513         rte_spinlock_unlock(&hw->lock);
2514
2515         return 0;
2516 }
2517
2518 static int
2519 hns3vf_start_service(struct hns3_adapter *hns)
2520 {
2521         struct hns3_hw *hw = &hns->hw;
2522         struct rte_eth_dev *eth_dev;
2523
2524         eth_dev = &rte_eth_devices[hw->data->port_id];
2525         hns3_set_rxtx_function(eth_dev);
2526         hns3_mp_req_start_rxtx(eth_dev);
2527         if (hw->adapter_state == HNS3_NIC_STARTED) {
2528                 hns3vf_start_poll_job(eth_dev);
2529
2530                 /* Enable interrupt of all rx queues before enabling queues */
2531                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2532                 /*
2533                  * Enable state of each rxq and txq will be recovered after
2534                  * reset, so we need to restore them before enable all tqps;
2535                  */
2536                 hns3_restore_tqp_enable_state(hw);
2537                 /*
2538                  * When finished the initialization, enable queues to receive
2539                  * and transmit packets.
2540                  */
2541                 hns3_enable_all_queues(hw, true);
2542         }
2543
2544         return 0;
2545 }
2546
2547 static int
2548 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2549 {
2550         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2551         struct rte_ether_addr *hw_mac;
2552         int ret;
2553
2554         /*
2555          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2556          * on the host by "ip link set ..." command. If the hns3 PF kernel
2557          * ethdev driver sets the MAC address for VF device after the
2558          * initialization of the related VF device, the PF driver will notify
2559          * VF driver to reset VF device to make the new MAC address effective
2560          * immediately. The hns3 VF PMD driver should check whether the MAC
2561          * address has been changed by the PF kernel ethdev driver, if changed
2562          * VF driver should configure hardware using the new MAC address in the
2563          * recovering hardware configuration stage of the reset process.
2564          */
2565         ret = hns3vf_get_host_mac_addr(hw);
2566         if (ret)
2567                 return ret;
2568
2569         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2570         ret = rte_is_zero_ether_addr(hw_mac);
2571         if (ret) {
2572                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2573         } else {
2574                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2575                 if (!ret) {
2576                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2577                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2578                                               &hw->data->mac_addrs[0]);
2579                         hns3_warn(hw, "Default MAC address has been changed to:"
2580                                   " %s by the host PF kernel ethdev driver",
2581                                   mac_str);
2582                 }
2583         }
2584
2585         return 0;
2586 }
2587
2588 static int
2589 hns3vf_restore_conf(struct hns3_adapter *hns)
2590 {
2591         struct hns3_hw *hw = &hns->hw;
2592         int ret;
2593
2594         ret = hns3vf_check_default_mac_change(hw);
2595         if (ret)
2596                 return ret;
2597
2598         ret = hns3_configure_all_mac_addr(hns, false);
2599         if (ret)
2600                 return ret;
2601
2602         ret = hns3_configure_all_mc_mac_addr(hns, false);
2603         if (ret)
2604                 goto err_mc_mac;
2605
2606         ret = hns3vf_restore_promisc(hns);
2607         if (ret)
2608                 goto err_vlan_table;
2609
2610         ret = hns3vf_restore_vlan_conf(hns);
2611         if (ret)
2612                 goto err_vlan_table;
2613
2614         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2615         if (ret)
2616                 goto err_vlan_table;
2617
2618         ret = hns3vf_restore_rx_interrupt(hw);
2619         if (ret)
2620                 goto err_vlan_table;
2621
2622         ret = hns3_restore_gro_conf(hw);
2623         if (ret)
2624                 goto err_vlan_table;
2625
2626         if (hw->adapter_state == HNS3_NIC_STARTED) {
2627                 ret = hns3vf_do_start(hns, false);
2628                 if (ret)
2629                         goto err_vlan_table;
2630                 hns3_info(hw, "hns3vf dev restart successful!");
2631         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2632                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2633
2634         ret = hns3vf_set_alive(hw, true);
2635         if (ret) {
2636                 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2637                 goto err_vlan_table;
2638         }
2639
2640         return 0;
2641
2642 err_vlan_table:
2643         hns3_configure_all_mc_mac_addr(hns, true);
2644 err_mc_mac:
2645         hns3_configure_all_mac_addr(hns, true);
2646         return ret;
2647 }
2648
2649 static enum hns3_reset_level
2650 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2651 {
2652         enum hns3_reset_level reset_level;
2653
2654         /* return the highest priority reset level amongst all */
2655         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2656                 reset_level = HNS3_VF_RESET;
2657         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2658                 reset_level = HNS3_VF_FULL_RESET;
2659         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2660                 reset_level = HNS3_VF_PF_FUNC_RESET;
2661         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2662                 reset_level = HNS3_VF_FUNC_RESET;
2663         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2664                 reset_level = HNS3_FLR_RESET;
2665         else
2666                 reset_level = HNS3_NONE_RESET;
2667
2668         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2669                 return HNS3_NONE_RESET;
2670
2671         return reset_level;
2672 }
2673
2674 static void
2675 hns3vf_reset_service(void *param)
2676 {
2677         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2678         struct hns3_hw *hw = &hns->hw;
2679         enum hns3_reset_level reset_level;
2680         struct timeval tv_delta;
2681         struct timeval tv_start;
2682         struct timeval tv;
2683         uint64_t msec;
2684
2685         /*
2686          * The interrupt is not triggered within the delay time.
2687          * The interrupt may have been lost. It is necessary to handle
2688          * the interrupt to recover from the error.
2689          */
2690         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2691                             SCHEDULE_DEFERRED) {
2692                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2693                                  __ATOMIC_RELAXED);
2694                 hns3_err(hw, "Handling interrupts in delayed tasks");
2695                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2696                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2697                 if (reset_level == HNS3_NONE_RESET) {
2698                         hns3_err(hw, "No reset level is set, try global reset");
2699                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2700                 }
2701         }
2702         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2703
2704         /*
2705          * Hardware reset has been notified, we now have to poll & check if
2706          * hardware has actually completed the reset sequence.
2707          */
2708         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2709         if (reset_level != HNS3_NONE_RESET) {
2710                 hns3_clock_gettime(&tv_start);
2711                 hns3_reset_process(hns, reset_level);
2712                 hns3_clock_gettime(&tv);
2713                 timersub(&tv, &tv_start, &tv_delta);
2714                 msec = hns3_clock_calctime_ms(&tv_delta);
2715                 if (msec > HNS3_RESET_PROCESS_MS)
2716                         hns3_err(hw, "%d handle long time delta %" PRIu64
2717                                  " ms time=%ld.%.6ld",
2718                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2719         }
2720 }
2721
2722 static int
2723 hns3vf_reinit_dev(struct hns3_adapter *hns)
2724 {
2725         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2726         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2727         struct hns3_hw *hw = &hns->hw;
2728         int ret;
2729
2730         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2731                 rte_intr_disable(pci_dev->intr_handle);
2732                 ret = hns3vf_set_bus_master(pci_dev, true);
2733                 if (ret < 0) {
2734                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2735                         return ret;
2736                 }
2737         }
2738
2739         /* Firmware command initialize */
2740         ret = hns3_cmd_init(hw);
2741         if (ret) {
2742                 hns3_err(hw, "Failed to init cmd: %d", ret);
2743                 return ret;
2744         }
2745
2746         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2747                 /*
2748                  * UIO enables msix by writing the pcie configuration space
2749                  * vfio_pci enables msix in rte_intr_enable.
2750                  */
2751                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2752                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2753                         if (hns3vf_enable_msix(pci_dev, true))
2754                                 hns3_err(hw, "Failed to enable msix");
2755                 }
2756
2757                 rte_intr_enable(pci_dev->intr_handle);
2758         }
2759
2760         ret = hns3_reset_all_tqps(hns);
2761         if (ret) {
2762                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2763                 return ret;
2764         }
2765
2766         ret = hns3vf_init_hardware(hns);
2767         if (ret) {
2768                 hns3_err(hw, "Failed to init hardware: %d", ret);
2769                 return ret;
2770         }
2771
2772         return 0;
2773 }
2774
2775 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2776         .dev_configure      = hns3vf_dev_configure,
2777         .dev_start          = hns3vf_dev_start,
2778         .dev_stop           = hns3vf_dev_stop,
2779         .dev_close          = hns3vf_dev_close,
2780         .mtu_set            = hns3vf_dev_mtu_set,
2781         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2782         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2783         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2784         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2785         .stats_get          = hns3_stats_get,
2786         .stats_reset        = hns3_stats_reset,
2787         .xstats_get         = hns3_dev_xstats_get,
2788         .xstats_get_names   = hns3_dev_xstats_get_names,
2789         .xstats_reset       = hns3_dev_xstats_reset,
2790         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2791         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2792         .dev_infos_get      = hns3vf_dev_infos_get,
2793         .fw_version_get     = hns3vf_fw_version_get,
2794         .rx_queue_setup     = hns3_rx_queue_setup,
2795         .tx_queue_setup     = hns3_tx_queue_setup,
2796         .rx_queue_release   = hns3_dev_rx_queue_release,
2797         .tx_queue_release   = hns3_dev_tx_queue_release,
2798         .rx_queue_start     = hns3_dev_rx_queue_start,
2799         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2800         .tx_queue_start     = hns3_dev_tx_queue_start,
2801         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2802         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2803         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2804         .rxq_info_get       = hns3_rxq_info_get,
2805         .txq_info_get       = hns3_txq_info_get,
2806         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2807         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2808         .mac_addr_add       = hns3vf_add_mac_addr,
2809         .mac_addr_remove    = hns3vf_remove_mac_addr,
2810         .mac_addr_set       = hns3vf_set_default_mac_addr,
2811         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2812         .link_update        = hns3vf_dev_link_update,
2813         .rss_hash_update    = hns3_dev_rss_hash_update,
2814         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2815         .reta_update        = hns3_dev_rss_reta_update,
2816         .reta_query         = hns3_dev_rss_reta_query,
2817         .flow_ops_get       = hns3_dev_flow_ops_get,
2818         .vlan_filter_set    = hns3vf_vlan_filter_set,
2819         .vlan_offload_set   = hns3vf_vlan_offload_set,
2820         .get_reg            = hns3_get_regs,
2821         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2822         .tx_done_cleanup    = hns3_tx_done_cleanup,
2823 };
2824
2825 static const struct hns3_reset_ops hns3vf_reset_ops = {
2826         .reset_service       = hns3vf_reset_service,
2827         .stop_service        = hns3vf_stop_service,
2828         .prepare_reset       = hns3vf_prepare_reset,
2829         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2830         .reinit_dev          = hns3vf_reinit_dev,
2831         .restore_conf        = hns3vf_restore_conf,
2832         .start_service       = hns3vf_start_service,
2833 };
2834
2835 static void
2836 hns3vf_init_hw_ops(struct hns3_hw *hw)
2837 {
2838         hw->ops.add_mc_mac_addr = hns3vf_add_mc_mac_addr;
2839         hw->ops.del_mc_mac_addr = hns3vf_remove_mc_mac_addr;
2840         hw->ops.add_uc_mac_addr = hns3vf_add_uc_mac_addr;
2841         hw->ops.del_uc_mac_addr = hns3vf_remove_uc_mac_addr;
2842 }
2843
2844 static int
2845 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2846 {
2847         struct hns3_adapter *hns = eth_dev->data->dev_private;
2848         struct hns3_hw *hw = &hns->hw;
2849         int ret;
2850
2851         PMD_INIT_FUNC_TRACE();
2852
2853         hns3_flow_init(eth_dev);
2854
2855         hns3_set_rxtx_function(eth_dev);
2856         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2857         eth_dev->rx_queue_count = hns3_rx_queue_count;
2858         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2859                 ret = hns3_mp_init_secondary();
2860                 if (ret) {
2861                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2862                                           "process, ret = %d", ret);
2863                         goto err_mp_init_secondary;
2864                 }
2865                 hw->secondary_cnt++;
2866                 hns3_tx_push_init(eth_dev);
2867                 return 0;
2868         }
2869
2870         ret = hns3_mp_init_primary();
2871         if (ret) {
2872                 PMD_INIT_LOG(ERR,
2873                              "Failed to init for primary process, ret = %d",
2874                              ret);
2875                 goto err_mp_init_primary;
2876         }
2877
2878         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2879         hns->is_vf = true;
2880         hw->data = eth_dev->data;
2881         hns3_parse_devargs(eth_dev);
2882
2883         ret = hns3_reset_init(hw);
2884         if (ret)
2885                 goto err_init_reset;
2886         hw->reset.ops = &hns3vf_reset_ops;
2887
2888         hns3vf_init_hw_ops(hw);
2889         ret = hns3vf_init_vf(eth_dev);
2890         if (ret) {
2891                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2892                 goto err_init_vf;
2893         }
2894
2895         /* Allocate memory for storing MAC addresses */
2896         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2897                                                sizeof(struct rte_ether_addr) *
2898                                                HNS3_VF_UC_MACADDR_NUM, 0);
2899         if (eth_dev->data->mac_addrs == NULL) {
2900                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2901                              "to store MAC addresses",
2902                              sizeof(struct rte_ether_addr) *
2903                              HNS3_VF_UC_MACADDR_NUM);
2904                 ret = -ENOMEM;
2905                 goto err_rte_zmalloc;
2906         }
2907
2908         /*
2909          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2910          * on the host by "ip link set ..." command. To avoid some incorrect
2911          * scenes, for example, hns3 VF PMD driver fails to receive and send
2912          * packets after user configure the MAC address by using the
2913          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2914          * address strategy as the hns3 kernel ethdev driver in the
2915          * initialization. If user configure a MAC address by the ip command
2916          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2917          * start with a random MAC address in the initialization.
2918          */
2919         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2920                 rte_eth_random_addr(hw->mac.mac_addr);
2921         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2922                             &eth_dev->data->mac_addrs[0]);
2923
2924         hw->adapter_state = HNS3_NIC_INITIALIZED;
2925
2926         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2927                             SCHEDULE_PENDING) {
2928                 hns3_err(hw, "Reschedule reset service after dev_init");
2929                 hns3_schedule_reset(hns);
2930         } else {
2931                 /* IMP will wait ready flag before reset */
2932                 hns3_notify_reset_ready(hw, false);
2933         }
2934         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2935                           eth_dev);
2936         return 0;
2937
2938 err_rte_zmalloc:
2939         hns3vf_uninit_vf(eth_dev);
2940
2941 err_init_vf:
2942         rte_free(hw->reset.wait_data);
2943
2944 err_init_reset:
2945         hns3_mp_uninit_primary();
2946
2947 err_mp_init_primary:
2948 err_mp_init_secondary:
2949         eth_dev->dev_ops = NULL;
2950         eth_dev->rx_pkt_burst = NULL;
2951         eth_dev->rx_descriptor_status = NULL;
2952         eth_dev->tx_pkt_burst = NULL;
2953         eth_dev->tx_pkt_prepare = NULL;
2954         eth_dev->tx_descriptor_status = NULL;
2955
2956         return ret;
2957 }
2958
2959 static int
2960 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2961 {
2962         struct hns3_adapter *hns = eth_dev->data->dev_private;
2963         struct hns3_hw *hw = &hns->hw;
2964
2965         PMD_INIT_FUNC_TRACE();
2966
2967         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2968                 return 0;
2969
2970         if (hw->adapter_state < HNS3_NIC_CLOSING)
2971                 hns3vf_dev_close(eth_dev);
2972
2973         hw->adapter_state = HNS3_NIC_REMOVED;
2974         return 0;
2975 }
2976
2977 static int
2978 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2979                      struct rte_pci_device *pci_dev)
2980 {
2981         return rte_eth_dev_pci_generic_probe(pci_dev,
2982                                              sizeof(struct hns3_adapter),
2983                                              hns3vf_dev_init);
2984 }
2985
2986 static int
2987 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2988 {
2989         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2990 }
2991
2992 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2993         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2994         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2995         { .vendor_id = 0, }, /* sentinel */
2996 };
2997
2998 static struct rte_pci_driver rte_hns3vf_pmd = {
2999         .id_table = pci_id_hns3vf_map,
3000         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3001         .probe = eth_hns3vf_pci_probe,
3002         .remove = eth_hns3vf_pci_remove,
3003 };
3004
3005 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
3006 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
3007 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
3008 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
3009                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
3010                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
3011                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
3012                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16_t> ");