1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
11 #include <arpa/inet.h>
12 #include <linux/pci_regs.h>
14 #include <rte_alarm.h>
15 #include <rte_atomic.h>
16 #include <rte_bus_pci.h>
17 #include <rte_byteorder.h>
18 #include <rte_common.h>
19 #include <rte_cycles.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
24 #include <rte_ethdev_pci.h>
25 #include <rte_interrupts.h>
31 #include "hns3_ethdev.h"
32 #include "hns3_logs.h"
33 #include "hns3_rxtx.h"
34 #include "hns3_regs.h"
35 #include "hns3_intr.h"
39 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */
40 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */
42 #define HNS3VF_RESET_WAIT_MS 20
43 #define HNS3VF_RESET_WAIT_CNT 2000
45 /* Reset related Registers */
46 #define HNS3_GLOBAL_RESET_BIT 0
47 #define HNS3_CORE_RESET_BIT 1
48 #define HNS3_IMP_RESET_BIT 2
49 #define HNS3_FUN_RST_ING_B 0
51 enum hns3vf_evt_cause {
52 HNS3VF_VECTOR0_EVENT_RST,
53 HNS3VF_VECTOR0_EVENT_MBX,
54 HNS3VF_VECTOR0_EVENT_OTHER,
57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
63 struct rte_ether_addr *mac_addr);
64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
65 struct rte_ether_addr *mac_addr);
66 /* set PCI bus mastering */
68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
72 rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND);
75 /* set the master bit */
76 reg |= PCI_COMMAND_MASTER;
78 reg &= ~(PCI_COMMAND_MASTER);
80 rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND);
84 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
85 * @cap: the capability
87 * Return the address of the given capability within the PCI capability list.
90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
92 #define MAX_PCIE_CAPABILITY 48
98 rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
99 if (!(status & PCI_STATUS_CAP_LIST))
102 ttl = MAX_PCIE_CAPABILITY;
103 rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
104 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
105 rte_pci_read_config(device, &id, sizeof(id),
106 (pos + PCI_CAP_LIST_ID));
114 rte_pci_read_config(device, &pos, sizeof(pos),
115 (pos + PCI_CAP_LIST_NEXT));
121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
126 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
128 rte_pci_read_config(device, &control, sizeof(control),
129 (pos + PCI_MSIX_FLAGS));
131 control |= PCI_MSIX_FLAGS_ENABLE;
133 control &= ~PCI_MSIX_FLAGS_ENABLE;
134 rte_pci_write_config(device, &control, sizeof(control),
135 (pos + PCI_MSIX_FLAGS));
142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
144 /* mac address was checked by upper level interface */
145 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
148 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
149 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
150 RTE_ETHER_ADDR_LEN, false, NULL, 0);
152 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
154 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
163 /* mac address was checked by upper level interface */
164 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
167 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
168 HNS3_MBX_MAC_VLAN_UC_REMOVE,
169 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
172 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
174 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
183 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
184 struct rte_ether_addr *addr;
188 for (i = 0; i < hw->mc_addrs_num; i++) {
189 addr = &hw->mc_addrs[i];
190 /* Check if there are duplicate addresses */
191 if (rte_is_same_ether_addr(addr, mac_addr)) {
192 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
194 hns3_err(hw, "failed to add mc mac addr, same addrs"
195 "(%s) is added by the set_mc_mac_addr_list "
201 ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
203 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
205 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
213 __rte_unused uint32_t idx,
214 __rte_unused uint32_t pool)
216 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
217 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
220 rte_spinlock_lock(&hw->lock);
223 * In hns3 network engine adding UC and MC mac address with different
224 * commands with firmware. We need to determine whether the input
225 * address is a UC or a MC address to call different commands.
226 * By the way, it is recommended calling the API function named
227 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
228 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
229 * may affect the specifications of UC mac addresses.
231 if (rte_is_multicast_ether_addr(mac_addr))
232 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
234 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
236 rte_spinlock_unlock(&hw->lock);
238 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
240 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
250 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
251 /* index will be checked by upper level rte interface */
252 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
253 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
256 rte_spinlock_lock(&hw->lock);
258 if (rte_is_multicast_ether_addr(mac_addr))
259 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
261 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
263 rte_spinlock_unlock(&hw->lock);
265 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
267 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
274 struct rte_ether_addr *mac_addr)
276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
277 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
278 struct rte_ether_addr *old_addr;
279 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
280 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
284 * It has been guaranteed that input parameter named mac_addr is valid
285 * address in the rte layer of DPDK framework.
287 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
288 rte_spinlock_lock(&hw->lock);
289 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
290 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
293 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
294 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
295 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
298 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
299 * driver. When user has configured a MAC address for VF device
300 * by "ip link set ..." command based on the PF device, the hns3
301 * PF kernel ethdev driver does not allow VF driver to request
302 * reconfiguring a different default MAC address, and return
303 * -EPREM to VF driver through mailbox.
306 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
308 hns3_warn(hw, "Has permanet mac addr(%s) for vf",
311 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
313 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
318 rte_ether_addr_copy(mac_addr,
319 (struct rte_ether_addr *)hw->mac.mac_addr);
320 rte_spinlock_unlock(&hw->lock);
326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
328 struct hns3_hw *hw = &hns->hw;
329 struct rte_ether_addr *addr;
330 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
335 for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
336 addr = &hw->data->mac_addrs[i];
337 if (rte_is_zero_ether_addr(addr))
339 if (rte_is_multicast_ether_addr(addr))
340 ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
341 hns3vf_add_mc_mac_addr(hw, addr);
343 ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
344 hns3vf_add_uc_mac_addr(hw, addr);
348 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
350 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
351 "ret = %d.", del ? "remove" : "restore",
359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
360 struct rte_ether_addr *mac_addr)
362 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
365 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
366 HNS3_MBX_MAC_VLAN_MC_ADD,
367 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
370 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
372 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
381 struct rte_ether_addr *mac_addr)
383 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
386 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
387 HNS3_MBX_MAC_VLAN_MC_REMOVE,
388 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
391 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
393 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
402 struct rte_ether_addr *mc_addr_set,
405 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
406 struct rte_ether_addr *addr;
410 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
411 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
412 "invalid. valid range: 0~%d",
413 nb_mc_addr, HNS3_MC_MACADDR_NUM);
417 /* Check if input mac addresses are valid */
418 for (i = 0; i < nb_mc_addr; i++) {
419 addr = &mc_addr_set[i];
420 if (!rte_is_multicast_ether_addr(addr)) {
421 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
424 "failed to set mc mac addr, addr(%s) invalid.",
429 /* Check if there are duplicate addresses */
430 for (j = i + 1; j < nb_mc_addr; j++) {
431 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
432 rte_ether_format_addr(mac_str,
433 RTE_ETHER_ADDR_FMT_SIZE,
435 hns3_err(hw, "failed to set mc mac addr, "
436 "addrs invalid. two same addrs(%s).",
443 * Check if there are duplicate addresses between mac_addrs
446 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
447 if (rte_is_same_ether_addr(addr,
448 &hw->data->mac_addrs[j])) {
449 rte_ether_format_addr(mac_str,
450 RTE_ETHER_ADDR_FMT_SIZE,
452 hns3_err(hw, "failed to set mc mac addr, "
453 "addrs invalid. addrs(%s) has already "
454 "configured in mac_addr add API",
465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
466 struct rte_ether_addr *mc_addr_set,
469 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
470 struct rte_ether_addr *addr;
477 ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
481 rte_spinlock_lock(&hw->lock);
482 cur_addr_num = hw->mc_addrs_num;
483 for (i = 0; i < cur_addr_num; i++) {
484 num = cur_addr_num - i - 1;
485 addr = &hw->mc_addrs[num];
486 ret = hns3vf_remove_mc_mac_addr(hw, addr);
488 rte_spinlock_unlock(&hw->lock);
495 set_addr_num = (int)nb_mc_addr;
496 for (i = 0; i < set_addr_num; i++) {
497 addr = &mc_addr_set[i];
498 ret = hns3vf_add_mc_mac_addr(hw, addr);
500 rte_spinlock_unlock(&hw->lock);
504 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
507 rte_spinlock_unlock(&hw->lock);
513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
515 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
516 struct hns3_hw *hw = &hns->hw;
517 struct rte_ether_addr *addr;
522 for (i = 0; i < hw->mc_addrs_num; i++) {
523 addr = &hw->mc_addrs[i];
524 if (!rte_is_multicast_ether_addr(addr))
527 ret = hns3vf_remove_mc_mac_addr(hw, addr);
529 ret = hns3vf_add_mc_mac_addr(hw, addr);
532 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
534 hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
535 del ? "Remove" : "Restore", mac_str, ret);
542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
543 bool en_uc_pmc, bool en_mc_pmc)
545 struct hns3_mbx_vf_to_pf_cmd *req;
546 struct hns3_cmd_desc desc;
549 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
552 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
553 * so there are some features for promiscuous/allmulticast mode in hns3
554 * VF PMD driver as below:
555 * 1. The promiscuous/allmulticast mode can be configured successfully
556 * only based on the trusted VF device. If based on the non trusted
557 * VF device, configuring promiscuous/allmulticast mode will fail.
558 * The hns3 VF device can be confiruged as trusted device by hns3 PF
559 * kernel ethdev driver on the host by the following command:
560 * "ip link set <eth num> vf <vf id> turst on"
561 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
562 * driver can receive the ingress and outgoing traffic. In the words,
563 * all the ingress packets, all the packets sent from the PF and
564 * other VFs on the same physical port.
565 * 3. Note: Because of the hardware constraints, By default vlan filter
566 * is enabled and couldn't be turned off based on VF device, so vlan
567 * filter is still effective even in promiscuous mode. If upper
568 * applications don't call rte_eth_dev_vlan_filter API function to
569 * set vlan based on VF device, hns3 VF PMD driver will can't receive
570 * the packets with vlan tag in promiscuoue mode.
572 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
573 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
574 req->msg[1] = en_bc_pmc ? 1 : 0;
575 req->msg[2] = en_uc_pmc ? 1 : 0;
576 req->msg[3] = en_mc_pmc ? 1 : 0;
578 ret = hns3_cmd_send(hw, &desc, 1);
580 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
588 struct hns3_adapter *hns = dev->data->dev_private;
589 struct hns3_hw *hw = &hns->hw;
592 ret = hns3vf_set_promisc_mode(hw, true, true, true);
594 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
602 bool allmulti = dev->data->all_multicast ? true : false;
603 struct hns3_adapter *hns = dev->data->dev_private;
604 struct hns3_hw *hw = &hns->hw;
607 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
609 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
617 struct hns3_adapter *hns = dev->data->dev_private;
618 struct hns3_hw *hw = &hns->hw;
621 if (dev->data->promiscuous)
624 ret = hns3vf_set_promisc_mode(hw, true, false, true);
626 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
634 struct hns3_adapter *hns = dev->data->dev_private;
635 struct hns3_hw *hw = &hns->hw;
638 if (dev->data->promiscuous)
641 ret = hns3vf_set_promisc_mode(hw, true, false, false);
643 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
649 hns3vf_restore_promisc(struct hns3_adapter *hns)
651 struct hns3_hw *hw = &hns->hw;
652 bool allmulti = hw->data->all_multicast ? true : false;
654 if (hw->data->promiscuous)
655 return hns3vf_set_promisc_mode(hw, true, true, true);
657 return hns3vf_set_promisc_mode(hw, true, false, allmulti);
661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
662 bool mmap, enum hns3_ring_type queue_type,
665 struct hns3_vf_bind_vector_msg bind_msg;
670 memset(&bind_msg, 0, sizeof(bind_msg));
671 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
672 HNS3_MBX_UNMAP_RING_TO_VECTOR;
673 bind_msg.vector_id = vector_id;
675 if (queue_type == HNS3_RING_TYPE_RX)
676 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
678 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
680 bind_msg.param[0].ring_type = queue_type;
681 bind_msg.ring_num = 1;
682 bind_msg.param[0].tqp_index = queue_id;
683 op_str = mmap ? "Map" : "Unmap";
684 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
685 sizeof(bind_msg), false, NULL, 0);
687 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
688 op_str, queue_id, bind_msg.vector_id, ret);
694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
701 * In hns3 network engine, vector 0 is always the misc interrupt of this
702 * function, vector 1~N can be used respectively for the queues of the
703 * function. Tx and Rx queues with the same number share the interrupt
704 * vector. In the initialization clearing the all hardware mapping
705 * relationship configurations between queues and interrupt vectors is
706 * needed, so some error caused by the residual configurations, such as
707 * the unexpected Tx interrupt, can be avoid.
709 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
710 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
711 vec = vec - 1; /* the last interrupt is reserved */
712 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
713 for (i = 0; i < hw->intr_tqps_num; i++) {
715 * Set gap limiter/rate limiter/quanity limiter algorithm
716 * configuration for interrupt coalesce of queue's interrupt.
718 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
719 HNS3_TQP_INTR_GL_DEFAULT);
720 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
721 HNS3_TQP_INTR_GL_DEFAULT);
722 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
723 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
725 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
726 HNS3_RING_TYPE_TX, i);
728 PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
729 "vector: %d, ret=%d", i, vec, ret);
733 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
734 HNS3_RING_TYPE_RX, i);
736 PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
737 "vector: %d, ret=%d", i, vec, ret);
746 hns3vf_dev_configure(struct rte_eth_dev *dev)
748 struct hns3_adapter *hns = dev->data->dev_private;
749 struct hns3_hw *hw = &hns->hw;
750 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
751 struct rte_eth_conf *conf = &dev->data->dev_conf;
752 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
753 uint16_t nb_rx_q = dev->data->nb_rx_queues;
754 uint16_t nb_tx_q = dev->data->nb_tx_queues;
755 struct rte_eth_rss_conf rss_conf;
761 * Hardware does not support individually enable/disable/reset the Tx or
762 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
763 * and Rx queues at the same time. When the numbers of Tx queues
764 * allocated by upper applications are not equal to the numbers of Rx
765 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
766 * of Tx/Rx queues. otherwise, network engine can not work as usual. But
767 * these fake queues are imperceptible, and can not be used by upper
770 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
772 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
776 hw->adapter_state = HNS3_NIC_CONFIGURING;
777 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
778 hns3_err(hw, "setting link speed/duplex not supported");
783 /* When RSS is not configured, redirect the packet queue 0 */
784 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
785 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
786 rss_conf = conf->rx_adv_conf.rss_conf;
787 if (rss_conf.rss_key == NULL) {
788 rss_conf.rss_key = rss_cfg->key;
789 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
792 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
798 * If jumbo frames are enabled, MTU needs to be refreshed
799 * according to the maximum RX packet length.
801 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
803 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
804 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
805 * can safely assign to "uint16_t" type variable.
807 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
808 ret = hns3vf_dev_mtu_set(dev, mtu);
811 dev->data->mtu = mtu;
814 ret = hns3vf_dev_configure_vlan(dev);
818 /* config hardware GRO */
819 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
820 ret = hns3_config_gro(hw, gro_en);
824 hns->rx_simple_allowed = true;
825 hns->rx_vec_allowed = true;
826 hns->tx_simple_allowed = true;
827 hns->tx_vec_allowed = true;
829 hns3_init_rx_ptype_tble(dev);
831 hw->adapter_state = HNS3_NIC_CONFIGURED;
835 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
836 hw->adapter_state = HNS3_NIC_INITIALIZED;
842 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
846 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
847 sizeof(mtu), true, NULL, 0);
849 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
855 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
857 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
858 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
862 * The hns3 PF/VF devices on the same port share the hardware MTU
863 * configuration. Currently, we send mailbox to inform hns3 PF kernel
864 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
865 * driver, there is no need to stop the port for hns3 VF device, and the
866 * MTU value issued by hns3 VF PMD driver must be less than or equal to
869 if (rte_atomic16_read(&hw->reset.resetting)) {
870 hns3_err(hw, "Failed to set mtu during resetting");
875 * when Rx of scattered packets is off, we have some possibility of
876 * using vector Rx process function or simple Rx functions in hns3 PMD
877 * driver. If the input MTU is increased and the maximum length of
878 * received packets is greater than the length of a buffer for Rx
879 * packet, the hardware network engine needs to use multiple BDs and
880 * buffers to store these packets. This will cause problems when still
881 * using vector Rx process function or simple Rx function to receiving
882 * packets. So, when Rx of scattered packets is off and device is
883 * started, it is not permitted to increase MTU so that the maximum
884 * length of Rx packets is greater than Rx buffer length.
886 if (dev->data->dev_started && !dev->data->scattered_rx &&
887 frame_size > hw->rx_buf_len) {
888 hns3_err(hw, "failed to set mtu because current is "
889 "not scattered rx mode");
893 rte_spinlock_lock(&hw->lock);
894 ret = hns3vf_config_mtu(hw, mtu);
896 rte_spinlock_unlock(&hw->lock);
899 if (frame_size > RTE_ETHER_MAX_LEN)
900 dev->data->dev_conf.rxmode.offloads |=
901 DEV_RX_OFFLOAD_JUMBO_FRAME;
903 dev->data->dev_conf.rxmode.offloads &=
904 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
905 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
906 rte_spinlock_unlock(&hw->lock);
912 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
914 struct hns3_adapter *hns = eth_dev->data->dev_private;
915 struct hns3_hw *hw = &hns->hw;
916 uint16_t q_num = hw->tqps_num;
919 * In interrupt mode, 'max_rx_queues' is set based on the number of
920 * MSI-X interrupt resources of the hardware.
922 if (hw->data->dev_conf.intr_conf.rxq == 1)
923 q_num = hw->intr_tqps_num;
925 info->max_rx_queues = q_num;
926 info->max_tx_queues = hw->tqps_num;
927 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
928 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
929 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
930 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
931 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
933 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
934 DEV_RX_OFFLOAD_UDP_CKSUM |
935 DEV_RX_OFFLOAD_TCP_CKSUM |
936 DEV_RX_OFFLOAD_SCTP_CKSUM |
937 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
938 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
939 DEV_RX_OFFLOAD_SCATTER |
940 DEV_RX_OFFLOAD_VLAN_STRIP |
941 DEV_RX_OFFLOAD_VLAN_FILTER |
942 DEV_RX_OFFLOAD_JUMBO_FRAME |
943 DEV_RX_OFFLOAD_RSS_HASH |
944 DEV_RX_OFFLOAD_TCP_LRO);
945 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
946 DEV_TX_OFFLOAD_IPV4_CKSUM |
947 DEV_TX_OFFLOAD_TCP_CKSUM |
948 DEV_TX_OFFLOAD_UDP_CKSUM |
949 DEV_TX_OFFLOAD_SCTP_CKSUM |
950 DEV_TX_OFFLOAD_MULTI_SEGS |
951 DEV_TX_OFFLOAD_TCP_TSO |
952 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
953 DEV_TX_OFFLOAD_GRE_TNL_TSO |
954 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
955 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
956 hns3_txvlan_cap_get(hw));
958 info->rx_desc_lim = (struct rte_eth_desc_lim) {
959 .nb_max = HNS3_MAX_RING_DESC,
960 .nb_min = HNS3_MIN_RING_DESC,
961 .nb_align = HNS3_ALIGN_RING_DESC,
964 info->tx_desc_lim = (struct rte_eth_desc_lim) {
965 .nb_max = HNS3_MAX_RING_DESC,
966 .nb_min = HNS3_MIN_RING_DESC,
967 .nb_align = HNS3_ALIGN_RING_DESC,
968 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
969 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
972 info->default_rxconf = (struct rte_eth_rxconf) {
973 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
975 * If there are no available Rx buffer descriptors, incoming
976 * packets are always dropped by hardware based on hns3 network
982 info->default_txconf = (struct rte_eth_txconf) {
983 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
987 info->vmdq_queue_num = 0;
989 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
990 info->hash_key_size = HNS3_RSS_KEY_SIZE;
991 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
992 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
993 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
999 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1001 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1005 hns3vf_disable_irq0(struct hns3_hw *hw)
1007 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1011 hns3vf_enable_irq0(struct hns3_hw *hw)
1013 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1016 static enum hns3vf_evt_cause
1017 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1019 struct hns3_hw *hw = &hns->hw;
1020 enum hns3vf_evt_cause ret;
1021 uint32_t cmdq_stat_reg;
1022 uint32_t rst_ing_reg;
1025 /* Fetch the events from their corresponding regs */
1026 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1028 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1029 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1030 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1031 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1032 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1033 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1034 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1035 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1037 hw->reset.stats.global_cnt++;
1038 hns3_warn(hw, "Global reset detected, clear reset status");
1040 hns3_schedule_delayed_reset(hns);
1041 hns3_warn(hw, "Global reset detected, don't clear reset status");
1044 ret = HNS3VF_VECTOR0_EVENT_RST;
1048 /* Check for vector0 mailbox(=CMDQ RX) event source */
1049 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1050 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1051 ret = HNS3VF_VECTOR0_EVENT_MBX;
1056 ret = HNS3VF_VECTOR0_EVENT_OTHER;
1064 hns3vf_interrupt_handler(void *param)
1066 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1067 struct hns3_adapter *hns = dev->data->dev_private;
1068 struct hns3_hw *hw = &hns->hw;
1069 enum hns3vf_evt_cause event_cause;
1072 if (hw->irq_thread_id == 0)
1073 hw->irq_thread_id = pthread_self();
1075 /* Disable interrupt */
1076 hns3vf_disable_irq0(hw);
1078 /* Read out interrupt causes */
1079 event_cause = hns3vf_check_event_cause(hns, &clearval);
1081 switch (event_cause) {
1082 case HNS3VF_VECTOR0_EVENT_RST:
1083 hns3_schedule_reset(hns);
1085 case HNS3VF_VECTOR0_EVENT_MBX:
1086 hns3_dev_handle_mbx_msg(hw);
1092 /* Clear interrupt causes */
1093 hns3vf_clear_event_cause(hw, clearval);
1095 /* Enable interrupt */
1096 hns3vf_enable_irq0(hw);
1100 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1102 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1103 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1104 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1108 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1110 struct hns3_dev_specs_0_cmd *req0;
1112 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1114 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1115 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1116 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1120 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1122 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1126 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1127 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1129 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1131 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1133 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1137 hns3vf_parse_dev_specifications(hw, desc);
1143 hns3vf_get_capability(struct hns3_hw *hw)
1145 struct rte_pci_device *pci_dev;
1146 struct rte_eth_dev *eth_dev;
1150 eth_dev = &rte_eth_devices[hw->data->port_id];
1151 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1153 /* Get PCI revision id */
1154 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1155 HNS3_PCI_REVISION_ID);
1156 if (ret != HNS3_PCI_REVISION_ID_LEN) {
1157 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1161 hw->revision = revision;
1163 if (revision < PCI_REVISION_ID_HIP09_A) {
1164 hns3vf_set_default_dev_specifications(hw);
1165 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1166 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
1167 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1168 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1169 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1173 ret = hns3vf_query_dev_specifications(hw);
1176 "failed to query dev specifications, ret = %d",
1181 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1182 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
1183 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1184 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1185 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1191 hns3vf_check_tqp_info(struct hns3_hw *hw)
1195 tqps_num = hw->tqps_num;
1196 if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1197 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1199 tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1203 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1208 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1213 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1214 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1215 true, &resp_msg, sizeof(resp_msg));
1217 if (ret == -ETIME) {
1219 * Getting current port based VLAN state from PF driver
1220 * will not affect VF driver's basic function. Because
1221 * the VF driver relies on hns3 PF kernel ether driver,
1222 * to avoid introducing compatibility issues with older
1223 * version of PF driver, no failure will be returned
1224 * when the return value is ETIME. This return value has
1225 * the following scenarios:
1226 * 1) Firmware didn't return the results in time
1227 * 2) the result return by firmware is timeout
1228 * 3) the older version of kernel side PF driver does
1229 * not support this mailbox message.
1230 * For scenarios 1 and 2, it is most likely that a
1231 * hardware error has occurred, or a hardware reset has
1232 * occurred. In this case, these errors will be caught
1233 * by other functions.
1235 PMD_INIT_LOG(WARNING,
1236 "failed to get PVID state for timeout, maybe "
1237 "kernel side PF driver doesn't support this "
1238 "mailbox message, or firmware didn't respond.");
1239 resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1241 PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1246 hw->port_base_vlan_cfg.state = resp_msg ?
1247 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1252 hns3vf_get_queue_info(struct hns3_hw *hw)
1254 #define HNS3VF_TQPS_RSS_INFO_LEN 6
1255 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1258 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1259 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1261 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1265 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1266 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1268 return hns3vf_check_tqp_info(hw);
1272 hns3vf_get_queue_depth(struct hns3_hw *hw)
1274 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4
1275 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1278 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1279 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1281 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1286 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1287 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1293 hns3vf_get_tc_info(struct hns3_hw *hw)
1298 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1299 true, &resp_msg, sizeof(resp_msg));
1301 hns3_err(hw, "VF request to get TC info from PF failed %d",
1306 hw->hw_tc_map = resp_msg;
1312 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1314 uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1317 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1318 true, host_mac, RTE_ETHER_ADDR_LEN);
1320 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1324 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1330 hns3vf_get_configuration(struct hns3_hw *hw)
1334 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1335 hw->rss_dis_flag = false;
1337 /* Get device capability */
1338 ret = hns3vf_get_capability(hw);
1340 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1344 /* Get queue configuration from PF */
1345 ret = hns3vf_get_queue_info(hw);
1349 /* Get queue depth info from PF */
1350 ret = hns3vf_get_queue_depth(hw);
1354 /* Get user defined VF MAC addr from PF */
1355 ret = hns3vf_get_host_mac_addr(hw);
1359 ret = hns3vf_get_port_base_vlan_filter_state(hw);
1363 /* Get tc configuration from PF */
1364 return hns3vf_get_tc_info(hw);
1368 hns3vf_set_tc_info(struct hns3_adapter *hns)
1370 struct hns3_hw *hw = &hns->hw;
1371 uint16_t nb_rx_q = hw->data->nb_rx_queues;
1372 uint16_t nb_tx_q = hw->data->nb_tx_queues;
1376 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1377 if (hw->hw_tc_map & BIT(i))
1380 if (nb_rx_q < hw->num_tc) {
1381 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1382 nb_rx_q, hw->num_tc);
1386 if (nb_tx_q < hw->num_tc) {
1387 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1388 nb_tx_q, hw->num_tc);
1392 hns3_set_rss_size(hw, nb_rx_q);
1393 hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1399 hns3vf_request_link_info(struct hns3_hw *hw)
1404 if (rte_atomic16_read(&hw->reset.resetting))
1406 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1407 &resp_msg, sizeof(resp_msg));
1409 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1413 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1415 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1416 struct hns3_hw *hw = &hns->hw;
1417 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1418 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1419 uint8_t is_kill = on ? 0 : 1;
1421 msg_data[0] = is_kill;
1422 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1423 memcpy(&msg_data[3], &proto, sizeof(proto));
1425 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1426 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1431 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1433 struct hns3_adapter *hns = dev->data->dev_private;
1434 struct hns3_hw *hw = &hns->hw;
1437 if (rte_atomic16_read(&hw->reset.resetting)) {
1439 "vf set vlan id failed during resetting, vlan_id =%u",
1443 rte_spinlock_lock(&hw->lock);
1444 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1445 rte_spinlock_unlock(&hw->lock);
1447 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1454 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1459 msg_data = enable ? 1 : 0;
1460 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1461 &msg_data, sizeof(msg_data), false, NULL, 0);
1463 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1469 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1471 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1472 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1473 unsigned int tmp_mask;
1476 if (rte_atomic16_read(&hw->reset.resetting)) {
1477 hns3_err(hw, "vf set vlan offload failed during resetting, "
1478 "mask = 0x%x", mask);
1482 tmp_mask = (unsigned int)mask;
1483 /* Vlan stripping setting */
1484 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1485 rte_spinlock_lock(&hw->lock);
1486 /* Enable or disable VLAN stripping */
1487 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1488 ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1490 ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1491 rte_spinlock_unlock(&hw->lock);
1498 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1500 struct rte_vlan_filter_conf *vfc;
1501 struct hns3_hw *hw = &hns->hw;
1508 vfc = &hw->data->vlan_filter_conf;
1509 for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1510 if (vfc->ids[i] == 0)
1515 * 64 means the num bits of ids, one bit corresponds to
1519 /* count trailing zeroes */
1520 vbit = ~ids & (ids - 1);
1521 /* clear least significant bit set */
1522 ids ^= (ids ^ (ids - 1)) ^ vbit;
1527 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1530 "VF handle vlan table failed, ret =%d, on = %d",
1541 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1543 return hns3vf_handle_all_vlan_table(hns, 0);
1547 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1549 struct hns3_hw *hw = &hns->hw;
1550 struct rte_eth_conf *dev_conf;
1554 dev_conf = &hw->data->dev_conf;
1555 en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1557 ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1559 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1565 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1567 struct hns3_adapter *hns = dev->data->dev_private;
1568 struct rte_eth_dev_data *data = dev->data;
1569 struct hns3_hw *hw = &hns->hw;
1572 if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1573 data->dev_conf.txmode.hw_vlan_reject_untagged ||
1574 data->dev_conf.txmode.hw_vlan_insert_pvid) {
1575 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1576 "or hw_vlan_insert_pvid is not support!");
1579 /* Apply vlan offload setting */
1580 ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1582 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1588 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1592 msg_data = alive ? 1 : 0;
1593 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1594 sizeof(msg_data), false, NULL, 0);
1598 hns3vf_keep_alive_handler(void *param)
1600 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1601 struct hns3_adapter *hns = eth_dev->data->dev_private;
1602 struct hns3_hw *hw = &hns->hw;
1606 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1607 false, &respmsg, sizeof(uint8_t));
1609 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1612 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1617 hns3vf_service_handler(void *param)
1619 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1620 struct hns3_adapter *hns = eth_dev->data->dev_private;
1621 struct hns3_hw *hw = &hns->hw;
1624 * The query link status and reset processing are executed in the
1625 * interrupt thread.When the IMP reset occurs, IMP will not respond,
1626 * and the query operation will time out after 30ms. In the case of
1627 * multiple PF/VFs, each query failure timeout causes the IMP reset
1628 * interrupt to fail to respond within 100ms.
1629 * Before querying the link status, check whether there is a reset
1630 * pending, and if so, abandon the query.
1632 if (!hns3vf_is_reset_pending(hns))
1633 hns3vf_request_link_info(hw);
1635 hns3_warn(hw, "Cancel the query when reset is pending");
1637 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1642 hns3_query_vf_resource(struct hns3_hw *hw)
1644 struct hns3_vf_res_cmd *req;
1645 struct hns3_cmd_desc desc;
1649 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1650 ret = hns3_cmd_send(hw, &desc, 1);
1652 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1656 req = (struct hns3_vf_res_cmd *)desc.data;
1657 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1658 HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1659 if (num_msi < HNS3_MIN_VECTOR_NUM) {
1660 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1661 num_msi, HNS3_MIN_VECTOR_NUM);
1665 hw->num_msi = num_msi;
1671 hns3vf_init_hardware(struct hns3_adapter *hns)
1673 struct hns3_hw *hw = &hns->hw;
1674 uint16_t mtu = hw->data->mtu;
1677 ret = hns3vf_set_promisc_mode(hw, true, false, false);
1681 ret = hns3vf_config_mtu(hw, mtu);
1683 goto err_init_hardware;
1685 ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1687 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1688 goto err_init_hardware;
1691 ret = hns3_config_gro(hw, false);
1693 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1694 goto err_init_hardware;
1698 * In the initialization clearing the all hardware mapping relationship
1699 * configurations between queues and interrupt vectors is needed, so
1700 * some error caused by the residual configurations, such as the
1701 * unexpected interrupt, can be avoid.
1703 ret = hns3vf_init_ring_with_vector(hw);
1705 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1706 goto err_init_hardware;
1709 ret = hns3vf_set_alive(hw, true);
1711 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1712 goto err_init_hardware;
1715 hns3vf_request_link_info(hw);
1719 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1724 hns3vf_clear_vport_list(struct hns3_hw *hw)
1726 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1727 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1732 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1734 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1735 struct hns3_adapter *hns = eth_dev->data->dev_private;
1736 struct hns3_hw *hw = &hns->hw;
1739 PMD_INIT_FUNC_TRACE();
1741 /* Get hardware io base address from pcie BAR2 IO space */
1742 hw->io_base = pci_dev->mem_resource[2].addr;
1744 /* Firmware command queue initialize */
1745 ret = hns3_cmd_init_queue(hw);
1747 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1748 goto err_cmd_init_queue;
1751 /* Firmware command initialize */
1752 ret = hns3_cmd_init(hw);
1754 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1758 /* Get VF resource */
1759 ret = hns3_query_vf_resource(hw);
1763 rte_spinlock_init(&hw->mbx_resp.lock);
1765 hns3vf_clear_event_cause(hw, 0);
1767 ret = rte_intr_callback_register(&pci_dev->intr_handle,
1768 hns3vf_interrupt_handler, eth_dev);
1770 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1771 goto err_intr_callback_register;
1774 /* Enable interrupt */
1775 rte_intr_enable(&pci_dev->intr_handle);
1776 hns3vf_enable_irq0(hw);
1778 /* Get configuration from PF */
1779 ret = hns3vf_get_configuration(hw);
1781 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1782 goto err_get_config;
1785 ret = hns3vf_clear_vport_list(hw);
1787 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1788 goto err_get_config;
1791 ret = hns3vf_init_hardware(hns);
1793 goto err_get_config;
1795 hns3_set_default_rss_args(hw);
1800 hns3vf_disable_irq0(hw);
1801 rte_intr_disable(&pci_dev->intr_handle);
1802 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1804 err_intr_callback_register:
1806 hns3_cmd_uninit(hw);
1807 hns3_cmd_destroy_queue(hw);
1815 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1817 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1818 struct hns3_adapter *hns = eth_dev->data->dev_private;
1819 struct hns3_hw *hw = &hns->hw;
1821 PMD_INIT_FUNC_TRACE();
1823 hns3_rss_uninit(hns);
1824 (void)hns3_config_gro(hw, false);
1825 (void)hns3vf_set_alive(hw, false);
1826 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1827 hns3vf_disable_irq0(hw);
1828 rte_intr_disable(&pci_dev->intr_handle);
1829 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1831 hns3_cmd_uninit(hw);
1832 hns3_cmd_destroy_queue(hw);
1837 hns3vf_do_stop(struct hns3_adapter *hns)
1839 struct hns3_hw *hw = &hns->hw;
1842 hw->mac.link_status = ETH_LINK_DOWN;
1844 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1845 hns3vf_configure_mac_addr(hns, true);
1848 reset_queue = false;
1849 return hns3_stop_queues(hns, reset_queue);
1853 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1855 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1856 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1857 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1858 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1859 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1862 if (dev->data->dev_conf.intr_conf.rxq == 0)
1865 /* unmap the ring with vector */
1866 if (rte_intr_allow_others(intr_handle)) {
1867 vec = RTE_INTR_VEC_RXTX_OFFSET;
1868 base = RTE_INTR_VEC_RXTX_OFFSET;
1870 if (rte_intr_dp_is_en(intr_handle)) {
1871 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1872 (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1875 if (vec < base + intr_handle->nb_efd - 1)
1879 /* Clean datapath event and queue/vec mapping */
1880 rte_intr_efd_disable(intr_handle);
1881 if (intr_handle->intr_vec) {
1882 rte_free(intr_handle->intr_vec);
1883 intr_handle->intr_vec = NULL;
1888 hns3vf_dev_stop(struct rte_eth_dev *dev)
1890 struct hns3_adapter *hns = dev->data->dev_private;
1891 struct hns3_hw *hw = &hns->hw;
1893 PMD_INIT_FUNC_TRACE();
1895 hw->adapter_state = HNS3_NIC_STOPPING;
1896 hns3_set_rxtx_function(dev);
1898 /* Disable datapath on secondary process. */
1899 hns3_mp_req_stop_rxtx(dev);
1900 /* Prevent crashes when queues are still in use. */
1901 rte_delay_ms(hw->tqps_num);
1903 rte_spinlock_lock(&hw->lock);
1904 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1905 hns3vf_do_stop(hns);
1906 hns3vf_unmap_rx_interrupt(dev);
1907 hns3_dev_release_mbufs(hns);
1908 hw->adapter_state = HNS3_NIC_CONFIGURED;
1910 hns3_rx_scattered_reset(dev);
1911 rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1912 rte_spinlock_unlock(&hw->lock);
1916 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1918 struct hns3_adapter *hns = eth_dev->data->dev_private;
1919 struct hns3_hw *hw = &hns->hw;
1921 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1924 if (hw->adapter_state == HNS3_NIC_STARTED)
1925 hns3vf_dev_stop(eth_dev);
1927 hw->adapter_state = HNS3_NIC_CLOSING;
1928 hns3_reset_abort(hns);
1929 hw->adapter_state = HNS3_NIC_CLOSED;
1930 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1931 hns3vf_configure_all_mc_mac_addr(hns, true);
1932 hns3vf_remove_all_vlan_table(hns);
1933 hns3vf_uninit_vf(eth_dev);
1934 hns3_free_all_queues(eth_dev);
1935 rte_free(hw->reset.wait_data);
1936 rte_free(eth_dev->process_private);
1937 eth_dev->process_private = NULL;
1938 hns3_mp_uninit_primary();
1939 hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1943 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1946 struct hns3_adapter *hns = eth_dev->data->dev_private;
1947 struct hns3_hw *hw = &hns->hw;
1948 uint32_t version = hw->fw_version;
1951 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1952 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1953 HNS3_FW_VERSION_BYTE3_S),
1954 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1955 HNS3_FW_VERSION_BYTE2_S),
1956 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1957 HNS3_FW_VERSION_BYTE1_S),
1958 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1959 HNS3_FW_VERSION_BYTE0_S));
1960 ret += 1; /* add the size of '\0' */
1961 if (fw_size < (uint32_t)ret)
1968 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1969 __rte_unused int wait_to_complete)
1971 struct hns3_adapter *hns = eth_dev->data->dev_private;
1972 struct hns3_hw *hw = &hns->hw;
1973 struct hns3_mac *mac = &hw->mac;
1974 struct rte_eth_link new_link;
1976 memset(&new_link, 0, sizeof(new_link));
1977 switch (mac->link_speed) {
1978 case ETH_SPEED_NUM_10M:
1979 case ETH_SPEED_NUM_100M:
1980 case ETH_SPEED_NUM_1G:
1981 case ETH_SPEED_NUM_10G:
1982 case ETH_SPEED_NUM_25G:
1983 case ETH_SPEED_NUM_40G:
1984 case ETH_SPEED_NUM_50G:
1985 case ETH_SPEED_NUM_100G:
1986 case ETH_SPEED_NUM_200G:
1987 new_link.link_speed = mac->link_speed;
1990 new_link.link_speed = ETH_SPEED_NUM_100M;
1994 new_link.link_duplex = mac->link_duplex;
1995 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1996 new_link.link_autoneg =
1997 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1999 return rte_eth_linkstatus_set(eth_dev, &new_link);
2003 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2005 struct hns3_hw *hw = &hns->hw;
2008 ret = hns3vf_set_tc_info(hns);
2012 ret = hns3_start_queues(hns, reset_queue);
2014 hns3_err(hw, "Failed to start queues: %d", ret);
2020 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2022 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2023 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2024 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2026 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2027 uint32_t intr_vector;
2031 if (dev->data->dev_conf.intr_conf.rxq == 0)
2034 /* disable uio/vfio intr/eventfd mapping */
2035 rte_intr_disable(intr_handle);
2037 /* check and configure queue intr-vector mapping */
2038 if (rte_intr_cap_multiple(intr_handle) ||
2039 !RTE_ETH_DEV_SRIOV(dev).active) {
2040 intr_vector = hw->used_rx_queues;
2041 /* It creates event fd for each intr vector when MSIX is used */
2042 if (rte_intr_efd_enable(intr_handle, intr_vector))
2045 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2046 intr_handle->intr_vec =
2047 rte_zmalloc("intr_vec",
2048 hw->used_rx_queues * sizeof(int), 0);
2049 if (intr_handle->intr_vec == NULL) {
2050 hns3_err(hw, "Failed to allocate %d rx_queues"
2051 " intr_vec", hw->used_rx_queues);
2053 goto vf_alloc_intr_vec_error;
2057 if (rte_intr_allow_others(intr_handle)) {
2058 vec = RTE_INTR_VEC_RXTX_OFFSET;
2059 base = RTE_INTR_VEC_RXTX_OFFSET;
2061 if (rte_intr_dp_is_en(intr_handle)) {
2062 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2063 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2067 goto vf_bind_vector_error;
2068 intr_handle->intr_vec[q_id] = vec;
2069 if (vec < base + intr_handle->nb_efd - 1)
2073 rte_intr_enable(intr_handle);
2076 vf_bind_vector_error:
2077 rte_intr_efd_disable(intr_handle);
2078 if (intr_handle->intr_vec) {
2079 free(intr_handle->intr_vec);
2080 intr_handle->intr_vec = NULL;
2083 vf_alloc_intr_vec_error:
2084 rte_intr_efd_disable(intr_handle);
2089 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2091 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2092 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2093 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2097 if (dev->data->dev_conf.intr_conf.rxq == 0)
2100 if (rte_intr_dp_is_en(intr_handle)) {
2101 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2102 ret = hns3vf_bind_ring_with_vector(hw,
2103 intr_handle->intr_vec[q_id], true,
2104 HNS3_RING_TYPE_RX, q_id);
2114 hns3vf_restore_filter(struct rte_eth_dev *dev)
2116 hns3_restore_rss_filter(dev);
2120 hns3vf_dev_start(struct rte_eth_dev *dev)
2122 struct hns3_adapter *hns = dev->data->dev_private;
2123 struct hns3_hw *hw = &hns->hw;
2126 PMD_INIT_FUNC_TRACE();
2127 if (rte_atomic16_read(&hw->reset.resetting))
2130 rte_spinlock_lock(&hw->lock);
2131 hw->adapter_state = HNS3_NIC_STARTING;
2132 ret = hns3vf_do_start(hns, true);
2134 hw->adapter_state = HNS3_NIC_CONFIGURED;
2135 rte_spinlock_unlock(&hw->lock);
2138 ret = hns3vf_map_rx_interrupt(dev);
2140 hw->adapter_state = HNS3_NIC_CONFIGURED;
2141 rte_spinlock_unlock(&hw->lock);
2144 hw->adapter_state = HNS3_NIC_STARTED;
2145 rte_spinlock_unlock(&hw->lock);
2147 hns3_rx_scattered_calc(dev);
2148 hns3_set_rxtx_function(dev);
2149 hns3_mp_req_start_rxtx(dev);
2150 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2152 hns3vf_restore_filter(dev);
2154 /* Enable interrupt of all rx queues before enabling queues */
2155 hns3_dev_all_rx_queue_intr_enable(hw, true);
2157 * When finished the initialization, enable queues to receive/transmit
2160 hns3_enable_all_queues(hw, true);
2166 is_vf_reset_done(struct hns3_hw *hw)
2168 #define HNS3_FUN_RST_ING_BITS \
2169 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2170 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2171 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2172 BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2176 if (hw->reset.level == HNS3_VF_RESET) {
2177 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2178 if (val & HNS3_VF_RST_ING_BIT)
2181 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2182 if (val & HNS3_FUN_RST_ING_BITS)
2189 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2191 struct hns3_hw *hw = &hns->hw;
2192 enum hns3_reset_level reset;
2195 * According to the protocol of PCIe, FLR to a PF device resets the PF
2196 * state as well as the SR-IOV extended capability including VF Enable
2197 * which means that VFs no longer exist.
2199 * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2200 * is in FLR stage, the register state of VF device is not reliable,
2201 * so register states detection can not be carried out. In this case,
2202 * we just ignore the register states and return false to indicate that
2203 * there are no other reset states that need to be processed by driver.
2205 if (hw->reset.level == HNS3_VF_FULL_RESET)
2208 /* Check the registers to confirm whether there is reset pending */
2209 hns3vf_check_event_cause(hns, NULL);
2210 reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2211 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2212 hns3_warn(hw, "High level reset %d is pending", reset);
2219 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2221 struct hns3_hw *hw = &hns->hw;
2222 struct hns3_wait_data *wait_data = hw->reset.wait_data;
2225 if (wait_data->result == HNS3_WAIT_SUCCESS) {
2227 * After vf reset is ready, the PF may not have completed
2228 * the reset processing. The vf sending mbox to PF may fail
2229 * during the pf reset, so it is better to add extra delay.
2231 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2232 hw->reset.level == HNS3_FLR_RESET)
2234 /* Reset retry process, no need to add extra delay. */
2235 if (hw->reset.attempts)
2237 if (wait_data->check_completion == NULL)
2240 wait_data->check_completion = NULL;
2241 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2242 wait_data->count = 1;
2243 wait_data->result = HNS3_WAIT_REQUEST;
2244 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2246 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2248 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2249 gettimeofday(&tv, NULL);
2250 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2251 tv.tv_sec, tv.tv_usec);
2253 } else if (wait_data->result == HNS3_WAIT_REQUEST)
2256 wait_data->hns = hns;
2257 wait_data->check_completion = is_vf_reset_done;
2258 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2259 HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2260 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2261 wait_data->count = HNS3VF_RESET_WAIT_CNT;
2262 wait_data->result = HNS3_WAIT_REQUEST;
2263 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2268 hns3vf_prepare_reset(struct hns3_adapter *hns)
2270 struct hns3_hw *hw = &hns->hw;
2273 if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2274 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2277 rte_atomic16_set(&hw->reset.disable_cmd, 1);
2283 hns3vf_stop_service(struct hns3_adapter *hns)
2285 struct hns3_hw *hw = &hns->hw;
2286 struct rte_eth_dev *eth_dev;
2288 eth_dev = &rte_eth_devices[hw->data->port_id];
2289 if (hw->adapter_state == HNS3_NIC_STARTED)
2290 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2291 hw->mac.link_status = ETH_LINK_DOWN;
2293 hns3_set_rxtx_function(eth_dev);
2295 /* Disable datapath on secondary process. */
2296 hns3_mp_req_stop_rxtx(eth_dev);
2297 rte_delay_ms(hw->tqps_num);
2299 rte_spinlock_lock(&hw->lock);
2300 if (hw->adapter_state == HNS3_NIC_STARTED ||
2301 hw->adapter_state == HNS3_NIC_STOPPING) {
2302 hns3vf_do_stop(hns);
2303 hw->reset.mbuf_deferred_free = true;
2305 hw->reset.mbuf_deferred_free = false;
2308 * It is cumbersome for hardware to pick-and-choose entries for deletion
2309 * from table space. Hence, for function reset software intervention is
2310 * required to delete the entries.
2312 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2313 hns3vf_configure_all_mc_mac_addr(hns, true);
2314 rte_spinlock_unlock(&hw->lock);
2320 hns3vf_start_service(struct hns3_adapter *hns)
2322 struct hns3_hw *hw = &hns->hw;
2323 struct rte_eth_dev *eth_dev;
2325 eth_dev = &rte_eth_devices[hw->data->port_id];
2326 hns3_set_rxtx_function(eth_dev);
2327 hns3_mp_req_start_rxtx(eth_dev);
2328 if (hw->adapter_state == HNS3_NIC_STARTED) {
2329 hns3vf_service_handler(eth_dev);
2331 /* Enable interrupt of all rx queues before enabling queues */
2332 hns3_dev_all_rx_queue_intr_enable(hw, true);
2334 * When finished the initialization, enable queues to receive
2335 * and transmit packets.
2337 hns3_enable_all_queues(hw, true);
2344 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2346 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2347 struct rte_ether_addr *hw_mac;
2351 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2352 * on the host by "ip link set ..." command. If the hns3 PF kernel
2353 * ethdev driver sets the MAC address for VF device after the
2354 * initialization of the related VF device, the PF driver will notify
2355 * VF driver to reset VF device to make the new MAC address effective
2356 * immediately. The hns3 VF PMD driver should check whether the MAC
2357 * address has been changed by the PF kernel ethdev driver, if changed
2358 * VF driver should configure hardware using the new MAC address in the
2359 * recovering hardware configuration stage of the reset process.
2361 ret = hns3vf_get_host_mac_addr(hw);
2365 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2366 ret = rte_is_zero_ether_addr(hw_mac);
2368 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2370 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2372 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2373 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2374 &hw->data->mac_addrs[0]);
2375 hns3_warn(hw, "Default MAC address has been changed to:"
2376 " %s by the host PF kernel ethdev driver",
2385 hns3vf_restore_conf(struct hns3_adapter *hns)
2387 struct hns3_hw *hw = &hns->hw;
2390 ret = hns3vf_check_default_mac_change(hw);
2394 ret = hns3vf_configure_mac_addr(hns, false);
2398 ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2402 ret = hns3vf_restore_promisc(hns);
2404 goto err_vlan_table;
2406 ret = hns3vf_restore_vlan_conf(hns);
2408 goto err_vlan_table;
2410 ret = hns3vf_get_port_base_vlan_filter_state(hw);
2412 goto err_vlan_table;
2414 ret = hns3vf_restore_rx_interrupt(hw);
2416 goto err_vlan_table;
2418 ret = hns3_restore_gro_conf(hw);
2420 goto err_vlan_table;
2422 if (hw->adapter_state == HNS3_NIC_STARTED) {
2423 ret = hns3vf_do_start(hns, false);
2425 goto err_vlan_table;
2426 hns3_info(hw, "hns3vf dev restart successful!");
2427 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2428 hw->adapter_state = HNS3_NIC_CONFIGURED;
2432 hns3vf_configure_all_mc_mac_addr(hns, true);
2434 hns3vf_configure_mac_addr(hns, true);
2438 static enum hns3_reset_level
2439 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2441 enum hns3_reset_level reset_level;
2443 /* return the highest priority reset level amongst all */
2444 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2445 reset_level = HNS3_VF_RESET;
2446 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2447 reset_level = HNS3_VF_FULL_RESET;
2448 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2449 reset_level = HNS3_VF_PF_FUNC_RESET;
2450 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2451 reset_level = HNS3_VF_FUNC_RESET;
2452 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2453 reset_level = HNS3_FLR_RESET;
2455 reset_level = HNS3_NONE_RESET;
2457 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2458 return HNS3_NONE_RESET;
2464 hns3vf_reset_service(void *param)
2466 struct hns3_adapter *hns = (struct hns3_adapter *)param;
2467 struct hns3_hw *hw = &hns->hw;
2468 enum hns3_reset_level reset_level;
2469 struct timeval tv_delta;
2470 struct timeval tv_start;
2475 * The interrupt is not triggered within the delay time.
2476 * The interrupt may have been lost. It is necessary to handle
2477 * the interrupt to recover from the error.
2479 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2480 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2481 hns3_err(hw, "Handling interrupts in delayed tasks");
2482 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2483 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2484 if (reset_level == HNS3_NONE_RESET) {
2485 hns3_err(hw, "No reset level is set, try global reset");
2486 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2489 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2492 * Hardware reset has been notified, we now have to poll & check if
2493 * hardware has actually completed the reset sequence.
2495 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2496 if (reset_level != HNS3_NONE_RESET) {
2497 gettimeofday(&tv_start, NULL);
2498 hns3_reset_process(hns, reset_level);
2499 gettimeofday(&tv, NULL);
2500 timersub(&tv, &tv_start, &tv_delta);
2501 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2502 tv_delta.tv_usec / USEC_PER_MSEC;
2503 if (msec > HNS3_RESET_PROCESS_MS)
2504 hns3_err(hw, "%d handle long time delta %" PRIx64
2505 " ms time=%ld.%.6ld",
2506 hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2511 hns3vf_reinit_dev(struct hns3_adapter *hns)
2513 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2514 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2515 struct hns3_hw *hw = &hns->hw;
2518 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2519 rte_intr_disable(&pci_dev->intr_handle);
2520 hns3vf_set_bus_master(pci_dev, true);
2523 /* Firmware command initialize */
2524 ret = hns3_cmd_init(hw);
2526 hns3_err(hw, "Failed to init cmd: %d", ret);
2530 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2532 * UIO enables msix by writing the pcie configuration space
2533 * vfio_pci enables msix in rte_intr_enable.
2535 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2536 pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2537 if (hns3vf_enable_msix(pci_dev, true))
2538 hns3_err(hw, "Failed to enable msix");
2541 rte_intr_enable(&pci_dev->intr_handle);
2544 ret = hns3_reset_all_queues(hns);
2546 hns3_err(hw, "Failed to reset all queues: %d", ret);
2550 ret = hns3vf_init_hardware(hns);
2552 hns3_err(hw, "Failed to init hardware: %d", ret);
2559 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2560 .dev_configure = hns3vf_dev_configure,
2561 .dev_start = hns3vf_dev_start,
2562 .dev_stop = hns3vf_dev_stop,
2563 .dev_close = hns3vf_dev_close,
2564 .mtu_set = hns3vf_dev_mtu_set,
2565 .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2566 .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2567 .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2568 .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2569 .stats_get = hns3_stats_get,
2570 .stats_reset = hns3_stats_reset,
2571 .xstats_get = hns3_dev_xstats_get,
2572 .xstats_get_names = hns3_dev_xstats_get_names,
2573 .xstats_reset = hns3_dev_xstats_reset,
2574 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
2575 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2576 .dev_infos_get = hns3vf_dev_infos_get,
2577 .fw_version_get = hns3vf_fw_version_get,
2578 .rx_queue_setup = hns3_rx_queue_setup,
2579 .tx_queue_setup = hns3_tx_queue_setup,
2580 .rx_queue_release = hns3_dev_rx_queue_release,
2581 .tx_queue_release = hns3_dev_tx_queue_release,
2582 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
2583 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
2584 .rxq_info_get = hns3_rxq_info_get,
2585 .txq_info_get = hns3_txq_info_get,
2586 .rx_burst_mode_get = hns3_rx_burst_mode_get,
2587 .tx_burst_mode_get = hns3_tx_burst_mode_get,
2588 .mac_addr_add = hns3vf_add_mac_addr,
2589 .mac_addr_remove = hns3vf_remove_mac_addr,
2590 .mac_addr_set = hns3vf_set_default_mac_addr,
2591 .set_mc_addr_list = hns3vf_set_mc_mac_addr_list,
2592 .link_update = hns3vf_dev_link_update,
2593 .rss_hash_update = hns3_dev_rss_hash_update,
2594 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
2595 .reta_update = hns3_dev_rss_reta_update,
2596 .reta_query = hns3_dev_rss_reta_query,
2597 .filter_ctrl = hns3_dev_filter_ctrl,
2598 .vlan_filter_set = hns3vf_vlan_filter_set,
2599 .vlan_offload_set = hns3vf_vlan_offload_set,
2600 .get_reg = hns3_get_regs,
2601 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2604 static const struct hns3_reset_ops hns3vf_reset_ops = {
2605 .reset_service = hns3vf_reset_service,
2606 .stop_service = hns3vf_stop_service,
2607 .prepare_reset = hns3vf_prepare_reset,
2608 .wait_hardware_ready = hns3vf_wait_hardware_ready,
2609 .reinit_dev = hns3vf_reinit_dev,
2610 .restore_conf = hns3vf_restore_conf,
2611 .start_service = hns3vf_start_service,
2615 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2617 struct hns3_adapter *hns = eth_dev->data->dev_private;
2618 struct hns3_hw *hw = &hns->hw;
2621 PMD_INIT_FUNC_TRACE();
2623 eth_dev->process_private = (struct hns3_process_private *)
2624 rte_zmalloc_socket("hns3_filter_list",
2625 sizeof(struct hns3_process_private),
2626 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2627 if (eth_dev->process_private == NULL) {
2628 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2632 /* initialize flow filter lists */
2633 hns3_filterlist_init(eth_dev);
2635 hns3_set_rxtx_function(eth_dev);
2636 eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2637 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2638 ret = hns3_mp_init_secondary();
2640 PMD_INIT_LOG(ERR, "Failed to init for secondary "
2641 "process, ret = %d", ret);
2642 goto err_mp_init_secondary;
2645 hw->secondary_cnt++;
2649 ret = hns3_mp_init_primary();
2652 "Failed to init for primary process, ret = %d",
2654 goto err_mp_init_primary;
2657 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2659 hw->data = eth_dev->data;
2661 ret = hns3_reset_init(hw);
2663 goto err_init_reset;
2664 hw->reset.ops = &hns3vf_reset_ops;
2666 ret = hns3vf_init_vf(eth_dev);
2668 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2672 /* Allocate memory for storing MAC addresses */
2673 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2674 sizeof(struct rte_ether_addr) *
2675 HNS3_VF_UC_MACADDR_NUM, 0);
2676 if (eth_dev->data->mac_addrs == NULL) {
2677 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2678 "to store MAC addresses",
2679 sizeof(struct rte_ether_addr) *
2680 HNS3_VF_UC_MACADDR_NUM);
2682 goto err_rte_zmalloc;
2686 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2687 * on the host by "ip link set ..." command. To avoid some incorrect
2688 * scenes, for example, hns3 VF PMD driver fails to receive and send
2689 * packets after user configure the MAC address by using the
2690 * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2691 * address strategy as the hns3 kernel ethdev driver in the
2692 * initialization. If user configure a MAC address by the ip command
2693 * for VF device, then hns3 VF PMD driver will start with it, otherwise
2694 * start with a random MAC address in the initialization.
2696 if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2697 rte_eth_random_addr(hw->mac.mac_addr);
2698 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2699 ð_dev->data->mac_addrs[0]);
2701 hw->adapter_state = HNS3_NIC_INITIALIZED;
2703 * Pass the information to the rte_eth_dev_close() that it should also
2704 * release the private port resources.
2706 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2708 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2709 hns3_err(hw, "Reschedule reset service after dev_init");
2710 hns3_schedule_reset(hns);
2712 /* IMP will wait ready flag before reset */
2713 hns3_notify_reset_ready(hw, false);
2715 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2720 hns3vf_uninit_vf(eth_dev);
2723 rte_free(hw->reset.wait_data);
2726 hns3_mp_uninit_primary();
2728 err_mp_init_primary:
2729 err_mp_init_secondary:
2730 eth_dev->dev_ops = NULL;
2731 eth_dev->rx_pkt_burst = NULL;
2732 eth_dev->tx_pkt_burst = NULL;
2733 eth_dev->tx_pkt_prepare = NULL;
2734 rte_free(eth_dev->process_private);
2735 eth_dev->process_private = NULL;
2741 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2743 struct hns3_adapter *hns = eth_dev->data->dev_private;
2744 struct hns3_hw *hw = &hns->hw;
2746 PMD_INIT_FUNC_TRACE();
2748 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2751 eth_dev->dev_ops = NULL;
2752 eth_dev->rx_pkt_burst = NULL;
2753 eth_dev->tx_pkt_burst = NULL;
2754 eth_dev->tx_pkt_prepare = NULL;
2756 if (hw->adapter_state < HNS3_NIC_CLOSING)
2757 hns3vf_dev_close(eth_dev);
2759 hw->adapter_state = HNS3_NIC_REMOVED;
2764 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2765 struct rte_pci_device *pci_dev)
2767 return rte_eth_dev_pci_generic_probe(pci_dev,
2768 sizeof(struct hns3_adapter),
2773 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2775 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2778 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2779 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2780 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2781 { .vendor_id = 0, /* sentinel */ },
2784 static struct rte_pci_driver rte_hns3vf_pmd = {
2785 .id_table = pci_id_hns3vf_map,
2786 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2787 .probe = eth_hns3vf_pci_probe,
2788 .remove = eth_hns3vf_pci_remove,
2791 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2792 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2793 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");