drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint16_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid.
 708          */
 709         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 710         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 711                 vec = vec - 1; /* the last interrupt is reserved */
 712         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 713         for (i = 0; i < hw->intr_tqps_num; i++) {
 714                 /*
 715                  * Set gap limiter/rate limiter/quanity limiter algorithm
 716                  * configuration for interrupt coalesce of queue's interrupt.
 717                  */
 718                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 719                                        HNS3_TQP_INTR_GL_DEFAULT);
 720                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 721                                        HNS3_TQP_INTR_GL_DEFAULT);
 722                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 723                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 724
 725                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 726                                                    HNS3_RING_TYPE_TX, i);
 727                 if (ret) {
 728                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 729                                           "vector: %d, ret=%d", i, vec, ret);
 730                         return ret;
 731                 }
 732
 733                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 734                                                    HNS3_RING_TYPE_RX, i);
 735                 if (ret) {
 736                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 737                                           "vector: %d, ret=%d", i, vec, ret);
 738                         return ret;
 739                 }
 740         }
 741
 742         return 0;
 743 }
 744
 745 static int
 746 hns3vf_dev_configure(struct rte_eth_dev *dev)
 747 {
 748         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 749         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 750         struct rte_eth_conf *conf = &dev->data->dev_conf;
 751         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 752         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 753         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 754         struct rte_eth_rss_conf rss_conf;
 755         uint16_t mtu;
 756         bool gro_en;
 757         int ret;
 758
 759         /*
 760          * Hardware does not support individually enable/disable/reset the Tx or
 761          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 762          * and Rx queues at the same time. When the numbers of Tx queues
 763          * allocated by upper applications are not equal to the numbers of Rx
 764          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 765          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 766          * these fake queues are imperceptible, and can not be used by upper
 767          * applications.
 768          */
 769         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 770         if (ret) {
 771                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 772                 return ret;
 773         }
 774
 775         hw->adapter_state = HNS3_NIC_CONFIGURING;
 776         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 777                 hns3_err(hw, "setting link speed/duplex not supported");
 778                 ret = -EINVAL;
 779                 goto cfg_err;
 780         }
 781
 782         /* When RSS is not configured, redirect the packet queue 0 */
 783         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 784                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 785                 rss_conf = conf->rx_adv_conf.rss_conf;
 786                 if (rss_conf.rss_key == NULL) {
 787                         rss_conf.rss_key = rss_cfg->key;
 788                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 789                 }
 790
 791                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 792                 if (ret)
 793                         goto cfg_err;
 794         }
 795
 796         /*
 797          * If jumbo frames are enabled, MTU needs to be refreshed
 798          * according to the maximum RX packet length.
 799          */
 800         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 801                 /*
 802                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 803                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 804                  * can safely assign to "uint16_t" type variable.
 805                  */
 806                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 807                 ret = hns3vf_dev_mtu_set(dev, mtu);
 808                 if (ret)
 809                         goto cfg_err;
 810                 dev->data->mtu = mtu;
 811         }
 812
 813         ret = hns3vf_dev_configure_vlan(dev);
 814         if (ret)
 815                 goto cfg_err;
 816
 817         /* config hardware GRO */
 818         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 819         ret = hns3_config_gro(hw, gro_en);
 820         if (ret)
 821                 goto cfg_err;
 822
 823         hw->adapter_state = HNS3_NIC_CONFIGURED;
 824         return 0;
 825
 826 cfg_err:
 827         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 828         hw->adapter_state = HNS3_NIC_INITIALIZED;
 829
 830         return ret;
 831 }
 832
 833 static int
 834 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 835 {
 836         int ret;
 837
 838         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 839                                 sizeof(mtu), true, NULL, 0);
 840         if (ret)
 841                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 842
 843         return ret;
 844 }
 845
 846 static int
 847 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 848 {
 849         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 850         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 851         int ret;
 852
 853         /*
 854          * The hns3 PF/VF devices on the same port share the hardware MTU
 855          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 856          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 857          * driver, there is no need to stop the port for hns3 VF device, and the
 858          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 859          * PF's MTU.
 860          */
 861         if (rte_atomic16_read(&hw->reset.resetting)) {
 862                 hns3_err(hw, "Failed to set mtu during resetting");
 863                 return -EIO;
 864         }
 865
 866         rte_spinlock_lock(&hw->lock);
 867         ret = hns3vf_config_mtu(hw, mtu);
 868         if (ret) {
 869                 rte_spinlock_unlock(&hw->lock);
 870                 return ret;
 871         }
 872         if (frame_size > RTE_ETHER_MAX_LEN)
 873                 dev->data->dev_conf.rxmode.offloads |=
 874                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 875         else
 876                 dev->data->dev_conf.rxmode.offloads &=
 877                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 878         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 879         rte_spinlock_unlock(&hw->lock);
 880
 881         return 0;
 882 }
 883
 884 static int
 885 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 886 {
 887         struct hns3_adapter *hns = eth_dev->data->dev_private;
 888         struct hns3_hw *hw = &hns->hw;
 889         uint16_t q_num = hw->tqps_num;
 890
 891         /*
 892          * In interrupt mode, 'max_rx_queues' is set based on the number of
 893          * MSI-X interrupt resources of the hardware.
 894          */
 895         if (hw->data->dev_conf.intr_conf.rxq == 1)
 896                 q_num = hw->intr_tqps_num;
 897
 898         info->max_rx_queues = q_num;
 899         info->max_tx_queues = hw->tqps_num;
 900         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 901         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 902         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 903         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 904         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 905
 906         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 907                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 908                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 909                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 910                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 911                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 912                                  DEV_RX_OFFLOAD_SCATTER |
 913                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 914                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 915                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 916                                  DEV_RX_OFFLOAD_RSS_HASH |
 917                                  DEV_RX_OFFLOAD_TCP_LRO);
 918         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 919         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 920                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 921                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 922                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 923                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 924                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 925                                  DEV_TX_OFFLOAD_TCP_TSO |
 926                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 927                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 928                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 929                                  info->tx_queue_offload_capa |
 930                                  hns3_txvlan_cap_get(hw));
 931
 932         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 933                 .nb_max = HNS3_MAX_RING_DESC,
 934                 .nb_min = HNS3_MIN_RING_DESC,
 935                 .nb_align = HNS3_ALIGN_RING_DESC,
 936         };
 937
 938         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 939                 .nb_max = HNS3_MAX_RING_DESC,
 940                 .nb_min = HNS3_MIN_RING_DESC,
 941                 .nb_align = HNS3_ALIGN_RING_DESC,
 942                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 943                 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT,
 944         };
 945
 946         info->default_rxconf = (struct rte_eth_rxconf) {
 947                 /*
 948                  * If there are no available Rx buffer descriptors, incoming
 949                  * packets are always dropped by hardware based on hns3 network
 950                  * engine.
 951                  */
 952                 .rx_drop_en = 1,
 953         };
 954
 955         info->vmdq_queue_num = 0;
 956
 957         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 958         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 959         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 960         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 961         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 962
 963         return 0;
 964 }
 965
 966 static void
 967 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 968 {
 969         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 970 }
 971
 972 static void
 973 hns3vf_disable_irq0(struct hns3_hw *hw)
 974 {
 975         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 976 }
 977
 978 static void
 979 hns3vf_enable_irq0(struct hns3_hw *hw)
 980 {
 981         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 982 }
 983
 984 static enum hns3vf_evt_cause
 985 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 986 {
 987         struct hns3_hw *hw = &hns->hw;
 988         enum hns3vf_evt_cause ret;
 989         uint32_t cmdq_stat_reg;
 990         uint32_t rst_ing_reg;
 991         uint32_t val;
 992
 993         /* Fetch the events from their corresponding regs */
 994         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 995
 996         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 997                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 998                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 999                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1000                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1001                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1002                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1003                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1004                 if (clearval) {
1005                         hw->reset.stats.global_cnt++;
1006                         hns3_warn(hw, "Global reset detected, clear reset status");
1007                 } else {
1008                         hns3_schedule_delayed_reset(hns);
1009                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1010                 }
1011
1012                 ret = HNS3VF_VECTOR0_EVENT_RST;
1013                 goto out;
1014         }
1015
1016         /* Check for vector0 mailbox(=CMDQ RX) event source */
1017         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1018                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1019                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1020                 goto out;
1021         }
1022
1023         val = 0;
1024         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1025 out:
1026         if (clearval)
1027                 *clearval = val;
1028         return ret;
1029 }
1030
1031 static void
1032 hns3vf_interrupt_handler(void *param)
1033 {
1034         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1035         struct hns3_adapter *hns = dev->data->dev_private;
1036         struct hns3_hw *hw = &hns->hw;
1037         enum hns3vf_evt_cause event_cause;
1038         uint32_t clearval;
1039
1040         if (hw->irq_thread_id == 0)
1041                 hw->irq_thread_id = pthread_self();
1042
1043         /* Disable interrupt */
1044         hns3vf_disable_irq0(hw);
1045
1046         /* Read out interrupt causes */
1047         event_cause = hns3vf_check_event_cause(hns, &clearval);
1048
1049         switch (event_cause) {
1050         case HNS3VF_VECTOR0_EVENT_RST:
1051                 hns3_schedule_reset(hns);
1052                 break;
1053         case HNS3VF_VECTOR0_EVENT_MBX:
1054                 hns3_dev_handle_mbx_msg(hw);
1055                 break;
1056         default:
1057                 break;
1058         }
1059
1060         /* Clear interrupt causes */
1061         hns3vf_clear_event_cause(hw, clearval);
1062
1063         /* Enable interrupt */
1064         hns3vf_enable_irq0(hw);
1065 }
1066
1067 static void
1068 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1069 {
1070         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1071         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1072         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1073 }
1074
1075 static void
1076 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1077 {
1078         struct hns3_dev_specs_0_cmd *req0;
1079
1080         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1081
1082         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1083         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1084         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1085 }
1086
1087 static int
1088 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1089 {
1090         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1091         int ret;
1092         int i;
1093
1094         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1095                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1096                                           true);
1097                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1098         }
1099         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1100
1101         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1102         if (ret)
1103                 return ret;
1104
1105         hns3vf_parse_dev_specifications(hw, desc);
1106
1107         return 0;
1108 }
1109
1110 static int
1111 hns3vf_get_capability(struct hns3_hw *hw)
1112 {
1113         struct rte_pci_device *pci_dev;
1114         struct rte_eth_dev *eth_dev;
1115         uint8_t revision;
1116         int ret;
1117
1118         eth_dev = &rte_eth_devices[hw->data->port_id];
1119         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1120
1121         /* Get PCI revision id */
1122         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1123                                   HNS3_PCI_REVISION_ID);
1124         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1125                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1126                              ret);
1127                 return -EIO;
1128         }
1129         hw->revision = revision;
1130
1131         if (revision < PCI_REVISION_ID_HIP09_A) {
1132                 hns3vf_set_default_dev_specifications(hw);
1133                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1134                 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
1135                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1136                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1137                 return 0;
1138         }
1139
1140         ret = hns3vf_query_dev_specifications(hw);
1141         if (ret) {
1142                 PMD_INIT_LOG(ERR,
1143                              "failed to query dev specifications, ret = %d",
1144                              ret);
1145                 return ret;
1146         }
1147
1148         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1149         hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
1150         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1151         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1152
1153         return 0;
1154 }
1155
1156 static int
1157 hns3vf_check_tqp_info(struct hns3_hw *hw)
1158 {
1159         uint16_t tqps_num;
1160
1161         tqps_num = hw->tqps_num;
1162         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1163                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1164                                   "range: 1~%d",
1165                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1166                 return -EINVAL;
1167         }
1168
1169         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1170
1171         return 0;
1172 }
1173 static int
1174 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1175 {
1176         uint8_t resp_msg;
1177         int ret;
1178
1179         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1180                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1181                                 true, &resp_msg, sizeof(resp_msg));
1182         if (ret) {
1183                 if (ret == -ETIME) {
1184                         /*
1185                          * Getting current port based VLAN state from PF driver
1186                          * will not affect VF driver's basic function. Because
1187                          * the VF driver relies on hns3 PF kernel ether driver,
1188                          * to avoid introducing compatibility issues with older
1189                          * version of PF driver, no failure will be returned
1190                          * when the return value is ETIME. This return value has
1191                          * the following scenarios:
1192                          * 1) Firmware didn't return the results in time
1193                          * 2) the result return by firmware is timeout
1194                          * 3) the older version of kernel side PF driver does
1195                          *    not support this mailbox message.
1196                          * For scenarios 1 and 2, it is most likely that a
1197                          * hardware error has occurred, or a hardware reset has
1198                          * occurred. In this case, these errors will be caught
1199                          * by other functions.
1200                          */
1201                         PMD_INIT_LOG(WARNING,
1202                                 "failed to get PVID state for timeout, maybe "
1203                                 "kernel side PF driver doesn't support this "
1204                                 "mailbox message, or firmware didn't respond.");
1205                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1206                 } else {
1207                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1208                                 " ret = %d", ret);
1209                         return ret;
1210                 }
1211         }
1212         hw->port_base_vlan_cfg.state = resp_msg ?
1213                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1214         return 0;
1215 }
1216
1217 static int
1218 hns3vf_get_queue_info(struct hns3_hw *hw)
1219 {
1220 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1221         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1222         int ret;
1223
1224         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1225                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1226         if (ret) {
1227                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1228                 return ret;
1229         }
1230
1231         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1232         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1233
1234         return hns3vf_check_tqp_info(hw);
1235 }
1236
1237 static int
1238 hns3vf_get_queue_depth(struct hns3_hw *hw)
1239 {
1240 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1241         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1242         int ret;
1243
1244         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1245                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1246         if (ret) {
1247                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1248                              ret);
1249                 return ret;
1250         }
1251
1252         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1253         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1254
1255         return 0;
1256 }
1257
1258 static int
1259 hns3vf_get_tc_info(struct hns3_hw *hw)
1260 {
1261         uint8_t resp_msg;
1262         int ret;
1263
1264         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1265                                 true, &resp_msg, sizeof(resp_msg));
1266         if (ret) {
1267                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1268                          ret);
1269                 return ret;
1270         }
1271
1272         hw->hw_tc_map = resp_msg;
1273
1274         return 0;
1275 }
1276
1277 static int
1278 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1279 {
1280         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1281         int ret;
1282
1283         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1284                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1285         if (ret) {
1286                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1287                 return ret;
1288         }
1289
1290         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1291
1292         return 0;
1293 }
1294
1295 static int
1296 hns3vf_get_configuration(struct hns3_hw *hw)
1297 {
1298         int ret;
1299
1300         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1301         hw->rss_dis_flag = false;
1302
1303         /* Get device capability */
1304         ret = hns3vf_get_capability(hw);
1305         if (ret) {
1306                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1307                 return ret;
1308         }
1309
1310         /* Get queue configuration from PF */
1311         ret = hns3vf_get_queue_info(hw);
1312         if (ret)
1313                 return ret;
1314
1315         /* Get queue depth info from PF */
1316         ret = hns3vf_get_queue_depth(hw);
1317         if (ret)
1318                 return ret;
1319
1320         /* Get user defined VF MAC addr from PF */
1321         ret = hns3vf_get_host_mac_addr(hw);
1322         if (ret)
1323                 return ret;
1324
1325         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1326         if (ret)
1327                 return ret;
1328
1329         /* Get tc configuration from PF */
1330         return hns3vf_get_tc_info(hw);
1331 }
1332
1333 static int
1334 hns3vf_set_tc_info(struct hns3_adapter *hns)
1335 {
1336         struct hns3_hw *hw = &hns->hw;
1337         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1338         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1339         uint8_t i;
1340
1341         hw->num_tc = 0;
1342         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1343                 if (hw->hw_tc_map & BIT(i))
1344                         hw->num_tc++;
1345
1346         if (nb_rx_q < hw->num_tc) {
1347                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1348                          nb_rx_q, hw->num_tc);
1349                 return -EINVAL;
1350         }
1351
1352         if (nb_tx_q < hw->num_tc) {
1353                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1354                          nb_tx_q, hw->num_tc);
1355                 return -EINVAL;
1356         }
1357
1358         hns3_set_rss_size(hw, nb_rx_q);
1359         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1360
1361         return 0;
1362 }
1363
1364 static void
1365 hns3vf_request_link_info(struct hns3_hw *hw)
1366 {
1367         uint8_t resp_msg;
1368         int ret;
1369
1370         if (rte_atomic16_read(&hw->reset.resetting))
1371                 return;
1372         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1373                                 &resp_msg, sizeof(resp_msg));
1374         if (ret)
1375                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1376 }
1377
1378 static int
1379 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1380 {
1381 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1382         struct hns3_hw *hw = &hns->hw;
1383         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1384         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1385         uint8_t is_kill = on ? 0 : 1;
1386
1387         msg_data[0] = is_kill;
1388         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1389         memcpy(&msg_data[3], &proto, sizeof(proto));
1390
1391         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1392                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1393                                  0);
1394 }
1395
1396 static int
1397 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1398 {
1399         struct hns3_adapter *hns = dev->data->dev_private;
1400         struct hns3_hw *hw = &hns->hw;
1401         int ret;
1402
1403         if (rte_atomic16_read(&hw->reset.resetting)) {
1404                 hns3_err(hw,
1405                          "vf set vlan id failed during resetting, vlan_id =%u",
1406                          vlan_id);
1407                 return -EIO;
1408         }
1409         rte_spinlock_lock(&hw->lock);
1410         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1411         rte_spinlock_unlock(&hw->lock);
1412         if (ret)
1413                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1414                          vlan_id, ret);
1415
1416         return ret;
1417 }
1418
1419 static int
1420 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1421 {
1422         uint8_t msg_data;
1423         int ret;
1424
1425         msg_data = enable ? 1 : 0;
1426         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1427                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1428         if (ret)
1429                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1430
1431         return ret;
1432 }
1433
1434 static int
1435 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1436 {
1437         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1438         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1439         unsigned int tmp_mask;
1440         int ret = 0;
1441
1442         if (rte_atomic16_read(&hw->reset.resetting)) {
1443                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1444                              "mask = 0x%x", mask);
1445                 return -EIO;
1446         }
1447
1448         tmp_mask = (unsigned int)mask;
1449         /* Vlan stripping setting */
1450         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1451                 rte_spinlock_lock(&hw->lock);
1452                 /* Enable or disable VLAN stripping */
1453                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1454                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1455                 else
1456                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1457                 rte_spinlock_unlock(&hw->lock);
1458         }
1459
1460         return ret;
1461 }
1462
1463 static int
1464 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1465 {
1466         struct rte_vlan_filter_conf *vfc;
1467         struct hns3_hw *hw = &hns->hw;
1468         uint16_t vlan_id;
1469         uint64_t vbit;
1470         uint64_t ids;
1471         int ret = 0;
1472         uint32_t i;
1473
1474         vfc = &hw->data->vlan_filter_conf;
1475         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1476                 if (vfc->ids[i] == 0)
1477                         continue;
1478                 ids = vfc->ids[i];
1479                 while (ids) {
1480                         /*
1481                          * 64 means the num bits of ids, one bit corresponds to
1482                          * one vlan id
1483                          */
1484                         vlan_id = 64 * i;
1485                         /* count trailing zeroes */
1486                         vbit = ~ids & (ids - 1);
1487                         /* clear least significant bit set */
1488                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1489                         for (; vbit;) {
1490                                 vbit >>= 1;
1491                                 vlan_id++;
1492                         }
1493                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1494                         if (ret) {
1495                                 hns3_err(hw,
1496                                          "VF handle vlan table failed, ret =%d, on = %d",
1497                                          ret, on);
1498                                 return ret;
1499                         }
1500                 }
1501         }
1502
1503         return ret;
1504 }
1505
1506 static int
1507 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1508 {
1509         return hns3vf_handle_all_vlan_table(hns, 0);
1510 }
1511
1512 static int
1513 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1514 {
1515         struct hns3_hw *hw = &hns->hw;
1516         struct rte_eth_conf *dev_conf;
1517         bool en;
1518         int ret;
1519
1520         dev_conf = &hw->data->dev_conf;
1521         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1522                                                                    : false;
1523         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1524         if (ret)
1525                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1526                          ret);
1527         return ret;
1528 }
1529
1530 static int
1531 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1532 {
1533         struct hns3_adapter *hns = dev->data->dev_private;
1534         struct rte_eth_dev_data *data = dev->data;
1535         struct hns3_hw *hw = &hns->hw;
1536         int ret;
1537
1538         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1539             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1540             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1541                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1542                               "or hw_vlan_insert_pvid is not support!");
1543         }
1544
1545         /* Apply vlan offload setting */
1546         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1547         if (ret)
1548                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1549
1550         return ret;
1551 }
1552
1553 static int
1554 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1555 {
1556         uint8_t msg_data;
1557
1558         msg_data = alive ? 1 : 0;
1559         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1560                                  sizeof(msg_data), false, NULL, 0);
1561 }
1562
1563 static void
1564 hns3vf_keep_alive_handler(void *param)
1565 {
1566         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1567         struct hns3_adapter *hns = eth_dev->data->dev_private;
1568         struct hns3_hw *hw = &hns->hw;
1569         uint8_t respmsg;
1570         int ret;
1571
1572         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1573                                 false, &respmsg, sizeof(uint8_t));
1574         if (ret)
1575                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1576                          ret);
1577
1578         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1579                           eth_dev);
1580 }
1581
1582 static void
1583 hns3vf_service_handler(void *param)
1584 {
1585         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1586         struct hns3_adapter *hns = eth_dev->data->dev_private;
1587         struct hns3_hw *hw = &hns->hw;
1588
1589         /*
1590          * The query link status and reset processing are executed in the
1591          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1592          * and the query operation will time out after 30ms. In the case of
1593          * multiple PF/VFs, each query failure timeout causes the IMP reset
1594          * interrupt to fail to respond within 100ms.
1595          * Before querying the link status, check whether there is a reset
1596          * pending, and if so, abandon the query.
1597          */
1598         if (!hns3vf_is_reset_pending(hns))
1599                 hns3vf_request_link_info(hw);
1600         else
1601                 hns3_warn(hw, "Cancel the query when reset is pending");
1602
1603         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1604                           eth_dev);
1605 }
1606
1607 static int
1608 hns3_query_vf_resource(struct hns3_hw *hw)
1609 {
1610         struct hns3_vf_res_cmd *req;
1611         struct hns3_cmd_desc desc;
1612         uint16_t num_msi;
1613         int ret;
1614
1615         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1616         ret = hns3_cmd_send(hw, &desc, 1);
1617         if (ret) {
1618                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1619                 return ret;
1620         }
1621
1622         req = (struct hns3_vf_res_cmd *)desc.data;
1623         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1624                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1625         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1626                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1627                          num_msi, HNS3_MIN_VECTOR_NUM);
1628                 return -EINVAL;
1629         }
1630
1631         hw->num_msi = num_msi;
1632
1633         return 0;
1634 }
1635
1636 static int
1637 hns3vf_init_hardware(struct hns3_adapter *hns)
1638 {
1639         struct hns3_hw *hw = &hns->hw;
1640         uint16_t mtu = hw->data->mtu;
1641         int ret;
1642
1643         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1644         if (ret)
1645                 return ret;
1646
1647         ret = hns3vf_config_mtu(hw, mtu);
1648         if (ret)
1649                 goto err_init_hardware;
1650
1651         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1652         if (ret) {
1653                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1654                 goto err_init_hardware;
1655         }
1656
1657         ret = hns3_config_gro(hw, false);
1658         if (ret) {
1659                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1660                 goto err_init_hardware;
1661         }
1662
1663         /*
1664          * In the initialization clearing the all hardware mapping relationship
1665          * configurations between queues and interrupt vectors is needed, so
1666          * some error caused by the residual configurations, such as the
1667          * unexpected interrupt, can be avoid.
1668          */
1669         ret = hns3vf_init_ring_with_vector(hw);
1670         if (ret) {
1671                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1672                 goto err_init_hardware;
1673         }
1674
1675         ret = hns3vf_set_alive(hw, true);
1676         if (ret) {
1677                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1678                 goto err_init_hardware;
1679         }
1680
1681         hns3vf_request_link_info(hw);
1682         return 0;
1683
1684 err_init_hardware:
1685         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1686         return ret;
1687 }
1688
1689 static int
1690 hns3vf_clear_vport_list(struct hns3_hw *hw)
1691 {
1692         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1693                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1694                                  NULL, 0);
1695 }
1696
1697 static int
1698 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1699 {
1700         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1701         struct hns3_adapter *hns = eth_dev->data->dev_private;
1702         struct hns3_hw *hw = &hns->hw;
1703         int ret;
1704
1705         PMD_INIT_FUNC_TRACE();
1706
1707         /* Get hardware io base address from pcie BAR2 IO space */
1708         hw->io_base = pci_dev->mem_resource[2].addr;
1709
1710         /* Firmware command queue initialize */
1711         ret = hns3_cmd_init_queue(hw);
1712         if (ret) {
1713                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1714                 goto err_cmd_init_queue;
1715         }
1716
1717         /* Firmware command initialize */
1718         ret = hns3_cmd_init(hw);
1719         if (ret) {
1720                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1721                 goto err_cmd_init;
1722         }
1723
1724         /* Get VF resource */
1725         ret = hns3_query_vf_resource(hw);
1726         if (ret)
1727                 goto err_cmd_init;
1728
1729         rte_spinlock_init(&hw->mbx_resp.lock);
1730
1731         hns3vf_clear_event_cause(hw, 0);
1732
1733         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1734                                          hns3vf_interrupt_handler, eth_dev);
1735         if (ret) {
1736                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1737                 goto err_intr_callback_register;
1738         }
1739
1740         /* Enable interrupt */
1741         rte_intr_enable(&pci_dev->intr_handle);
1742         hns3vf_enable_irq0(hw);
1743
1744         /* Get configuration from PF */
1745         ret = hns3vf_get_configuration(hw);
1746         if (ret) {
1747                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1748                 goto err_get_config;
1749         }
1750
1751         /*
1752          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1753          * on the host by "ip link set ..." command. To avoid some incorrect
1754          * scenes, for example, hns3 VF PMD driver fails to receive and send
1755          * packets after user configure the MAC address by using the
1756          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
1757          * address strategy as the hns3 kernel ethdev driver in the
1758          * initialization. If user configure a MAC address by the ip command
1759          * for VF device, then hns3 VF PMD driver will start with it, otherwise
1760          * start with a random MAC address in the initialization.
1761          */
1762         ret = rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr);
1763         if (ret)
1764                 rte_eth_random_addr(hw->mac.mac_addr);
1765
1766         ret = hns3vf_clear_vport_list(hw);
1767         if (ret) {
1768                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1769                 goto err_get_config;
1770         }
1771
1772         ret = hns3vf_init_hardware(hns);
1773         if (ret)
1774                 goto err_get_config;
1775
1776         hns3_set_default_rss_args(hw);
1777
1778         return 0;
1779
1780 err_get_config:
1781         hns3vf_disable_irq0(hw);
1782         rte_intr_disable(&pci_dev->intr_handle);
1783         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1784                              eth_dev);
1785 err_intr_callback_register:
1786 err_cmd_init:
1787         hns3_cmd_uninit(hw);
1788         hns3_cmd_destroy_queue(hw);
1789 err_cmd_init_queue:
1790         hw->io_base = NULL;
1791
1792         return ret;
1793 }
1794
1795 static void
1796 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1797 {
1798         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1799         struct hns3_adapter *hns = eth_dev->data->dev_private;
1800         struct hns3_hw *hw = &hns->hw;
1801
1802         PMD_INIT_FUNC_TRACE();
1803
1804         hns3_rss_uninit(hns);
1805         (void)hns3_config_gro(hw, false);
1806         (void)hns3vf_set_alive(hw, false);
1807         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1808         hns3vf_disable_irq0(hw);
1809         rte_intr_disable(&pci_dev->intr_handle);
1810         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1811                              eth_dev);
1812         hns3_cmd_uninit(hw);
1813         hns3_cmd_destroy_queue(hw);
1814         hw->io_base = NULL;
1815 }
1816
1817 static int
1818 hns3vf_do_stop(struct hns3_adapter *hns)
1819 {
1820         struct hns3_hw *hw = &hns->hw;
1821         bool reset_queue;
1822
1823         hw->mac.link_status = ETH_LINK_DOWN;
1824
1825         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1826                 hns3vf_configure_mac_addr(hns, true);
1827                 reset_queue = true;
1828         } else
1829                 reset_queue = false;
1830         return hns3_stop_queues(hns, reset_queue);
1831 }
1832
1833 static void
1834 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1835 {
1836         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1838         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1839         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1840         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1841         uint16_t q_id;
1842
1843         if (dev->data->dev_conf.intr_conf.rxq == 0)
1844                 return;
1845
1846         /* unmap the ring with vector */
1847         if (rte_intr_allow_others(intr_handle)) {
1848                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1849                 base = RTE_INTR_VEC_RXTX_OFFSET;
1850         }
1851         if (rte_intr_dp_is_en(intr_handle)) {
1852                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1853                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1854                                                            HNS3_RING_TYPE_RX,
1855                                                            q_id);
1856                         if (vec < base + intr_handle->nb_efd - 1)
1857                                 vec++;
1858                 }
1859         }
1860         /* Clean datapath event and queue/vec mapping */
1861         rte_intr_efd_disable(intr_handle);
1862         if (intr_handle->intr_vec) {
1863                 rte_free(intr_handle->intr_vec);
1864                 intr_handle->intr_vec = NULL;
1865         }
1866 }
1867
1868 static void
1869 hns3vf_dev_stop(struct rte_eth_dev *dev)
1870 {
1871         struct hns3_adapter *hns = dev->data->dev_private;
1872         struct hns3_hw *hw = &hns->hw;
1873
1874         PMD_INIT_FUNC_TRACE();
1875
1876         hw->adapter_state = HNS3_NIC_STOPPING;
1877         hns3_set_rxtx_function(dev);
1878         rte_wmb();
1879         /* Disable datapath on secondary process. */
1880         hns3_mp_req_stop_rxtx(dev);
1881         /* Prevent crashes when queues are still in use. */
1882         rte_delay_ms(hw->tqps_num);
1883
1884         rte_spinlock_lock(&hw->lock);
1885         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1886                 hns3vf_do_stop(hns);
1887                 hns3vf_unmap_rx_interrupt(dev);
1888                 hns3_dev_release_mbufs(hns);
1889                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1890         }
1891         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1892         rte_spinlock_unlock(&hw->lock);
1893 }
1894
1895 static void
1896 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1897 {
1898         struct hns3_adapter *hns = eth_dev->data->dev_private;
1899         struct hns3_hw *hw = &hns->hw;
1900
1901         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1902                 return;
1903
1904         if (hw->adapter_state == HNS3_NIC_STARTED)
1905                 hns3vf_dev_stop(eth_dev);
1906
1907         hw->adapter_state = HNS3_NIC_CLOSING;
1908         hns3_reset_abort(hns);
1909         hw->adapter_state = HNS3_NIC_CLOSED;
1910         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1911         hns3vf_configure_all_mc_mac_addr(hns, true);
1912         hns3vf_remove_all_vlan_table(hns);
1913         hns3vf_uninit_vf(eth_dev);
1914         hns3_free_all_queues(eth_dev);
1915         rte_free(hw->reset.wait_data);
1916         rte_free(eth_dev->process_private);
1917         eth_dev->process_private = NULL;
1918         hns3_mp_uninit_primary();
1919         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1920 }
1921
1922 static int
1923 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1924                       size_t fw_size)
1925 {
1926         struct hns3_adapter *hns = eth_dev->data->dev_private;
1927         struct hns3_hw *hw = &hns->hw;
1928         uint32_t version = hw->fw_version;
1929         int ret;
1930
1931         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1932                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1933                                       HNS3_FW_VERSION_BYTE3_S),
1934                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1935                                       HNS3_FW_VERSION_BYTE2_S),
1936                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1937                                       HNS3_FW_VERSION_BYTE1_S),
1938                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1939                                       HNS3_FW_VERSION_BYTE0_S));
1940         ret += 1; /* add the size of '\0' */
1941         if (fw_size < (uint32_t)ret)
1942                 return ret;
1943         else
1944                 return 0;
1945 }
1946
1947 static int
1948 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1949                        __rte_unused int wait_to_complete)
1950 {
1951         struct hns3_adapter *hns = eth_dev->data->dev_private;
1952         struct hns3_hw *hw = &hns->hw;
1953         struct hns3_mac *mac = &hw->mac;
1954         struct rte_eth_link new_link;
1955
1956         memset(&new_link, 0, sizeof(new_link));
1957         switch (mac->link_speed) {
1958         case ETH_SPEED_NUM_10M:
1959         case ETH_SPEED_NUM_100M:
1960         case ETH_SPEED_NUM_1G:
1961         case ETH_SPEED_NUM_10G:
1962         case ETH_SPEED_NUM_25G:
1963         case ETH_SPEED_NUM_40G:
1964         case ETH_SPEED_NUM_50G:
1965         case ETH_SPEED_NUM_100G:
1966         case ETH_SPEED_NUM_200G:
1967                 new_link.link_speed = mac->link_speed;
1968                 break;
1969         default:
1970                 new_link.link_speed = ETH_SPEED_NUM_100M;
1971                 break;
1972         }
1973
1974         new_link.link_duplex = mac->link_duplex;
1975         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1976         new_link.link_autoneg =
1977             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1978
1979         return rte_eth_linkstatus_set(eth_dev, &new_link);
1980 }
1981
1982 static int
1983 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1984 {
1985         struct hns3_hw *hw = &hns->hw;
1986         int ret;
1987
1988         ret = hns3vf_set_tc_info(hns);
1989         if (ret)
1990                 return ret;
1991
1992         ret = hns3_start_queues(hns, reset_queue);
1993         if (ret)
1994                 hns3_err(hw, "Failed to start queues: %d", ret);
1995
1996         return ret;
1997 }
1998
1999 static int
2000 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2001 {
2002         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2003         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2004         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2006         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2007         uint32_t intr_vector;
2008         uint16_t q_id;
2009         int ret;
2010
2011         if (dev->data->dev_conf.intr_conf.rxq == 0)
2012                 return 0;
2013
2014         /* disable uio/vfio intr/eventfd mapping */
2015         rte_intr_disable(intr_handle);
2016
2017         /* check and configure queue intr-vector mapping */
2018         if (rte_intr_cap_multiple(intr_handle) ||
2019             !RTE_ETH_DEV_SRIOV(dev).active) {
2020                 intr_vector = hw->used_rx_queues;
2021                 /* It creates event fd for each intr vector when MSIX is used */
2022                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2023                         return -EINVAL;
2024         }
2025         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2026                 intr_handle->intr_vec =
2027                         rte_zmalloc("intr_vec",
2028                                     hw->used_rx_queues * sizeof(int), 0);
2029                 if (intr_handle->intr_vec == NULL) {
2030                         hns3_err(hw, "Failed to allocate %d rx_queues"
2031                                      " intr_vec", hw->used_rx_queues);
2032                         ret = -ENOMEM;
2033                         goto vf_alloc_intr_vec_error;
2034                 }
2035         }
2036
2037         if (rte_intr_allow_others(intr_handle)) {
2038                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2039                 base = RTE_INTR_VEC_RXTX_OFFSET;
2040         }
2041         if (rte_intr_dp_is_en(intr_handle)) {
2042                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2043                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2044                                                            HNS3_RING_TYPE_RX,
2045                                                            q_id);
2046                         if (ret)
2047                                 goto vf_bind_vector_error;
2048                         intr_handle->intr_vec[q_id] = vec;
2049                         if (vec < base + intr_handle->nb_efd - 1)
2050                                 vec++;
2051                 }
2052         }
2053         rte_intr_enable(intr_handle);
2054         return 0;
2055
2056 vf_bind_vector_error:
2057         rte_intr_efd_disable(intr_handle);
2058         if (intr_handle->intr_vec) {
2059                 free(intr_handle->intr_vec);
2060                 intr_handle->intr_vec = NULL;
2061         }
2062         return ret;
2063 vf_alloc_intr_vec_error:
2064         rte_intr_efd_disable(intr_handle);
2065         return ret;
2066 }
2067
2068 static int
2069 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2070 {
2071         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2072         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2073         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2074         uint16_t q_id;
2075         int ret;
2076
2077         if (dev->data->dev_conf.intr_conf.rxq == 0)
2078                 return 0;
2079
2080         if (rte_intr_dp_is_en(intr_handle)) {
2081                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2082                         ret = hns3vf_bind_ring_with_vector(hw,
2083                                         intr_handle->intr_vec[q_id], true,
2084                                         HNS3_RING_TYPE_RX, q_id);
2085                         if (ret)
2086                                 return ret;
2087                 }
2088         }
2089
2090         return 0;
2091 }
2092
2093 static void
2094 hns3vf_restore_filter(struct rte_eth_dev *dev)
2095 {
2096         hns3_restore_rss_filter(dev);
2097 }
2098
2099 static int
2100 hns3vf_dev_start(struct rte_eth_dev *dev)
2101 {
2102         struct hns3_adapter *hns = dev->data->dev_private;
2103         struct hns3_hw *hw = &hns->hw;
2104         int ret;
2105
2106         PMD_INIT_FUNC_TRACE();
2107         if (rte_atomic16_read(&hw->reset.resetting))
2108                 return -EBUSY;
2109
2110         rte_spinlock_lock(&hw->lock);
2111         hw->adapter_state = HNS3_NIC_STARTING;
2112         ret = hns3vf_do_start(hns, true);
2113         if (ret) {
2114                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2115                 rte_spinlock_unlock(&hw->lock);
2116                 return ret;
2117         }
2118         ret = hns3vf_map_rx_interrupt(dev);
2119         if (ret) {
2120                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2121                 rte_spinlock_unlock(&hw->lock);
2122                 return ret;
2123         }
2124         hw->adapter_state = HNS3_NIC_STARTED;
2125         rte_spinlock_unlock(&hw->lock);
2126
2127         hns3_set_rxtx_function(dev);
2128         hns3_mp_req_start_rxtx(dev);
2129         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2130
2131         hns3vf_restore_filter(dev);
2132
2133         /* Enable interrupt of all rx queues before enabling queues */
2134         hns3_dev_all_rx_queue_intr_enable(hw, true);
2135         /*
2136          * When finished the initialization, enable queues to receive/transmit
2137          * packets.
2138          */
2139         hns3_enable_all_queues(hw, true);
2140
2141         return ret;
2142 }
2143
2144 static bool
2145 is_vf_reset_done(struct hns3_hw *hw)
2146 {
2147 #define HNS3_FUN_RST_ING_BITS \
2148         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2149          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2150          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2151          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2152
2153         uint32_t val;
2154
2155         if (hw->reset.level == HNS3_VF_RESET) {
2156                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2157                 if (val & HNS3_VF_RST_ING_BIT)
2158                         return false;
2159         } else {
2160                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2161                 if (val & HNS3_FUN_RST_ING_BITS)
2162                         return false;
2163         }
2164         return true;
2165 }
2166
2167 bool
2168 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2169 {
2170         struct hns3_hw *hw = &hns->hw;
2171         enum hns3_reset_level reset;
2172
2173         hns3vf_check_event_cause(hns, NULL);
2174         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2175         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2176                 hns3_warn(hw, "High level reset %d is pending", reset);
2177                 return true;
2178         }
2179         return false;
2180 }
2181
2182 static int
2183 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2184 {
2185         struct hns3_hw *hw = &hns->hw;
2186         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2187         struct timeval tv;
2188
2189         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2190                 /*
2191                  * After vf reset is ready, the PF may not have completed
2192                  * the reset processing. The vf sending mbox to PF may fail
2193                  * during the pf reset, so it is better to add extra delay.
2194                  */
2195                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2196                     hw->reset.level == HNS3_FLR_RESET)
2197                         return 0;
2198                 /* Reset retry process, no need to add extra delay. */
2199                 if (hw->reset.attempts)
2200                         return 0;
2201                 if (wait_data->check_completion == NULL)
2202                         return 0;
2203
2204                 wait_data->check_completion = NULL;
2205                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2206                 wait_data->count = 1;
2207                 wait_data->result = HNS3_WAIT_REQUEST;
2208                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2209                                   wait_data);
2210                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2211                 return -EAGAIN;
2212         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2213                 gettimeofday(&tv, NULL);
2214                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2215                           tv.tv_sec, tv.tv_usec);
2216                 return -ETIME;
2217         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2218                 return -EAGAIN;
2219
2220         wait_data->hns = hns;
2221         wait_data->check_completion = is_vf_reset_done;
2222         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2223                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2224         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2225         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2226         wait_data->result = HNS3_WAIT_REQUEST;
2227         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2228         return -EAGAIN;
2229 }
2230
2231 static int
2232 hns3vf_prepare_reset(struct hns3_adapter *hns)
2233 {
2234         struct hns3_hw *hw = &hns->hw;
2235         int ret = 0;
2236
2237         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2238                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2239                                         0, true, NULL, 0);
2240         }
2241         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2242
2243         return ret;
2244 }
2245
2246 static int
2247 hns3vf_stop_service(struct hns3_adapter *hns)
2248 {
2249         struct hns3_hw *hw = &hns->hw;
2250         struct rte_eth_dev *eth_dev;
2251
2252         eth_dev = &rte_eth_devices[hw->data->port_id];
2253         if (hw->adapter_state == HNS3_NIC_STARTED)
2254                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2255         hw->mac.link_status = ETH_LINK_DOWN;
2256
2257         hns3_set_rxtx_function(eth_dev);
2258         rte_wmb();
2259         /* Disable datapath on secondary process. */
2260         hns3_mp_req_stop_rxtx(eth_dev);
2261         rte_delay_ms(hw->tqps_num);
2262
2263         rte_spinlock_lock(&hw->lock);
2264         if (hw->adapter_state == HNS3_NIC_STARTED ||
2265             hw->adapter_state == HNS3_NIC_STOPPING) {
2266                 hns3vf_do_stop(hns);
2267                 hw->reset.mbuf_deferred_free = true;
2268         } else
2269                 hw->reset.mbuf_deferred_free = false;
2270
2271         /*
2272          * It is cumbersome for hardware to pick-and-choose entries for deletion
2273          * from table space. Hence, for function reset software intervention is
2274          * required to delete the entries.
2275          */
2276         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2277                 hns3vf_configure_all_mc_mac_addr(hns, true);
2278         rte_spinlock_unlock(&hw->lock);
2279
2280         return 0;
2281 }
2282
2283 static int
2284 hns3vf_start_service(struct hns3_adapter *hns)
2285 {
2286         struct hns3_hw *hw = &hns->hw;
2287         struct rte_eth_dev *eth_dev;
2288
2289         eth_dev = &rte_eth_devices[hw->data->port_id];
2290         hns3_set_rxtx_function(eth_dev);
2291         hns3_mp_req_start_rxtx(eth_dev);
2292         if (hw->adapter_state == HNS3_NIC_STARTED) {
2293                 hns3vf_service_handler(eth_dev);
2294
2295                 /* Enable interrupt of all rx queues before enabling queues */
2296                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2297                 /*
2298                  * When finished the initialization, enable queues to receive
2299                  * and transmit packets.
2300                  */
2301                 hns3_enable_all_queues(hw, true);
2302         }
2303
2304         return 0;
2305 }
2306
2307 static int
2308 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2309 {
2310         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2311         struct rte_ether_addr *hw_mac;
2312         int ret;
2313
2314         /*
2315          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2316          * on the host by "ip link set ..." command. If the hns3 PF kernel
2317          * ethdev driver sets the MAC address for VF device after the
2318          * initialization of the related VF device, the PF driver will notify
2319          * VF driver to reset VF device to make the new MAC address effective
2320          * immediately. The hns3 VF PMD driver should check whether the MAC
2321          * address has been changed by the PF kernel ethdev driver, if changed
2322          * VF driver should configure hardware using the new MAC address in the
2323          * recovering hardware configuration stage of the reset process.
2324          */
2325         ret = hns3vf_get_host_mac_addr(hw);
2326         if (ret)
2327                 return ret;
2328
2329         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2330         ret = rte_is_zero_ether_addr(hw_mac);
2331         if (ret) {
2332                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2333         } else {
2334                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2335                 if (!ret) {
2336                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2337                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2338                                               &hw->data->mac_addrs[0]);
2339                         hns3_warn(hw, "Default MAC address has been changed to:"
2340                                   " %s by the host PF kernel ethdev driver",
2341                                   mac_str);
2342                 }
2343         }
2344
2345         return 0;
2346 }
2347
2348 static int
2349 hns3vf_restore_conf(struct hns3_adapter *hns)
2350 {
2351         struct hns3_hw *hw = &hns->hw;
2352         int ret;
2353
2354         ret = hns3vf_check_default_mac_change(hw);
2355         if (ret)
2356                 return ret;
2357
2358         ret = hns3vf_configure_mac_addr(hns, false);
2359         if (ret)
2360                 return ret;
2361
2362         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2363         if (ret)
2364                 goto err_mc_mac;
2365
2366         ret = hns3vf_restore_promisc(hns);
2367         if (ret)
2368                 goto err_vlan_table;
2369
2370         ret = hns3vf_restore_vlan_conf(hns);
2371         if (ret)
2372                 goto err_vlan_table;
2373
2374         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2375         if (ret)
2376                 goto err_vlan_table;
2377
2378         ret = hns3vf_restore_rx_interrupt(hw);
2379         if (ret)
2380                 goto err_vlan_table;
2381
2382         ret = hns3_restore_gro_conf(hw);
2383         if (ret)
2384                 goto err_vlan_table;
2385
2386         if (hw->adapter_state == HNS3_NIC_STARTED) {
2387                 ret = hns3vf_do_start(hns, false);
2388                 if (ret)
2389                         goto err_vlan_table;
2390                 hns3_info(hw, "hns3vf dev restart successful!");
2391         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2392                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2393         return 0;
2394
2395 err_vlan_table:
2396         hns3vf_configure_all_mc_mac_addr(hns, true);
2397 err_mc_mac:
2398         hns3vf_configure_mac_addr(hns, true);
2399         return ret;
2400 }
2401
2402 static enum hns3_reset_level
2403 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2404 {
2405         enum hns3_reset_level reset_level;
2406
2407         /* return the highest priority reset level amongst all */
2408         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2409                 reset_level = HNS3_VF_RESET;
2410         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2411                 reset_level = HNS3_VF_FULL_RESET;
2412         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2413                 reset_level = HNS3_VF_PF_FUNC_RESET;
2414         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2415                 reset_level = HNS3_VF_FUNC_RESET;
2416         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2417                 reset_level = HNS3_FLR_RESET;
2418         else
2419                 reset_level = HNS3_NONE_RESET;
2420
2421         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2422                 return HNS3_NONE_RESET;
2423
2424         return reset_level;
2425 }
2426
2427 static void
2428 hns3vf_reset_service(void *param)
2429 {
2430         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2431         struct hns3_hw *hw = &hns->hw;
2432         enum hns3_reset_level reset_level;
2433         struct timeval tv_delta;
2434         struct timeval tv_start;
2435         struct timeval tv;
2436         uint64_t msec;
2437
2438         /*
2439          * The interrupt is not triggered within the delay time.
2440          * The interrupt may have been lost. It is necessary to handle
2441          * the interrupt to recover from the error.
2442          */
2443         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2444                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2445                 hns3_err(hw, "Handling interrupts in delayed tasks");
2446                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2447                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2448                 if (reset_level == HNS3_NONE_RESET) {
2449                         hns3_err(hw, "No reset level is set, try global reset");
2450                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2451                 }
2452         }
2453         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2454
2455         /*
2456          * Hardware reset has been notified, we now have to poll & check if
2457          * hardware has actually completed the reset sequence.
2458          */
2459         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2460         if (reset_level != HNS3_NONE_RESET) {
2461                 gettimeofday(&tv_start, NULL);
2462                 hns3_reset_process(hns, reset_level);
2463                 gettimeofday(&tv, NULL);
2464                 timersub(&tv, &tv_start, &tv_delta);
2465                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2466                        tv_delta.tv_usec / USEC_PER_MSEC;
2467                 if (msec > HNS3_RESET_PROCESS_MS)
2468                         hns3_err(hw, "%d handle long time delta %" PRIx64
2469                                  " ms time=%ld.%.6ld",
2470                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2471         }
2472 }
2473
2474 static int
2475 hns3vf_reinit_dev(struct hns3_adapter *hns)
2476 {
2477         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2478         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2479         struct hns3_hw *hw = &hns->hw;
2480         int ret;
2481
2482         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2483                 rte_intr_disable(&pci_dev->intr_handle);
2484                 hns3vf_set_bus_master(pci_dev, true);
2485         }
2486
2487         /* Firmware command initialize */
2488         ret = hns3_cmd_init(hw);
2489         if (ret) {
2490                 hns3_err(hw, "Failed to init cmd: %d", ret);
2491                 return ret;
2492         }
2493
2494         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2495                 /*
2496                  * UIO enables msix by writing the pcie configuration space
2497                  * vfio_pci enables msix in rte_intr_enable.
2498                  */
2499                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2500                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2501                         if (hns3vf_enable_msix(pci_dev, true))
2502                                 hns3_err(hw, "Failed to enable msix");
2503                 }
2504
2505                 rte_intr_enable(&pci_dev->intr_handle);
2506         }
2507
2508         ret = hns3_reset_all_queues(hns);
2509         if (ret) {
2510                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2511                 return ret;
2512         }
2513
2514         ret = hns3vf_init_hardware(hns);
2515         if (ret) {
2516                 hns3_err(hw, "Failed to init hardware: %d", ret);
2517                 return ret;
2518         }
2519
2520         return 0;
2521 }
2522
2523 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2524         .dev_start          = hns3vf_dev_start,
2525         .dev_stop           = hns3vf_dev_stop,
2526         .dev_close          = hns3vf_dev_close,
2527         .mtu_set            = hns3vf_dev_mtu_set,
2528         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2529         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2530         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2531         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2532         .stats_get          = hns3_stats_get,
2533         .stats_reset        = hns3_stats_reset,
2534         .xstats_get         = hns3_dev_xstats_get,
2535         .xstats_get_names   = hns3_dev_xstats_get_names,
2536         .xstats_reset       = hns3_dev_xstats_reset,
2537         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2538         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2539         .dev_infos_get      = hns3vf_dev_infos_get,
2540         .fw_version_get     = hns3vf_fw_version_get,
2541         .rx_queue_setup     = hns3_rx_queue_setup,
2542         .tx_queue_setup     = hns3_tx_queue_setup,
2543         .rx_queue_release   = hns3_dev_rx_queue_release,
2544         .tx_queue_release   = hns3_dev_tx_queue_release,
2545         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2546         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2547         .rxq_info_get       = hns3_rxq_info_get,
2548         .txq_info_get       = hns3_txq_info_get,
2549         .dev_configure      = hns3vf_dev_configure,
2550         .mac_addr_add       = hns3vf_add_mac_addr,
2551         .mac_addr_remove    = hns3vf_remove_mac_addr,
2552         .mac_addr_set       = hns3vf_set_default_mac_addr,
2553         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2554         .link_update        = hns3vf_dev_link_update,
2555         .rss_hash_update    = hns3_dev_rss_hash_update,
2556         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2557         .reta_update        = hns3_dev_rss_reta_update,
2558         .reta_query         = hns3_dev_rss_reta_query,
2559         .filter_ctrl        = hns3_dev_filter_ctrl,
2560         .vlan_filter_set    = hns3vf_vlan_filter_set,
2561         .vlan_offload_set   = hns3vf_vlan_offload_set,
2562         .get_reg            = hns3_get_regs,
2563         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2564 };
2565
2566 static const struct hns3_reset_ops hns3vf_reset_ops = {
2567         .reset_service       = hns3vf_reset_service,
2568         .stop_service        = hns3vf_stop_service,
2569         .prepare_reset       = hns3vf_prepare_reset,
2570         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2571         .reinit_dev          = hns3vf_reinit_dev,
2572         .restore_conf        = hns3vf_restore_conf,
2573         .start_service       = hns3vf_start_service,
2574 };
2575
2576 static int
2577 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2578 {
2579         struct hns3_adapter *hns = eth_dev->data->dev_private;
2580         struct hns3_hw *hw = &hns->hw;
2581         int ret;
2582
2583         PMD_INIT_FUNC_TRACE();
2584
2585         eth_dev->process_private = (struct hns3_process_private *)
2586             rte_zmalloc_socket("hns3_filter_list",
2587                                sizeof(struct hns3_process_private),
2588                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2589         if (eth_dev->process_private == NULL) {
2590                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2591                 return -ENOMEM;
2592         }
2593
2594         /* initialize flow filter lists */
2595         hns3_filterlist_init(eth_dev);
2596
2597         hns3_set_rxtx_function(eth_dev);
2598         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2599         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2600                 ret = hns3_mp_init_secondary();
2601                 if (ret) {
2602                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2603                                           "process, ret = %d", ret);
2604                         goto err_mp_init_secondary;
2605                 }
2606
2607                 hw->secondary_cnt++;
2608                 return 0;
2609         }
2610
2611         ret = hns3_mp_init_primary();
2612         if (ret) {
2613                 PMD_INIT_LOG(ERR,
2614                              "Failed to init for primary process, ret = %d",
2615                              ret);
2616                 goto err_mp_init_primary;
2617         }
2618
2619         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2620         hns->is_vf = true;
2621         hw->data = eth_dev->data;
2622
2623         ret = hns3_reset_init(hw);
2624         if (ret)
2625                 goto err_init_reset;
2626         hw->reset.ops = &hns3vf_reset_ops;
2627
2628         ret = hns3vf_init_vf(eth_dev);
2629         if (ret) {
2630                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2631                 goto err_init_vf;
2632         }
2633
2634         /* Allocate memory for storing MAC addresses */
2635         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2636                                                sizeof(struct rte_ether_addr) *
2637                                                HNS3_VF_UC_MACADDR_NUM, 0);
2638         if (eth_dev->data->mac_addrs == NULL) {
2639                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2640                              "to store MAC addresses",
2641                              sizeof(struct rte_ether_addr) *
2642                              HNS3_VF_UC_MACADDR_NUM);
2643                 ret = -ENOMEM;
2644                 goto err_rte_zmalloc;
2645         }
2646
2647         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2648                             &eth_dev->data->mac_addrs[0]);
2649         hw->adapter_state = HNS3_NIC_INITIALIZED;
2650         /*
2651          * Pass the information to the rte_eth_dev_close() that it should also
2652          * release the private port resources.
2653          */
2654         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2655
2656         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2657                 hns3_err(hw, "Reschedule reset service after dev_init");
2658                 hns3_schedule_reset(hns);
2659         } else {
2660                 /* IMP will wait ready flag before reset */
2661                 hns3_notify_reset_ready(hw, false);
2662         }
2663         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2664                           eth_dev);
2665         return 0;
2666
2667 err_rte_zmalloc:
2668         hns3vf_uninit_vf(eth_dev);
2669
2670 err_init_vf:
2671         rte_free(hw->reset.wait_data);
2672
2673 err_init_reset:
2674         hns3_mp_uninit_primary();
2675
2676 err_mp_init_primary:
2677 err_mp_init_secondary:
2678         eth_dev->dev_ops = NULL;
2679         eth_dev->rx_pkt_burst = NULL;
2680         eth_dev->tx_pkt_burst = NULL;
2681         eth_dev->tx_pkt_prepare = NULL;
2682         rte_free(eth_dev->process_private);
2683         eth_dev->process_private = NULL;
2684
2685         return ret;
2686 }
2687
2688 static int
2689 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2690 {
2691         struct hns3_adapter *hns = eth_dev->data->dev_private;
2692         struct hns3_hw *hw = &hns->hw;
2693
2694         PMD_INIT_FUNC_TRACE();
2695
2696         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2697                 return -EPERM;
2698
2699         eth_dev->dev_ops = NULL;
2700         eth_dev->rx_pkt_burst = NULL;
2701         eth_dev->tx_pkt_burst = NULL;
2702         eth_dev->tx_pkt_prepare = NULL;
2703
2704         if (hw->adapter_state < HNS3_NIC_CLOSING)
2705                 hns3vf_dev_close(eth_dev);
2706
2707         hw->adapter_state = HNS3_NIC_REMOVED;
2708         return 0;
2709 }
2710
2711 static int
2712 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2713                      struct rte_pci_device *pci_dev)
2714 {
2715         return rte_eth_dev_pci_generic_probe(pci_dev,
2716                                              sizeof(struct hns3_adapter),
2717                                              hns3vf_dev_init);
2718 }
2719
2720 static int
2721 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2722 {
2723         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2724 }
2725
2726 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2727         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2728         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2729         { .vendor_id = 0, /* sentinel */ },
2730 };
2731
2732 static struct rte_pci_driver rte_hns3vf_pmd = {
2733         .id_table = pci_id_hns3vf_map,
2734         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2735         .probe = eth_hns3vf_pci_probe,
2736         .remove = eth_hns3vf_pci_remove,
2737 };
2738
2739 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2740 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2741 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");