drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
  48                                    __rte_unused int wait_to_complete);
  49
  50 /* set PCI bus mastering */
  51 static int
  52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  53 {
  54         uint16_t reg;
  55         int ret;
  56
  57         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  58         if (ret < 0) {
  59                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  60                              PCI_COMMAND);
  61                 return ret;
  62         }
  63
  64         if (op)
  65                 /* set the master bit */
  66                 reg |= PCI_COMMAND_MASTER;
  67         else
  68                 reg &= ~(PCI_COMMAND_MASTER);
  69
  70         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  71 }
  72
  73 /**
  74  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  75  * @cap: the capability
  76  *
  77  * Return the address of the given capability within the PCI capability list.
  78  */
  79 static int
  80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  81 {
  82 #define MAX_PCIE_CAPABILITY 48
  83         uint16_t status;
  84         uint8_t pos;
  85         uint8_t id;
  86         int ttl;
  87         int ret;
  88
  89         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  90         if (ret < 0) {
  91                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  92                 return 0;
  93         }
  94
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 100                                   PCI_CAPABILITY_LIST);
 101         if (ret < 0) {
 102                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 103                              PCI_CAPABILITY_LIST);
 104                 return 0;
 105         }
 106
 107         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 108                 ret = rte_pci_read_config(device, &id, sizeof(id),
 109                                           (pos + PCI_CAP_LIST_ID));
 110                 if (ret < 0) {
 111                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 112                                      (pos + PCI_CAP_LIST_ID));
 113                         break;
 114                 }
 115
 116                 if (id == 0xFF)
 117                         break;
 118
 119                 if (id == cap)
 120                         return (int)pos;
 121
 122                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 123                                           (pos + PCI_CAP_LIST_NEXT));
 124                 if (ret < 0) {
 125                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 126                                      (pos + PCI_CAP_LIST_NEXT));
 127                         break;
 128                 }
 129         }
 130         return 0;
 131 }
 132
 133 static int
 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 135 {
 136         uint16_t control;
 137         int pos;
 138         int ret;
 139
 140         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 141         if (pos) {
 142                 ret = rte_pci_read_config(device, &control, sizeof(control),
 143                                     (pos + PCI_MSIX_FLAGS));
 144                 if (ret < 0) {
 145                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 146                                      (pos + PCI_MSIX_FLAGS));
 147                         return -ENXIO;
 148                 }
 149
 150                 if (op)
 151                         control |= PCI_MSIX_FLAGS_ENABLE;
 152                 else
 153                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 154                 ret = rte_pci_write_config(device, &control, sizeof(control),
 155                                           (pos + PCI_MSIX_FLAGS));
 156                 if (ret < 0) {
 157                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 158                                     (pos + PCI_MSIX_FLAGS));
 159                         return -ENXIO;
 160                 }
 161
 162                 return 0;
 163         }
 164
 165         return -ENXIO;
 166 }
 167
 168 static int
 169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 170 {
 171         /* mac address was checked by upper level interface */
 172         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 173         int ret;
 174
 175         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 176                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 177                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 178         if (ret) {
 179                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 180                                       mac_addr);
 181                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 182                          mac_str, ret);
 183         }
 184         return ret;
 185 }
 186
 187 static int
 188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 189 {
 190         /* mac address was checked by upper level interface */
 191         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 192         int ret;
 193
 194         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 195                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 196                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 197                                 false, NULL, 0);
 198         if (ret) {
 199                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 200                                       mac_addr);
 201                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 202                          mac_str, ret);
 203         }
 204         return ret;
 205 }
 206
 207 static int
 208 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 209 {
 210         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 211         int ret;
 212
 213         if (hns3_find_duplicate_mc_addr(hw, mac_addr))
 214                 return -EINVAL;
 215
 216         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 217         if (ret) {
 218                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 219                                       mac_addr);
 220                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 221                          mac_str, ret);
 222         }
 223         return ret;
 224 }
 225
 226 static int
 227 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 228                     __rte_unused uint32_t idx,
 229                     __rte_unused uint32_t pool)
 230 {
 231         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 232         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 233         int ret;
 234
 235         rte_spinlock_lock(&hw->lock);
 236
 237         /*
 238          * In hns3 network engine adding UC and MC mac address with different
 239          * commands with firmware. We need to determine whether the input
 240          * address is a UC or a MC address to call different commands.
 241          * By the way, it is recommended calling the API function named
 242          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 243          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 244          * may affect the specifications of UC mac addresses.
 245          */
 246         if (rte_is_multicast_ether_addr(mac_addr))
 247                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 248         else
 249                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 250
 251         rte_spinlock_unlock(&hw->lock);
 252         if (ret) {
 253                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 254                                       mac_addr);
 255                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 256                          ret);
 257         }
 258
 259         return ret;
 260 }
 261
 262 static void
 263 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 264 {
 265         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 266         /* index will be checked by upper level rte interface */
 267         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 268         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 269         int ret;
 270
 271         rte_spinlock_lock(&hw->lock);
 272
 273         if (rte_is_multicast_ether_addr(mac_addr))
 274                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 275         else
 276                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 277
 278         rte_spinlock_unlock(&hw->lock);
 279         if (ret) {
 280                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 281                                       mac_addr);
 282                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 283                          mac_str, ret);
 284         }
 285 }
 286
 287 static int
 288 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 289                             struct rte_ether_addr *mac_addr)
 290 {
 291 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 292         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 293         struct rte_ether_addr *old_addr;
 294         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 295         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 296         int ret;
 297
 298         /*
 299          * It has been guaranteed that input parameter named mac_addr is valid
 300          * address in the rte layer of DPDK framework.
 301          */
 302         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 303         rte_spinlock_lock(&hw->lock);
 304         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 305         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 306                RTE_ETHER_ADDR_LEN);
 307
 308         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 309                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 310                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 311         if (ret) {
 312                 /*
 313                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 314                  * driver. When user has configured a MAC address for VF device
 315                  * by "ip link set ..." command based on the PF device, the hns3
 316                  * PF kernel ethdev driver does not allow VF driver to request
 317                  * reconfiguring a different default MAC address, and return
 318                  * -EPREM to VF driver through mailbox.
 319                  */
 320                 if (ret == -EPERM) {
 321                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 322                                               old_addr);
 323                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 324                                   mac_str);
 325                 } else {
 326                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 327                                               mac_addr);
 328                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 329                                  mac_str, ret);
 330                 }
 331         }
 332
 333         rte_ether_addr_copy(mac_addr,
 334                             (struct rte_ether_addr *)hw->mac.mac_addr);
 335         rte_spinlock_unlock(&hw->lock);
 336
 337         return ret;
 338 }
 339
 340 static int
 341 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 342 {
 343         struct hns3_hw *hw = &hns->hw;
 344         struct rte_ether_addr *addr;
 345         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 346         int err = 0;
 347         int ret;
 348         int i;
 349
 350         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 351                 addr = &hw->data->mac_addrs[i];
 352                 if (rte_is_zero_ether_addr(addr))
 353                         continue;
 354                 if (rte_is_multicast_ether_addr(addr))
 355                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 356                               hns3vf_add_mc_mac_addr(hw, addr);
 357                 else
 358                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 359                               hns3vf_add_uc_mac_addr(hw, addr);
 360
 361                 if (ret) {
 362                         err = ret;
 363                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 364                                               addr);
 365                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 366                                  "ret = %d.", del ? "remove" : "restore",
 367                                  mac_str, i, ret);
 368                 }
 369         }
 370         return err;
 371 }
 372
 373 static int
 374 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 375                        struct rte_ether_addr *mac_addr)
 376 {
 377         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 378         int ret;
 379
 380         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 381                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 382                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 383                                 NULL, 0);
 384         if (ret) {
 385                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 386                                       mac_addr);
 387                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 388                          mac_str, ret);
 389         }
 390
 391         return ret;
 392 }
 393
 394 static int
 395 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 396                           struct rte_ether_addr *mac_addr)
 397 {
 398         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 399         int ret;
 400
 401         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 402                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 403                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 404                                 NULL, 0);
 405         if (ret) {
 406                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 407                                       mac_addr);
 408                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 409                          mac_str, ret);
 410         }
 411
 412         return ret;
 413 }
 414
 415 static int
 416 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 417                              struct rte_ether_addr *mc_addr_set,
 418                              uint32_t nb_mc_addr)
 419 {
 420         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 421         struct rte_ether_addr *addr;
 422         uint32_t i;
 423         uint32_t j;
 424
 425         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 426                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
 427                          "invalid. valid range: 0~%d",
 428                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 429                 return -EINVAL;
 430         }
 431
 432         /* Check if input mac addresses are valid */
 433         for (i = 0; i < nb_mc_addr; i++) {
 434                 addr = &mc_addr_set[i];
 435                 if (!rte_is_multicast_ether_addr(addr)) {
 436                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 437                                               addr);
 438                         hns3_err(hw,
 439                                  "failed to set mc mac addr, addr(%s) invalid.",
 440                                  mac_str);
 441                         return -EINVAL;
 442                 }
 443
 444                 /* Check if there are duplicate addresses */
 445                 for (j = i + 1; j < nb_mc_addr; j++) {
 446                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 447                                 hns3_ether_format_addr(mac_str,
 448                                                       RTE_ETHER_ADDR_FMT_SIZE,
 449                                                       addr);
 450                                 hns3_err(hw, "failed to set mc mac addr, "
 451                                          "addrs invalid. two same addrs(%s).",
 452                                          mac_str);
 453                                 return -EINVAL;
 454                         }
 455                 }
 456
 457                 /*
 458                  * Check if there are duplicate addresses between mac_addrs
 459                  * and mc_addr_set
 460                  */
 461                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 462                         if (rte_is_same_ether_addr(addr,
 463                                                    &hw->data->mac_addrs[j])) {
 464                                 hns3_ether_format_addr(mac_str,
 465                                                       RTE_ETHER_ADDR_FMT_SIZE,
 466                                                       addr);
 467                                 hns3_err(hw, "failed to set mc mac addr, "
 468                                          "addrs invalid. addrs(%s) has already "
 469                                          "configured in mac_addr add API",
 470                                          mac_str);
 471                                 return -EINVAL;
 472                         }
 473                 }
 474         }
 475
 476         return 0;
 477 }
 478
 479 static int
 480 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 481                             struct rte_ether_addr *mc_addr_set,
 482                             uint32_t nb_mc_addr)
 483 {
 484         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 485         struct rte_ether_addr *addr;
 486         int cur_addr_num;
 487         int set_addr_num;
 488         int num;
 489         int ret;
 490         int i;
 491
 492         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 493         if (ret)
 494                 return ret;
 495
 496         rte_spinlock_lock(&hw->lock);
 497         cur_addr_num = hw->mc_addrs_num;
 498         for (i = 0; i < cur_addr_num; i++) {
 499                 num = cur_addr_num - i - 1;
 500                 addr = &hw->mc_addrs[num];
 501                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 502                 if (ret) {
 503                         rte_spinlock_unlock(&hw->lock);
 504                         return ret;
 505                 }
 506
 507                 hw->mc_addrs_num--;
 508         }
 509
 510         set_addr_num = (int)nb_mc_addr;
 511         for (i = 0; i < set_addr_num; i++) {
 512                 addr = &mc_addr_set[i];
 513                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 514                 if (ret) {
 515                         rte_spinlock_unlock(&hw->lock);
 516                         return ret;
 517                 }
 518
 519                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 520                 hw->mc_addrs_num++;
 521         }
 522         rte_spinlock_unlock(&hw->lock);
 523
 524         return 0;
 525 }
 526
 527 static int
 528 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 529 {
 530         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 531         struct hns3_hw *hw = &hns->hw;
 532         struct rte_ether_addr *addr;
 533         int err = 0;
 534         int ret;
 535         int i;
 536
 537         for (i = 0; i < hw->mc_addrs_num; i++) {
 538                 addr = &hw->mc_addrs[i];
 539                 if (!rte_is_multicast_ether_addr(addr))
 540                         continue;
 541                 if (del)
 542                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 543                 else
 544                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 545                 if (ret) {
 546                         err = ret;
 547                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 548                                               addr);
 549                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 550                                  del ? "Remove" : "Restore", mac_str, ret);
 551                 }
 552         }
 553         return err;
 554 }
 555
 556 static int
 557 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 558                         bool en_uc_pmc, bool en_mc_pmc)
 559 {
 560         struct hns3_mbx_vf_to_pf_cmd *req;
 561         struct hns3_cmd_desc desc;
 562         int ret;
 563
 564         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 565
 566         /*
 567          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 568          * so there are some features for promiscuous/allmulticast mode in hns3
 569          * VF PMD driver as below:
 570          * 1. The promiscuous/allmulticast mode can be configured successfully
 571          *    only based on the trusted VF device. If based on the non trusted
 572          *    VF device, configuring promiscuous/allmulticast mode will fail.
 573          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 574          *    kernel ethdev driver on the host by the following command:
 575          *      "ip link set <eth num> vf <vf id> turst on"
 576          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 577          *    driver can receive the ingress and outgoing traffic. In the words,
 578          *    all the ingress packets, all the packets sent from the PF and
 579          *    other VFs on the same physical port.
 580          * 3. Note: Because of the hardware constraints, By default vlan filter
 581          *    is enabled and couldn't be turned off based on VF device, so vlan
 582          *    filter is still effective even in promiscuous mode. If upper
 583          *    applications don't call rte_eth_dev_vlan_filter API function to
 584          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 585          *    the packets with vlan tag in promiscuoue mode.
 586          */
 587         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 588         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 589         req->msg[1] = en_bc_pmc ? 1 : 0;
 590         req->msg[2] = en_uc_pmc ? 1 : 0;
 591         req->msg[3] = en_mc_pmc ? 1 : 0;
 592         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 593
 594         ret = hns3_cmd_send(hw, &desc, 1);
 595         if (ret)
 596                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 597
 598         return ret;
 599 }
 600
 601 static int
 602 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 603 {
 604         struct hns3_adapter *hns = dev->data->dev_private;
 605         struct hns3_hw *hw = &hns->hw;
 606         int ret;
 607
 608         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 609         if (ret)
 610                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 611                         ret);
 612         return ret;
 613 }
 614
 615 static int
 616 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 617 {
 618         bool allmulti = dev->data->all_multicast ? true : false;
 619         struct hns3_adapter *hns = dev->data->dev_private;
 620         struct hns3_hw *hw = &hns->hw;
 621         int ret;
 622
 623         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 624         if (ret)
 625                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 626                         ret);
 627         return ret;
 628 }
 629
 630 static int
 631 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 632 {
 633         struct hns3_adapter *hns = dev->data->dev_private;
 634         struct hns3_hw *hw = &hns->hw;
 635         int ret;
 636
 637         if (dev->data->promiscuous)
 638                 return 0;
 639
 640         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 641         if (ret)
 642                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 643                         ret);
 644         return ret;
 645 }
 646
 647 static int
 648 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 649 {
 650         struct hns3_adapter *hns = dev->data->dev_private;
 651         struct hns3_hw *hw = &hns->hw;
 652         int ret;
 653
 654         if (dev->data->promiscuous)
 655                 return 0;
 656
 657         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 658         if (ret)
 659                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 660                         ret);
 661         return ret;
 662 }
 663
 664 static int
 665 hns3vf_restore_promisc(struct hns3_adapter *hns)
 666 {
 667         struct hns3_hw *hw = &hns->hw;
 668         bool allmulti = hw->data->all_multicast ? true : false;
 669
 670         if (hw->data->promiscuous)
 671                 return hns3vf_set_promisc_mode(hw, true, true, true);
 672
 673         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 674 }
 675
 676 static int
 677 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 678                              bool mmap, enum hns3_ring_type queue_type,
 679                              uint16_t queue_id)
 680 {
 681         struct hns3_vf_bind_vector_msg bind_msg;
 682         const char *op_str;
 683         uint16_t code;
 684         int ret;
 685
 686         memset(&bind_msg, 0, sizeof(bind_msg));
 687         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 688                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 689         bind_msg.vector_id = vector_id;
 690
 691         if (queue_type == HNS3_RING_TYPE_RX)
 692                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 693         else
 694                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 695
 696         bind_msg.param[0].ring_type = queue_type;
 697         bind_msg.ring_num = 1;
 698         bind_msg.param[0].tqp_index = queue_id;
 699         op_str = mmap ? "Map" : "Unmap";
 700         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 701                                 sizeof(bind_msg), false, NULL, 0);
 702         if (ret)
 703                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 704                          op_str, queue_id, bind_msg.vector_id, ret);
 705
 706         return ret;
 707 }
 708
 709 static int
 710 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 711 {
 712         uint16_t vec;
 713         int ret;
 714         int i;
 715
 716         /*
 717          * In hns3 network engine, vector 0 is always the misc interrupt of this
 718          * function, vector 1~N can be used respectively for the queues of the
 719          * function. Tx and Rx queues with the same number share the interrupt
 720          * vector. In the initialization clearing the all hardware mapping
 721          * relationship configurations between queues and interrupt vectors is
 722          * needed, so some error caused by the residual configurations, such as
 723          * the unexpected Tx interrupt, can be avoid.
 724          */
 725         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 726         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 727                 vec = vec - 1; /* the last interrupt is reserved */
 728         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 729         for (i = 0; i < hw->intr_tqps_num; i++) {
 730                 /*
 731                  * Set gap limiter/rate limiter/quanity limiter algorithm
 732                  * configuration for interrupt coalesce of queue's interrupt.
 733                  */
 734                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 735                                        HNS3_TQP_INTR_GL_DEFAULT);
 736                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 737                                        HNS3_TQP_INTR_GL_DEFAULT);
 738                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 739                 /*
 740                  * QL(quantity limiter) is not used currently, just set 0 to
 741                  * close it.
 742                  */
 743                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 744
 745                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 746                                                    HNS3_RING_TYPE_TX, i);
 747                 if (ret) {
 748                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 749                                           "vector: %u, ret=%d", i, vec, ret);
 750                         return ret;
 751                 }
 752
 753                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 754                                                    HNS3_RING_TYPE_RX, i);
 755                 if (ret) {
 756                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 757                                           "vector: %u, ret=%d", i, vec, ret);
 758                         return ret;
 759                 }
 760         }
 761
 762         return 0;
 763 }
 764
 765 static int
 766 hns3vf_dev_configure(struct rte_eth_dev *dev)
 767 {
 768         struct hns3_adapter *hns = dev->data->dev_private;
 769         struct hns3_hw *hw = &hns->hw;
 770         struct rte_eth_conf *conf = &dev->data->dev_conf;
 771         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 772         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 773         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 774         struct rte_eth_rss_conf rss_conf;
 775         bool gro_en;
 776         int ret;
 777
 778         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 779
 780         /*
 781          * Some versions of hardware network engine does not support
 782          * individually enable/disable/reset the Tx or Rx queue. These devices
 783          * must enable/disable/reset Tx and Rx queues at the same time. When the
 784          * numbers of Tx queues allocated by upper applications are not equal to
 785          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 786          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 787          * work as usual. But these fake queues are imperceptible, and can not
 788          * be used by upper applications.
 789          */
 790         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 791         if (ret) {
 792                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
 793                 hw->cfg_max_queues = 0;
 794                 return ret;
 795         }
 796
 797         hw->adapter_state = HNS3_NIC_CONFIGURING;
 798         if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
 799                 hns3_err(hw, "setting link speed/duplex not supported");
 800                 ret = -EINVAL;
 801                 goto cfg_err;
 802         }
 803
 804         /* When RSS is not configured, redirect the packet queue 0 */
 805         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
 806                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
 807                 hw->rss_dis_flag = false;
 808                 rss_conf = conf->rx_adv_conf.rss_conf;
 809                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 810                 if (ret)
 811                         goto cfg_err;
 812         }
 813
 814         ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
 815         if (ret != 0)
 816                 goto cfg_err;
 817
 818         ret = hns3vf_dev_configure_vlan(dev);
 819         if (ret)
 820                 goto cfg_err;
 821
 822         /* config hardware GRO */
 823         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
 824         ret = hns3_config_gro(hw, gro_en);
 825         if (ret)
 826                 goto cfg_err;
 827
 828         hns3_init_rx_ptype_tble(dev);
 829
 830         hw->adapter_state = HNS3_NIC_CONFIGURED;
 831         return 0;
 832
 833 cfg_err:
 834         hw->cfg_max_queues = 0;
 835         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 836         hw->adapter_state = HNS3_NIC_INITIALIZED;
 837
 838         return ret;
 839 }
 840
 841 static int
 842 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 843 {
 844         int ret;
 845
 846         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 847                                 sizeof(mtu), true, NULL, 0);
 848         if (ret)
 849                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 850
 851         return ret;
 852 }
 853
 854 static int
 855 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 856 {
 857         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 858         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 859         int ret;
 860
 861         /*
 862          * The hns3 PF/VF devices on the same port share the hardware MTU
 863          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 864          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 865          * driver, there is no need to stop the port for hns3 VF device, and the
 866          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 867          * PF's MTU.
 868          */
 869         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 870                 hns3_err(hw, "Failed to set mtu during resetting");
 871                 return -EIO;
 872         }
 873
 874         /*
 875          * when Rx of scattered packets is off, we have some possibility of
 876          * using vector Rx process function or simple Rx functions in hns3 PMD
 877          * driver. If the input MTU is increased and the maximum length of
 878          * received packets is greater than the length of a buffer for Rx
 879          * packet, the hardware network engine needs to use multiple BDs and
 880          * buffers to store these packets. This will cause problems when still
 881          * using vector Rx process function or simple Rx function to receiving
 882          * packets. So, when Rx of scattered packets is off and device is
 883          * started, it is not permitted to increase MTU so that the maximum
 884          * length of Rx packets is greater than Rx buffer length.
 885          */
 886         if (dev->data->dev_started && !dev->data->scattered_rx &&
 887             frame_size > hw->rx_buf_len) {
 888                 hns3_err(hw, "failed to set mtu because current is "
 889                         "not scattered rx mode");
 890                 return -EOPNOTSUPP;
 891         }
 892
 893         rte_spinlock_lock(&hw->lock);
 894         ret = hns3vf_config_mtu(hw, mtu);
 895         if (ret) {
 896                 rte_spinlock_unlock(&hw->lock);
 897                 return ret;
 898         }
 899         rte_spinlock_unlock(&hw->lock);
 900
 901         return 0;
 902 }
 903
 904 static int
 905 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 906 {
 907         struct hns3_adapter *hns = eth_dev->data->dev_private;
 908         struct hns3_hw *hw = &hns->hw;
 909         uint16_t q_num = hw->tqps_num;
 910
 911         /*
 912          * In interrupt mode, 'max_rx_queues' is set based on the number of
 913          * MSI-X interrupt resources of the hardware.
 914          */
 915         if (hw->data->dev_conf.intr_conf.rxq == 1)
 916                 q_num = hw->intr_tqps_num;
 917
 918         info->max_rx_queues = q_num;
 919         info->max_tx_queues = hw->tqps_num;
 920         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 921         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 922         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 923         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 924         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 925
 926         info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
 927                                  RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
 928                                  RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
 929                                  RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
 930                                  RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 931                                  RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
 932                                  RTE_ETH_RX_OFFLOAD_SCATTER |
 933                                  RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
 934                                  RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
 935                                  RTE_ETH_RX_OFFLOAD_RSS_HASH |
 936                                  RTE_ETH_RX_OFFLOAD_TCP_LRO);
 937         info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 938                                  RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
 939                                  RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
 940                                  RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
 941                                  RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
 942                                  RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
 943                                  RTE_ETH_TX_OFFLOAD_TCP_TSO |
 944                                  RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
 945                                  RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
 946                                  RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
 947                                  RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
 948                                  hns3_txvlan_cap_get(hw));
 949
 950         if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
 951                 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
 952
 953         if (hns3_dev_get_support(hw, INDEP_TXRX))
 954                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 955                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 956
 957         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 958                 .nb_max = HNS3_MAX_RING_DESC,
 959                 .nb_min = HNS3_MIN_RING_DESC,
 960                 .nb_align = HNS3_ALIGN_RING_DESC,
 961         };
 962
 963         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 964                 .nb_max = HNS3_MAX_RING_DESC,
 965                 .nb_min = HNS3_MIN_RING_DESC,
 966                 .nb_align = HNS3_ALIGN_RING_DESC,
 967                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 968                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
 969         };
 970
 971         info->default_rxconf = (struct rte_eth_rxconf) {
 972                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 973                 /*
 974                  * If there are no available Rx buffer descriptors, incoming
 975                  * packets are always dropped by hardware based on hns3 network
 976                  * engine.
 977                  */
 978                 .rx_drop_en = 1,
 979                 .offloads = 0,
 980         };
 981         info->default_txconf = (struct rte_eth_txconf) {
 982                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 983                 .offloads = 0,
 984         };
 985
 986         info->reta_size = hw->rss_ind_tbl_size;
 987         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 988         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 989
 990         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 991         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 992         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 993         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 994         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 995         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 996
 997         return 0;
 998 }
 999
1000 static void
1001 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1002 {
1003         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1004 }
1005
1006 static void
1007 hns3vf_disable_irq0(struct hns3_hw *hw)
1008 {
1009         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1010 }
1011
1012 static void
1013 hns3vf_enable_irq0(struct hns3_hw *hw)
1014 {
1015         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1016 }
1017
1018 static enum hns3vf_evt_cause
1019 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1020 {
1021         struct hns3_hw *hw = &hns->hw;
1022         enum hns3vf_evt_cause ret;
1023         uint32_t cmdq_stat_reg;
1024         uint32_t rst_ing_reg;
1025         uint32_t val;
1026
1027         /* Fetch the events from their corresponding regs */
1028         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1029         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1030                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1031                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1032                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1033                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
1034                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1035                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1036                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1037                 if (clearval) {
1038                         hw->reset.stats.global_cnt++;
1039                         hns3_warn(hw, "Global reset detected, clear reset status");
1040                 } else {
1041                         hns3_schedule_delayed_reset(hns);
1042                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1043                 }
1044
1045                 ret = HNS3VF_VECTOR0_EVENT_RST;
1046                 goto out;
1047         }
1048
1049         /* Check for vector0 mailbox(=CMDQ RX) event source */
1050         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1051                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1052                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1053                 goto out;
1054         }
1055
1056         val = 0;
1057         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1058 out:
1059         if (clearval)
1060                 *clearval = val;
1061         return ret;
1062 }
1063
1064 static void
1065 hns3vf_interrupt_handler(void *param)
1066 {
1067         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1068         struct hns3_adapter *hns = dev->data->dev_private;
1069         struct hns3_hw *hw = &hns->hw;
1070         enum hns3vf_evt_cause event_cause;
1071         uint32_t clearval;
1072
1073         /* Disable interrupt */
1074         hns3vf_disable_irq0(hw);
1075
1076         /* Read out interrupt causes */
1077         event_cause = hns3vf_check_event_cause(hns, &clearval);
1078         /* Clear interrupt causes */
1079         hns3vf_clear_event_cause(hw, clearval);
1080
1081         switch (event_cause) {
1082         case HNS3VF_VECTOR0_EVENT_RST:
1083                 hns3_schedule_reset(hns);
1084                 break;
1085         case HNS3VF_VECTOR0_EVENT_MBX:
1086                 hns3_dev_handle_mbx_msg(hw);
1087                 break;
1088         default:
1089                 break;
1090         }
1091
1092         /* Enable interrupt */
1093         hns3vf_enable_irq0(hw);
1094 }
1095
1096 static void
1097 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1098 {
1099         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1100         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1101         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1102         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1103 }
1104
1105 static void
1106 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1107 {
1108         struct hns3_dev_specs_0_cmd *req0;
1109
1110         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1111
1112         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1113         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1114         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1115         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1116 }
1117
1118 static int
1119 hns3vf_check_dev_specifications(struct hns3_hw *hw)
1120 {
1121         if (hw->rss_ind_tbl_size == 0 ||
1122             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
1123                 hns3_warn(hw, "the size of hash lookup table configured (%u)"
1124                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
1125                               HNS3_RSS_IND_TBL_SIZE_MAX);
1126                 return -EINVAL;
1127         }
1128
1129         return 0;
1130 }
1131
1132 static int
1133 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1134 {
1135         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1136         int ret;
1137         int i;
1138
1139         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1140                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1141                                           true);
1142                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1143         }
1144         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1145
1146         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1147         if (ret)
1148                 return ret;
1149
1150         hns3vf_parse_dev_specifications(hw, desc);
1151
1152         return hns3vf_check_dev_specifications(hw);
1153 }
1154
1155 void
1156 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
1157 {
1158         uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
1159                                    HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1160         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1161         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1162
1163         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1164                 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1165                                           __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1166 }
1167
1168 static void
1169 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
1170 {
1171 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS      500
1172
1173         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1174         int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
1175         uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1176         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1177         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1178
1179         __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
1180                          __ATOMIC_RELEASE);
1181
1182         (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1183                                 NULL, 0);
1184
1185         while (remain_ms > 0) {
1186                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
1187                 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
1188                         HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1189                         break;
1190                 remain_ms--;
1191         }
1192
1193         /*
1194          * When exit above loop, the pf_push_lsc_cap could be one of the three
1195          * state: unknown (means pf not ack), not_supported, supported.
1196          * Here config it as 'not_supported' when it's 'unknown' state.
1197          */
1198         __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1199                                   __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1200
1201         if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
1202                 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
1203                 hns3_info(hw, "detect PF support push link status change!");
1204         } else {
1205                 /*
1206                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
1207                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
1208                  * the RTE_ETH_DEV_INTR_LSC capability.
1209                  */
1210                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1211         }
1212 }
1213
1214 static int
1215 hns3vf_get_capability(struct hns3_hw *hw)
1216 {
1217         struct rte_pci_device *pci_dev;
1218         struct rte_eth_dev *eth_dev;
1219         uint8_t revision;
1220         int ret;
1221
1222         eth_dev = &rte_eth_devices[hw->data->port_id];
1223         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1224
1225         /* Get PCI revision id */
1226         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1227                                   HNS3_PCI_REVISION_ID);
1228         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1229                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1230                              ret);
1231                 return -EIO;
1232         }
1233         hw->revision = revision;
1234
1235         if (revision < PCI_REVISION_ID_HIP09_A) {
1236                 hns3vf_set_default_dev_specifications(hw);
1237                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1238                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1239                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1240                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
1241                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1242                 hw->rss_info.ipv6_sctp_offload_supported = false;
1243                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1244                 return 0;
1245         }
1246
1247         ret = hns3vf_query_dev_specifications(hw);
1248         if (ret) {
1249                 PMD_INIT_LOG(ERR,
1250                              "failed to query dev specifications, ret = %d",
1251                              ret);
1252                 return ret;
1253         }
1254
1255         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1256         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1257         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1258         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1259         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1260         hw->rss_info.ipv6_sctp_offload_supported = true;
1261         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1262
1263         return 0;
1264 }
1265
1266 static int
1267 hns3vf_check_tqp_info(struct hns3_hw *hw)
1268 {
1269         if (hw->tqps_num == 0) {
1270                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1271                 return -EINVAL;
1272         }
1273
1274         if (hw->rss_size_max == 0) {
1275                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1276                 return -EINVAL;
1277         }
1278
1279         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1280
1281         return 0;
1282 }
1283
1284 static int
1285 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1286 {
1287         uint8_t resp_msg;
1288         int ret;
1289
1290         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1291                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1292                                 true, &resp_msg, sizeof(resp_msg));
1293         if (ret) {
1294                 if (ret == -ETIME) {
1295                         /*
1296                          * Getting current port based VLAN state from PF driver
1297                          * will not affect VF driver's basic function. Because
1298                          * the VF driver relies on hns3 PF kernel ether driver,
1299                          * to avoid introducing compatibility issues with older
1300                          * version of PF driver, no failure will be returned
1301                          * when the return value is ETIME. This return value has
1302                          * the following scenarios:
1303                          * 1) Firmware didn't return the results in time
1304                          * 2) the result return by firmware is timeout
1305                          * 3) the older version of kernel side PF driver does
1306                          *    not support this mailbox message.
1307                          * For scenarios 1 and 2, it is most likely that a
1308                          * hardware error has occurred, or a hardware reset has
1309                          * occurred. In this case, these errors will be caught
1310                          * by other functions.
1311                          */
1312                         PMD_INIT_LOG(WARNING,
1313                                 "failed to get PVID state for timeout, maybe "
1314                                 "kernel side PF driver doesn't support this "
1315                                 "mailbox message, or firmware didn't respond.");
1316                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1317                 } else {
1318                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1319                                 " ret = %d", ret);
1320                         return ret;
1321                 }
1322         }
1323         hw->port_base_vlan_cfg.state = resp_msg ?
1324                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1325         return 0;
1326 }
1327
1328 static int
1329 hns3vf_get_queue_info(struct hns3_hw *hw)
1330 {
1331 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1332         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1333         int ret;
1334
1335         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1336                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1337         if (ret) {
1338                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1339                 return ret;
1340         }
1341
1342         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1343         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1344
1345         return hns3vf_check_tqp_info(hw);
1346 }
1347
1348 static int
1349 hns3vf_get_queue_depth(struct hns3_hw *hw)
1350 {
1351 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1352         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1353         int ret;
1354
1355         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1356                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1357         if (ret) {
1358                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1359                              ret);
1360                 return ret;
1361         }
1362
1363         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1364         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1365
1366         return 0;
1367 }
1368
1369 static void
1370 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1371 {
1372         if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1373                 hns3_set_bit(hw->capability,
1374                                 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1375 }
1376
1377 static int
1378 hns3vf_get_num_tc(struct hns3_hw *hw)
1379 {
1380         uint8_t num_tc = 0;
1381         uint32_t i;
1382
1383         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1384                 if (hw->hw_tc_map & BIT(i))
1385                         num_tc++;
1386         }
1387         return num_tc;
1388 }
1389
1390 static int
1391 hns3vf_get_basic_info(struct hns3_hw *hw)
1392 {
1393         uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1394         struct hns3_basic_info *basic_info;
1395         int ret;
1396
1397         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1398                                 true, resp_msg, sizeof(resp_msg));
1399         if (ret) {
1400                 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1401                                 ret);
1402                 return ret;
1403         }
1404
1405         basic_info = (struct hns3_basic_info *)resp_msg;
1406         hw->hw_tc_map = basic_info->hw_tc_map;
1407         hw->num_tc = hns3vf_get_num_tc(hw);
1408         hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1409         hns3vf_update_caps(hw, basic_info->caps);
1410
1411         return 0;
1412 }
1413
1414 static int
1415 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1416 {
1417         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1418         int ret;
1419
1420         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1421                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1422         if (ret) {
1423                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1424                 return ret;
1425         }
1426
1427         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1428
1429         return 0;
1430 }
1431
1432 static int
1433 hns3vf_get_configuration(struct hns3_hw *hw)
1434 {
1435         int ret;
1436
1437         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1438         hw->rss_dis_flag = false;
1439
1440         /* Get device capability */
1441         ret = hns3vf_get_capability(hw);
1442         if (ret) {
1443                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1444                 return ret;
1445         }
1446
1447         hns3vf_get_push_lsc_cap(hw);
1448
1449         /* Get basic info from PF */
1450         ret = hns3vf_get_basic_info(hw);
1451         if (ret)
1452                 return ret;
1453
1454         /* Get queue configuration from PF */
1455         ret = hns3vf_get_queue_info(hw);
1456         if (ret)
1457                 return ret;
1458
1459         /* Get queue depth info from PF */
1460         ret = hns3vf_get_queue_depth(hw);
1461         if (ret)
1462                 return ret;
1463
1464         /* Get user defined VF MAC addr from PF */
1465         ret = hns3vf_get_host_mac_addr(hw);
1466         if (ret)
1467                 return ret;
1468
1469         return hns3vf_get_port_base_vlan_filter_state(hw);
1470 }
1471
1472 static int
1473 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1474                             uint16_t nb_tx_q)
1475 {
1476         struct hns3_hw *hw = &hns->hw;
1477
1478         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1479 }
1480
1481 static void
1482 hns3vf_request_link_info(struct hns3_hw *hw)
1483 {
1484         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1485         bool send_req;
1486         int ret;
1487
1488         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1489                 return;
1490
1491         send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1492                    vf->req_link_info_cnt > 0;
1493         if (!send_req)
1494                 return;
1495
1496         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1497                                 NULL, 0);
1498         if (ret) {
1499                 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1500                 return;
1501         }
1502
1503         if (vf->req_link_info_cnt > 0)
1504                 vf->req_link_info_cnt--;
1505 }
1506
1507 void
1508 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1509                           uint32_t link_speed, uint8_t link_duplex)
1510 {
1511         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1512         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1513         struct hns3_mac *mac = &hw->mac;
1514         int ret;
1515
1516         /*
1517          * PF kernel driver may push link status when VF driver is in resetting,
1518          * driver will stop polling job in this case, after resetting done
1519          * driver will start polling job again.
1520          * When polling job started, driver will get initial link status by
1521          * sending request to PF kernel driver, then could update link status by
1522          * process PF kernel driver's link status mailbox message.
1523          */
1524         if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1525                 return;
1526
1527         if (hw->adapter_state != HNS3_NIC_STARTED)
1528                 return;
1529
1530         mac->link_status = link_status;
1531         mac->link_speed = link_speed;
1532         mac->link_duplex = link_duplex;
1533         ret = hns3vf_dev_link_update(dev, 0);
1534         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1535                 hns3_start_report_lse(dev);
1536 }
1537
1538 static int
1539 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1540 {
1541 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1542         struct hns3_hw *hw = &hns->hw;
1543         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1544         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1545         uint8_t is_kill = on ? 0 : 1;
1546
1547         msg_data[0] = is_kill;
1548         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1549         memcpy(&msg_data[3], &proto, sizeof(proto));
1550
1551         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1552                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1553                                  0);
1554 }
1555
1556 static int
1557 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1558 {
1559         struct hns3_adapter *hns = dev->data->dev_private;
1560         struct hns3_hw *hw = &hns->hw;
1561         int ret;
1562
1563         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1564                 hns3_err(hw,
1565                          "vf set vlan id failed during resetting, vlan_id =%u",
1566                          vlan_id);
1567                 return -EIO;
1568         }
1569         rte_spinlock_lock(&hw->lock);
1570         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1571         rte_spinlock_unlock(&hw->lock);
1572         if (ret)
1573                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1574                          vlan_id, ret);
1575
1576         return ret;
1577 }
1578
1579 static int
1580 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1581 {
1582         uint8_t msg_data;
1583         int ret;
1584
1585         if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1586                 return 0;
1587
1588         msg_data = enable ? 1 : 0;
1589         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1590                         HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1591                         sizeof(msg_data), true, NULL, 0);
1592         if (ret)
1593                 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1594                                 enable ? "enable" : "disable", ret);
1595
1596         return ret;
1597 }
1598
1599 static int
1600 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1601 {
1602         uint8_t msg_data;
1603         int ret;
1604
1605         msg_data = enable ? 1 : 0;
1606         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1607                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1608         if (ret)
1609                 hns3_err(hw, "vf %s strip failed, ret = %d.",
1610                                 enable ? "enable" : "disable", ret);
1611
1612         return ret;
1613 }
1614
1615 static int
1616 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1617 {
1618         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1619         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1620         unsigned int tmp_mask;
1621         int ret = 0;
1622
1623         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1624                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1625                              "mask = 0x%x", mask);
1626                 return -EIO;
1627         }
1628
1629         tmp_mask = (unsigned int)mask;
1630
1631         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
1632                 rte_spinlock_lock(&hw->lock);
1633                 /* Enable or disable VLAN filter */
1634                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1635                         ret = hns3vf_en_vlan_filter(hw, true);
1636                 else
1637                         ret = hns3vf_en_vlan_filter(hw, false);
1638                 rte_spinlock_unlock(&hw->lock);
1639                 if (ret)
1640                         return ret;
1641         }
1642
1643         /* Vlan stripping setting */
1644         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
1645                 rte_spinlock_lock(&hw->lock);
1646                 /* Enable or disable VLAN stripping */
1647                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1648                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1649                 else
1650                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1651                 rte_spinlock_unlock(&hw->lock);
1652         }
1653
1654         return ret;
1655 }
1656
1657 static int
1658 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1659 {
1660         struct rte_vlan_filter_conf *vfc;
1661         struct hns3_hw *hw = &hns->hw;
1662         uint16_t vlan_id;
1663         uint64_t vbit;
1664         uint64_t ids;
1665         int ret = 0;
1666         uint32_t i;
1667
1668         vfc = &hw->data->vlan_filter_conf;
1669         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1670                 if (vfc->ids[i] == 0)
1671                         continue;
1672                 ids = vfc->ids[i];
1673                 while (ids) {
1674                         /*
1675                          * 64 means the num bits of ids, one bit corresponds to
1676                          * one vlan id
1677                          */
1678                         vlan_id = 64 * i;
1679                         /* count trailing zeroes */
1680                         vbit = ~ids & (ids - 1);
1681                         /* clear least significant bit set */
1682                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1683                         for (; vbit;) {
1684                                 vbit >>= 1;
1685                                 vlan_id++;
1686                         }
1687                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1688                         if (ret) {
1689                                 hns3_err(hw,
1690                                          "VF handle vlan table failed, ret =%d, on = %d",
1691                                          ret, on);
1692                                 return ret;
1693                         }
1694                 }
1695         }
1696
1697         return ret;
1698 }
1699
1700 static int
1701 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1702 {
1703         return hns3vf_handle_all_vlan_table(hns, 0);
1704 }
1705
1706 static int
1707 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1708 {
1709         struct hns3_hw *hw = &hns->hw;
1710         struct rte_eth_conf *dev_conf;
1711         bool en;
1712         int ret;
1713
1714         dev_conf = &hw->data->dev_conf;
1715         en = dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? true
1716                                                                    : false;
1717         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1718         if (ret)
1719                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1720                          ret);
1721         return ret;
1722 }
1723
1724 static int
1725 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1726 {
1727         struct hns3_adapter *hns = dev->data->dev_private;
1728         struct rte_eth_dev_data *data = dev->data;
1729         struct hns3_hw *hw = &hns->hw;
1730         int ret;
1731
1732         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1733             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1734             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1735                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1736                               "or hw_vlan_insert_pvid is not support!");
1737         }
1738
1739         /* Apply vlan offload setting */
1740         ret = hns3vf_vlan_offload_set(dev, RTE_ETH_VLAN_STRIP_MASK |
1741                                         RTE_ETH_VLAN_FILTER_MASK);
1742         if (ret)
1743                 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1744
1745         return ret;
1746 }
1747
1748 static int
1749 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1750 {
1751         uint8_t msg_data;
1752
1753         msg_data = alive ? 1 : 0;
1754         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1755                                  sizeof(msg_data), false, NULL, 0);
1756 }
1757
1758 static void
1759 hns3vf_keep_alive_handler(void *param)
1760 {
1761         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1762         struct hns3_adapter *hns = eth_dev->data->dev_private;
1763         struct hns3_hw *hw = &hns->hw;
1764         int ret;
1765
1766         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1767                                 false, NULL, 0);
1768         if (ret)
1769                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1770                          ret);
1771
1772         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1773                           eth_dev);
1774 }
1775
1776 static void
1777 hns3vf_service_handler(void *param)
1778 {
1779         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1780         struct hns3_adapter *hns = eth_dev->data->dev_private;
1781         struct hns3_hw *hw = &hns->hw;
1782
1783         /*
1784          * The query link status and reset processing are executed in the
1785          * interrupt thread. When the IMP reset occurs, IMP will not respond,
1786          * and the query operation will timeout after 30ms. In the case of
1787          * multiple PF/VFs, each query failure timeout causes the IMP reset
1788          * interrupt to fail to respond within 100ms.
1789          * Before querying the link status, check whether there is a reset
1790          * pending, and if so, abandon the query.
1791          */
1792         if (!hns3vf_is_reset_pending(hns))
1793                 hns3vf_request_link_info(hw);
1794         else
1795                 hns3_warn(hw, "Cancel the query when reset is pending");
1796
1797         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1798                           eth_dev);
1799 }
1800
1801 static void
1802 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1803 {
1804 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT      3
1805
1806         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1807
1808         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1809                 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1810
1811         __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1812
1813         hns3vf_service_handler(dev);
1814 }
1815
1816 static void
1817 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1818 {
1819         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1820
1821         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1822
1823         __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1824 }
1825
1826 static int
1827 hns3_query_vf_resource(struct hns3_hw *hw)
1828 {
1829         struct hns3_vf_res_cmd *req;
1830         struct hns3_cmd_desc desc;
1831         uint16_t num_msi;
1832         int ret;
1833
1834         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1835         ret = hns3_cmd_send(hw, &desc, 1);
1836         if (ret) {
1837                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1838                 return ret;
1839         }
1840
1841         req = (struct hns3_vf_res_cmd *)desc.data;
1842         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1843                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1844         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1845                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1846                          num_msi, HNS3_MIN_VECTOR_NUM);
1847                 return -EINVAL;
1848         }
1849
1850         hw->num_msi = num_msi;
1851
1852         return 0;
1853 }
1854
1855 static int
1856 hns3vf_init_hardware(struct hns3_adapter *hns)
1857 {
1858         struct hns3_hw *hw = &hns->hw;
1859         uint16_t mtu = hw->data->mtu;
1860         int ret;
1861
1862         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1863         if (ret)
1864                 return ret;
1865
1866         ret = hns3vf_config_mtu(hw, mtu);
1867         if (ret)
1868                 goto err_init_hardware;
1869
1870         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1871         if (ret) {
1872                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1873                 goto err_init_hardware;
1874         }
1875
1876         ret = hns3_config_gro(hw, false);
1877         if (ret) {
1878                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1879                 goto err_init_hardware;
1880         }
1881
1882         /*
1883          * In the initialization clearing the all hardware mapping relationship
1884          * configurations between queues and interrupt vectors is needed, so
1885          * some error caused by the residual configurations, such as the
1886          * unexpected interrupt, can be avoid.
1887          */
1888         ret = hns3vf_init_ring_with_vector(hw);
1889         if (ret) {
1890                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1891                 goto err_init_hardware;
1892         }
1893
1894         return 0;
1895
1896 err_init_hardware:
1897         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1898         return ret;
1899 }
1900
1901 static int
1902 hns3vf_clear_vport_list(struct hns3_hw *hw)
1903 {
1904         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1905                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1906                                  NULL, 0);
1907 }
1908
1909 static int
1910 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1911 {
1912         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1913         struct hns3_adapter *hns = eth_dev->data->dev_private;
1914         struct hns3_hw *hw = &hns->hw;
1915         int ret;
1916
1917         PMD_INIT_FUNC_TRACE();
1918
1919         /* Get hardware io base address from pcie BAR2 IO space */
1920         hw->io_base = pci_dev->mem_resource[2].addr;
1921
1922         /* Firmware command queue initialize */
1923         ret = hns3_cmd_init_queue(hw);
1924         if (ret) {
1925                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1926                 goto err_cmd_init_queue;
1927         }
1928
1929         /* Firmware command initialize */
1930         ret = hns3_cmd_init(hw);
1931         if (ret) {
1932                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1933                 goto err_cmd_init;
1934         }
1935
1936         hns3_tx_push_init(eth_dev);
1937
1938         /* Get VF resource */
1939         ret = hns3_query_vf_resource(hw);
1940         if (ret)
1941                 goto err_cmd_init;
1942
1943         rte_spinlock_init(&hw->mbx_resp.lock);
1944
1945         hns3vf_clear_event_cause(hw, 0);
1946
1947         ret = rte_intr_callback_register(pci_dev->intr_handle,
1948                                          hns3vf_interrupt_handler, eth_dev);
1949         if (ret) {
1950                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1951                 goto err_intr_callback_register;
1952         }
1953
1954         /* Enable interrupt */
1955         rte_intr_enable(pci_dev->intr_handle);
1956         hns3vf_enable_irq0(hw);
1957
1958         /* Get configuration from PF */
1959         ret = hns3vf_get_configuration(hw);
1960         if (ret) {
1961                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1962                 goto err_get_config;
1963         }
1964
1965         ret = hns3_tqp_stats_init(hw);
1966         if (ret)
1967                 goto err_get_config;
1968
1969         /* Hardware statistics of imissed registers cleared. */
1970         ret = hns3_update_imissed_stats(hw, true);
1971         if (ret) {
1972                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1973                 goto err_set_tc_queue;
1974         }
1975
1976         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1977         if (ret) {
1978                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1979                 goto err_set_tc_queue;
1980         }
1981
1982         ret = hns3vf_clear_vport_list(hw);
1983         if (ret) {
1984                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1985                 goto err_set_tc_queue;
1986         }
1987
1988         ret = hns3vf_init_hardware(hns);
1989         if (ret)
1990                 goto err_set_tc_queue;
1991
1992         hns3_rss_set_default_args(hw);
1993
1994         ret = hns3vf_set_alive(hw, true);
1995         if (ret) {
1996                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1997                 goto err_set_tc_queue;
1998         }
1999
2000         return 0;
2001
2002 err_set_tc_queue:
2003         hns3_tqp_stats_uninit(hw);
2004
2005 err_get_config:
2006         hns3vf_disable_irq0(hw);
2007         rte_intr_disable(pci_dev->intr_handle);
2008         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
2009                              eth_dev);
2010 err_intr_callback_register:
2011 err_cmd_init:
2012         hns3_cmd_uninit(hw);
2013         hns3_cmd_destroy_queue(hw);
2014 err_cmd_init_queue:
2015         hw->io_base = NULL;
2016
2017         return ret;
2018 }
2019
2020 static void
2021 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
2022 {
2023         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2024         struct hns3_adapter *hns = eth_dev->data->dev_private;
2025         struct hns3_hw *hw = &hns->hw;
2026
2027         PMD_INIT_FUNC_TRACE();
2028
2029         hns3_rss_uninit(hns);
2030         (void)hns3_config_gro(hw, false);
2031         (void)hns3vf_set_alive(hw, false);
2032         (void)hns3vf_set_promisc_mode(hw, false, false, false);
2033         hns3_flow_uninit(eth_dev);
2034         hns3_tqp_stats_uninit(hw);
2035         hns3vf_disable_irq0(hw);
2036         rte_intr_disable(pci_dev->intr_handle);
2037         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
2038                              eth_dev);
2039         hns3_cmd_uninit(hw);
2040         hns3_cmd_destroy_queue(hw);
2041         hw->io_base = NULL;
2042 }
2043
2044 static int
2045 hns3vf_do_stop(struct hns3_adapter *hns)
2046 {
2047         struct hns3_hw *hw = &hns->hw;
2048         int ret;
2049
2050         hw->mac.link_status = RTE_ETH_LINK_DOWN;
2051
2052         /*
2053          * The "hns3vf_do_stop" function will also be called by .stop_service to
2054          * prepare reset. At the time of global or IMP reset, the command cannot
2055          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
2056          * accessed during the reset process. So the mbuf can not be released
2057          * during reset and is required to be released after the reset is
2058          * completed.
2059          */
2060         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
2061                 hns3_dev_release_mbufs(hns);
2062
2063         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
2064                 hns3vf_configure_mac_addr(hns, true);
2065                 ret = hns3_reset_all_tqps(hns);
2066                 if (ret) {
2067                         hns3_err(hw, "failed to reset all queues ret = %d",
2068                                  ret);
2069                         return ret;
2070                 }
2071         }
2072         return 0;
2073 }
2074
2075 static void
2076 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
2077 {
2078         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2080         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2081         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2082         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2083         uint16_t q_id;
2084
2085         if (dev->data->dev_conf.intr_conf.rxq == 0)
2086                 return;
2087
2088         /* unmap the ring with vector */
2089         if (rte_intr_allow_others(intr_handle)) {
2090                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2091                 base = RTE_INTR_VEC_RXTX_OFFSET;
2092         }
2093         if (rte_intr_dp_is_en(intr_handle)) {
2094                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2095                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
2096                                                            HNS3_RING_TYPE_RX,
2097                                                            q_id);
2098                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
2099                             - 1)
2100                                 vec++;
2101                 }
2102         }
2103         /* Clean datapath event and queue/vec mapping */
2104         rte_intr_efd_disable(intr_handle);
2105
2106         /* Cleanup vector list */
2107         rte_intr_vec_list_free(intr_handle);
2108 }
2109
2110 static int
2111 hns3vf_dev_stop(struct rte_eth_dev *dev)
2112 {
2113         struct hns3_adapter *hns = dev->data->dev_private;
2114         struct hns3_hw *hw = &hns->hw;
2115
2116         PMD_INIT_FUNC_TRACE();
2117         dev->data->dev_started = 0;
2118
2119         hw->adapter_state = HNS3_NIC_STOPPING;
2120         hns3_set_rxtx_function(dev);
2121         rte_wmb();
2122         /* Disable datapath on secondary process. */
2123         hns3_mp_req_stop_rxtx(dev);
2124         /* Prevent crashes when queues are still in use. */
2125         rte_delay_ms(hw->cfg_max_queues);
2126
2127         rte_spinlock_lock(&hw->lock);
2128         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
2129                 hns3_stop_tqps(hw);
2130                 hns3vf_do_stop(hns);
2131                 hns3vf_unmap_rx_interrupt(dev);
2132                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2133         }
2134         hns3_rx_scattered_reset(dev);
2135         hns3vf_stop_poll_job(dev);
2136         hns3_stop_report_lse(dev);
2137         rte_spinlock_unlock(&hw->lock);
2138
2139         return 0;
2140 }
2141
2142 static int
2143 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
2144 {
2145         struct hns3_adapter *hns = eth_dev->data->dev_private;
2146         struct hns3_hw *hw = &hns->hw;
2147         int ret = 0;
2148
2149         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2150                 return 0;
2151
2152         if (hw->adapter_state == HNS3_NIC_STARTED)
2153                 ret = hns3vf_dev_stop(eth_dev);
2154
2155         hw->adapter_state = HNS3_NIC_CLOSING;
2156         hns3_reset_abort(hns);
2157         hw->adapter_state = HNS3_NIC_CLOSED;
2158         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
2159         hns3vf_configure_all_mc_mac_addr(hns, true);
2160         hns3vf_remove_all_vlan_table(hns);
2161         hns3vf_uninit_vf(eth_dev);
2162         hns3_free_all_queues(eth_dev);
2163         rte_free(hw->reset.wait_data);
2164         hns3_mp_uninit_primary();
2165         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
2166
2167         return ret;
2168 }
2169
2170 static int
2171 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2172                       size_t fw_size)
2173 {
2174         struct hns3_adapter *hns = eth_dev->data->dev_private;
2175         struct hns3_hw *hw = &hns->hw;
2176         uint32_t version = hw->fw_version;
2177         int ret;
2178
2179         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2180                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2181                                       HNS3_FW_VERSION_BYTE3_S),
2182                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2183                                       HNS3_FW_VERSION_BYTE2_S),
2184                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2185                                       HNS3_FW_VERSION_BYTE1_S),
2186                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2187                                       HNS3_FW_VERSION_BYTE0_S));
2188         if (ret < 0)
2189                 return -EINVAL;
2190
2191         ret += 1; /* add the size of '\0' */
2192         if (fw_size < (size_t)ret)
2193                 return ret;
2194         else
2195                 return 0;
2196 }
2197
2198 static int
2199 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2200                        __rte_unused int wait_to_complete)
2201 {
2202         struct hns3_adapter *hns = eth_dev->data->dev_private;
2203         struct hns3_hw *hw = &hns->hw;
2204         struct hns3_mac *mac = &hw->mac;
2205         struct rte_eth_link new_link;
2206
2207         memset(&new_link, 0, sizeof(new_link));
2208         switch (mac->link_speed) {
2209         case RTE_ETH_SPEED_NUM_10M:
2210         case RTE_ETH_SPEED_NUM_100M:
2211         case RTE_ETH_SPEED_NUM_1G:
2212         case RTE_ETH_SPEED_NUM_10G:
2213         case RTE_ETH_SPEED_NUM_25G:
2214         case RTE_ETH_SPEED_NUM_40G:
2215         case RTE_ETH_SPEED_NUM_50G:
2216         case RTE_ETH_SPEED_NUM_100G:
2217         case RTE_ETH_SPEED_NUM_200G:
2218                 if (mac->link_status)
2219                         new_link.link_speed = mac->link_speed;
2220                 break;
2221         default:
2222                 if (mac->link_status)
2223                         new_link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2224                 break;
2225         }
2226
2227         if (!mac->link_status)
2228                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2229
2230         new_link.link_duplex = mac->link_duplex;
2231         new_link.link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2232         new_link.link_autoneg =
2233             !(eth_dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED);
2234
2235         return rte_eth_linkstatus_set(eth_dev, &new_link);
2236 }
2237
2238 static int
2239 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2240 {
2241         struct hns3_hw *hw = &hns->hw;
2242         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2243         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2244         int ret;
2245
2246         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2247         if (ret)
2248                 return ret;
2249
2250         hns3_enable_rxd_adv_layout(hw);
2251
2252         ret = hns3_init_queues(hns, reset_queue);
2253         if (ret)
2254                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2255
2256         return ret;
2257 }
2258
2259 static int
2260 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2261 {
2262         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2263         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2264         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2265         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2266         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2267         uint32_t intr_vector;
2268         uint16_t q_id;
2269         int ret;
2270
2271         /*
2272          * hns3 needs a separate interrupt to be used as event interrupt which
2273          * could not be shared with task queue pair, so KERNEL drivers need
2274          * support multiple interrupt vectors.
2275          */
2276         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2277             !rte_intr_cap_multiple(intr_handle))
2278                 return 0;
2279
2280         rte_intr_disable(intr_handle);
2281         intr_vector = hw->used_rx_queues;
2282         /* It creates event fd for each intr vector when MSIX is used */
2283         if (rte_intr_efd_enable(intr_handle, intr_vector))
2284                 return -EINVAL;
2285
2286         /* Allocate vector list */
2287         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
2288                                     hw->used_rx_queues)) {
2289                 hns3_err(hw, "Failed to allocate %u rx_queues"
2290                          " intr_vec", hw->used_rx_queues);
2291                 ret = -ENOMEM;
2292                 goto vf_alloc_intr_vec_error;
2293         }
2294
2295         if (rte_intr_allow_others(intr_handle)) {
2296                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2297                 base = RTE_INTR_VEC_RXTX_OFFSET;
2298         }
2299
2300         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2301                 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2302                                                    HNS3_RING_TYPE_RX, q_id);
2303                 if (ret)
2304                         goto vf_bind_vector_error;
2305
2306                 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
2307                         goto vf_bind_vector_error;
2308
2309                 /*
2310                  * If there are not enough efds (e.g. not enough interrupt),
2311                  * remaining queues will be bond to the last interrupt.
2312                  */
2313                 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
2314                         vec++;
2315         }
2316         rte_intr_enable(intr_handle);
2317         return 0;
2318
2319 vf_bind_vector_error:
2320         rte_intr_vec_list_free(intr_handle);
2321 vf_alloc_intr_vec_error:
2322         rte_intr_efd_disable(intr_handle);
2323         return ret;
2324 }
2325
2326 static int
2327 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2328 {
2329         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2330         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2331         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2332         uint16_t q_id;
2333         int ret;
2334
2335         if (dev->data->dev_conf.intr_conf.rxq == 0)
2336                 return 0;
2337
2338         if (rte_intr_dp_is_en(intr_handle)) {
2339                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2340                         ret = hns3vf_bind_ring_with_vector(hw,
2341                                 rte_intr_vec_list_index_get(intr_handle,
2342                                                                    q_id),
2343                                 true, HNS3_RING_TYPE_RX, q_id);
2344                         if (ret)
2345                                 return ret;
2346                 }
2347         }
2348
2349         return 0;
2350 }
2351
2352 static void
2353 hns3vf_restore_filter(struct rte_eth_dev *dev)
2354 {
2355         hns3_restore_rss_filter(dev);
2356 }
2357
2358 static int
2359 hns3vf_dev_start(struct rte_eth_dev *dev)
2360 {
2361         struct hns3_adapter *hns = dev->data->dev_private;
2362         struct hns3_hw *hw = &hns->hw;
2363         int ret;
2364
2365         PMD_INIT_FUNC_TRACE();
2366         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2367                 return -EBUSY;
2368
2369         rte_spinlock_lock(&hw->lock);
2370         hw->adapter_state = HNS3_NIC_STARTING;
2371         ret = hns3vf_do_start(hns, true);
2372         if (ret) {
2373                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2374                 rte_spinlock_unlock(&hw->lock);
2375                 return ret;
2376         }
2377         ret = hns3vf_map_rx_interrupt(dev);
2378         if (ret)
2379                 goto map_rx_inter_err;
2380
2381         /*
2382          * There are three register used to control the status of a TQP
2383          * (contains a pair of Tx queue and Rx queue) in the new version network
2384          * engine. One is used to control the enabling of Tx queue, the other is
2385          * used to control the enabling of Rx queue, and the last is the master
2386          * switch used to control the enabling of the tqp. The Tx register and
2387          * TQP register must be enabled at the same time to enable a Tx queue.
2388          * The same applies to the Rx queue. For the older network enginem, this
2389          * function only refresh the enabled flag, and it is used to update the
2390          * status of queue in the dpdk framework.
2391          */
2392         ret = hns3_start_all_txqs(dev);
2393         if (ret)
2394                 goto map_rx_inter_err;
2395
2396         ret = hns3_start_all_rxqs(dev);
2397         if (ret)
2398                 goto start_all_rxqs_fail;
2399
2400         hw->adapter_state = HNS3_NIC_STARTED;
2401         rte_spinlock_unlock(&hw->lock);
2402
2403         hns3_rx_scattered_calc(dev);
2404         hns3_set_rxtx_function(dev);
2405         hns3_mp_req_start_rxtx(dev);
2406
2407         hns3vf_restore_filter(dev);
2408
2409         /* Enable interrupt of all rx queues before enabling queues */
2410         hns3_dev_all_rx_queue_intr_enable(hw, true);
2411         hns3_start_tqps(hw);
2412
2413         if (dev->data->dev_conf.intr_conf.lsc != 0)
2414                 hns3vf_dev_link_update(dev, 0);
2415         hns3vf_start_poll_job(dev);
2416
2417         return ret;
2418
2419 start_all_rxqs_fail:
2420         hns3_stop_all_txqs(dev);
2421 map_rx_inter_err:
2422         (void)hns3vf_do_stop(hns);
2423         hw->adapter_state = HNS3_NIC_CONFIGURED;
2424         rte_spinlock_unlock(&hw->lock);
2425
2426         return ret;
2427 }
2428
2429 static bool
2430 is_vf_reset_done(struct hns3_hw *hw)
2431 {
2432 #define HNS3_FUN_RST_ING_BITS \
2433         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2434          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2435          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2436          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2437
2438         uint32_t val;
2439
2440         if (hw->reset.level == HNS3_VF_RESET) {
2441                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2442                 if (val & HNS3_VF_RST_ING_BIT)
2443                         return false;
2444         } else {
2445                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2446                 if (val & HNS3_FUN_RST_ING_BITS)
2447                         return false;
2448         }
2449         return true;
2450 }
2451
2452 bool
2453 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2454 {
2455         struct hns3_hw *hw = &hns->hw;
2456         enum hns3_reset_level reset;
2457
2458         /*
2459          * According to the protocol of PCIe, FLR to a PF device resets the PF
2460          * state as well as the SR-IOV extended capability including VF Enable
2461          * which means that VFs no longer exist.
2462          *
2463          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2464          * is in FLR stage, the register state of VF device is not reliable,
2465          * so register states detection can not be carried out. In this case,
2466          * we just ignore the register states and return false to indicate that
2467          * there are no other reset states that need to be processed by driver.
2468          */
2469         if (hw->reset.level == HNS3_VF_FULL_RESET)
2470                 return false;
2471
2472         /* Check the registers to confirm whether there is reset pending */
2473         hns3vf_check_event_cause(hns, NULL);
2474         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2475         if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2476             hw->reset.level < reset) {
2477                 hns3_warn(hw, "High level reset %d is pending", reset);
2478                 return true;
2479         }
2480         return false;
2481 }
2482
2483 static int
2484 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2485 {
2486         struct hns3_hw *hw = &hns->hw;
2487         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2488         struct timeval tv;
2489
2490         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2491                 /*
2492                  * After vf reset is ready, the PF may not have completed
2493                  * the reset processing. The vf sending mbox to PF may fail
2494                  * during the pf reset, so it is better to add extra delay.
2495                  */
2496                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2497                     hw->reset.level == HNS3_FLR_RESET)
2498                         return 0;
2499                 /* Reset retry process, no need to add extra delay. */
2500                 if (hw->reset.attempts)
2501                         return 0;
2502                 if (wait_data->check_completion == NULL)
2503                         return 0;
2504
2505                 wait_data->check_completion = NULL;
2506                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2507                 wait_data->count = 1;
2508                 wait_data->result = HNS3_WAIT_REQUEST;
2509                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2510                                   wait_data);
2511                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2512                 return -EAGAIN;
2513         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2514                 hns3_clock_gettime(&tv);
2515                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2516                           tv.tv_sec, tv.tv_usec);
2517                 return -ETIME;
2518         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2519                 return -EAGAIN;
2520
2521         wait_data->hns = hns;
2522         wait_data->check_completion = is_vf_reset_done;
2523         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2524                                 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2525         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2526         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2527         wait_data->result = HNS3_WAIT_REQUEST;
2528         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2529         return -EAGAIN;
2530 }
2531
2532 static int
2533 hns3vf_prepare_reset(struct hns3_adapter *hns)
2534 {
2535         struct hns3_hw *hw = &hns->hw;
2536         int ret;
2537
2538         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2539                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2540                                         0, true, NULL, 0);
2541                 if (ret)
2542                         return ret;
2543         }
2544         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2545
2546         return 0;
2547 }
2548
2549 static int
2550 hns3vf_stop_service(struct hns3_adapter *hns)
2551 {
2552         struct hns3_hw *hw = &hns->hw;
2553         struct rte_eth_dev *eth_dev;
2554
2555         eth_dev = &rte_eth_devices[hw->data->port_id];
2556         if (hw->adapter_state == HNS3_NIC_STARTED) {
2557                 /*
2558                  * Make sure call update link status before hns3vf_stop_poll_job
2559                  * because update link status depend on polling job exist.
2560                  */
2561                 hns3vf_update_link_status(hw, RTE_ETH_LINK_DOWN, hw->mac.link_speed,
2562                                           hw->mac.link_duplex);
2563                 hns3vf_stop_poll_job(eth_dev);
2564         }
2565         hw->mac.link_status = RTE_ETH_LINK_DOWN;
2566
2567         hns3_set_rxtx_function(eth_dev);
2568         rte_wmb();
2569         /* Disable datapath on secondary process. */
2570         hns3_mp_req_stop_rxtx(eth_dev);
2571         rte_delay_ms(hw->cfg_max_queues);
2572
2573         rte_spinlock_lock(&hw->lock);
2574         if (hw->adapter_state == HNS3_NIC_STARTED ||
2575             hw->adapter_state == HNS3_NIC_STOPPING) {
2576                 hns3_enable_all_queues(hw, false);
2577                 hns3vf_do_stop(hns);
2578                 hw->reset.mbuf_deferred_free = true;
2579         } else
2580                 hw->reset.mbuf_deferred_free = false;
2581
2582         /*
2583          * It is cumbersome for hardware to pick-and-choose entries for deletion
2584          * from table space. Hence, for function reset software intervention is
2585          * required to delete the entries.
2586          */
2587         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2588                 hns3vf_configure_all_mc_mac_addr(hns, true);
2589         rte_spinlock_unlock(&hw->lock);
2590
2591         return 0;
2592 }
2593
2594 static int
2595 hns3vf_start_service(struct hns3_adapter *hns)
2596 {
2597         struct hns3_hw *hw = &hns->hw;
2598         struct rte_eth_dev *eth_dev;
2599
2600         eth_dev = &rte_eth_devices[hw->data->port_id];
2601         hns3_set_rxtx_function(eth_dev);
2602         hns3_mp_req_start_rxtx(eth_dev);
2603         if (hw->adapter_state == HNS3_NIC_STARTED) {
2604                 hns3vf_start_poll_job(eth_dev);
2605
2606                 /* Enable interrupt of all rx queues before enabling queues */
2607                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2608                 /*
2609                  * Enable state of each rxq and txq will be recovered after
2610                  * reset, so we need to restore them before enable all tqps;
2611                  */
2612                 hns3_restore_tqp_enable_state(hw);
2613                 /*
2614                  * When finished the initialization, enable queues to receive
2615                  * and transmit packets.
2616                  */
2617                 hns3_enable_all_queues(hw, true);
2618         }
2619
2620         return 0;
2621 }
2622
2623 static int
2624 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2625 {
2626         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2627         struct rte_ether_addr *hw_mac;
2628         int ret;
2629
2630         /*
2631          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2632          * on the host by "ip link set ..." command. If the hns3 PF kernel
2633          * ethdev driver sets the MAC address for VF device after the
2634          * initialization of the related VF device, the PF driver will notify
2635          * VF driver to reset VF device to make the new MAC address effective
2636          * immediately. The hns3 VF PMD driver should check whether the MAC
2637          * address has been changed by the PF kernel ethdev driver, if changed
2638          * VF driver should configure hardware using the new MAC address in the
2639          * recovering hardware configuration stage of the reset process.
2640          */
2641         ret = hns3vf_get_host_mac_addr(hw);
2642         if (ret)
2643                 return ret;
2644
2645         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2646         ret = rte_is_zero_ether_addr(hw_mac);
2647         if (ret) {
2648                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2649         } else {
2650                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2651                 if (!ret) {
2652                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2653                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2654                                               &hw->data->mac_addrs[0]);
2655                         hns3_warn(hw, "Default MAC address has been changed to:"
2656                                   " %s by the host PF kernel ethdev driver",
2657                                   mac_str);
2658                 }
2659         }
2660
2661         return 0;
2662 }
2663
2664 static int
2665 hns3vf_restore_conf(struct hns3_adapter *hns)
2666 {
2667         struct hns3_hw *hw = &hns->hw;
2668         int ret;
2669
2670         ret = hns3vf_check_default_mac_change(hw);
2671         if (ret)
2672                 return ret;
2673
2674         ret = hns3vf_configure_mac_addr(hns, false);
2675         if (ret)
2676                 return ret;
2677
2678         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2679         if (ret)
2680                 goto err_mc_mac;
2681
2682         ret = hns3vf_restore_promisc(hns);
2683         if (ret)
2684                 goto err_vlan_table;
2685
2686         ret = hns3vf_restore_vlan_conf(hns);
2687         if (ret)
2688                 goto err_vlan_table;
2689
2690         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2691         if (ret)
2692                 goto err_vlan_table;
2693
2694         ret = hns3vf_restore_rx_interrupt(hw);
2695         if (ret)
2696                 goto err_vlan_table;
2697
2698         ret = hns3_restore_gro_conf(hw);
2699         if (ret)
2700                 goto err_vlan_table;
2701
2702         if (hw->adapter_state == HNS3_NIC_STARTED) {
2703                 ret = hns3vf_do_start(hns, false);
2704                 if (ret)
2705                         goto err_vlan_table;
2706                 hns3_info(hw, "hns3vf dev restart successful!");
2707         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2708                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2709
2710         ret = hns3vf_set_alive(hw, true);
2711         if (ret) {
2712                 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2713                 goto err_vlan_table;
2714         }
2715
2716         return 0;
2717
2718 err_vlan_table:
2719         hns3vf_configure_all_mc_mac_addr(hns, true);
2720 err_mc_mac:
2721         hns3vf_configure_mac_addr(hns, true);
2722         return ret;
2723 }
2724
2725 static enum hns3_reset_level
2726 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2727 {
2728         enum hns3_reset_level reset_level;
2729
2730         /* return the highest priority reset level amongst all */
2731         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2732                 reset_level = HNS3_VF_RESET;
2733         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2734                 reset_level = HNS3_VF_FULL_RESET;
2735         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2736                 reset_level = HNS3_VF_PF_FUNC_RESET;
2737         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2738                 reset_level = HNS3_VF_FUNC_RESET;
2739         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2740                 reset_level = HNS3_FLR_RESET;
2741         else
2742                 reset_level = HNS3_NONE_RESET;
2743
2744         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2745                 return HNS3_NONE_RESET;
2746
2747         return reset_level;
2748 }
2749
2750 static void
2751 hns3vf_reset_service(void *param)
2752 {
2753         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2754         struct hns3_hw *hw = &hns->hw;
2755         enum hns3_reset_level reset_level;
2756         struct timeval tv_delta;
2757         struct timeval tv_start;
2758         struct timeval tv;
2759         uint64_t msec;
2760
2761         /*
2762          * The interrupt is not triggered within the delay time.
2763          * The interrupt may have been lost. It is necessary to handle
2764          * the interrupt to recover from the error.
2765          */
2766         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2767                             SCHEDULE_DEFERRED) {
2768                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2769                                  __ATOMIC_RELAXED);
2770                 hns3_err(hw, "Handling interrupts in delayed tasks");
2771                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2772                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2773                 if (reset_level == HNS3_NONE_RESET) {
2774                         hns3_err(hw, "No reset level is set, try global reset");
2775                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2776                 }
2777         }
2778         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2779
2780         /*
2781          * Hardware reset has been notified, we now have to poll & check if
2782          * hardware has actually completed the reset sequence.
2783          */
2784         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2785         if (reset_level != HNS3_NONE_RESET) {
2786                 hns3_clock_gettime(&tv_start);
2787                 hns3_reset_process(hns, reset_level);
2788                 hns3_clock_gettime(&tv);
2789                 timersub(&tv, &tv_start, &tv_delta);
2790                 msec = hns3_clock_calctime_ms(&tv_delta);
2791                 if (msec > HNS3_RESET_PROCESS_MS)
2792                         hns3_err(hw, "%d handle long time delta %" PRIu64
2793                                  " ms time=%ld.%.6ld",
2794                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2795         }
2796 }
2797
2798 static int
2799 hns3vf_reinit_dev(struct hns3_adapter *hns)
2800 {
2801         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2802         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2803         struct hns3_hw *hw = &hns->hw;
2804         int ret;
2805
2806         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2807                 rte_intr_disable(pci_dev->intr_handle);
2808                 ret = hns3vf_set_bus_master(pci_dev, true);
2809                 if (ret < 0) {
2810                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2811                         return ret;
2812                 }
2813         }
2814
2815         /* Firmware command initialize */
2816         ret = hns3_cmd_init(hw);
2817         if (ret) {
2818                 hns3_err(hw, "Failed to init cmd: %d", ret);
2819                 return ret;
2820         }
2821
2822         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2823                 /*
2824                  * UIO enables msix by writing the pcie configuration space
2825                  * vfio_pci enables msix in rte_intr_enable.
2826                  */
2827                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2828                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2829                         if (hns3vf_enable_msix(pci_dev, true))
2830                                 hns3_err(hw, "Failed to enable msix");
2831                 }
2832
2833                 rte_intr_enable(pci_dev->intr_handle);
2834         }
2835
2836         ret = hns3_reset_all_tqps(hns);
2837         if (ret) {
2838                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2839                 return ret;
2840         }
2841
2842         ret = hns3vf_init_hardware(hns);
2843         if (ret) {
2844                 hns3_err(hw, "Failed to init hardware: %d", ret);
2845                 return ret;
2846         }
2847
2848         return 0;
2849 }
2850
2851 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2852         .dev_configure      = hns3vf_dev_configure,
2853         .dev_start          = hns3vf_dev_start,
2854         .dev_stop           = hns3vf_dev_stop,
2855         .dev_close          = hns3vf_dev_close,
2856         .mtu_set            = hns3vf_dev_mtu_set,
2857         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2858         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2859         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2860         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2861         .stats_get          = hns3_stats_get,
2862         .stats_reset        = hns3_stats_reset,
2863         .xstats_get         = hns3_dev_xstats_get,
2864         .xstats_get_names   = hns3_dev_xstats_get_names,
2865         .xstats_reset       = hns3_dev_xstats_reset,
2866         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2867         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2868         .dev_infos_get      = hns3vf_dev_infos_get,
2869         .fw_version_get     = hns3vf_fw_version_get,
2870         .rx_queue_setup     = hns3_rx_queue_setup,
2871         .tx_queue_setup     = hns3_tx_queue_setup,
2872         .rx_queue_release   = hns3_dev_rx_queue_release,
2873         .tx_queue_release   = hns3_dev_tx_queue_release,
2874         .rx_queue_start     = hns3_dev_rx_queue_start,
2875         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2876         .tx_queue_start     = hns3_dev_tx_queue_start,
2877         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2878         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2879         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2880         .rxq_info_get       = hns3_rxq_info_get,
2881         .txq_info_get       = hns3_txq_info_get,
2882         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2883         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2884         .mac_addr_add       = hns3vf_add_mac_addr,
2885         .mac_addr_remove    = hns3vf_remove_mac_addr,
2886         .mac_addr_set       = hns3vf_set_default_mac_addr,
2887         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2888         .link_update        = hns3vf_dev_link_update,
2889         .rss_hash_update    = hns3_dev_rss_hash_update,
2890         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2891         .reta_update        = hns3_dev_rss_reta_update,
2892         .reta_query         = hns3_dev_rss_reta_query,
2893         .flow_ops_get       = hns3_dev_flow_ops_get,
2894         .vlan_filter_set    = hns3vf_vlan_filter_set,
2895         .vlan_offload_set   = hns3vf_vlan_offload_set,
2896         .get_reg            = hns3_get_regs,
2897         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2898         .tx_done_cleanup    = hns3_tx_done_cleanup,
2899 };
2900
2901 static const struct hns3_reset_ops hns3vf_reset_ops = {
2902         .reset_service       = hns3vf_reset_service,
2903         .stop_service        = hns3vf_stop_service,
2904         .prepare_reset       = hns3vf_prepare_reset,
2905         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2906         .reinit_dev          = hns3vf_reinit_dev,
2907         .restore_conf        = hns3vf_restore_conf,
2908         .start_service       = hns3vf_start_service,
2909 };
2910
2911 static int
2912 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2913 {
2914         struct hns3_adapter *hns = eth_dev->data->dev_private;
2915         struct hns3_hw *hw = &hns->hw;
2916         int ret;
2917
2918         PMD_INIT_FUNC_TRACE();
2919
2920         hns3_flow_init(eth_dev);
2921
2922         hns3_set_rxtx_function(eth_dev);
2923         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2924         eth_dev->rx_queue_count = hns3_rx_queue_count;
2925         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2926                 ret = hns3_mp_init_secondary();
2927                 if (ret) {
2928                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2929                                           "process, ret = %d", ret);
2930                         goto err_mp_init_secondary;
2931                 }
2932                 hw->secondary_cnt++;
2933                 hns3_tx_push_init(eth_dev);
2934                 return 0;
2935         }
2936
2937         ret = hns3_mp_init_primary();
2938         if (ret) {
2939                 PMD_INIT_LOG(ERR,
2940                              "Failed to init for primary process, ret = %d",
2941                              ret);
2942                 goto err_mp_init_primary;
2943         }
2944
2945         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2946         hns->is_vf = true;
2947         hw->data = eth_dev->data;
2948         hns3_parse_devargs(eth_dev);
2949
2950         ret = hns3_reset_init(hw);
2951         if (ret)
2952                 goto err_init_reset;
2953         hw->reset.ops = &hns3vf_reset_ops;
2954
2955         ret = hns3vf_init_vf(eth_dev);
2956         if (ret) {
2957                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2958                 goto err_init_vf;
2959         }
2960
2961         /* Allocate memory for storing MAC addresses */
2962         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2963                                                sizeof(struct rte_ether_addr) *
2964                                                HNS3_VF_UC_MACADDR_NUM, 0);
2965         if (eth_dev->data->mac_addrs == NULL) {
2966                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2967                              "to store MAC addresses",
2968                              sizeof(struct rte_ether_addr) *
2969                              HNS3_VF_UC_MACADDR_NUM);
2970                 ret = -ENOMEM;
2971                 goto err_rte_zmalloc;
2972         }
2973
2974         /*
2975          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2976          * on the host by "ip link set ..." command. To avoid some incorrect
2977          * scenes, for example, hns3 VF PMD driver fails to receive and send
2978          * packets after user configure the MAC address by using the
2979          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2980          * address strategy as the hns3 kernel ethdev driver in the
2981          * initialization. If user configure a MAC address by the ip command
2982          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2983          * start with a random MAC address in the initialization.
2984          */
2985         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2986                 rte_eth_random_addr(hw->mac.mac_addr);
2987         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2988                             &eth_dev->data->mac_addrs[0]);
2989
2990         hw->adapter_state = HNS3_NIC_INITIALIZED;
2991
2992         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2993                             SCHEDULE_PENDING) {
2994                 hns3_err(hw, "Reschedule reset service after dev_init");
2995                 hns3_schedule_reset(hns);
2996         } else {
2997                 /* IMP will wait ready flag before reset */
2998                 hns3_notify_reset_ready(hw, false);
2999         }
3000         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
3001                           eth_dev);
3002         return 0;
3003
3004 err_rte_zmalloc:
3005         hns3vf_uninit_vf(eth_dev);
3006
3007 err_init_vf:
3008         rte_free(hw->reset.wait_data);
3009
3010 err_init_reset:
3011         hns3_mp_uninit_primary();
3012
3013 err_mp_init_primary:
3014 err_mp_init_secondary:
3015         eth_dev->dev_ops = NULL;
3016         eth_dev->rx_pkt_burst = NULL;
3017         eth_dev->rx_descriptor_status = NULL;
3018         eth_dev->tx_pkt_burst = NULL;
3019         eth_dev->tx_pkt_prepare = NULL;
3020         eth_dev->tx_descriptor_status = NULL;
3021
3022         return ret;
3023 }
3024
3025 static int
3026 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
3027 {
3028         struct hns3_adapter *hns = eth_dev->data->dev_private;
3029         struct hns3_hw *hw = &hns->hw;
3030
3031         PMD_INIT_FUNC_TRACE();
3032
3033         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3034                 return 0;
3035
3036         if (hw->adapter_state < HNS3_NIC_CLOSING)
3037                 hns3vf_dev_close(eth_dev);
3038
3039         hw->adapter_state = HNS3_NIC_REMOVED;
3040         return 0;
3041 }
3042
3043 static int
3044 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3045                      struct rte_pci_device *pci_dev)
3046 {
3047         return rte_eth_dev_pci_generic_probe(pci_dev,
3048                                              sizeof(struct hns3_adapter),
3049                                              hns3vf_dev_init);
3050 }
3051
3052 static int
3053 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
3054 {
3055         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
3056 }
3057
3058 static const struct rte_pci_id pci_id_hns3vf_map[] = {
3059         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
3060         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
3061         { .vendor_id = 0, }, /* sentinel */
3062 };
3063
3064 static struct rte_pci_driver rte_hns3vf_pmd = {
3065         .id_table = pci_id_hns3vf_map,
3066         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3067         .probe = eth_hns3vf_pci_probe,
3068         .remove = eth_hns3vf_pci_remove,
3069 };
3070
3071 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
3072 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
3073 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
3074 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
3075                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
3076                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
3077                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
3078                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16_t> ");