drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 /* set PCI bus mastering */
  63 static void
  64 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  65 {
  66         uint16_t reg;
  67
  68         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  69
  70         if (op)
  71                 /* set the master bit */
  72                 reg |= PCI_COMMAND_MASTER;
  73         else
  74                 reg &= ~(PCI_COMMAND_MASTER);
  75
  76         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  77 }
  78
  79 /**
  80  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  81  * @cap: the capability
  82  *
  83  * Return the address of the given capability within the PCI capability list.
  84  */
  85 static int
  86 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  87 {
  88 #define MAX_PCIE_CAPABILITY 48
  89         uint16_t status;
  90         uint8_t pos;
  91         uint8_t id;
  92         int ttl;
  93
  94         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 100         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 101                 rte_pci_read_config(device, &id, sizeof(id),
 102                                     (pos + PCI_CAP_LIST_ID));
 103
 104                 if (id == 0xFF)
 105                         break;
 106
 107                 if (id == cap)
 108                         return (int)pos;
 109
 110                 rte_pci_read_config(device, &pos, sizeof(pos),
 111                                     (pos + PCI_CAP_LIST_NEXT));
 112         }
 113         return 0;
 114 }
 115
 116 static int
 117 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 118 {
 119         uint16_t control;
 120         int pos;
 121
 122         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 123         if (pos) {
 124                 rte_pci_read_config(device, &control, sizeof(control),
 125                                     (pos + PCI_MSIX_FLAGS));
 126                 if (op)
 127                         control |= PCI_MSIX_FLAGS_ENABLE;
 128                 else
 129                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 130                 rte_pci_write_config(device, &control, sizeof(control),
 131                                      (pos + PCI_MSIX_FLAGS));
 132                 return 0;
 133         }
 134         return -ENXIO;
 135 }
 136
 137 static int
 138 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 139                     __attribute__ ((unused)) uint32_t idx,
 140                     __attribute__ ((unused)) uint32_t pool)
 141 {
 142         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 143         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 144         int ret;
 145
 146         rte_spinlock_lock(&hw->lock);
 147         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 148                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 149                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 150         rte_spinlock_unlock(&hw->lock);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "Failed to add mac addr(%s) for vf: %d", mac_str,
 155                          ret);
 156         }
 157
 158         return ret;
 159 }
 160
 161 static void
 162 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 163 {
 164         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 165         /* index will be checked by upper level rte interface */
 166         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 167         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 168         int ret;
 169
 170         rte_spinlock_lock(&hw->lock);
 171         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 172                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 173                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 174                                 NULL, 0);
 175         rte_spinlock_unlock(&hw->lock);
 176         if (ret) {
 177                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 178                                       mac_addr);
 179                 hns3_err(hw, "Failed to remove mac addr(%s) for vf: %d",
 180                          mac_str, ret);
 181         }
 182 }
 183
 184 static int
 185 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 186                             struct rte_ether_addr *mac_addr)
 187 {
 188 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 189         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 190         struct rte_ether_addr *old_addr;
 191         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 192         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 193         int ret;
 194
 195         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 196                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 197                                       mac_addr);
 198                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid.",
 199                          mac_str);
 200                 return -EINVAL;
 201         }
 202
 203         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 204         rte_spinlock_lock(&hw->lock);
 205         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 206         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 207                RTE_ETHER_ADDR_LEN);
 208
 209         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 210                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 211                                 HNS3_TWO_ETHER_ADDR_LEN, false, NULL, 0);
 212         if (ret) {
 213                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 214                                       mac_addr);
 215                 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d", mac_str,
 216                          ret);
 217         }
 218
 219         rte_ether_addr_copy(mac_addr,
 220                             (struct rte_ether_addr *)hw->mac.mac_addr);
 221         rte_spinlock_unlock(&hw->lock);
 222
 223         return ret;
 224 }
 225
 226 static int
 227 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 228 {
 229         struct hns3_hw *hw = &hns->hw;
 230         struct rte_ether_addr *addr;
 231         enum hns3_mbx_mac_vlan_subcode opcode;
 232         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 233         int ret = 0;
 234         int i;
 235
 236         if (del)
 237                 opcode = HNS3_MBX_MAC_VLAN_UC_REMOVE;
 238         else
 239                 opcode = HNS3_MBX_MAC_VLAN_UC_ADD;
 240         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 241                 addr = &hw->data->mac_addrs[i];
 242                 if (!rte_is_valid_assigned_ether_addr(addr))
 243                         continue;
 244                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr);
 245                 hns3_dbg(hw, "rm mac addr: %s", mac_str);
 246                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, opcode,
 247                                         addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 248                                         false, NULL, 0);
 249                 if (ret) {
 250                         hns3_err(hw, "Failed to remove mac addr for vf: %d",
 251                                  ret);
 252                         break;
 253                 }
 254         }
 255         return ret;
 256 }
 257
 258 static int
 259 hns3vf_add_mc_mac_addr(struct hns3_adapter *hns,
 260                        struct rte_ether_addr *mac_addr)
 261 {
 262         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 263         struct hns3_hw *hw = &hns->hw;
 264         int ret;
 265
 266         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 267                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 268                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 269                                 NULL, 0);
 270         if (ret) {
 271                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 272                                       mac_addr);
 273                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 274                          mac_str, ret);
 275                 return ret;
 276         }
 277
 278         return 0;
 279 }
 280
 281 static int
 282 hns3vf_remove_mc_mac_addr(struct hns3_adapter *hns,
 283                           struct rte_ether_addr *mac_addr)
 284 {
 285         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 286         struct hns3_hw *hw = &hns->hw;
 287         int ret;
 288
 289         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 290                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 291                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 292                                 NULL, 0);
 293         if (ret) {
 294                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 295                                       mac_addr);
 296                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 297                          mac_str, ret);
 298                 return ret;
 299         }
 300
 301         return 0;
 302 }
 303
 304 static int
 305 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 306                             struct rte_ether_addr *mc_addr_set,
 307                             uint32_t nb_mc_addr)
 308 {
 309         struct hns3_adapter *hns = dev->data->dev_private;
 310         struct hns3_hw *hw = &hns->hw;
 311         struct rte_ether_addr *addr;
 312         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 313         int cur_addr_num;
 314         int set_addr_num;
 315         int num;
 316         int ret;
 317         int i;
 318
 319         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 320                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
 321                          "invalid. valid range: 0~%d",
 322                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 323                 return -EINVAL;
 324         }
 325
 326         set_addr_num = (int)nb_mc_addr;
 327         for (i = 0; i < set_addr_num; i++) {
 328                 addr = &mc_addr_set[i];
 329                 if (!rte_is_multicast_ether_addr(addr)) {
 330                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 331                                               addr);
 332                         hns3_err(hw,
 333                                  "Failed to set mc mac addr, addr(%s) invalid.",
 334                                  mac_str);
 335                         return -EINVAL;
 336                 }
 337         }
 338         rte_spinlock_lock(&hw->lock);
 339         cur_addr_num = hw->mc_addrs_num;
 340         for (i = 0; i < cur_addr_num; i++) {
 341                 num = cur_addr_num - i - 1;
 342                 addr = &hw->mc_addrs[num];
 343                 ret = hns3vf_remove_mc_mac_addr(hns, addr);
 344                 if (ret) {
 345                         rte_spinlock_unlock(&hw->lock);
 346                         return ret;
 347                 }
 348
 349                 hw->mc_addrs_num--;
 350         }
 351
 352         for (i = 0; i < set_addr_num; i++) {
 353                 addr = &mc_addr_set[i];
 354                 ret = hns3vf_add_mc_mac_addr(hns, addr);
 355                 if (ret) {
 356                         rte_spinlock_unlock(&hw->lock);
 357                         return ret;
 358                 }
 359
 360                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 361                 hw->mc_addrs_num++;
 362         }
 363         rte_spinlock_unlock(&hw->lock);
 364
 365         return 0;
 366 }
 367
 368 static int
 369 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 370 {
 371         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 372         struct hns3_hw *hw = &hns->hw;
 373         struct rte_ether_addr *addr;
 374         int err = 0;
 375         int ret;
 376         int i;
 377
 378         for (i = 0; i < hw->mc_addrs_num; i++) {
 379                 addr = &hw->mc_addrs[i];
 380                 if (!rte_is_multicast_ether_addr(addr))
 381                         continue;
 382                 if (del)
 383                         ret = hns3vf_remove_mc_mac_addr(hns, addr);
 384                 else
 385                         ret = hns3vf_add_mc_mac_addr(hns, addr);
 386                 if (ret) {
 387                         err = ret;
 388                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 389                                               addr);
 390                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 391                                  del ? "Remove" : "Restore", mac_str, ret);
 392                 }
 393         }
 394         return err;
 395 }
 396
 397 static int
 398 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc)
 399 {
 400         struct hns3_mbx_vf_to_pf_cmd *req;
 401         struct hns3_cmd_desc desc;
 402         int ret;
 403
 404         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 405
 406         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 407         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 408         req->msg[1] = en_bc_pmc ? 1 : 0;
 409
 410         ret = hns3_cmd_send(hw, &desc, 1);
 411         if (ret)
 412                 hns3_err(hw, "Set promisc mode fail, status is %d", ret);
 413
 414         return ret;
 415 }
 416
 417 static int
 418 hns3vf_dev_configure(struct rte_eth_dev *dev)
 419 {
 420         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 421         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 422         struct rte_eth_conf *conf = &dev->data->dev_conf;
 423         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 424         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 425         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 426         struct rte_eth_rss_conf rss_conf;
 427         uint16_t mtu;
 428         int ret;
 429
 430         /*
 431          * Hardware does not support individually enable/disable/reset the Tx or
 432          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 433          * and Rx queues at the same time. When the numbers of Tx queues
 434          * allocated by upper applications are not equal to the numbers of Rx
 435          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 436          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 437          * these fake queues are imperceptible, and can not be used by upper
 438          * applications.
 439          */
 440         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 441         if (ret) {
 442                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 443                 return ret;
 444         }
 445
 446         hw->adapter_state = HNS3_NIC_CONFIGURING;
 447         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 448                 hns3_err(hw, "setting link speed/duplex not supported");
 449                 ret = -EINVAL;
 450                 goto cfg_err;
 451         }
 452
 453         /* When RSS is not configured, redirect the packet queue 0 */
 454         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 455                 rss_conf = conf->rx_adv_conf.rss_conf;
 456                 if (rss_conf.rss_key == NULL) {
 457                         rss_conf.rss_key = rss_cfg->key;
 458                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 459                 }
 460
 461                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 462                 if (ret)
 463                         goto cfg_err;
 464         }
 465
 466         /*
 467          * If jumbo frames are enabled, MTU needs to be refreshed
 468          * according to the maximum RX packet length.
 469          */
 470         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 471                 /*
 472                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 473                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 474                  * can safely assign to "uint16_t" type variable.
 475                  */
 476                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 477                 ret = hns3vf_dev_mtu_set(dev, mtu);
 478                 if (ret)
 479                         goto cfg_err;
 480                 dev->data->mtu = mtu;
 481         }
 482
 483         ret = hns3vf_dev_configure_vlan(dev);
 484         if (ret)
 485                 goto cfg_err;
 486
 487         hw->adapter_state = HNS3_NIC_CONFIGURED;
 488         return 0;
 489
 490 cfg_err:
 491         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 492         hw->adapter_state = HNS3_NIC_INITIALIZED;
 493
 494         return ret;
 495 }
 496
 497 static int
 498 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 499 {
 500         int ret;
 501
 502         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 503                                 sizeof(mtu), true, NULL, 0);
 504         if (ret)
 505                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 506
 507         return ret;
 508 }
 509
 510 static int
 511 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 512 {
 513         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 514         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 515         int ret;
 516
 517         if (dev->data->dev_started) {
 518                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
 519                          "before configuration", dev->data->port_id);
 520                 return -EBUSY;
 521         }
 522
 523         if (rte_atomic16_read(&hw->reset.resetting)) {
 524                 hns3_err(hw, "Failed to set mtu during resetting");
 525                 return -EIO;
 526         }
 527
 528         rte_spinlock_lock(&hw->lock);
 529         ret = hns3vf_config_mtu(hw, mtu);
 530         if (ret) {
 531                 rte_spinlock_unlock(&hw->lock);
 532                 return ret;
 533         }
 534         if (frame_size > RTE_ETHER_MAX_LEN)
 535                 dev->data->dev_conf.rxmode.offloads |=
 536                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 537         else
 538                 dev->data->dev_conf.rxmode.offloads &=
 539                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 540         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 541         rte_spinlock_unlock(&hw->lock);
 542
 543         return 0;
 544 }
 545
 546 static int
 547 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 548 {
 549         struct hns3_adapter *hns = eth_dev->data->dev_private;
 550         struct hns3_hw *hw = &hns->hw;
 551
 552         info->max_rx_queues = hw->tqps_num;
 553         info->max_tx_queues = hw->tqps_num;
 554         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 555         info->min_rx_bufsize = hw->rx_buf_len;
 556         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 557         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 558
 559         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 560                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 561                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 562                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 563                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 564                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 565                                  DEV_RX_OFFLOAD_KEEP_CRC |
 566                                  DEV_RX_OFFLOAD_SCATTER |
 567                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 568                                  DEV_RX_OFFLOAD_QINQ_STRIP |
 569                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 570                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
 571         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 572         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 573                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 574                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 575                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 576                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 577                                  DEV_TX_OFFLOAD_VLAN_INSERT |
 578                                  DEV_TX_OFFLOAD_QINQ_INSERT |
 579                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 580                                  info->tx_queue_offload_capa);
 581
 582         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 583                 .nb_max = HNS3_MAX_RING_DESC,
 584                 .nb_min = HNS3_MIN_RING_DESC,
 585                 .nb_align = HNS3_ALIGN_RING_DESC,
 586         };
 587
 588         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 589                 .nb_max = HNS3_MAX_RING_DESC,
 590                 .nb_min = HNS3_MIN_RING_DESC,
 591                 .nb_align = HNS3_ALIGN_RING_DESC,
 592         };
 593
 594         info->vmdq_queue_num = 0;
 595
 596         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 597         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 598         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 599         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 600         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 601
 602         return 0;
 603 }
 604
 605 static void
 606 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 607 {
 608         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 609 }
 610
 611 static void
 612 hns3vf_disable_irq0(struct hns3_hw *hw)
 613 {
 614         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 615 }
 616
 617 static void
 618 hns3vf_enable_irq0(struct hns3_hw *hw)
 619 {
 620         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 621 }
 622
 623 static enum hns3vf_evt_cause
 624 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 625 {
 626         struct hns3_hw *hw = &hns->hw;
 627         enum hns3vf_evt_cause ret;
 628         uint32_t cmdq_stat_reg;
 629         uint32_t rst_ing_reg;
 630         uint32_t val;
 631
 632         /* Fetch the events from their corresponding regs */
 633         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 634
 635         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 636                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 637                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 638                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 639                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 640                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 641                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 642                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 643                 if (clearval) {
 644                         hw->reset.stats.global_cnt++;
 645                         hns3_warn(hw, "Global reset detected, clear reset status");
 646                 } else {
 647                         hns3_schedule_delayed_reset(hns);
 648                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 649                 }
 650
 651                 ret = HNS3VF_VECTOR0_EVENT_RST;
 652                 goto out;
 653         }
 654
 655         /* Check for vector0 mailbox(=CMDQ RX) event source */
 656         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
 657                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 658                 ret = HNS3VF_VECTOR0_EVENT_MBX;
 659                 goto out;
 660         }
 661
 662         val = 0;
 663         ret = HNS3VF_VECTOR0_EVENT_OTHER;
 664 out:
 665         if (clearval)
 666                 *clearval = val;
 667         return ret;
 668 }
 669
 670 static void
 671 hns3vf_interrupt_handler(void *param)
 672 {
 673         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 674         struct hns3_adapter *hns = dev->data->dev_private;
 675         struct hns3_hw *hw = &hns->hw;
 676         enum hns3vf_evt_cause event_cause;
 677         uint32_t clearval;
 678
 679         if (hw->irq_thread_id == 0)
 680                 hw->irq_thread_id = pthread_self();
 681
 682         /* Disable interrupt */
 683         hns3vf_disable_irq0(hw);
 684
 685         /* Read out interrupt causes */
 686         event_cause = hns3vf_check_event_cause(hns, &clearval);
 687
 688         switch (event_cause) {
 689         case HNS3VF_VECTOR0_EVENT_RST:
 690                 hns3_schedule_reset(hns);
 691                 break;
 692         case HNS3VF_VECTOR0_EVENT_MBX:
 693                 hns3_dev_handle_mbx_msg(hw);
 694                 break;
 695         default:
 696                 break;
 697         }
 698
 699         /* Clear interrupt causes */
 700         hns3vf_clear_event_cause(hw, clearval);
 701
 702         /* Enable interrupt */
 703         hns3vf_enable_irq0(hw);
 704 }
 705
 706 static int
 707 hns3vf_check_tqp_info(struct hns3_hw *hw)
 708 {
 709         uint16_t tqps_num;
 710
 711         tqps_num = hw->tqps_num;
 712         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
 713                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
 714                                   "range: 1~%d",
 715                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
 716                 return -EINVAL;
 717         }
 718
 719         if (hw->rx_buf_len == 0)
 720                 hw->rx_buf_len = HNS3_DEFAULT_RX_BUF_LEN;
 721         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
 722
 723         return 0;
 724 }
 725
 726 static int
 727 hns3vf_get_queue_info(struct hns3_hw *hw)
 728 {
 729 #define HNS3VF_TQPS_RSS_INFO_LEN        6
 730         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
 731         int ret;
 732
 733         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
 734                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
 735         if (ret) {
 736                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
 737                 return ret;
 738         }
 739
 740         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
 741         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
 742         memcpy(&hw->rx_buf_len, &resp_msg[4], sizeof(uint16_t));
 743
 744         return hns3vf_check_tqp_info(hw);
 745 }
 746
 747 static int
 748 hns3vf_get_queue_depth(struct hns3_hw *hw)
 749 {
 750 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
 751         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
 752         int ret;
 753
 754         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
 755                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
 756         if (ret) {
 757                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
 758                              ret);
 759                 return ret;
 760         }
 761
 762         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
 763         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
 764
 765         return 0;
 766 }
 767
 768 static int
 769 hns3vf_get_tc_info(struct hns3_hw *hw)
 770 {
 771         uint8_t resp_msg;
 772         int ret;
 773
 774         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
 775                                 true, &resp_msg, sizeof(resp_msg));
 776         if (ret) {
 777                 hns3_err(hw, "VF request to get TC info from PF failed %d",
 778                          ret);
 779                 return ret;
 780         }
 781
 782         hw->hw_tc_map = resp_msg;
 783
 784         return 0;
 785 }
 786
 787 static int
 788 hns3vf_get_configuration(struct hns3_hw *hw)
 789 {
 790         int ret;
 791
 792         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
 793
 794         /* Get queue configuration from PF */
 795         ret = hns3vf_get_queue_info(hw);
 796         if (ret)
 797                 return ret;
 798
 799         /* Get queue depth info from PF */
 800         ret = hns3vf_get_queue_depth(hw);
 801         if (ret)
 802                 return ret;
 803
 804         /* Get tc configuration from PF */
 805         return hns3vf_get_tc_info(hw);
 806 }
 807
 808 static int
 809 hns3vf_set_tc_info(struct hns3_adapter *hns)
 810 {
 811         struct hns3_hw *hw = &hns->hw;
 812         uint16_t nb_rx_q = hw->data->nb_rx_queues;
 813         uint16_t nb_tx_q = hw->data->nb_tx_queues;
 814         uint8_t i;
 815
 816         hw->num_tc = 0;
 817         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
 818                 if (hw->hw_tc_map & BIT(i))
 819                         hw->num_tc++;
 820
 821         if (nb_rx_q < hw->num_tc) {
 822                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
 823                          nb_rx_q, hw->num_tc);
 824                 return -EINVAL;
 825         }
 826
 827         if (nb_tx_q < hw->num_tc) {
 828                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
 829                          nb_tx_q, hw->num_tc);
 830                 return -EINVAL;
 831         }
 832
 833         hns3_set_rss_size(hw, nb_rx_q);
 834         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
 835
 836         return 0;
 837 }
 838
 839 static void
 840 hns3vf_request_link_info(struct hns3_hw *hw)
 841 {
 842         uint8_t resp_msg;
 843         int ret;
 844
 845         if (rte_atomic16_read(&hw->reset.resetting))
 846                 return;
 847         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
 848                                 &resp_msg, sizeof(resp_msg));
 849         if (ret)
 850                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
 851 }
 852
 853 static int
 854 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 855 {
 856 #define HNS3VF_VLAN_MBX_MSG_LEN 5
 857         struct hns3_hw *hw = &hns->hw;
 858         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
 859         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
 860         uint8_t is_kill = on ? 0 : 1;
 861
 862         msg_data[0] = is_kill;
 863         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
 864         memcpy(&msg_data[3], &proto, sizeof(proto));
 865
 866         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
 867                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
 868                                  0);
 869 }
 870
 871 static int
 872 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 873 {
 874         struct hns3_adapter *hns = dev->data->dev_private;
 875         struct hns3_hw *hw = &hns->hw;
 876         int ret;
 877
 878         if (rte_atomic16_read(&hw->reset.resetting)) {
 879                 hns3_err(hw,
 880                          "vf set vlan id failed during resetting, vlan_id =%u",
 881                          vlan_id);
 882                 return -EIO;
 883         }
 884         rte_spinlock_lock(&hw->lock);
 885         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
 886         rte_spinlock_unlock(&hw->lock);
 887         if (ret)
 888                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
 889                          vlan_id, ret);
 890
 891         return ret;
 892 }
 893
 894 static int
 895 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
 896 {
 897         uint8_t msg_data;
 898         int ret;
 899
 900         msg_data = enable ? 1 : 0;
 901         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
 902                                 &msg_data, sizeof(msg_data), false, NULL, 0);
 903         if (ret)
 904                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
 905
 906         return ret;
 907 }
 908
 909 static int
 910 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 911 {
 912         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 913         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 914         unsigned int tmp_mask;
 915
 916         tmp_mask = (unsigned int)mask;
 917         /* Vlan stripping setting */
 918         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 919                 rte_spinlock_lock(&hw->lock);
 920                 /* Enable or disable VLAN stripping */
 921                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 922                         hns3vf_en_hw_strip_rxvtag(hw, true);
 923                 else
 924                         hns3vf_en_hw_strip_rxvtag(hw, false);
 925                 rte_spinlock_unlock(&hw->lock);
 926         }
 927
 928         return 0;
 929 }
 930
 931 static int
 932 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
 933 {
 934         struct rte_vlan_filter_conf *vfc;
 935         struct hns3_hw *hw = &hns->hw;
 936         uint16_t vlan_id;
 937         uint64_t vbit;
 938         uint64_t ids;
 939         int ret = 0;
 940         uint32_t i;
 941
 942         vfc = &hw->data->vlan_filter_conf;
 943         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
 944                 if (vfc->ids[i] == 0)
 945                         continue;
 946                 ids = vfc->ids[i];
 947                 while (ids) {
 948                         /*
 949                          * 64 means the num bits of ids, one bit corresponds to
 950                          * one vlan id
 951                          */
 952                         vlan_id = 64 * i;
 953                         /* count trailing zeroes */
 954                         vbit = ~ids & (ids - 1);
 955                         /* clear least significant bit set */
 956                         ids ^= (ids ^ (ids - 1)) ^ vbit;
 957                         for (; vbit;) {
 958                                 vbit >>= 1;
 959                                 vlan_id++;
 960                         }
 961                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
 962                         if (ret) {
 963                                 hns3_err(hw,
 964                                          "VF handle vlan table failed, ret =%d, on = %d",
 965                                          ret, on);
 966                                 return ret;
 967                         }
 968                 }
 969         }
 970
 971         return ret;
 972 }
 973
 974 static int
 975 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
 976 {
 977         return hns3vf_handle_all_vlan_table(hns, 0);
 978 }
 979
 980 static int
 981 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
 982 {
 983         struct hns3_hw *hw = &hns->hw;
 984         struct rte_eth_conf *dev_conf;
 985         bool en;
 986         int ret;
 987
 988         dev_conf = &hw->data->dev_conf;
 989         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
 990                                                                    : false;
 991         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
 992         if (ret)
 993                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
 994                          ret);
 995         return ret;
 996 }
 997
 998 static int
 999 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1000 {
1001         struct hns3_adapter *hns = dev->data->dev_private;
1002         struct rte_eth_dev_data *data = dev->data;
1003         struct hns3_hw *hw = &hns->hw;
1004         int ret;
1005
1006         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1007             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1008             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1009                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1010                               "or hw_vlan_insert_pvid is not support!");
1011         }
1012
1013         /* Apply vlan offload setting */
1014         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1015         if (ret)
1016                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1017
1018         return ret;
1019 }
1020
1021 static int
1022 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1023 {
1024         uint8_t msg_data;
1025
1026         msg_data = alive ? 1 : 0;
1027         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1028                                  sizeof(msg_data), false, NULL, 0);
1029 }
1030
1031 static void
1032 hns3vf_keep_alive_handler(void *param)
1033 {
1034         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1035         struct hns3_adapter *hns = eth_dev->data->dev_private;
1036         struct hns3_hw *hw = &hns->hw;
1037         uint8_t respmsg;
1038         int ret;
1039
1040         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1041                                 false, &respmsg, sizeof(uint8_t));
1042         if (ret)
1043                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1044                          ret);
1045
1046         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1047                           eth_dev);
1048 }
1049
1050 static void
1051 hns3vf_service_handler(void *param)
1052 {
1053         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1054         struct hns3_adapter *hns = eth_dev->data->dev_private;
1055         struct hns3_hw *hw = &hns->hw;
1056
1057         /*
1058          * The query link status and reset processing are executed in the
1059          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1060          * and the query operation will time out after 30ms. In the case of
1061          * multiple PF/VFs, each query failure timeout causes the IMP reset
1062          * interrupt to fail to respond within 100ms.
1063          * Before querying the link status, check whether there is a reset
1064          * pending, and if so, abandon the query.
1065          */
1066         if (!hns3vf_is_reset_pending(hns))
1067                 hns3vf_request_link_info(hw);
1068         else
1069                 hns3_warn(hw, "Cancel the query when reset is pending");
1070
1071         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1072                           eth_dev);
1073 }
1074
1075 static int
1076 hns3vf_init_hardware(struct hns3_adapter *hns)
1077 {
1078         struct hns3_hw *hw = &hns->hw;
1079         uint16_t mtu = hw->data->mtu;
1080         int ret;
1081
1082         ret = hns3vf_set_promisc_mode(hw, true);
1083         if (ret)
1084                 return ret;
1085
1086         ret = hns3vf_config_mtu(hw, mtu);
1087         if (ret)
1088                 goto err_init_hardware;
1089
1090         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1091         if (ret) {
1092                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1093                 goto err_init_hardware;
1094         }
1095
1096         ret = hns3_config_gro(hw, false);
1097         if (ret) {
1098                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1099                 goto err_init_hardware;
1100         }
1101
1102         ret = hns3vf_set_alive(hw, true);
1103         if (ret) {
1104                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1105                 goto err_init_hardware;
1106         }
1107
1108         hns3vf_request_link_info(hw);
1109         return 0;
1110
1111 err_init_hardware:
1112         (void)hns3vf_set_promisc_mode(hw, false);
1113         return ret;
1114 }
1115
1116 static int
1117 hns3vf_clear_vport_list(struct hns3_hw *hw)
1118 {
1119         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1120                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1121                                  NULL, 0);
1122 }
1123
1124 static int
1125 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1126 {
1127         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1128         struct hns3_adapter *hns = eth_dev->data->dev_private;
1129         struct hns3_hw *hw = &hns->hw;
1130         int ret;
1131
1132         PMD_INIT_FUNC_TRACE();
1133
1134         /* Get hardware io base address from pcie BAR2 IO space */
1135         hw->io_base = pci_dev->mem_resource[2].addr;
1136
1137         /* Firmware command queue initialize */
1138         ret = hns3_cmd_init_queue(hw);
1139         if (ret) {
1140                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1141                 goto err_cmd_init_queue;
1142         }
1143
1144         /* Firmware command initialize */
1145         ret = hns3_cmd_init(hw);
1146         if (ret) {
1147                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1148                 goto err_cmd_init;
1149         }
1150
1151         rte_spinlock_init(&hw->mbx_resp.lock);
1152
1153         hns3vf_clear_event_cause(hw, 0);
1154
1155         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1156                                          hns3vf_interrupt_handler, eth_dev);
1157         if (ret) {
1158                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1159                 goto err_intr_callback_register;
1160         }
1161
1162         /* Enable interrupt */
1163         rte_intr_enable(&pci_dev->intr_handle);
1164         hns3vf_enable_irq0(hw);
1165
1166         /* Get configuration from PF */
1167         ret = hns3vf_get_configuration(hw);
1168         if (ret) {
1169                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1170                 goto err_get_config;
1171         }
1172
1173         rte_eth_random_addr(hw->mac.mac_addr); /* Generate a random mac addr */
1174
1175         ret = hns3vf_clear_vport_list(hw);
1176         if (ret) {
1177                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1178                 goto err_get_config;
1179         }
1180
1181         ret = hns3vf_init_hardware(hns);
1182         if (ret)
1183                 goto err_get_config;
1184
1185         hns3_set_default_rss_args(hw);
1186
1187         return 0;
1188
1189 err_get_config:
1190         hns3vf_disable_irq0(hw);
1191         rte_intr_disable(&pci_dev->intr_handle);
1192         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1193                              eth_dev);
1194 err_intr_callback_register:
1195         hns3_cmd_uninit(hw);
1196
1197 err_cmd_init:
1198         hns3_cmd_destroy_queue(hw);
1199
1200 err_cmd_init_queue:
1201         hw->io_base = NULL;
1202
1203         return ret;
1204 }
1205
1206 static void
1207 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1208 {
1209         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1210         struct hns3_adapter *hns = eth_dev->data->dev_private;
1211         struct hns3_hw *hw = &hns->hw;
1212
1213         PMD_INIT_FUNC_TRACE();
1214
1215         hns3_rss_uninit(hns);
1216         (void)hns3vf_set_alive(hw, false);
1217         (void)hns3vf_set_promisc_mode(hw, false);
1218         hns3vf_disable_irq0(hw);
1219         rte_intr_disable(&pci_dev->intr_handle);
1220         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1221                              eth_dev);
1222         hns3_cmd_uninit(hw);
1223         hns3_cmd_destroy_queue(hw);
1224         hw->io_base = NULL;
1225 }
1226
1227 static int
1228 hns3vf_bind_ring_with_vector(struct rte_eth_dev *dev, uint8_t vector_id,
1229                              bool mmap, uint16_t queue_id)
1230
1231 {
1232         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1233         struct hns3_vf_bind_vector_msg bind_msg;
1234         uint16_t code;
1235         int ret;
1236
1237         memset(&bind_msg, 0, sizeof(bind_msg));
1238         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
1239                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
1240         bind_msg.vector_id = vector_id;
1241         bind_msg.ring_num = 1;
1242         bind_msg.param[0].ring_type = HNS3_RING_TYPE_RX;
1243         bind_msg.param[0].tqp_index = queue_id;
1244         bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
1245
1246         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
1247                                 sizeof(bind_msg), false, NULL, 0);
1248         if (ret) {
1249                 hns3_err(hw, "Map TQP %d fail, vector_id is %d, ret is %d.",
1250                          queue_id, vector_id, ret);
1251                 return ret;
1252         }
1253
1254         return 0;
1255 }
1256
1257 static int
1258 hns3vf_do_stop(struct hns3_adapter *hns)
1259 {
1260         struct hns3_hw *hw = &hns->hw;
1261         bool reset_queue;
1262
1263         hw->mac.link_status = ETH_LINK_DOWN;
1264
1265         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1266                 hns3vf_configure_mac_addr(hns, true);
1267                 reset_queue = true;
1268         } else
1269                 reset_queue = false;
1270         return hns3_stop_queues(hns, reset_queue);
1271 }
1272
1273 static void
1274 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1275 {
1276         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1277         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1278         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1279         uint8_t base = 0;
1280         uint8_t vec = 0;
1281         uint16_t q_id;
1282
1283         if (dev->data->dev_conf.intr_conf.rxq == 0)
1284                 return;
1285
1286         /* unmap the ring with vector */
1287         if (rte_intr_allow_others(intr_handle)) {
1288                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1289                 base = RTE_INTR_VEC_RXTX_OFFSET;
1290         }
1291         if (rte_intr_dp_is_en(intr_handle)) {
1292                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1293                         (void)hns3vf_bind_ring_with_vector(dev, vec, false,
1294                                                            q_id);
1295                         if (vec < base + intr_handle->nb_efd - 1)
1296                                 vec++;
1297                 }
1298         }
1299         /* Clean datapath event and queue/vec mapping */
1300         rte_intr_efd_disable(intr_handle);
1301         if (intr_handle->intr_vec) {
1302                 rte_free(intr_handle->intr_vec);
1303                 intr_handle->intr_vec = NULL;
1304         }
1305 }
1306
1307 static void
1308 hns3vf_dev_stop(struct rte_eth_dev *dev)
1309 {
1310         struct hns3_adapter *hns = dev->data->dev_private;
1311         struct hns3_hw *hw = &hns->hw;
1312
1313         PMD_INIT_FUNC_TRACE();
1314
1315         hw->adapter_state = HNS3_NIC_STOPPING;
1316         hns3_set_rxtx_function(dev);
1317         rte_wmb();
1318         /* Disable datapath on secondary process. */
1319         hns3_mp_req_stop_rxtx(dev);
1320         /* Prevent crashes when queues are still in use. */
1321         rte_delay_ms(hw->tqps_num);
1322
1323         rte_spinlock_lock(&hw->lock);
1324         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1325                 hns3vf_do_stop(hns);
1326                 hns3_dev_release_mbufs(hns);
1327                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1328         }
1329         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1330         rte_spinlock_unlock(&hw->lock);
1331
1332         hns3vf_unmap_rx_interrupt(dev);
1333 }
1334
1335 static void
1336 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1337 {
1338         struct hns3_adapter *hns = eth_dev->data->dev_private;
1339         struct hns3_hw *hw = &hns->hw;
1340
1341         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1342                 return;
1343
1344         if (hw->adapter_state == HNS3_NIC_STARTED)
1345                 hns3vf_dev_stop(eth_dev);
1346
1347         hw->adapter_state = HNS3_NIC_CLOSING;
1348         hns3_reset_abort(hns);
1349         hw->adapter_state = HNS3_NIC_CLOSED;
1350         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1351         hns3vf_configure_all_mc_mac_addr(hns, true);
1352         hns3vf_remove_all_vlan_table(hns);
1353         hns3vf_uninit_vf(eth_dev);
1354         hns3_free_all_queues(eth_dev);
1355         rte_free(hw->reset.wait_data);
1356         rte_free(eth_dev->process_private);
1357         eth_dev->process_private = NULL;
1358         hns3_mp_uninit_primary();
1359         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1360 }
1361
1362 static int
1363 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1364                        __rte_unused int wait_to_complete)
1365 {
1366         struct hns3_adapter *hns = eth_dev->data->dev_private;
1367         struct hns3_hw *hw = &hns->hw;
1368         struct hns3_mac *mac = &hw->mac;
1369         struct rte_eth_link new_link;
1370
1371         memset(&new_link, 0, sizeof(new_link));
1372         switch (mac->link_speed) {
1373         case ETH_SPEED_NUM_10M:
1374         case ETH_SPEED_NUM_100M:
1375         case ETH_SPEED_NUM_1G:
1376         case ETH_SPEED_NUM_10G:
1377         case ETH_SPEED_NUM_25G:
1378         case ETH_SPEED_NUM_40G:
1379         case ETH_SPEED_NUM_50G:
1380         case ETH_SPEED_NUM_100G:
1381                 new_link.link_speed = mac->link_speed;
1382                 break;
1383         default:
1384                 new_link.link_speed = ETH_SPEED_NUM_100M;
1385                 break;
1386         }
1387
1388         new_link.link_duplex = mac->link_duplex;
1389         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1390         new_link.link_autoneg =
1391             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1392
1393         return rte_eth_linkstatus_set(eth_dev, &new_link);
1394 }
1395
1396 static int
1397 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1398 {
1399         struct hns3_hw *hw = &hns->hw;
1400         int ret;
1401
1402         ret = hns3vf_set_tc_info(hns);
1403         if (ret)
1404                 return ret;
1405
1406         ret = hns3_start_queues(hns, reset_queue);
1407         if (ret) {
1408                 hns3_err(hw, "Failed to start queues: %d", ret);
1409                 return ret;
1410         }
1411
1412         return 0;
1413 }
1414
1415 static int
1416 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1417 {
1418         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1419         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1420         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1421         uint32_t intr_vector;
1422         uint8_t base = 0;
1423         uint8_t vec = 0;
1424         uint16_t q_id;
1425         int ret;
1426
1427         if (dev->data->dev_conf.intr_conf.rxq == 0)
1428                 return 0;
1429
1430         /* disable uio/vfio intr/eventfd mapping */
1431         rte_intr_disable(intr_handle);
1432
1433         /* check and configure queue intr-vector mapping */
1434         if (rte_intr_cap_multiple(intr_handle) ||
1435             !RTE_ETH_DEV_SRIOV(dev).active) {
1436                 intr_vector = hw->used_rx_queues;
1437                 /* It creates event fd for each intr vector when MSIX is used */
1438                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1439                         return -EINVAL;
1440         }
1441         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1442                 intr_handle->intr_vec =
1443                         rte_zmalloc("intr_vec",
1444                                     hw->used_rx_queues * sizeof(int), 0);
1445                 if (intr_handle->intr_vec == NULL) {
1446                         hns3_err(hw, "Failed to allocate %d rx_queues"
1447                                      " intr_vec", hw->used_rx_queues);
1448                         ret = -ENOMEM;
1449                         goto vf_alloc_intr_vec_error;
1450                 }
1451         }
1452
1453         if (rte_intr_allow_others(intr_handle)) {
1454                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1455                 base = RTE_INTR_VEC_RXTX_OFFSET;
1456         }
1457         if (rte_intr_dp_is_en(intr_handle)) {
1458                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1459                         ret = hns3vf_bind_ring_with_vector(dev, vec, true,
1460                                                            q_id);
1461                         if (ret)
1462                                 goto vf_bind_vector_error;
1463                         intr_handle->intr_vec[q_id] = vec;
1464                         if (vec < base + intr_handle->nb_efd - 1)
1465                                 vec++;
1466                 }
1467         }
1468         rte_intr_enable(intr_handle);
1469         return 0;
1470
1471 vf_bind_vector_error:
1472         rte_intr_efd_disable(intr_handle);
1473         if (intr_handle->intr_vec) {
1474                 free(intr_handle->intr_vec);
1475                 intr_handle->intr_vec = NULL;
1476         }
1477         return ret;
1478 vf_alloc_intr_vec_error:
1479         rte_intr_efd_disable(intr_handle);
1480         return ret;
1481 }
1482
1483 static int
1484 hns3vf_dev_start(struct rte_eth_dev *dev)
1485 {
1486         struct hns3_adapter *hns = dev->data->dev_private;
1487         struct hns3_hw *hw = &hns->hw;
1488         int ret;
1489
1490         PMD_INIT_FUNC_TRACE();
1491         if (rte_atomic16_read(&hw->reset.resetting))
1492                 return -EBUSY;
1493
1494         rte_spinlock_lock(&hw->lock);
1495         hw->adapter_state = HNS3_NIC_STARTING;
1496         ret = hns3vf_do_start(hns, true);
1497         if (ret) {
1498                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1499                 rte_spinlock_unlock(&hw->lock);
1500                 return ret;
1501         }
1502         hw->adapter_state = HNS3_NIC_STARTED;
1503         rte_spinlock_unlock(&hw->lock);
1504
1505         ret = hns3vf_map_rx_interrupt(dev);
1506         if (ret)
1507                 return ret;
1508         hns3_set_rxtx_function(dev);
1509         hns3_mp_req_start_rxtx(dev);
1510         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
1511         return ret;
1512 }
1513
1514 static bool
1515 is_vf_reset_done(struct hns3_hw *hw)
1516 {
1517 #define HNS3_FUN_RST_ING_BITS \
1518         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
1519          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
1520          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
1521          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
1522
1523         uint32_t val;
1524
1525         if (hw->reset.level == HNS3_VF_RESET) {
1526                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1527                 if (val & HNS3_VF_RST_ING_BIT)
1528                         return false;
1529         } else {
1530                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1531                 if (val & HNS3_FUN_RST_ING_BITS)
1532                         return false;
1533         }
1534         return true;
1535 }
1536
1537 bool
1538 hns3vf_is_reset_pending(struct hns3_adapter *hns)
1539 {
1540         struct hns3_hw *hw = &hns->hw;
1541         enum hns3_reset_level reset;
1542
1543         hns3vf_check_event_cause(hns, NULL);
1544         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
1545         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
1546                 hns3_warn(hw, "High level reset %d is pending", reset);
1547                 return true;
1548         }
1549         return false;
1550 }
1551
1552 static int
1553 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
1554 {
1555         struct hns3_hw *hw = &hns->hw;
1556         struct hns3_wait_data *wait_data = hw->reset.wait_data;
1557         struct timeval tv;
1558
1559         if (wait_data->result == HNS3_WAIT_SUCCESS) {
1560                 /*
1561                  * After vf reset is ready, the PF may not have completed
1562                  * the reset processing. The vf sending mbox to PF may fail
1563                  * during the pf reset, so it is better to add extra delay.
1564                  */
1565                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
1566                     hw->reset.level == HNS3_FLR_RESET)
1567                         return 0;
1568                 /* Reset retry process, no need to add extra delay. */
1569                 if (hw->reset.attempts)
1570                         return 0;
1571                 if (wait_data->check_completion == NULL)
1572                         return 0;
1573
1574                 wait_data->check_completion = NULL;
1575                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
1576                 wait_data->count = 1;
1577                 wait_data->result = HNS3_WAIT_REQUEST;
1578                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
1579                                   wait_data);
1580                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
1581                 return -EAGAIN;
1582         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
1583                 gettimeofday(&tv, NULL);
1584                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
1585                           tv.tv_sec, tv.tv_usec);
1586                 return -ETIME;
1587         } else if (wait_data->result == HNS3_WAIT_REQUEST)
1588                 return -EAGAIN;
1589
1590         wait_data->hns = hns;
1591         wait_data->check_completion = is_vf_reset_done;
1592         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
1593                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
1594         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
1595         wait_data->count = HNS3VF_RESET_WAIT_CNT;
1596         wait_data->result = HNS3_WAIT_REQUEST;
1597         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
1598         return -EAGAIN;
1599 }
1600
1601 static int
1602 hns3vf_prepare_reset(struct hns3_adapter *hns)
1603 {
1604         struct hns3_hw *hw = &hns->hw;
1605         int ret = 0;
1606
1607         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
1608                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
1609                                         0, true, NULL, 0);
1610         }
1611         rte_atomic16_set(&hw->reset.disable_cmd, 1);
1612
1613         return ret;
1614 }
1615
1616 static int
1617 hns3vf_stop_service(struct hns3_adapter *hns)
1618 {
1619         struct hns3_hw *hw = &hns->hw;
1620         struct rte_eth_dev *eth_dev;
1621
1622         eth_dev = &rte_eth_devices[hw->data->port_id];
1623         rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
1624         hw->mac.link_status = ETH_LINK_DOWN;
1625
1626         hns3_set_rxtx_function(eth_dev);
1627         rte_wmb();
1628         /* Disable datapath on secondary process. */
1629         hns3_mp_req_stop_rxtx(eth_dev);
1630         rte_delay_ms(hw->tqps_num);
1631
1632         rte_spinlock_lock(&hw->lock);
1633         if (hw->adapter_state == HNS3_NIC_STARTED ||
1634             hw->adapter_state == HNS3_NIC_STOPPING) {
1635                 hns3vf_do_stop(hns);
1636                 hw->reset.mbuf_deferred_free = true;
1637         } else
1638                 hw->reset.mbuf_deferred_free = false;
1639
1640         /*
1641          * It is cumbersome for hardware to pick-and-choose entries for deletion
1642          * from table space. Hence, for function reset software intervention is
1643          * required to delete the entries.
1644          */
1645         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
1646                 hns3vf_configure_all_mc_mac_addr(hns, true);
1647         rte_spinlock_unlock(&hw->lock);
1648
1649         return 0;
1650 }
1651
1652 static int
1653 hns3vf_start_service(struct hns3_adapter *hns)
1654 {
1655         struct hns3_hw *hw = &hns->hw;
1656         struct rte_eth_dev *eth_dev;
1657
1658         eth_dev = &rte_eth_devices[hw->data->port_id];
1659         hns3_set_rxtx_function(eth_dev);
1660         hns3_mp_req_start_rxtx(eth_dev);
1661
1662         hns3vf_service_handler(eth_dev);
1663         return 0;
1664 }
1665
1666 static int
1667 hns3vf_restore_conf(struct hns3_adapter *hns)
1668 {
1669         struct hns3_hw *hw = &hns->hw;
1670         int ret;
1671
1672         ret = hns3vf_configure_mac_addr(hns, false);
1673         if (ret)
1674                 return ret;
1675
1676         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
1677         if (ret)
1678                 goto err_mc_mac;
1679
1680         ret = hns3vf_restore_vlan_conf(hns);
1681         if (ret)
1682                 goto err_vlan_table;
1683
1684         if (hw->adapter_state == HNS3_NIC_STARTED) {
1685                 ret = hns3vf_do_start(hns, false);
1686                 if (ret)
1687                         goto err_vlan_table;
1688                 hns3_info(hw, "hns3vf dev restart successful!");
1689         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
1690                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1691         return 0;
1692
1693 err_vlan_table:
1694         hns3vf_configure_all_mc_mac_addr(hns, true);
1695 err_mc_mac:
1696         hns3vf_configure_mac_addr(hns, true);
1697         return ret;
1698 }
1699
1700 static enum hns3_reset_level
1701 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
1702 {
1703         enum hns3_reset_level reset_level;
1704
1705         /* return the highest priority reset level amongst all */
1706         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
1707                 reset_level = HNS3_VF_RESET;
1708         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
1709                 reset_level = HNS3_VF_FULL_RESET;
1710         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
1711                 reset_level = HNS3_VF_PF_FUNC_RESET;
1712         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
1713                 reset_level = HNS3_VF_FUNC_RESET;
1714         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
1715                 reset_level = HNS3_FLR_RESET;
1716         else
1717                 reset_level = HNS3_NONE_RESET;
1718
1719         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
1720                 return HNS3_NONE_RESET;
1721
1722         return reset_level;
1723 }
1724
1725 static void
1726 hns3vf_reset_service(void *param)
1727 {
1728         struct hns3_adapter *hns = (struct hns3_adapter *)param;
1729         struct hns3_hw *hw = &hns->hw;
1730         enum hns3_reset_level reset_level;
1731         struct timeval tv_delta;
1732         struct timeval tv_start;
1733         struct timeval tv;
1734         uint64_t msec;
1735
1736         /*
1737          * The interrupt is not triggered within the delay time.
1738          * The interrupt may have been lost. It is necessary to handle
1739          * the interrupt to recover from the error.
1740          */
1741         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
1742                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
1743                 hns3_err(hw, "Handling interrupts in delayed tasks");
1744                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
1745                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
1746                 if (reset_level == HNS3_NONE_RESET) {
1747                         hns3_err(hw, "No reset level is set, try global reset");
1748                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1749                 }
1750         }
1751         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
1752
1753         /*
1754          * Hardware reset has been notified, we now have to poll & check if
1755          * hardware has actually completed the reset sequence.
1756          */
1757         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
1758         if (reset_level != HNS3_NONE_RESET) {
1759                 gettimeofday(&tv_start, NULL);
1760                 hns3_reset_process(hns, reset_level);
1761                 gettimeofday(&tv, NULL);
1762                 timersub(&tv, &tv_start, &tv_delta);
1763                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
1764                        tv_delta.tv_usec / USEC_PER_MSEC;
1765                 if (msec > HNS3_RESET_PROCESS_MS)
1766                         hns3_err(hw, "%d handle long time delta %" PRIx64
1767                                  " ms time=%ld.%.6ld",
1768                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
1769         }
1770 }
1771
1772 static int
1773 hns3vf_reinit_dev(struct hns3_adapter *hns)
1774 {
1775         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
1776         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1777         struct hns3_hw *hw = &hns->hw;
1778         int ret;
1779
1780         if (hw->reset.level == HNS3_VF_FULL_RESET) {
1781                 rte_intr_disable(&pci_dev->intr_handle);
1782                 hns3vf_set_bus_master(pci_dev, true);
1783         }
1784
1785         /* Firmware command initialize */
1786         ret = hns3_cmd_init(hw);
1787         if (ret) {
1788                 hns3_err(hw, "Failed to init cmd: %d", ret);
1789                 goto err_cmd_init;
1790         }
1791
1792         if (hw->reset.level == HNS3_VF_FULL_RESET) {
1793                 /*
1794                  * UIO enables msix by writing the pcie configuration space
1795                  * vfio_pci enables msix in rte_intr_enable.
1796                  */
1797                 if (pci_dev->kdrv == RTE_KDRV_IGB_UIO ||
1798                     pci_dev->kdrv == RTE_KDRV_UIO_GENERIC) {
1799                         if (hns3vf_enable_msix(pci_dev, true))
1800                                 hns3_err(hw, "Failed to enable msix");
1801                 }
1802
1803                 rte_intr_enable(&pci_dev->intr_handle);
1804         }
1805
1806         ret = hns3_reset_all_queues(hns);
1807         if (ret) {
1808                 hns3_err(hw, "Failed to reset all queues: %d", ret);
1809                 goto err_init;
1810         }
1811
1812         ret = hns3vf_init_hardware(hns);
1813         if (ret) {
1814                 hns3_err(hw, "Failed to init hardware: %d", ret);
1815                 goto err_init;
1816         }
1817
1818         return 0;
1819
1820 err_cmd_init:
1821         hns3vf_set_bus_master(pci_dev, false);
1822 err_init:
1823         hns3_cmd_uninit(hw);
1824         return ret;
1825 }
1826
1827 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
1828         .dev_start          = hns3vf_dev_start,
1829         .dev_stop           = hns3vf_dev_stop,
1830         .dev_close          = hns3vf_dev_close,
1831         .mtu_set            = hns3vf_dev_mtu_set,
1832         .stats_get          = hns3_stats_get,
1833         .stats_reset        = hns3_stats_reset,
1834         .xstats_get         = hns3_dev_xstats_get,
1835         .xstats_get_names   = hns3_dev_xstats_get_names,
1836         .xstats_reset       = hns3_dev_xstats_reset,
1837         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
1838         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
1839         .dev_infos_get      = hns3vf_dev_infos_get,
1840         .rx_queue_setup     = hns3_rx_queue_setup,
1841         .tx_queue_setup     = hns3_tx_queue_setup,
1842         .rx_queue_release   = hns3_dev_rx_queue_release,
1843         .tx_queue_release   = hns3_dev_tx_queue_release,
1844         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
1845         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
1846         .dev_configure      = hns3vf_dev_configure,
1847         .mac_addr_add       = hns3vf_add_mac_addr,
1848         .mac_addr_remove    = hns3vf_remove_mac_addr,
1849         .mac_addr_set       = hns3vf_set_default_mac_addr,
1850         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
1851         .link_update        = hns3vf_dev_link_update,
1852         .rss_hash_update    = hns3_dev_rss_hash_update,
1853         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
1854         .reta_update        = hns3_dev_rss_reta_update,
1855         .reta_query         = hns3_dev_rss_reta_query,
1856         .filter_ctrl        = hns3_dev_filter_ctrl,
1857         .vlan_filter_set    = hns3vf_vlan_filter_set,
1858         .vlan_offload_set   = hns3vf_vlan_offload_set,
1859         .get_reg            = hns3_get_regs,
1860         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
1861 };
1862
1863 static const struct hns3_reset_ops hns3vf_reset_ops = {
1864         .reset_service       = hns3vf_reset_service,
1865         .stop_service        = hns3vf_stop_service,
1866         .prepare_reset       = hns3vf_prepare_reset,
1867         .wait_hardware_ready = hns3vf_wait_hardware_ready,
1868         .reinit_dev          = hns3vf_reinit_dev,
1869         .restore_conf        = hns3vf_restore_conf,
1870         .start_service       = hns3vf_start_service,
1871 };
1872
1873 static int
1874 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
1875 {
1876         struct hns3_adapter *hns = eth_dev->data->dev_private;
1877         struct hns3_hw *hw = &hns->hw;
1878         int ret;
1879
1880         PMD_INIT_FUNC_TRACE();
1881
1882         eth_dev->process_private = (struct hns3_process_private *)
1883             rte_zmalloc_socket("hns3_filter_list",
1884                                sizeof(struct hns3_process_private),
1885                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
1886         if (eth_dev->process_private == NULL) {
1887                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
1888                 return -ENOMEM;
1889         }
1890
1891         /* initialize flow filter lists */
1892         hns3_filterlist_init(eth_dev);
1893
1894         hns3_set_rxtx_function(eth_dev);
1895         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
1896         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1897                 hns3_mp_init_secondary();
1898                 hw->secondary_cnt++;
1899                 return 0;
1900         }
1901
1902         hns3_mp_init_primary();
1903
1904         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
1905         hns->is_vf = true;
1906         hw->data = eth_dev->data;
1907
1908         ret = hns3_reset_init(hw);
1909         if (ret)
1910                 goto err_init_reset;
1911         hw->reset.ops = &hns3vf_reset_ops;
1912
1913         ret = hns3vf_init_vf(eth_dev);
1914         if (ret) {
1915                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
1916                 goto err_init_vf;
1917         }
1918
1919         /* Allocate memory for storing MAC addresses */
1920         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
1921                                                sizeof(struct rte_ether_addr) *
1922                                                HNS3_VF_UC_MACADDR_NUM, 0);
1923         if (eth_dev->data->mac_addrs == NULL) {
1924                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
1925                              "to store MAC addresses",
1926                              sizeof(struct rte_ether_addr) *
1927                              HNS3_VF_UC_MACADDR_NUM);
1928                 ret = -ENOMEM;
1929                 goto err_rte_zmalloc;
1930         }
1931
1932         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
1933                             &eth_dev->data->mac_addrs[0]);
1934         hw->adapter_state = HNS3_NIC_INITIALIZED;
1935         /*
1936          * Pass the information to the rte_eth_dev_close() that it should also
1937          * release the private port resources.
1938          */
1939         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1940
1941         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
1942                 hns3_err(hw, "Reschedule reset service after dev_init");
1943                 hns3_schedule_reset(hns);
1944         } else {
1945                 /* IMP will wait ready flag before reset */
1946                 hns3_notify_reset_ready(hw, false);
1947         }
1948         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1949                           eth_dev);
1950         return 0;
1951
1952 err_rte_zmalloc:
1953         hns3vf_uninit_vf(eth_dev);
1954
1955 err_init_vf:
1956         rte_free(hw->reset.wait_data);
1957
1958 err_init_reset:
1959         eth_dev->dev_ops = NULL;
1960         eth_dev->rx_pkt_burst = NULL;
1961         eth_dev->tx_pkt_burst = NULL;
1962         eth_dev->tx_pkt_prepare = NULL;
1963         rte_free(eth_dev->process_private);
1964         eth_dev->process_private = NULL;
1965
1966         return ret;
1967 }
1968
1969 static int
1970 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
1971 {
1972         struct hns3_adapter *hns = eth_dev->data->dev_private;
1973         struct hns3_hw *hw = &hns->hw;
1974
1975         PMD_INIT_FUNC_TRACE();
1976
1977         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1978                 return -EPERM;
1979
1980         eth_dev->dev_ops = NULL;
1981         eth_dev->rx_pkt_burst = NULL;
1982         eth_dev->tx_pkt_burst = NULL;
1983         eth_dev->tx_pkt_prepare = NULL;
1984
1985         if (hw->adapter_state < HNS3_NIC_CLOSING)
1986                 hns3vf_dev_close(eth_dev);
1987
1988         hw->adapter_state = HNS3_NIC_REMOVED;
1989         return 0;
1990 }
1991
1992 static int
1993 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1994                      struct rte_pci_device *pci_dev)
1995 {
1996         return rte_eth_dev_pci_generic_probe(pci_dev,
1997                                              sizeof(struct hns3_adapter),
1998                                              hns3vf_dev_init);
1999 }
2000
2001 static int
2002 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2003 {
2004         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2005 }
2006
2007 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2008         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2009         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2010         { .vendor_id = 0, /* sentinel */ },
2011 };
2012
2013 static struct rte_pci_driver rte_hns3vf_pmd = {
2014         .id_table = pci_id_hns3vf_map,
2015         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2016         .probe = eth_hns3vf_pci_probe,
2017         .remove = eth_hns3vf_pci_remove,
2018 };
2019
2020 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2021 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2022 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");