drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
  48                                    __rte_unused int wait_to_complete);
  49
  50 /* set PCI bus mastering */
  51 static int
  52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  53 {
  54         uint16_t reg;
  55         int ret;
  56
  57         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  58         if (ret < 0) {
  59                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  60                              PCI_COMMAND);
  61                 return ret;
  62         }
  63
  64         if (op)
  65                 /* set the master bit */
  66                 reg |= PCI_COMMAND_MASTER;
  67         else
  68                 reg &= ~(PCI_COMMAND_MASTER);
  69
  70         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  71 }
  72
  73 /**
  74  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  75  * @cap: the capability
  76  *
  77  * Return the address of the given capability within the PCI capability list.
  78  */
  79 static int
  80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  81 {
  82 #define MAX_PCIE_CAPABILITY 48
  83         uint16_t status;
  84         uint8_t pos;
  85         uint8_t id;
  86         int ttl;
  87         int ret;
  88
  89         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  90         if (ret < 0) {
  91                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  92                 return 0;
  93         }
  94
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 100                                   PCI_CAPABILITY_LIST);
 101         if (ret < 0) {
 102                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 103                              PCI_CAPABILITY_LIST);
 104                 return 0;
 105         }
 106
 107         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 108                 ret = rte_pci_read_config(device, &id, sizeof(id),
 109                                           (pos + PCI_CAP_LIST_ID));
 110                 if (ret < 0) {
 111                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 112                                      (pos + PCI_CAP_LIST_ID));
 113                         break;
 114                 }
 115
 116                 if (id == 0xFF)
 117                         break;
 118
 119                 if (id == cap)
 120                         return (int)pos;
 121
 122                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 123                                           (pos + PCI_CAP_LIST_NEXT));
 124                 if (ret < 0) {
 125                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 126                                      (pos + PCI_CAP_LIST_NEXT));
 127                         break;
 128                 }
 129         }
 130         return 0;
 131 }
 132
 133 static int
 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 135 {
 136         uint16_t control;
 137         int pos;
 138         int ret;
 139
 140         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 141         if (pos) {
 142                 ret = rte_pci_read_config(device, &control, sizeof(control),
 143                                     (pos + PCI_MSIX_FLAGS));
 144                 if (ret < 0) {
 145                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 146                                      (pos + PCI_MSIX_FLAGS));
 147                         return -ENXIO;
 148                 }
 149
 150                 if (op)
 151                         control |= PCI_MSIX_FLAGS_ENABLE;
 152                 else
 153                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 154                 ret = rte_pci_write_config(device, &control, sizeof(control),
 155                                           (pos + PCI_MSIX_FLAGS));
 156                 if (ret < 0) {
 157                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 158                                     (pos + PCI_MSIX_FLAGS));
 159                         return -ENXIO;
 160                 }
 161
 162                 return 0;
 163         }
 164
 165         return -ENXIO;
 166 }
 167
 168 static int
 169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 170 {
 171         /* mac address was checked by upper level interface */
 172         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 173         int ret;
 174
 175         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 176                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 177                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 178         if (ret) {
 179                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 180                                       mac_addr);
 181                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 182                          mac_str, ret);
 183         }
 184         return ret;
 185 }
 186
 187 static int
 188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 189 {
 190         /* mac address was checked by upper level interface */
 191         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 192         int ret;
 193
 194         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 195                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 196                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 197                                 false, NULL, 0);
 198         if (ret) {
 199                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 200                                       mac_addr);
 201                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 202                          mac_str, ret);
 203         }
 204         return ret;
 205 }
 206
 207 static int
 208 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 209                     __rte_unused uint32_t idx,
 210                     __rte_unused uint32_t pool)
 211 {
 212         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 213         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 214         int ret;
 215
 216         rte_spinlock_lock(&hw->lock);
 217
 218         /*
 219          * In hns3 network engine adding UC and MC mac address with different
 220          * commands with firmware. We need to determine whether the input
 221          * address is a UC or a MC address to call different commands.
 222          * By the way, it is recommended calling the API function named
 223          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 224          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 225          * may affect the specifications of UC mac addresses.
 226          */
 227         if (rte_is_multicast_ether_addr(mac_addr)) {
 228                 if (hns3_find_duplicate_mc_addr(hw, mac_addr)) {
 229                         rte_spinlock_unlock(&hw->lock);
 230                         return -EINVAL;
 231                 }
 232                 ret = hw->ops.add_mc_mac_addr(hw, mac_addr);
 233         } else {
 234                 ret = hw->ops.add_uc_mac_addr(hw, mac_addr);
 235         }
 236
 237         rte_spinlock_unlock(&hw->lock);
 238         if (ret) {
 239                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 240                                       mac_addr);
 241                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 242                          ret);
 243         }
 244
 245         return ret;
 246 }
 247
 248 static void
 249 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 250 {
 251         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 252         /* index will be checked by upper level rte interface */
 253         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 254         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 255         int ret;
 256
 257         rte_spinlock_lock(&hw->lock);
 258
 259         if (rte_is_multicast_ether_addr(mac_addr))
 260                 ret = hw->ops.del_mc_mac_addr(hw, mac_addr);
 261         else
 262                 ret = hw->ops.del_uc_mac_addr(hw, mac_addr);
 263
 264         rte_spinlock_unlock(&hw->lock);
 265         if (ret) {
 266                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 267                                       mac_addr);
 268                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 269                          mac_str, ret);
 270         }
 271 }
 272
 273 static int
 274 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 275                             struct rte_ether_addr *mac_addr)
 276 {
 277 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 278         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 279         struct rte_ether_addr *old_addr;
 280         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 281         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 282         int ret;
 283
 284         /*
 285          * It has been guaranteed that input parameter named mac_addr is valid
 286          * address in the rte layer of DPDK framework.
 287          */
 288         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 289         rte_spinlock_lock(&hw->lock);
 290         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 291         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 292                RTE_ETHER_ADDR_LEN);
 293
 294         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 295                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 296                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 297         if (ret) {
 298                 /*
 299                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 300                  * driver. When user has configured a MAC address for VF device
 301                  * by "ip link set ..." command based on the PF device, the hns3
 302                  * PF kernel ethdev driver does not allow VF driver to request
 303                  * reconfiguring a different default MAC address, and return
 304                  * -EPREM to VF driver through mailbox.
 305                  */
 306                 if (ret == -EPERM) {
 307                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 308                                               old_addr);
 309                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 310                                   mac_str);
 311                 } else {
 312                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 313                                               mac_addr);
 314                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 315                                  mac_str, ret);
 316                 }
 317         }
 318
 319         rte_ether_addr_copy(mac_addr,
 320                             (struct rte_ether_addr *)hw->mac.mac_addr);
 321         rte_spinlock_unlock(&hw->lock);
 322
 323         return ret;
 324 }
 325
 326 static int
 327 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 328 {
 329         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 330         struct hns3_hw *hw = &hns->hw;
 331         struct hns3_hw_ops *ops = &hw->ops;
 332         struct rte_ether_addr *addr;
 333         int err = 0;
 334         int ret;
 335         int i;
 336
 337         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 338                 addr = &hw->data->mac_addrs[i];
 339                 if (rte_is_zero_ether_addr(addr))
 340                         continue;
 341                 if (rte_is_multicast_ether_addr(addr))
 342                         ret = del ? ops->del_mc_mac_addr(hw, addr) :
 343                               ops->add_mc_mac_addr(hw, addr);
 344                 else
 345                         ret = del ? ops->del_uc_mac_addr(hw, addr) :
 346                               ops->add_uc_mac_addr(hw, addr);
 347
 348                 if (ret) {
 349                         err = ret;
 350                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 351                                               addr);
 352                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 353                                  "ret = %d.", del ? "remove" : "restore",
 354                                  mac_str, i, ret);
 355                 }
 356         }
 357         return err;
 358 }
 359
 360 static int
 361 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 362                        struct rte_ether_addr *mac_addr)
 363 {
 364         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 365         int ret;
 366
 367         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 368                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 369                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 370                                 NULL, 0);
 371         if (ret) {
 372                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 373                                       mac_addr);
 374                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 375                          mac_str, ret);
 376         }
 377
 378         return ret;
 379 }
 380
 381 static int
 382 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 383                           struct rte_ether_addr *mac_addr)
 384 {
 385         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 386         int ret;
 387
 388         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 389                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 390                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 391                                 NULL, 0);
 392         if (ret) {
 393                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 394                                       mac_addr);
 395                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 396                          mac_str, ret);
 397         }
 398
 399         return ret;
 400 }
 401
 402 static int
 403 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 404                              struct rte_ether_addr *mc_addr_set,
 405                              uint32_t nb_mc_addr)
 406 {
 407         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 408         struct rte_ether_addr *addr;
 409         uint32_t i;
 410         uint32_t j;
 411
 412         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 413                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
 414                          "invalid. valid range: 0~%d",
 415                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 416                 return -EINVAL;
 417         }
 418
 419         /* Check if input mac addresses are valid */
 420         for (i = 0; i < nb_mc_addr; i++) {
 421                 addr = &mc_addr_set[i];
 422                 if (!rte_is_multicast_ether_addr(addr)) {
 423                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 424                                               addr);
 425                         hns3_err(hw,
 426                                  "failed to set mc mac addr, addr(%s) invalid.",
 427                                  mac_str);
 428                         return -EINVAL;
 429                 }
 430
 431                 /* Check if there are duplicate addresses */
 432                 for (j = i + 1; j < nb_mc_addr; j++) {
 433                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 434                                 hns3_ether_format_addr(mac_str,
 435                                                       RTE_ETHER_ADDR_FMT_SIZE,
 436                                                       addr);
 437                                 hns3_err(hw, "failed to set mc mac addr, "
 438                                          "addrs invalid. two same addrs(%s).",
 439                                          mac_str);
 440                                 return -EINVAL;
 441                         }
 442                 }
 443
 444                 /*
 445                  * Check if there are duplicate addresses between mac_addrs
 446                  * and mc_addr_set
 447                  */
 448                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 449                         if (rte_is_same_ether_addr(addr,
 450                                                    &hw->data->mac_addrs[j])) {
 451                                 hns3_ether_format_addr(mac_str,
 452                                                       RTE_ETHER_ADDR_FMT_SIZE,
 453                                                       addr);
 454                                 hns3_err(hw, "failed to set mc mac addr, "
 455                                          "addrs invalid. addrs(%s) has already "
 456                                          "configured in mac_addr add API",
 457                                          mac_str);
 458                                 return -EINVAL;
 459                         }
 460                 }
 461         }
 462
 463         return 0;
 464 }
 465
 466 static int
 467 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 468                             struct rte_ether_addr *mc_addr_set,
 469                             uint32_t nb_mc_addr)
 470 {
 471         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 472         struct rte_ether_addr *addr;
 473         int cur_addr_num;
 474         int set_addr_num;
 475         int num;
 476         int ret;
 477         int i;
 478
 479         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 480         if (ret)
 481                 return ret;
 482
 483         rte_spinlock_lock(&hw->lock);
 484         cur_addr_num = hw->mc_addrs_num;
 485         for (i = 0; i < cur_addr_num; i++) {
 486                 num = cur_addr_num - i - 1;
 487                 addr = &hw->mc_addrs[num];
 488                 ret = hw->ops.del_mc_mac_addr(hw, addr);
 489                 if (ret) {
 490                         rte_spinlock_unlock(&hw->lock);
 491                         return ret;
 492                 }
 493
 494                 hw->mc_addrs_num--;
 495         }
 496
 497         set_addr_num = (int)nb_mc_addr;
 498         for (i = 0; i < set_addr_num; i++) {
 499                 addr = &mc_addr_set[i];
 500                 ret = hw->ops.add_mc_mac_addr(hw, addr);
 501                 if (ret) {
 502                         rte_spinlock_unlock(&hw->lock);
 503                         return ret;
 504                 }
 505
 506                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 507                 hw->mc_addrs_num++;
 508         }
 509         rte_spinlock_unlock(&hw->lock);
 510
 511         return 0;
 512 }
 513
 514 static int
 515 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 516 {
 517         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 518         struct hns3_hw *hw = &hns->hw;
 519         struct rte_ether_addr *addr;
 520         int err = 0;
 521         int ret;
 522         int i;
 523
 524         for (i = 0; i < hw->mc_addrs_num; i++) {
 525                 addr = &hw->mc_addrs[i];
 526                 if (!rte_is_multicast_ether_addr(addr))
 527                         continue;
 528                 if (del)
 529                         ret = hw->ops.del_mc_mac_addr(hw, addr);
 530                 else
 531                         ret = hw->ops.add_mc_mac_addr(hw, addr);
 532                 if (ret) {
 533                         err = ret;
 534                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 535                                               addr);
 536                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 537                                  del ? "Remove" : "Restore", mac_str, ret);
 538                 }
 539         }
 540         return err;
 541 }
 542
 543 static int
 544 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 545                         bool en_uc_pmc, bool en_mc_pmc)
 546 {
 547         struct hns3_mbx_vf_to_pf_cmd *req;
 548         struct hns3_cmd_desc desc;
 549         int ret;
 550
 551         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 552
 553         /*
 554          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 555          * so there are some features for promiscuous/allmulticast mode in hns3
 556          * VF PMD driver as below:
 557          * 1. The promiscuous/allmulticast mode can be configured successfully
 558          *    only based on the trusted VF device. If based on the non trusted
 559          *    VF device, configuring promiscuous/allmulticast mode will fail.
 560          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 561          *    kernel ethdev driver on the host by the following command:
 562          *      "ip link set <eth num> vf <vf id> turst on"
 563          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 564          *    driver can receive the ingress and outgoing traffic. In the words,
 565          *    all the ingress packets, all the packets sent from the PF and
 566          *    other VFs on the same physical port.
 567          * 3. Note: Because of the hardware constraints, By default vlan filter
 568          *    is enabled and couldn't be turned off based on VF device, so vlan
 569          *    filter is still effective even in promiscuous mode. If upper
 570          *    applications don't call rte_eth_dev_vlan_filter API function to
 571          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 572          *    the packets with vlan tag in promiscuoue mode.
 573          */
 574         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 575         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 576         req->msg[1] = en_bc_pmc ? 1 : 0;
 577         req->msg[2] = en_uc_pmc ? 1 : 0;
 578         req->msg[3] = en_mc_pmc ? 1 : 0;
 579         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 580
 581         ret = hns3_cmd_send(hw, &desc, 1);
 582         if (ret)
 583                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 584
 585         return ret;
 586 }
 587
 588 static int
 589 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 590 {
 591         struct hns3_adapter *hns = dev->data->dev_private;
 592         struct hns3_hw *hw = &hns->hw;
 593         int ret;
 594
 595         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 596         if (ret)
 597                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 598                         ret);
 599         return ret;
 600 }
 601
 602 static int
 603 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 604 {
 605         bool allmulti = dev->data->all_multicast ? true : false;
 606         struct hns3_adapter *hns = dev->data->dev_private;
 607         struct hns3_hw *hw = &hns->hw;
 608         int ret;
 609
 610         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 611         if (ret)
 612                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 613                         ret);
 614         return ret;
 615 }
 616
 617 static int
 618 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 619 {
 620         struct hns3_adapter *hns = dev->data->dev_private;
 621         struct hns3_hw *hw = &hns->hw;
 622         int ret;
 623
 624         if (dev->data->promiscuous)
 625                 return 0;
 626
 627         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 628         if (ret)
 629                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 630                         ret);
 631         return ret;
 632 }
 633
 634 static int
 635 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 636 {
 637         struct hns3_adapter *hns = dev->data->dev_private;
 638         struct hns3_hw *hw = &hns->hw;
 639         int ret;
 640
 641         if (dev->data->promiscuous)
 642                 return 0;
 643
 644         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 645         if (ret)
 646                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 647                         ret);
 648         return ret;
 649 }
 650
 651 static int
 652 hns3vf_restore_promisc(struct hns3_adapter *hns)
 653 {
 654         struct hns3_hw *hw = &hns->hw;
 655         bool allmulti = hw->data->all_multicast ? true : false;
 656
 657         if (hw->data->promiscuous)
 658                 return hns3vf_set_promisc_mode(hw, true, true, true);
 659
 660         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 661 }
 662
 663 static int
 664 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 665                              bool mmap, enum hns3_ring_type queue_type,
 666                              uint16_t queue_id)
 667 {
 668         struct hns3_vf_bind_vector_msg bind_msg;
 669         const char *op_str;
 670         uint16_t code;
 671         int ret;
 672
 673         memset(&bind_msg, 0, sizeof(bind_msg));
 674         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 675                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 676         bind_msg.vector_id = vector_id;
 677
 678         if (queue_type == HNS3_RING_TYPE_RX)
 679                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 680         else
 681                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 682
 683         bind_msg.param[0].ring_type = queue_type;
 684         bind_msg.ring_num = 1;
 685         bind_msg.param[0].tqp_index = queue_id;
 686         op_str = mmap ? "Map" : "Unmap";
 687         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 688                                 sizeof(bind_msg), false, NULL, 0);
 689         if (ret)
 690                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 691                          op_str, queue_id, bind_msg.vector_id, ret);
 692
 693         return ret;
 694 }
 695
 696 static int
 697 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 698 {
 699         uint16_t vec;
 700         int ret;
 701         int i;
 702
 703         /*
 704          * In hns3 network engine, vector 0 is always the misc interrupt of this
 705          * function, vector 1~N can be used respectively for the queues of the
 706          * function. Tx and Rx queues with the same number share the interrupt
 707          * vector. In the initialization clearing the all hardware mapping
 708          * relationship configurations between queues and interrupt vectors is
 709          * needed, so some error caused by the residual configurations, such as
 710          * the unexpected Tx interrupt, can be avoid.
 711          */
 712         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 713         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 714                 vec = vec - 1; /* the last interrupt is reserved */
 715         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 716         for (i = 0; i < hw->intr_tqps_num; i++) {
 717                 /*
 718                  * Set gap limiter/rate limiter/quanity limiter algorithm
 719                  * configuration for interrupt coalesce of queue's interrupt.
 720                  */
 721                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 722                                        HNS3_TQP_INTR_GL_DEFAULT);
 723                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 724                                        HNS3_TQP_INTR_GL_DEFAULT);
 725                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 726                 /*
 727                  * QL(quantity limiter) is not used currently, just set 0 to
 728                  * close it.
 729                  */
 730                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 731
 732                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 733                                                    HNS3_RING_TYPE_TX, i);
 734                 if (ret) {
 735                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 736                                           "vector: %u, ret=%d", i, vec, ret);
 737                         return ret;
 738                 }
 739
 740                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 741                                                    HNS3_RING_TYPE_RX, i);
 742                 if (ret) {
 743                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 744                                           "vector: %u, ret=%d", i, vec, ret);
 745                         return ret;
 746                 }
 747         }
 748
 749         return 0;
 750 }
 751
 752 static int
 753 hns3vf_dev_configure(struct rte_eth_dev *dev)
 754 {
 755         struct hns3_adapter *hns = dev->data->dev_private;
 756         struct hns3_hw *hw = &hns->hw;
 757         struct rte_eth_conf *conf = &dev->data->dev_conf;
 758         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 759         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 760         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 761         struct rte_eth_rss_conf rss_conf;
 762         bool gro_en;
 763         int ret;
 764
 765         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 766
 767         /*
 768          * Some versions of hardware network engine does not support
 769          * individually enable/disable/reset the Tx or Rx queue. These devices
 770          * must enable/disable/reset Tx and Rx queues at the same time. When the
 771          * numbers of Tx queues allocated by upper applications are not equal to
 772          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 773          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 774          * work as usual. But these fake queues are imperceptible, and can not
 775          * be used by upper applications.
 776          */
 777         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 778         if (ret) {
 779                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
 780                 hw->cfg_max_queues = 0;
 781                 return ret;
 782         }
 783
 784         hw->adapter_state = HNS3_NIC_CONFIGURING;
 785         if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
 786                 hns3_err(hw, "setting link speed/duplex not supported");
 787                 ret = -EINVAL;
 788                 goto cfg_err;
 789         }
 790
 791         /* When RSS is not configured, redirect the packet queue 0 */
 792         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
 793                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
 794                 hw->rss_dis_flag = false;
 795                 rss_conf = conf->rx_adv_conf.rss_conf;
 796                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 797                 if (ret)
 798                         goto cfg_err;
 799         }
 800
 801         ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
 802         if (ret != 0)
 803                 goto cfg_err;
 804
 805         ret = hns3vf_dev_configure_vlan(dev);
 806         if (ret)
 807                 goto cfg_err;
 808
 809         /* config hardware GRO */
 810         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
 811         ret = hns3_config_gro(hw, gro_en);
 812         if (ret)
 813                 goto cfg_err;
 814
 815         hns3_init_rx_ptype_tble(dev);
 816
 817         hw->adapter_state = HNS3_NIC_CONFIGURED;
 818         return 0;
 819
 820 cfg_err:
 821         hw->cfg_max_queues = 0;
 822         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 823         hw->adapter_state = HNS3_NIC_INITIALIZED;
 824
 825         return ret;
 826 }
 827
 828 static int
 829 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 830 {
 831         int ret;
 832
 833         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 834                                 sizeof(mtu), true, NULL, 0);
 835         if (ret)
 836                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 837
 838         return ret;
 839 }
 840
 841 static int
 842 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 843 {
 844         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 845         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 846         int ret;
 847
 848         /*
 849          * The hns3 PF/VF devices on the same port share the hardware MTU
 850          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 851          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 852          * driver, there is no need to stop the port for hns3 VF device, and the
 853          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 854          * PF's MTU.
 855          */
 856         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 857                 hns3_err(hw, "Failed to set mtu during resetting");
 858                 return -EIO;
 859         }
 860
 861         /*
 862          * when Rx of scattered packets is off, we have some possibility of
 863          * using vector Rx process function or simple Rx functions in hns3 PMD
 864          * driver. If the input MTU is increased and the maximum length of
 865          * received packets is greater than the length of a buffer for Rx
 866          * packet, the hardware network engine needs to use multiple BDs and
 867          * buffers to store these packets. This will cause problems when still
 868          * using vector Rx process function or simple Rx function to receiving
 869          * packets. So, when Rx of scattered packets is off and device is
 870          * started, it is not permitted to increase MTU so that the maximum
 871          * length of Rx packets is greater than Rx buffer length.
 872          */
 873         if (dev->data->dev_started && !dev->data->scattered_rx &&
 874             frame_size > hw->rx_buf_len) {
 875                 hns3_err(hw, "failed to set mtu because current is "
 876                         "not scattered rx mode");
 877                 return -EOPNOTSUPP;
 878         }
 879
 880         rte_spinlock_lock(&hw->lock);
 881         ret = hns3vf_config_mtu(hw, mtu);
 882         if (ret) {
 883                 rte_spinlock_unlock(&hw->lock);
 884                 return ret;
 885         }
 886         rte_spinlock_unlock(&hw->lock);
 887
 888         return 0;
 889 }
 890
 891 static int
 892 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 893 {
 894         struct hns3_adapter *hns = eth_dev->data->dev_private;
 895         struct hns3_hw *hw = &hns->hw;
 896         uint16_t q_num = hw->tqps_num;
 897
 898         /*
 899          * In interrupt mode, 'max_rx_queues' is set based on the number of
 900          * MSI-X interrupt resources of the hardware.
 901          */
 902         if (hw->data->dev_conf.intr_conf.rxq == 1)
 903                 q_num = hw->intr_tqps_num;
 904
 905         info->max_rx_queues = q_num;
 906         info->max_tx_queues = hw->tqps_num;
 907         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 908         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 909         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 910         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 911         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 912
 913         info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
 914                                  RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
 915                                  RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
 916                                  RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
 917                                  RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 918                                  RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
 919                                  RTE_ETH_RX_OFFLOAD_SCATTER |
 920                                  RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
 921                                  RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
 922                                  RTE_ETH_RX_OFFLOAD_RSS_HASH |
 923                                  RTE_ETH_RX_OFFLOAD_TCP_LRO);
 924         info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 925                                  RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
 926                                  RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
 927                                  RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
 928                                  RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
 929                                  RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
 930                                  RTE_ETH_TX_OFFLOAD_TCP_TSO |
 931                                  RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
 932                                  RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
 933                                  RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
 934                                  RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
 935                                  hns3_txvlan_cap_get(hw));
 936
 937         if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
 938                 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
 939
 940         if (hns3_dev_get_support(hw, INDEP_TXRX))
 941                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 942                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 943
 944         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 945                 .nb_max = HNS3_MAX_RING_DESC,
 946                 .nb_min = HNS3_MIN_RING_DESC,
 947                 .nb_align = HNS3_ALIGN_RING_DESC,
 948         };
 949
 950         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 951                 .nb_max = HNS3_MAX_RING_DESC,
 952                 .nb_min = HNS3_MIN_RING_DESC,
 953                 .nb_align = HNS3_ALIGN_RING_DESC,
 954                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 955                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
 956         };
 957
 958         info->default_rxconf = (struct rte_eth_rxconf) {
 959                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 960                 /*
 961                  * If there are no available Rx buffer descriptors, incoming
 962                  * packets are always dropped by hardware based on hns3 network
 963                  * engine.
 964                  */
 965                 .rx_drop_en = 1,
 966                 .offloads = 0,
 967         };
 968         info->default_txconf = (struct rte_eth_txconf) {
 969                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 970                 .offloads = 0,
 971         };
 972
 973         info->reta_size = hw->rss_ind_tbl_size;
 974         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 975         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 976
 977         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 978         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 979         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 980         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 981         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 982         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 983
 984         return 0;
 985 }
 986
 987 static void
 988 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 989 {
 990         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 991 }
 992
 993 static void
 994 hns3vf_disable_irq0(struct hns3_hw *hw)
 995 {
 996         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 997 }
 998
 999 static void
1000 hns3vf_enable_irq0(struct hns3_hw *hw)
1001 {
1002         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1003 }
1004
1005 static enum hns3vf_evt_cause
1006 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1007 {
1008         struct hns3_hw *hw = &hns->hw;
1009         enum hns3vf_evt_cause ret;
1010         uint32_t cmdq_stat_reg;
1011         uint32_t rst_ing_reg;
1012         uint32_t val;
1013
1014         /* Fetch the events from their corresponding regs */
1015         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1016         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1017                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1018                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1019                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1020                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
1021                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1022                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1023                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1024                 if (clearval) {
1025                         hw->reset.stats.global_cnt++;
1026                         hns3_warn(hw, "Global reset detected, clear reset status");
1027                 } else {
1028                         hns3_schedule_delayed_reset(hns);
1029                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1030                 }
1031
1032                 ret = HNS3VF_VECTOR0_EVENT_RST;
1033                 goto out;
1034         }
1035
1036         /* Check for vector0 mailbox(=CMDQ RX) event source */
1037         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1038                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1039                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1040                 goto out;
1041         }
1042
1043         val = 0;
1044         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1045 out:
1046         if (clearval)
1047                 *clearval = val;
1048         return ret;
1049 }
1050
1051 static void
1052 hns3vf_interrupt_handler(void *param)
1053 {
1054         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1055         struct hns3_adapter *hns = dev->data->dev_private;
1056         struct hns3_hw *hw = &hns->hw;
1057         enum hns3vf_evt_cause event_cause;
1058         uint32_t clearval;
1059
1060         /* Disable interrupt */
1061         hns3vf_disable_irq0(hw);
1062
1063         /* Read out interrupt causes */
1064         event_cause = hns3vf_check_event_cause(hns, &clearval);
1065         /* Clear interrupt causes */
1066         hns3vf_clear_event_cause(hw, clearval);
1067
1068         switch (event_cause) {
1069         case HNS3VF_VECTOR0_EVENT_RST:
1070                 hns3_schedule_reset(hns);
1071                 break;
1072         case HNS3VF_VECTOR0_EVENT_MBX:
1073                 hns3_dev_handle_mbx_msg(hw);
1074                 break;
1075         default:
1076                 break;
1077         }
1078
1079         /* Enable interrupt */
1080         hns3vf_enable_irq0(hw);
1081 }
1082
1083 static void
1084 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1085 {
1086         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1087         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1088         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1089         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1090 }
1091
1092 static void
1093 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1094 {
1095         struct hns3_dev_specs_0_cmd *req0;
1096
1097         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1098
1099         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1100         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1101         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1102         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1103 }
1104
1105 static int
1106 hns3vf_check_dev_specifications(struct hns3_hw *hw)
1107 {
1108         if (hw->rss_ind_tbl_size == 0 ||
1109             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
1110                 hns3_warn(hw, "the size of hash lookup table configured (%u)"
1111                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
1112                               HNS3_RSS_IND_TBL_SIZE_MAX);
1113                 return -EINVAL;
1114         }
1115
1116         return 0;
1117 }
1118
1119 static int
1120 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1121 {
1122         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1123         int ret;
1124         int i;
1125
1126         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1127                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1128                                           true);
1129                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1130         }
1131         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1132
1133         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1134         if (ret)
1135                 return ret;
1136
1137         hns3vf_parse_dev_specifications(hw, desc);
1138
1139         return hns3vf_check_dev_specifications(hw);
1140 }
1141
1142 void
1143 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
1144 {
1145         uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
1146                                    HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1147         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1148         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1149
1150         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1151                 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1152                                           __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1153 }
1154
1155 static void
1156 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
1157 {
1158 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS      500
1159
1160         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1161         int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
1162         uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1163         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1164         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1165
1166         __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
1167                          __ATOMIC_RELEASE);
1168
1169         (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1170                                 NULL, 0);
1171
1172         while (remain_ms > 0) {
1173                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
1174                 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
1175                         HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1176                         break;
1177                 remain_ms--;
1178         }
1179
1180         /*
1181          * When exit above loop, the pf_push_lsc_cap could be one of the three
1182          * state: unknown (means pf not ack), not_supported, supported.
1183          * Here config it as 'not_supported' when it's 'unknown' state.
1184          */
1185         __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1186                                   __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1187
1188         if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
1189                 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
1190                 hns3_info(hw, "detect PF support push link status change!");
1191         } else {
1192                 /*
1193                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
1194                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
1195                  * the RTE_ETH_DEV_INTR_LSC capability.
1196                  */
1197                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1198         }
1199 }
1200
1201 static int
1202 hns3vf_get_capability(struct hns3_hw *hw)
1203 {
1204         struct rte_pci_device *pci_dev;
1205         struct rte_eth_dev *eth_dev;
1206         uint8_t revision;
1207         int ret;
1208
1209         eth_dev = &rte_eth_devices[hw->data->port_id];
1210         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1211
1212         /* Get PCI revision id */
1213         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1214                                   HNS3_PCI_REVISION_ID);
1215         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1216                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1217                              ret);
1218                 return -EIO;
1219         }
1220         hw->revision = revision;
1221
1222         if (revision < PCI_REVISION_ID_HIP09_A) {
1223                 hns3vf_set_default_dev_specifications(hw);
1224                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1225                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1226                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1227                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
1228                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1229                 hw->rss_info.ipv6_sctp_offload_supported = false;
1230                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1231                 return 0;
1232         }
1233
1234         ret = hns3vf_query_dev_specifications(hw);
1235         if (ret) {
1236                 PMD_INIT_LOG(ERR,
1237                              "failed to query dev specifications, ret = %d",
1238                              ret);
1239                 return ret;
1240         }
1241
1242         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1243         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1244         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1245         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1246         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1247         hw->rss_info.ipv6_sctp_offload_supported = true;
1248         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1249
1250         return 0;
1251 }
1252
1253 static int
1254 hns3vf_check_tqp_info(struct hns3_hw *hw)
1255 {
1256         if (hw->tqps_num == 0) {
1257                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1258                 return -EINVAL;
1259         }
1260
1261         if (hw->rss_size_max == 0) {
1262                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1263                 return -EINVAL;
1264         }
1265
1266         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1267
1268         return 0;
1269 }
1270
1271 static int
1272 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1273 {
1274         uint8_t resp_msg;
1275         int ret;
1276
1277         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1278                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1279                                 true, &resp_msg, sizeof(resp_msg));
1280         if (ret) {
1281                 if (ret == -ETIME) {
1282                         /*
1283                          * Getting current port based VLAN state from PF driver
1284                          * will not affect VF driver's basic function. Because
1285                          * the VF driver relies on hns3 PF kernel ether driver,
1286                          * to avoid introducing compatibility issues with older
1287                          * version of PF driver, no failure will be returned
1288                          * when the return value is ETIME. This return value has
1289                          * the following scenarios:
1290                          * 1) Firmware didn't return the results in time
1291                          * 2) the result return by firmware is timeout
1292                          * 3) the older version of kernel side PF driver does
1293                          *    not support this mailbox message.
1294                          * For scenarios 1 and 2, it is most likely that a
1295                          * hardware error has occurred, or a hardware reset has
1296                          * occurred. In this case, these errors will be caught
1297                          * by other functions.
1298                          */
1299                         PMD_INIT_LOG(WARNING,
1300                                 "failed to get PVID state for timeout, maybe "
1301                                 "kernel side PF driver doesn't support this "
1302                                 "mailbox message, or firmware didn't respond.");
1303                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1304                 } else {
1305                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1306                                 " ret = %d", ret);
1307                         return ret;
1308                 }
1309         }
1310         hw->port_base_vlan_cfg.state = resp_msg ?
1311                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1312         return 0;
1313 }
1314
1315 static int
1316 hns3vf_get_queue_info(struct hns3_hw *hw)
1317 {
1318 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1319         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1320         int ret;
1321
1322         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1323                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1324         if (ret) {
1325                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1326                 return ret;
1327         }
1328
1329         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1330         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1331
1332         return hns3vf_check_tqp_info(hw);
1333 }
1334
1335 static int
1336 hns3vf_get_queue_depth(struct hns3_hw *hw)
1337 {
1338 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1339         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1340         int ret;
1341
1342         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1343                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1344         if (ret) {
1345                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1346                              ret);
1347                 return ret;
1348         }
1349
1350         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1351         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1352
1353         return 0;
1354 }
1355
1356 static void
1357 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1358 {
1359         if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1360                 hns3_set_bit(hw->capability,
1361                                 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1362 }
1363
1364 static int
1365 hns3vf_get_num_tc(struct hns3_hw *hw)
1366 {
1367         uint8_t num_tc = 0;
1368         uint32_t i;
1369
1370         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1371                 if (hw->hw_tc_map & BIT(i))
1372                         num_tc++;
1373         }
1374         return num_tc;
1375 }
1376
1377 static int
1378 hns3vf_get_basic_info(struct hns3_hw *hw)
1379 {
1380         uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1381         struct hns3_basic_info *basic_info;
1382         int ret;
1383
1384         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1385                                 true, resp_msg, sizeof(resp_msg));
1386         if (ret) {
1387                 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1388                                 ret);
1389                 return ret;
1390         }
1391
1392         basic_info = (struct hns3_basic_info *)resp_msg;
1393         hw->hw_tc_map = basic_info->hw_tc_map;
1394         hw->num_tc = hns3vf_get_num_tc(hw);
1395         hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1396         hns3vf_update_caps(hw, basic_info->caps);
1397
1398         return 0;
1399 }
1400
1401 static int
1402 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1403 {
1404         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1405         int ret;
1406
1407         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1408                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1409         if (ret) {
1410                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1411                 return ret;
1412         }
1413
1414         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1415
1416         return 0;
1417 }
1418
1419 static int
1420 hns3vf_get_configuration(struct hns3_hw *hw)
1421 {
1422         int ret;
1423
1424         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1425         hw->rss_dis_flag = false;
1426
1427         /* Get device capability */
1428         ret = hns3vf_get_capability(hw);
1429         if (ret) {
1430                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1431                 return ret;
1432         }
1433
1434         hns3vf_get_push_lsc_cap(hw);
1435
1436         /* Get basic info from PF */
1437         ret = hns3vf_get_basic_info(hw);
1438         if (ret)
1439                 return ret;
1440
1441         /* Get queue configuration from PF */
1442         ret = hns3vf_get_queue_info(hw);
1443         if (ret)
1444                 return ret;
1445
1446         /* Get queue depth info from PF */
1447         ret = hns3vf_get_queue_depth(hw);
1448         if (ret)
1449                 return ret;
1450
1451         /* Get user defined VF MAC addr from PF */
1452         ret = hns3vf_get_host_mac_addr(hw);
1453         if (ret)
1454                 return ret;
1455
1456         return hns3vf_get_port_base_vlan_filter_state(hw);
1457 }
1458
1459 static int
1460 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1461                             uint16_t nb_tx_q)
1462 {
1463         struct hns3_hw *hw = &hns->hw;
1464
1465         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1466 }
1467
1468 static void
1469 hns3vf_request_link_info(struct hns3_hw *hw)
1470 {
1471         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1472         bool send_req;
1473         int ret;
1474
1475         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1476                 return;
1477
1478         send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1479                    vf->req_link_info_cnt > 0;
1480         if (!send_req)
1481                 return;
1482
1483         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1484                                 NULL, 0);
1485         if (ret) {
1486                 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1487                 return;
1488         }
1489
1490         if (vf->req_link_info_cnt > 0)
1491                 vf->req_link_info_cnt--;
1492 }
1493
1494 void
1495 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1496                           uint32_t link_speed, uint8_t link_duplex)
1497 {
1498         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1499         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1500         struct hns3_mac *mac = &hw->mac;
1501         int ret;
1502
1503         /*
1504          * PF kernel driver may push link status when VF driver is in resetting,
1505          * driver will stop polling job in this case, after resetting done
1506          * driver will start polling job again.
1507          * When polling job started, driver will get initial link status by
1508          * sending request to PF kernel driver, then could update link status by
1509          * process PF kernel driver's link status mailbox message.
1510          */
1511         if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1512                 return;
1513
1514         if (hw->adapter_state != HNS3_NIC_STARTED)
1515                 return;
1516
1517         mac->link_status = link_status;
1518         mac->link_speed = link_speed;
1519         mac->link_duplex = link_duplex;
1520         ret = hns3vf_dev_link_update(dev, 0);
1521         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1522                 hns3_start_report_lse(dev);
1523 }
1524
1525 static int
1526 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1527 {
1528 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1529         struct hns3_hw *hw = &hns->hw;
1530         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1531         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1532         uint8_t is_kill = on ? 0 : 1;
1533
1534         msg_data[0] = is_kill;
1535         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1536         memcpy(&msg_data[3], &proto, sizeof(proto));
1537
1538         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1539                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1540                                  0);
1541 }
1542
1543 static int
1544 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1545 {
1546         struct hns3_adapter *hns = dev->data->dev_private;
1547         struct hns3_hw *hw = &hns->hw;
1548         int ret;
1549
1550         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1551                 hns3_err(hw,
1552                          "vf set vlan id failed during resetting, vlan_id =%u",
1553                          vlan_id);
1554                 return -EIO;
1555         }
1556         rte_spinlock_lock(&hw->lock);
1557         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1558         rte_spinlock_unlock(&hw->lock);
1559         if (ret)
1560                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1561                          vlan_id, ret);
1562
1563         return ret;
1564 }
1565
1566 static int
1567 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1568 {
1569         uint8_t msg_data;
1570         int ret;
1571
1572         if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1573                 return 0;
1574
1575         msg_data = enable ? 1 : 0;
1576         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1577                         HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1578                         sizeof(msg_data), true, NULL, 0);
1579         if (ret)
1580                 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1581                                 enable ? "enable" : "disable", ret);
1582
1583         return ret;
1584 }
1585
1586 static int
1587 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1588 {
1589         uint8_t msg_data;
1590         int ret;
1591
1592         msg_data = enable ? 1 : 0;
1593         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1594                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1595         if (ret)
1596                 hns3_err(hw, "vf %s strip failed, ret = %d.",
1597                                 enable ? "enable" : "disable", ret);
1598
1599         return ret;
1600 }
1601
1602 static int
1603 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1604 {
1605         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1607         unsigned int tmp_mask;
1608         int ret = 0;
1609
1610         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1611                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1612                              "mask = 0x%x", mask);
1613                 return -EIO;
1614         }
1615
1616         tmp_mask = (unsigned int)mask;
1617
1618         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
1619                 rte_spinlock_lock(&hw->lock);
1620                 /* Enable or disable VLAN filter */
1621                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1622                         ret = hns3vf_en_vlan_filter(hw, true);
1623                 else
1624                         ret = hns3vf_en_vlan_filter(hw, false);
1625                 rte_spinlock_unlock(&hw->lock);
1626                 if (ret)
1627                         return ret;
1628         }
1629
1630         /* Vlan stripping setting */
1631         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
1632                 rte_spinlock_lock(&hw->lock);
1633                 /* Enable or disable VLAN stripping */
1634                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1635                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1636                 else
1637                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1638                 rte_spinlock_unlock(&hw->lock);
1639         }
1640
1641         return ret;
1642 }
1643
1644 static int
1645 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1646 {
1647         struct rte_vlan_filter_conf *vfc;
1648         struct hns3_hw *hw = &hns->hw;
1649         uint16_t vlan_id;
1650         uint64_t vbit;
1651         uint64_t ids;
1652         int ret = 0;
1653         uint32_t i;
1654
1655         vfc = &hw->data->vlan_filter_conf;
1656         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1657                 if (vfc->ids[i] == 0)
1658                         continue;
1659                 ids = vfc->ids[i];
1660                 while (ids) {
1661                         /*
1662                          * 64 means the num bits of ids, one bit corresponds to
1663                          * one vlan id
1664                          */
1665                         vlan_id = 64 * i;
1666                         /* count trailing zeroes */
1667                         vbit = ~ids & (ids - 1);
1668                         /* clear least significant bit set */
1669                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1670                         for (; vbit;) {
1671                                 vbit >>= 1;
1672                                 vlan_id++;
1673                         }
1674                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1675                         if (ret) {
1676                                 hns3_err(hw,
1677                                          "VF handle vlan table failed, ret =%d, on = %d",
1678                                          ret, on);
1679                                 return ret;
1680                         }
1681                 }
1682         }
1683
1684         return ret;
1685 }
1686
1687 static int
1688 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1689 {
1690         return hns3vf_handle_all_vlan_table(hns, 0);
1691 }
1692
1693 static int
1694 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1695 {
1696         struct hns3_hw *hw = &hns->hw;
1697         struct rte_eth_conf *dev_conf;
1698         bool en;
1699         int ret;
1700
1701         dev_conf = &hw->data->dev_conf;
1702         en = dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? true
1703                                                                    : false;
1704         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1705         if (ret)
1706                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1707                          ret);
1708         return ret;
1709 }
1710
1711 static int
1712 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1713 {
1714         struct hns3_adapter *hns = dev->data->dev_private;
1715         struct rte_eth_dev_data *data = dev->data;
1716         struct hns3_hw *hw = &hns->hw;
1717         int ret;
1718
1719         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1720             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1721             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1722                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1723                               "or hw_vlan_insert_pvid is not support!");
1724         }
1725
1726         /* Apply vlan offload setting */
1727         ret = hns3vf_vlan_offload_set(dev, RTE_ETH_VLAN_STRIP_MASK |
1728                                         RTE_ETH_VLAN_FILTER_MASK);
1729         if (ret)
1730                 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1731
1732         return ret;
1733 }
1734
1735 static int
1736 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1737 {
1738         uint8_t msg_data;
1739
1740         msg_data = alive ? 1 : 0;
1741         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1742                                  sizeof(msg_data), false, NULL, 0);
1743 }
1744
1745 static void
1746 hns3vf_keep_alive_handler(void *param)
1747 {
1748         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1749         struct hns3_adapter *hns = eth_dev->data->dev_private;
1750         struct hns3_hw *hw = &hns->hw;
1751         int ret;
1752
1753         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1754                                 false, NULL, 0);
1755         if (ret)
1756                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1757                          ret);
1758
1759         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1760                           eth_dev);
1761 }
1762
1763 static void
1764 hns3vf_service_handler(void *param)
1765 {
1766         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1767         struct hns3_adapter *hns = eth_dev->data->dev_private;
1768         struct hns3_hw *hw = &hns->hw;
1769
1770         /*
1771          * The query link status and reset processing are executed in the
1772          * interrupt thread. When the IMP reset occurs, IMP will not respond,
1773          * and the query operation will timeout after 30ms. In the case of
1774          * multiple PF/VFs, each query failure timeout causes the IMP reset
1775          * interrupt to fail to respond within 100ms.
1776          * Before querying the link status, check whether there is a reset
1777          * pending, and if so, abandon the query.
1778          */
1779         if (!hns3vf_is_reset_pending(hns))
1780                 hns3vf_request_link_info(hw);
1781         else
1782                 hns3_warn(hw, "Cancel the query when reset is pending");
1783
1784         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1785                           eth_dev);
1786 }
1787
1788 static void
1789 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1790 {
1791 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT      3
1792
1793         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1794
1795         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1796                 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1797
1798         __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1799
1800         hns3vf_service_handler(dev);
1801 }
1802
1803 static void
1804 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1805 {
1806         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1807
1808         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1809
1810         __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1811 }
1812
1813 static int
1814 hns3_query_vf_resource(struct hns3_hw *hw)
1815 {
1816         struct hns3_vf_res_cmd *req;
1817         struct hns3_cmd_desc desc;
1818         uint16_t num_msi;
1819         int ret;
1820
1821         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1822         ret = hns3_cmd_send(hw, &desc, 1);
1823         if (ret) {
1824                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1825                 return ret;
1826         }
1827
1828         req = (struct hns3_vf_res_cmd *)desc.data;
1829         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1830                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1831         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1832                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1833                          num_msi, HNS3_MIN_VECTOR_NUM);
1834                 return -EINVAL;
1835         }
1836
1837         hw->num_msi = num_msi;
1838
1839         return 0;
1840 }
1841
1842 static int
1843 hns3vf_init_hardware(struct hns3_adapter *hns)
1844 {
1845         struct hns3_hw *hw = &hns->hw;
1846         uint16_t mtu = hw->data->mtu;
1847         int ret;
1848
1849         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1850         if (ret)
1851                 return ret;
1852
1853         ret = hns3vf_config_mtu(hw, mtu);
1854         if (ret)
1855                 goto err_init_hardware;
1856
1857         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1858         if (ret) {
1859                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1860                 goto err_init_hardware;
1861         }
1862
1863         ret = hns3_config_gro(hw, false);
1864         if (ret) {
1865                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1866                 goto err_init_hardware;
1867         }
1868
1869         /*
1870          * In the initialization clearing the all hardware mapping relationship
1871          * configurations between queues and interrupt vectors is needed, so
1872          * some error caused by the residual configurations, such as the
1873          * unexpected interrupt, can be avoid.
1874          */
1875         ret = hns3vf_init_ring_with_vector(hw);
1876         if (ret) {
1877                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1878                 goto err_init_hardware;
1879         }
1880
1881         return 0;
1882
1883 err_init_hardware:
1884         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1885         return ret;
1886 }
1887
1888 static int
1889 hns3vf_clear_vport_list(struct hns3_hw *hw)
1890 {
1891         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1892                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1893                                  NULL, 0);
1894 }
1895
1896 static int
1897 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1898 {
1899         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1900         struct hns3_adapter *hns = eth_dev->data->dev_private;
1901         struct hns3_hw *hw = &hns->hw;
1902         int ret;
1903
1904         PMD_INIT_FUNC_TRACE();
1905
1906         /* Get hardware io base address from pcie BAR2 IO space */
1907         hw->io_base = pci_dev->mem_resource[2].addr;
1908
1909         /* Firmware command queue initialize */
1910         ret = hns3_cmd_init_queue(hw);
1911         if (ret) {
1912                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1913                 goto err_cmd_init_queue;
1914         }
1915
1916         /* Firmware command initialize */
1917         ret = hns3_cmd_init(hw);
1918         if (ret) {
1919                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1920                 goto err_cmd_init;
1921         }
1922
1923         hns3_tx_push_init(eth_dev);
1924
1925         /* Get VF resource */
1926         ret = hns3_query_vf_resource(hw);
1927         if (ret)
1928                 goto err_cmd_init;
1929
1930         rte_spinlock_init(&hw->mbx_resp.lock);
1931
1932         hns3vf_clear_event_cause(hw, 0);
1933
1934         ret = rte_intr_callback_register(pci_dev->intr_handle,
1935                                          hns3vf_interrupt_handler, eth_dev);
1936         if (ret) {
1937                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1938                 goto err_intr_callback_register;
1939         }
1940
1941         /* Enable interrupt */
1942         rte_intr_enable(pci_dev->intr_handle);
1943         hns3vf_enable_irq0(hw);
1944
1945         /* Get configuration from PF */
1946         ret = hns3vf_get_configuration(hw);
1947         if (ret) {
1948                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1949                 goto err_get_config;
1950         }
1951
1952         ret = hns3_tqp_stats_init(hw);
1953         if (ret)
1954                 goto err_get_config;
1955
1956         /* Hardware statistics of imissed registers cleared. */
1957         ret = hns3_update_imissed_stats(hw, true);
1958         if (ret) {
1959                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1960                 goto err_set_tc_queue;
1961         }
1962
1963         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1964         if (ret) {
1965                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1966                 goto err_set_tc_queue;
1967         }
1968
1969         ret = hns3vf_clear_vport_list(hw);
1970         if (ret) {
1971                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1972                 goto err_set_tc_queue;
1973         }
1974
1975         ret = hns3vf_init_hardware(hns);
1976         if (ret)
1977                 goto err_set_tc_queue;
1978
1979         hns3_rss_set_default_args(hw);
1980
1981         ret = hns3vf_set_alive(hw, true);
1982         if (ret) {
1983                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1984                 goto err_set_tc_queue;
1985         }
1986
1987         return 0;
1988
1989 err_set_tc_queue:
1990         hns3_tqp_stats_uninit(hw);
1991
1992 err_get_config:
1993         hns3vf_disable_irq0(hw);
1994         rte_intr_disable(pci_dev->intr_handle);
1995         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1996                              eth_dev);
1997 err_intr_callback_register:
1998 err_cmd_init:
1999         hns3_cmd_uninit(hw);
2000         hns3_cmd_destroy_queue(hw);
2001 err_cmd_init_queue:
2002         hw->io_base = NULL;
2003
2004         return ret;
2005 }
2006
2007 static void
2008 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
2009 {
2010         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2011         struct hns3_adapter *hns = eth_dev->data->dev_private;
2012         struct hns3_hw *hw = &hns->hw;
2013
2014         PMD_INIT_FUNC_TRACE();
2015
2016         hns3_rss_uninit(hns);
2017         (void)hns3_config_gro(hw, false);
2018         (void)hns3vf_set_alive(hw, false);
2019         (void)hns3vf_set_promisc_mode(hw, false, false, false);
2020         hns3_flow_uninit(eth_dev);
2021         hns3_tqp_stats_uninit(hw);
2022         hns3vf_disable_irq0(hw);
2023         rte_intr_disable(pci_dev->intr_handle);
2024         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
2025                              eth_dev);
2026         hns3_cmd_uninit(hw);
2027         hns3_cmd_destroy_queue(hw);
2028         hw->io_base = NULL;
2029 }
2030
2031 static int
2032 hns3vf_do_stop(struct hns3_adapter *hns)
2033 {
2034         struct hns3_hw *hw = &hns->hw;
2035         int ret;
2036
2037         hw->mac.link_status = RTE_ETH_LINK_DOWN;
2038
2039         /*
2040          * The "hns3vf_do_stop" function will also be called by .stop_service to
2041          * prepare reset. At the time of global or IMP reset, the command cannot
2042          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
2043          * accessed during the reset process. So the mbuf can not be released
2044          * during reset and is required to be released after the reset is
2045          * completed.
2046          */
2047         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
2048                 hns3_dev_release_mbufs(hns);
2049
2050         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
2051                 hns3vf_configure_mac_addr(hns, true);
2052                 ret = hns3_reset_all_tqps(hns);
2053                 if (ret) {
2054                         hns3_err(hw, "failed to reset all queues ret = %d",
2055                                  ret);
2056                         return ret;
2057                 }
2058         }
2059         return 0;
2060 }
2061
2062 static void
2063 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
2064 {
2065         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2066         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2067         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2068         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2069         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2070         uint16_t q_id;
2071
2072         if (dev->data->dev_conf.intr_conf.rxq == 0)
2073                 return;
2074
2075         /* unmap the ring with vector */
2076         if (rte_intr_allow_others(intr_handle)) {
2077                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2078                 base = RTE_INTR_VEC_RXTX_OFFSET;
2079         }
2080         if (rte_intr_dp_is_en(intr_handle)) {
2081                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2082                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
2083                                                            HNS3_RING_TYPE_RX,
2084                                                            q_id);
2085                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
2086                             - 1)
2087                                 vec++;
2088                 }
2089         }
2090         /* Clean datapath event and queue/vec mapping */
2091         rte_intr_efd_disable(intr_handle);
2092
2093         /* Cleanup vector list */
2094         rte_intr_vec_list_free(intr_handle);
2095 }
2096
2097 static int
2098 hns3vf_dev_stop(struct rte_eth_dev *dev)
2099 {
2100         struct hns3_adapter *hns = dev->data->dev_private;
2101         struct hns3_hw *hw = &hns->hw;
2102
2103         PMD_INIT_FUNC_TRACE();
2104         dev->data->dev_started = 0;
2105
2106         hw->adapter_state = HNS3_NIC_STOPPING;
2107         hns3_set_rxtx_function(dev);
2108         rte_wmb();
2109         /* Disable datapath on secondary process. */
2110         hns3_mp_req_stop_rxtx(dev);
2111         /* Prevent crashes when queues are still in use. */
2112         rte_delay_ms(hw->cfg_max_queues);
2113
2114         rte_spinlock_lock(&hw->lock);
2115         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
2116                 hns3_stop_tqps(hw);
2117                 hns3vf_do_stop(hns);
2118                 hns3vf_unmap_rx_interrupt(dev);
2119                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2120         }
2121         hns3_rx_scattered_reset(dev);
2122         hns3vf_stop_poll_job(dev);
2123         hns3_stop_report_lse(dev);
2124         rte_spinlock_unlock(&hw->lock);
2125
2126         return 0;
2127 }
2128
2129 static int
2130 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
2131 {
2132         struct hns3_adapter *hns = eth_dev->data->dev_private;
2133         struct hns3_hw *hw = &hns->hw;
2134         int ret = 0;
2135
2136         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2137                 return 0;
2138
2139         if (hw->adapter_state == HNS3_NIC_STARTED)
2140                 ret = hns3vf_dev_stop(eth_dev);
2141
2142         hw->adapter_state = HNS3_NIC_CLOSING;
2143         hns3_reset_abort(hns);
2144         hw->adapter_state = HNS3_NIC_CLOSED;
2145         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
2146         hns3vf_configure_all_mc_mac_addr(hns, true);
2147         hns3vf_remove_all_vlan_table(hns);
2148         hns3vf_uninit_vf(eth_dev);
2149         hns3_free_all_queues(eth_dev);
2150         rte_free(hw->reset.wait_data);
2151         hns3_mp_uninit_primary();
2152         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
2153
2154         return ret;
2155 }
2156
2157 static int
2158 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2159                       size_t fw_size)
2160 {
2161         struct hns3_adapter *hns = eth_dev->data->dev_private;
2162         struct hns3_hw *hw = &hns->hw;
2163         uint32_t version = hw->fw_version;
2164         int ret;
2165
2166         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2167                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2168                                       HNS3_FW_VERSION_BYTE3_S),
2169                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2170                                       HNS3_FW_VERSION_BYTE2_S),
2171                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2172                                       HNS3_FW_VERSION_BYTE1_S),
2173                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2174                                       HNS3_FW_VERSION_BYTE0_S));
2175         if (ret < 0)
2176                 return -EINVAL;
2177
2178         ret += 1; /* add the size of '\0' */
2179         if (fw_size < (size_t)ret)
2180                 return ret;
2181         else
2182                 return 0;
2183 }
2184
2185 static int
2186 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2187                        __rte_unused int wait_to_complete)
2188 {
2189         struct hns3_adapter *hns = eth_dev->data->dev_private;
2190         struct hns3_hw *hw = &hns->hw;
2191         struct hns3_mac *mac = &hw->mac;
2192         struct rte_eth_link new_link;
2193
2194         memset(&new_link, 0, sizeof(new_link));
2195         switch (mac->link_speed) {
2196         case RTE_ETH_SPEED_NUM_10M:
2197         case RTE_ETH_SPEED_NUM_100M:
2198         case RTE_ETH_SPEED_NUM_1G:
2199         case RTE_ETH_SPEED_NUM_10G:
2200         case RTE_ETH_SPEED_NUM_25G:
2201         case RTE_ETH_SPEED_NUM_40G:
2202         case RTE_ETH_SPEED_NUM_50G:
2203         case RTE_ETH_SPEED_NUM_100G:
2204         case RTE_ETH_SPEED_NUM_200G:
2205                 if (mac->link_status)
2206                         new_link.link_speed = mac->link_speed;
2207                 break;
2208         default:
2209                 if (mac->link_status)
2210                         new_link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2211                 break;
2212         }
2213
2214         if (!mac->link_status)
2215                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2216
2217         new_link.link_duplex = mac->link_duplex;
2218         new_link.link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2219         new_link.link_autoneg =
2220             !(eth_dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED);
2221
2222         return rte_eth_linkstatus_set(eth_dev, &new_link);
2223 }
2224
2225 static int
2226 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2227 {
2228         struct hns3_hw *hw = &hns->hw;
2229         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2230         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2231         int ret;
2232
2233         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2234         if (ret)
2235                 return ret;
2236
2237         hns3_enable_rxd_adv_layout(hw);
2238
2239         ret = hns3_init_queues(hns, reset_queue);
2240         if (ret)
2241                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2242
2243         return ret;
2244 }
2245
2246 static int
2247 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2248 {
2249         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2250         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2251         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2252         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2253         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2254         uint32_t intr_vector;
2255         uint16_t q_id;
2256         int ret;
2257
2258         /*
2259          * hns3 needs a separate interrupt to be used as event interrupt which
2260          * could not be shared with task queue pair, so KERNEL drivers need
2261          * support multiple interrupt vectors.
2262          */
2263         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2264             !rte_intr_cap_multiple(intr_handle))
2265                 return 0;
2266
2267         rte_intr_disable(intr_handle);
2268         intr_vector = hw->used_rx_queues;
2269         /* It creates event fd for each intr vector when MSIX is used */
2270         if (rte_intr_efd_enable(intr_handle, intr_vector))
2271                 return -EINVAL;
2272
2273         /* Allocate vector list */
2274         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
2275                                     hw->used_rx_queues)) {
2276                 hns3_err(hw, "Failed to allocate %u rx_queues"
2277                          " intr_vec", hw->used_rx_queues);
2278                 ret = -ENOMEM;
2279                 goto vf_alloc_intr_vec_error;
2280         }
2281
2282         if (rte_intr_allow_others(intr_handle)) {
2283                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2284                 base = RTE_INTR_VEC_RXTX_OFFSET;
2285         }
2286
2287         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2288                 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2289                                                    HNS3_RING_TYPE_RX, q_id);
2290                 if (ret)
2291                         goto vf_bind_vector_error;
2292
2293                 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
2294                         goto vf_bind_vector_error;
2295
2296                 /*
2297                  * If there are not enough efds (e.g. not enough interrupt),
2298                  * remaining queues will be bond to the last interrupt.
2299                  */
2300                 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
2301                         vec++;
2302         }
2303         rte_intr_enable(intr_handle);
2304         return 0;
2305
2306 vf_bind_vector_error:
2307         rte_intr_vec_list_free(intr_handle);
2308 vf_alloc_intr_vec_error:
2309         rte_intr_efd_disable(intr_handle);
2310         return ret;
2311 }
2312
2313 static int
2314 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2315 {
2316         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2317         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2318         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2319         uint16_t q_id;
2320         int ret;
2321
2322         if (dev->data->dev_conf.intr_conf.rxq == 0)
2323                 return 0;
2324
2325         if (rte_intr_dp_is_en(intr_handle)) {
2326                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2327                         ret = hns3vf_bind_ring_with_vector(hw,
2328                                 rte_intr_vec_list_index_get(intr_handle,
2329                                                                    q_id),
2330                                 true, HNS3_RING_TYPE_RX, q_id);
2331                         if (ret)
2332                                 return ret;
2333                 }
2334         }
2335
2336         return 0;
2337 }
2338
2339 static void
2340 hns3vf_restore_filter(struct rte_eth_dev *dev)
2341 {
2342         hns3_restore_rss_filter(dev);
2343 }
2344
2345 static int
2346 hns3vf_dev_start(struct rte_eth_dev *dev)
2347 {
2348         struct hns3_adapter *hns = dev->data->dev_private;
2349         struct hns3_hw *hw = &hns->hw;
2350         int ret;
2351
2352         PMD_INIT_FUNC_TRACE();
2353         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2354                 return -EBUSY;
2355
2356         rte_spinlock_lock(&hw->lock);
2357         hw->adapter_state = HNS3_NIC_STARTING;
2358         ret = hns3vf_do_start(hns, true);
2359         if (ret) {
2360                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2361                 rte_spinlock_unlock(&hw->lock);
2362                 return ret;
2363         }
2364         ret = hns3vf_map_rx_interrupt(dev);
2365         if (ret)
2366                 goto map_rx_inter_err;
2367
2368         /*
2369          * There are three register used to control the status of a TQP
2370          * (contains a pair of Tx queue and Rx queue) in the new version network
2371          * engine. One is used to control the enabling of Tx queue, the other is
2372          * used to control the enabling of Rx queue, and the last is the master
2373          * switch used to control the enabling of the tqp. The Tx register and
2374          * TQP register must be enabled at the same time to enable a Tx queue.
2375          * The same applies to the Rx queue. For the older network enginem, this
2376          * function only refresh the enabled flag, and it is used to update the
2377          * status of queue in the dpdk framework.
2378          */
2379         ret = hns3_start_all_txqs(dev);
2380         if (ret)
2381                 goto map_rx_inter_err;
2382
2383         ret = hns3_start_all_rxqs(dev);
2384         if (ret)
2385                 goto start_all_rxqs_fail;
2386
2387         hw->adapter_state = HNS3_NIC_STARTED;
2388         rte_spinlock_unlock(&hw->lock);
2389
2390         hns3_rx_scattered_calc(dev);
2391         hns3_set_rxtx_function(dev);
2392         hns3_mp_req_start_rxtx(dev);
2393
2394         hns3vf_restore_filter(dev);
2395
2396         /* Enable interrupt of all rx queues before enabling queues */
2397         hns3_dev_all_rx_queue_intr_enable(hw, true);
2398         hns3_start_tqps(hw);
2399
2400         if (dev->data->dev_conf.intr_conf.lsc != 0)
2401                 hns3vf_dev_link_update(dev, 0);
2402         hns3vf_start_poll_job(dev);
2403
2404         return ret;
2405
2406 start_all_rxqs_fail:
2407         hns3_stop_all_txqs(dev);
2408 map_rx_inter_err:
2409         (void)hns3vf_do_stop(hns);
2410         hw->adapter_state = HNS3_NIC_CONFIGURED;
2411         rte_spinlock_unlock(&hw->lock);
2412
2413         return ret;
2414 }
2415
2416 static bool
2417 is_vf_reset_done(struct hns3_hw *hw)
2418 {
2419 #define HNS3_FUN_RST_ING_BITS \
2420         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2421          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2422          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2423          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2424
2425         uint32_t val;
2426
2427         if (hw->reset.level == HNS3_VF_RESET) {
2428                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2429                 if (val & HNS3_VF_RST_ING_BIT)
2430                         return false;
2431         } else {
2432                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2433                 if (val & HNS3_FUN_RST_ING_BITS)
2434                         return false;
2435         }
2436         return true;
2437 }
2438
2439 bool
2440 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2441 {
2442         struct hns3_hw *hw = &hns->hw;
2443         enum hns3_reset_level reset;
2444
2445         /*
2446          * According to the protocol of PCIe, FLR to a PF device resets the PF
2447          * state as well as the SR-IOV extended capability including VF Enable
2448          * which means that VFs no longer exist.
2449          *
2450          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2451          * is in FLR stage, the register state of VF device is not reliable,
2452          * so register states detection can not be carried out. In this case,
2453          * we just ignore the register states and return false to indicate that
2454          * there are no other reset states that need to be processed by driver.
2455          */
2456         if (hw->reset.level == HNS3_VF_FULL_RESET)
2457                 return false;
2458
2459         /* Check the registers to confirm whether there is reset pending */
2460         hns3vf_check_event_cause(hns, NULL);
2461         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2462         if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2463             hw->reset.level < reset) {
2464                 hns3_warn(hw, "High level reset %d is pending", reset);
2465                 return true;
2466         }
2467         return false;
2468 }
2469
2470 static int
2471 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2472 {
2473         struct hns3_hw *hw = &hns->hw;
2474         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2475         struct timeval tv;
2476
2477         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2478                 /*
2479                  * After vf reset is ready, the PF may not have completed
2480                  * the reset processing. The vf sending mbox to PF may fail
2481                  * during the pf reset, so it is better to add extra delay.
2482                  */
2483                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2484                     hw->reset.level == HNS3_FLR_RESET)
2485                         return 0;
2486                 /* Reset retry process, no need to add extra delay. */
2487                 if (hw->reset.attempts)
2488                         return 0;
2489                 if (wait_data->check_completion == NULL)
2490                         return 0;
2491
2492                 wait_data->check_completion = NULL;
2493                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2494                 wait_data->count = 1;
2495                 wait_data->result = HNS3_WAIT_REQUEST;
2496                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2497                                   wait_data);
2498                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2499                 return -EAGAIN;
2500         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2501                 hns3_clock_gettime(&tv);
2502                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2503                           tv.tv_sec, tv.tv_usec);
2504                 return -ETIME;
2505         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2506                 return -EAGAIN;
2507
2508         wait_data->hns = hns;
2509         wait_data->check_completion = is_vf_reset_done;
2510         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2511                                 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2512         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2513         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2514         wait_data->result = HNS3_WAIT_REQUEST;
2515         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2516         return -EAGAIN;
2517 }
2518
2519 static int
2520 hns3vf_prepare_reset(struct hns3_adapter *hns)
2521 {
2522         struct hns3_hw *hw = &hns->hw;
2523         int ret;
2524
2525         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2526                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2527                                         0, true, NULL, 0);
2528                 if (ret)
2529                         return ret;
2530         }
2531         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2532
2533         return 0;
2534 }
2535
2536 static int
2537 hns3vf_stop_service(struct hns3_adapter *hns)
2538 {
2539         struct hns3_hw *hw = &hns->hw;
2540         struct rte_eth_dev *eth_dev;
2541
2542         eth_dev = &rte_eth_devices[hw->data->port_id];
2543         if (hw->adapter_state == HNS3_NIC_STARTED) {
2544                 /*
2545                  * Make sure call update link status before hns3vf_stop_poll_job
2546                  * because update link status depend on polling job exist.
2547                  */
2548                 hns3vf_update_link_status(hw, RTE_ETH_LINK_DOWN, hw->mac.link_speed,
2549                                           hw->mac.link_duplex);
2550                 hns3vf_stop_poll_job(eth_dev);
2551         }
2552         hw->mac.link_status = RTE_ETH_LINK_DOWN;
2553
2554         hns3_set_rxtx_function(eth_dev);
2555         rte_wmb();
2556         /* Disable datapath on secondary process. */
2557         hns3_mp_req_stop_rxtx(eth_dev);
2558         rte_delay_ms(hw->cfg_max_queues);
2559
2560         rte_spinlock_lock(&hw->lock);
2561         if (hw->adapter_state == HNS3_NIC_STARTED ||
2562             hw->adapter_state == HNS3_NIC_STOPPING) {
2563                 hns3_enable_all_queues(hw, false);
2564                 hns3vf_do_stop(hns);
2565                 hw->reset.mbuf_deferred_free = true;
2566         } else
2567                 hw->reset.mbuf_deferred_free = false;
2568
2569         /*
2570          * It is cumbersome for hardware to pick-and-choose entries for deletion
2571          * from table space. Hence, for function reset software intervention is
2572          * required to delete the entries.
2573          */
2574         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2575                 hns3vf_configure_all_mc_mac_addr(hns, true);
2576         rte_spinlock_unlock(&hw->lock);
2577
2578         return 0;
2579 }
2580
2581 static int
2582 hns3vf_start_service(struct hns3_adapter *hns)
2583 {
2584         struct hns3_hw *hw = &hns->hw;
2585         struct rte_eth_dev *eth_dev;
2586
2587         eth_dev = &rte_eth_devices[hw->data->port_id];
2588         hns3_set_rxtx_function(eth_dev);
2589         hns3_mp_req_start_rxtx(eth_dev);
2590         if (hw->adapter_state == HNS3_NIC_STARTED) {
2591                 hns3vf_start_poll_job(eth_dev);
2592
2593                 /* Enable interrupt of all rx queues before enabling queues */
2594                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2595                 /*
2596                  * Enable state of each rxq and txq will be recovered after
2597                  * reset, so we need to restore them before enable all tqps;
2598                  */
2599                 hns3_restore_tqp_enable_state(hw);
2600                 /*
2601                  * When finished the initialization, enable queues to receive
2602                  * and transmit packets.
2603                  */
2604                 hns3_enable_all_queues(hw, true);
2605         }
2606
2607         return 0;
2608 }
2609
2610 static int
2611 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2612 {
2613         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2614         struct rte_ether_addr *hw_mac;
2615         int ret;
2616
2617         /*
2618          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2619          * on the host by "ip link set ..." command. If the hns3 PF kernel
2620          * ethdev driver sets the MAC address for VF device after the
2621          * initialization of the related VF device, the PF driver will notify
2622          * VF driver to reset VF device to make the new MAC address effective
2623          * immediately. The hns3 VF PMD driver should check whether the MAC
2624          * address has been changed by the PF kernel ethdev driver, if changed
2625          * VF driver should configure hardware using the new MAC address in the
2626          * recovering hardware configuration stage of the reset process.
2627          */
2628         ret = hns3vf_get_host_mac_addr(hw);
2629         if (ret)
2630                 return ret;
2631
2632         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2633         ret = rte_is_zero_ether_addr(hw_mac);
2634         if (ret) {
2635                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2636         } else {
2637                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2638                 if (!ret) {
2639                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2640                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2641                                               &hw->data->mac_addrs[0]);
2642                         hns3_warn(hw, "Default MAC address has been changed to:"
2643                                   " %s by the host PF kernel ethdev driver",
2644                                   mac_str);
2645                 }
2646         }
2647
2648         return 0;
2649 }
2650
2651 static int
2652 hns3vf_restore_conf(struct hns3_adapter *hns)
2653 {
2654         struct hns3_hw *hw = &hns->hw;
2655         int ret;
2656
2657         ret = hns3vf_check_default_mac_change(hw);
2658         if (ret)
2659                 return ret;
2660
2661         ret = hns3vf_configure_mac_addr(hns, false);
2662         if (ret)
2663                 return ret;
2664
2665         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2666         if (ret)
2667                 goto err_mc_mac;
2668
2669         ret = hns3vf_restore_promisc(hns);
2670         if (ret)
2671                 goto err_vlan_table;
2672
2673         ret = hns3vf_restore_vlan_conf(hns);
2674         if (ret)
2675                 goto err_vlan_table;
2676
2677         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2678         if (ret)
2679                 goto err_vlan_table;
2680
2681         ret = hns3vf_restore_rx_interrupt(hw);
2682         if (ret)
2683                 goto err_vlan_table;
2684
2685         ret = hns3_restore_gro_conf(hw);
2686         if (ret)
2687                 goto err_vlan_table;
2688
2689         if (hw->adapter_state == HNS3_NIC_STARTED) {
2690                 ret = hns3vf_do_start(hns, false);
2691                 if (ret)
2692                         goto err_vlan_table;
2693                 hns3_info(hw, "hns3vf dev restart successful!");
2694         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2695                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2696
2697         ret = hns3vf_set_alive(hw, true);
2698         if (ret) {
2699                 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2700                 goto err_vlan_table;
2701         }
2702
2703         return 0;
2704
2705 err_vlan_table:
2706         hns3vf_configure_all_mc_mac_addr(hns, true);
2707 err_mc_mac:
2708         hns3vf_configure_mac_addr(hns, true);
2709         return ret;
2710 }
2711
2712 static enum hns3_reset_level
2713 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2714 {
2715         enum hns3_reset_level reset_level;
2716
2717         /* return the highest priority reset level amongst all */
2718         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2719                 reset_level = HNS3_VF_RESET;
2720         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2721                 reset_level = HNS3_VF_FULL_RESET;
2722         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2723                 reset_level = HNS3_VF_PF_FUNC_RESET;
2724         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2725                 reset_level = HNS3_VF_FUNC_RESET;
2726         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2727                 reset_level = HNS3_FLR_RESET;
2728         else
2729                 reset_level = HNS3_NONE_RESET;
2730
2731         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2732                 return HNS3_NONE_RESET;
2733
2734         return reset_level;
2735 }
2736
2737 static void
2738 hns3vf_reset_service(void *param)
2739 {
2740         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2741         struct hns3_hw *hw = &hns->hw;
2742         enum hns3_reset_level reset_level;
2743         struct timeval tv_delta;
2744         struct timeval tv_start;
2745         struct timeval tv;
2746         uint64_t msec;
2747
2748         /*
2749          * The interrupt is not triggered within the delay time.
2750          * The interrupt may have been lost. It is necessary to handle
2751          * the interrupt to recover from the error.
2752          */
2753         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2754                             SCHEDULE_DEFERRED) {
2755                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2756                                  __ATOMIC_RELAXED);
2757                 hns3_err(hw, "Handling interrupts in delayed tasks");
2758                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2759                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2760                 if (reset_level == HNS3_NONE_RESET) {
2761                         hns3_err(hw, "No reset level is set, try global reset");
2762                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2763                 }
2764         }
2765         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2766
2767         /*
2768          * Hardware reset has been notified, we now have to poll & check if
2769          * hardware has actually completed the reset sequence.
2770          */
2771         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2772         if (reset_level != HNS3_NONE_RESET) {
2773                 hns3_clock_gettime(&tv_start);
2774                 hns3_reset_process(hns, reset_level);
2775                 hns3_clock_gettime(&tv);
2776                 timersub(&tv, &tv_start, &tv_delta);
2777                 msec = hns3_clock_calctime_ms(&tv_delta);
2778                 if (msec > HNS3_RESET_PROCESS_MS)
2779                         hns3_err(hw, "%d handle long time delta %" PRIu64
2780                                  " ms time=%ld.%.6ld",
2781                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2782         }
2783 }
2784
2785 static int
2786 hns3vf_reinit_dev(struct hns3_adapter *hns)
2787 {
2788         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2789         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2790         struct hns3_hw *hw = &hns->hw;
2791         int ret;
2792
2793         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2794                 rte_intr_disable(pci_dev->intr_handle);
2795                 ret = hns3vf_set_bus_master(pci_dev, true);
2796                 if (ret < 0) {
2797                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2798                         return ret;
2799                 }
2800         }
2801
2802         /* Firmware command initialize */
2803         ret = hns3_cmd_init(hw);
2804         if (ret) {
2805                 hns3_err(hw, "Failed to init cmd: %d", ret);
2806                 return ret;
2807         }
2808
2809         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2810                 /*
2811                  * UIO enables msix by writing the pcie configuration space
2812                  * vfio_pci enables msix in rte_intr_enable.
2813                  */
2814                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2815                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2816                         if (hns3vf_enable_msix(pci_dev, true))
2817                                 hns3_err(hw, "Failed to enable msix");
2818                 }
2819
2820                 rte_intr_enable(pci_dev->intr_handle);
2821         }
2822
2823         ret = hns3_reset_all_tqps(hns);
2824         if (ret) {
2825                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2826                 return ret;
2827         }
2828
2829         ret = hns3vf_init_hardware(hns);
2830         if (ret) {
2831                 hns3_err(hw, "Failed to init hardware: %d", ret);
2832                 return ret;
2833         }
2834
2835         return 0;
2836 }
2837
2838 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2839         .dev_configure      = hns3vf_dev_configure,
2840         .dev_start          = hns3vf_dev_start,
2841         .dev_stop           = hns3vf_dev_stop,
2842         .dev_close          = hns3vf_dev_close,
2843         .mtu_set            = hns3vf_dev_mtu_set,
2844         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2845         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2846         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2847         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2848         .stats_get          = hns3_stats_get,
2849         .stats_reset        = hns3_stats_reset,
2850         .xstats_get         = hns3_dev_xstats_get,
2851         .xstats_get_names   = hns3_dev_xstats_get_names,
2852         .xstats_reset       = hns3_dev_xstats_reset,
2853         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2854         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2855         .dev_infos_get      = hns3vf_dev_infos_get,
2856         .fw_version_get     = hns3vf_fw_version_get,
2857         .rx_queue_setup     = hns3_rx_queue_setup,
2858         .tx_queue_setup     = hns3_tx_queue_setup,
2859         .rx_queue_release   = hns3_dev_rx_queue_release,
2860         .tx_queue_release   = hns3_dev_tx_queue_release,
2861         .rx_queue_start     = hns3_dev_rx_queue_start,
2862         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2863         .tx_queue_start     = hns3_dev_tx_queue_start,
2864         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2865         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2866         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2867         .rxq_info_get       = hns3_rxq_info_get,
2868         .txq_info_get       = hns3_txq_info_get,
2869         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2870         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2871         .mac_addr_add       = hns3vf_add_mac_addr,
2872         .mac_addr_remove    = hns3vf_remove_mac_addr,
2873         .mac_addr_set       = hns3vf_set_default_mac_addr,
2874         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2875         .link_update        = hns3vf_dev_link_update,
2876         .rss_hash_update    = hns3_dev_rss_hash_update,
2877         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2878         .reta_update        = hns3_dev_rss_reta_update,
2879         .reta_query         = hns3_dev_rss_reta_query,
2880         .flow_ops_get       = hns3_dev_flow_ops_get,
2881         .vlan_filter_set    = hns3vf_vlan_filter_set,
2882         .vlan_offload_set   = hns3vf_vlan_offload_set,
2883         .get_reg            = hns3_get_regs,
2884         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2885         .tx_done_cleanup    = hns3_tx_done_cleanup,
2886 };
2887
2888 static const struct hns3_reset_ops hns3vf_reset_ops = {
2889         .reset_service       = hns3vf_reset_service,
2890         .stop_service        = hns3vf_stop_service,
2891         .prepare_reset       = hns3vf_prepare_reset,
2892         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2893         .reinit_dev          = hns3vf_reinit_dev,
2894         .restore_conf        = hns3vf_restore_conf,
2895         .start_service       = hns3vf_start_service,
2896 };
2897
2898 static void
2899 hns3vf_init_hw_ops(struct hns3_hw *hw)
2900 {
2901         hw->ops.add_mc_mac_addr = hns3vf_add_mc_mac_addr;
2902         hw->ops.del_mc_mac_addr = hns3vf_remove_mc_mac_addr;
2903         hw->ops.add_uc_mac_addr = hns3vf_add_uc_mac_addr;
2904         hw->ops.del_uc_mac_addr = hns3vf_remove_uc_mac_addr;
2905 }
2906
2907 static int
2908 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2909 {
2910         struct hns3_adapter *hns = eth_dev->data->dev_private;
2911         struct hns3_hw *hw = &hns->hw;
2912         int ret;
2913
2914         PMD_INIT_FUNC_TRACE();
2915
2916         hns3_flow_init(eth_dev);
2917
2918         hns3_set_rxtx_function(eth_dev);
2919         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2920         eth_dev->rx_queue_count = hns3_rx_queue_count;
2921         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2922                 ret = hns3_mp_init_secondary();
2923                 if (ret) {
2924                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2925                                           "process, ret = %d", ret);
2926                         goto err_mp_init_secondary;
2927                 }
2928                 hw->secondary_cnt++;
2929                 hns3_tx_push_init(eth_dev);
2930                 return 0;
2931         }
2932
2933         ret = hns3_mp_init_primary();
2934         if (ret) {
2935                 PMD_INIT_LOG(ERR,
2936                              "Failed to init for primary process, ret = %d",
2937                              ret);
2938                 goto err_mp_init_primary;
2939         }
2940
2941         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2942         hns->is_vf = true;
2943         hw->data = eth_dev->data;
2944         hns3_parse_devargs(eth_dev);
2945
2946         ret = hns3_reset_init(hw);
2947         if (ret)
2948                 goto err_init_reset;
2949         hw->reset.ops = &hns3vf_reset_ops;
2950
2951         hns3vf_init_hw_ops(hw);
2952         ret = hns3vf_init_vf(eth_dev);
2953         if (ret) {
2954                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2955                 goto err_init_vf;
2956         }
2957
2958         /* Allocate memory for storing MAC addresses */
2959         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2960                                                sizeof(struct rte_ether_addr) *
2961                                                HNS3_VF_UC_MACADDR_NUM, 0);
2962         if (eth_dev->data->mac_addrs == NULL) {
2963                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2964                              "to store MAC addresses",
2965                              sizeof(struct rte_ether_addr) *
2966                              HNS3_VF_UC_MACADDR_NUM);
2967                 ret = -ENOMEM;
2968                 goto err_rte_zmalloc;
2969         }
2970
2971         /*
2972          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2973          * on the host by "ip link set ..." command. To avoid some incorrect
2974          * scenes, for example, hns3 VF PMD driver fails to receive and send
2975          * packets after user configure the MAC address by using the
2976          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2977          * address strategy as the hns3 kernel ethdev driver in the
2978          * initialization. If user configure a MAC address by the ip command
2979          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2980          * start with a random MAC address in the initialization.
2981          */
2982         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2983                 rte_eth_random_addr(hw->mac.mac_addr);
2984         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2985                             &eth_dev->data->mac_addrs[0]);
2986
2987         hw->adapter_state = HNS3_NIC_INITIALIZED;
2988
2989         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2990                             SCHEDULE_PENDING) {
2991                 hns3_err(hw, "Reschedule reset service after dev_init");
2992                 hns3_schedule_reset(hns);
2993         } else {
2994                 /* IMP will wait ready flag before reset */
2995                 hns3_notify_reset_ready(hw, false);
2996         }
2997         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2998                           eth_dev);
2999         return 0;
3000
3001 err_rte_zmalloc:
3002         hns3vf_uninit_vf(eth_dev);
3003
3004 err_init_vf:
3005         rte_free(hw->reset.wait_data);
3006
3007 err_init_reset:
3008         hns3_mp_uninit_primary();
3009
3010 err_mp_init_primary:
3011 err_mp_init_secondary:
3012         eth_dev->dev_ops = NULL;
3013         eth_dev->rx_pkt_burst = NULL;
3014         eth_dev->rx_descriptor_status = NULL;
3015         eth_dev->tx_pkt_burst = NULL;
3016         eth_dev->tx_pkt_prepare = NULL;
3017         eth_dev->tx_descriptor_status = NULL;
3018
3019         return ret;
3020 }
3021
3022 static int
3023 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
3024 {
3025         struct hns3_adapter *hns = eth_dev->data->dev_private;
3026         struct hns3_hw *hw = &hns->hw;
3027
3028         PMD_INIT_FUNC_TRACE();
3029
3030         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3031                 return 0;
3032
3033         if (hw->adapter_state < HNS3_NIC_CLOSING)
3034                 hns3vf_dev_close(eth_dev);
3035
3036         hw->adapter_state = HNS3_NIC_REMOVED;
3037         return 0;
3038 }
3039
3040 static int
3041 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3042                      struct rte_pci_device *pci_dev)
3043 {
3044         return rte_eth_dev_pci_generic_probe(pci_dev,
3045                                              sizeof(struct hns3_adapter),
3046                                              hns3vf_dev_init);
3047 }
3048
3049 static int
3050 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
3051 {
3052         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
3053 }
3054
3055 static const struct rte_pci_id pci_id_hns3vf_map[] = {
3056         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
3057         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
3058         { .vendor_id = 0, }, /* sentinel */
3059 };
3060
3061 static struct rte_pci_driver rte_hns3vf_pmd = {
3062         .id_table = pci_id_hns3vf_map,
3063         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3064         .probe = eth_hns3vf_pci_probe,
3065         .remove = eth_hns3vf_pci_remove,
3066 };
3067
3068 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
3069 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
3070 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
3071 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
3072                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
3073                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
3074                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
3075                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16_t> ");