drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
  48                                    __rte_unused int wait_to_complete);
  49
  50 /* set PCI bus mastering */
  51 static int
  52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  53 {
  54         uint16_t reg;
  55         int ret;
  56
  57         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  58         if (ret < 0) {
  59                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  60                              PCI_COMMAND);
  61                 return ret;
  62         }
  63
  64         if (op)
  65                 /* set the master bit */
  66                 reg |= PCI_COMMAND_MASTER;
  67         else
  68                 reg &= ~(PCI_COMMAND_MASTER);
  69
  70         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  71 }
  72
  73 /**
  74  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  75  * @cap: the capability
  76  *
  77  * Return the address of the given capability within the PCI capability list.
  78  */
  79 static int
  80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  81 {
  82 #define MAX_PCIE_CAPABILITY 48
  83         uint16_t status;
  84         uint8_t pos;
  85         uint8_t id;
  86         int ttl;
  87         int ret;
  88
  89         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  90         if (ret < 0) {
  91                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  92                 return 0;
  93         }
  94
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 100                                   PCI_CAPABILITY_LIST);
 101         if (ret < 0) {
 102                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 103                              PCI_CAPABILITY_LIST);
 104                 return 0;
 105         }
 106
 107         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 108                 ret = rte_pci_read_config(device, &id, sizeof(id),
 109                                           (pos + PCI_CAP_LIST_ID));
 110                 if (ret < 0) {
 111                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 112                                      (pos + PCI_CAP_LIST_ID));
 113                         break;
 114                 }
 115
 116                 if (id == 0xFF)
 117                         break;
 118
 119                 if (id == cap)
 120                         return (int)pos;
 121
 122                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 123                                           (pos + PCI_CAP_LIST_NEXT));
 124                 if (ret < 0) {
 125                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 126                                      (pos + PCI_CAP_LIST_NEXT));
 127                         break;
 128                 }
 129         }
 130         return 0;
 131 }
 132
 133 static int
 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 135 {
 136         uint16_t control;
 137         int pos;
 138         int ret;
 139
 140         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 141         if (pos) {
 142                 ret = rte_pci_read_config(device, &control, sizeof(control),
 143                                     (pos + PCI_MSIX_FLAGS));
 144                 if (ret < 0) {
 145                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 146                                      (pos + PCI_MSIX_FLAGS));
 147                         return -ENXIO;
 148                 }
 149
 150                 if (op)
 151                         control |= PCI_MSIX_FLAGS_ENABLE;
 152                 else
 153                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 154                 ret = rte_pci_write_config(device, &control, sizeof(control),
 155                                           (pos + PCI_MSIX_FLAGS));
 156                 if (ret < 0) {
 157                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 158                                     (pos + PCI_MSIX_FLAGS));
 159                         return -ENXIO;
 160                 }
 161
 162                 return 0;
 163         }
 164
 165         return -ENXIO;
 166 }
 167
 168 static int
 169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 170 {
 171         /* mac address was checked by upper level interface */
 172         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 173         int ret;
 174
 175         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 176                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 177                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 178         if (ret) {
 179                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 180                                       mac_addr);
 181                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 182                          mac_str, ret);
 183         }
 184         return ret;
 185 }
 186
 187 static int
 188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 189 {
 190         /* mac address was checked by upper level interface */
 191         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 192         int ret;
 193
 194         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 195                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 196                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 197                                 false, NULL, 0);
 198         if (ret) {
 199                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 200                                       mac_addr);
 201                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 202                          mac_str, ret);
 203         }
 204         return ret;
 205 }
 206
 207 static int
 208 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 209                             struct rte_ether_addr *mac_addr)
 210 {
 211 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 212         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 213         struct rte_ether_addr *old_addr;
 214         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 215         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 216         int ret;
 217
 218         /*
 219          * It has been guaranteed that input parameter named mac_addr is valid
 220          * address in the rte layer of DPDK framework.
 221          */
 222         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 223         rte_spinlock_lock(&hw->lock);
 224         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 225         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 226                RTE_ETHER_ADDR_LEN);
 227
 228         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 229                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 230                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 231         if (ret) {
 232                 /*
 233                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 234                  * driver. When user has configured a MAC address for VF device
 235                  * by "ip link set ..." command based on the PF device, the hns3
 236                  * PF kernel ethdev driver does not allow VF driver to request
 237                  * reconfiguring a different default MAC address, and return
 238                  * -EPREM to VF driver through mailbox.
 239                  */
 240                 if (ret == -EPERM) {
 241                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 242                                               old_addr);
 243                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 244                                   mac_str);
 245                 } else {
 246                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 247                                               mac_addr);
 248                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 249                                  mac_str, ret);
 250                 }
 251         }
 252
 253         rte_ether_addr_copy(mac_addr,
 254                             (struct rte_ether_addr *)hw->mac.mac_addr);
 255         rte_spinlock_unlock(&hw->lock);
 256
 257         return ret;
 258 }
 259
 260 static int
 261 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 262                        struct rte_ether_addr *mac_addr)
 263 {
 264         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 265         int ret;
 266
 267         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 268                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 269                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 270                                 NULL, 0);
 271         if (ret) {
 272                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 273                                       mac_addr);
 274                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 275                          mac_str, ret);
 276         }
 277
 278         return ret;
 279 }
 280
 281 static int
 282 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 283                           struct rte_ether_addr *mac_addr)
 284 {
 285         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 286         int ret;
 287
 288         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 289                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 290                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 291                                 NULL, 0);
 292         if (ret) {
 293                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 294                                       mac_addr);
 295                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 296                          mac_str, ret);
 297         }
 298
 299         return ret;
 300 }
 301
 302 static int
 303 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 304                         bool en_uc_pmc, bool en_mc_pmc)
 305 {
 306         struct hns3_mbx_vf_to_pf_cmd *req;
 307         struct hns3_cmd_desc desc;
 308         int ret;
 309
 310         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 311
 312         /*
 313          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 314          * so there are some features for promiscuous/allmulticast mode in hns3
 315          * VF PMD driver as below:
 316          * 1. The promiscuous/allmulticast mode can be configured successfully
 317          *    only based on the trusted VF device. If based on the non trusted
 318          *    VF device, configuring promiscuous/allmulticast mode will fail.
 319          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 320          *    kernel ethdev driver on the host by the following command:
 321          *      "ip link set <eth num> vf <vf id> turst on"
 322          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 323          *    driver can receive the ingress and outgoing traffic. In the words,
 324          *    all the ingress packets, all the packets sent from the PF and
 325          *    other VFs on the same physical port.
 326          * 3. Note: Because of the hardware constraints, By default vlan filter
 327          *    is enabled and couldn't be turned off based on VF device, so vlan
 328          *    filter is still effective even in promiscuous mode. If upper
 329          *    applications don't call rte_eth_dev_vlan_filter API function to
 330          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 331          *    the packets with vlan tag in promiscuoue mode.
 332          */
 333         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 334         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 335         req->msg[1] = en_bc_pmc ? 1 : 0;
 336         req->msg[2] = en_uc_pmc ? 1 : 0;
 337         req->msg[3] = en_mc_pmc ? 1 : 0;
 338         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 339
 340         ret = hns3_cmd_send(hw, &desc, 1);
 341         if (ret)
 342                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 343
 344         return ret;
 345 }
 346
 347 static int
 348 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 349 {
 350         struct hns3_adapter *hns = dev->data->dev_private;
 351         struct hns3_hw *hw = &hns->hw;
 352         int ret;
 353
 354         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 355         if (ret)
 356                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 357                         ret);
 358         return ret;
 359 }
 360
 361 static int
 362 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 363 {
 364         bool allmulti = dev->data->all_multicast ? true : false;
 365         struct hns3_adapter *hns = dev->data->dev_private;
 366         struct hns3_hw *hw = &hns->hw;
 367         int ret;
 368
 369         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 370         if (ret)
 371                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 372                         ret);
 373         return ret;
 374 }
 375
 376 static int
 377 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 378 {
 379         struct hns3_adapter *hns = dev->data->dev_private;
 380         struct hns3_hw *hw = &hns->hw;
 381         int ret;
 382
 383         if (dev->data->promiscuous)
 384                 return 0;
 385
 386         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 387         if (ret)
 388                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 389                         ret);
 390         return ret;
 391 }
 392
 393 static int
 394 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 395 {
 396         struct hns3_adapter *hns = dev->data->dev_private;
 397         struct hns3_hw *hw = &hns->hw;
 398         int ret;
 399
 400         if (dev->data->promiscuous)
 401                 return 0;
 402
 403         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 404         if (ret)
 405                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 406                         ret);
 407         return ret;
 408 }
 409
 410 static int
 411 hns3vf_restore_promisc(struct hns3_adapter *hns)
 412 {
 413         struct hns3_hw *hw = &hns->hw;
 414         bool allmulti = hw->data->all_multicast ? true : false;
 415
 416         if (hw->data->promiscuous)
 417                 return hns3vf_set_promisc_mode(hw, true, true, true);
 418
 419         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 420 }
 421
 422 static int
 423 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 424                              bool mmap, enum hns3_ring_type queue_type,
 425                              uint16_t queue_id)
 426 {
 427         struct hns3_vf_bind_vector_msg bind_msg;
 428         const char *op_str;
 429         uint16_t code;
 430         int ret;
 431
 432         memset(&bind_msg, 0, sizeof(bind_msg));
 433         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 434                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 435         bind_msg.vector_id = vector_id;
 436
 437         if (queue_type == HNS3_RING_TYPE_RX)
 438                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 439         else
 440                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 441
 442         bind_msg.param[0].ring_type = queue_type;
 443         bind_msg.ring_num = 1;
 444         bind_msg.param[0].tqp_index = queue_id;
 445         op_str = mmap ? "Map" : "Unmap";
 446         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 447                                 sizeof(bind_msg), false, NULL, 0);
 448         if (ret)
 449                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 450                          op_str, queue_id, bind_msg.vector_id, ret);
 451
 452         return ret;
 453 }
 454
 455 static int
 456 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 457 {
 458         uint16_t vec;
 459         int ret;
 460         int i;
 461
 462         /*
 463          * In hns3 network engine, vector 0 is always the misc interrupt of this
 464          * function, vector 1~N can be used respectively for the queues of the
 465          * function. Tx and Rx queues with the same number share the interrupt
 466          * vector. In the initialization clearing the all hardware mapping
 467          * relationship configurations between queues and interrupt vectors is
 468          * needed, so some error caused by the residual configurations, such as
 469          * the unexpected Tx interrupt, can be avoid.
 470          */
 471         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 472         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 473                 vec = vec - 1; /* the last interrupt is reserved */
 474         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 475         for (i = 0; i < hw->intr_tqps_num; i++) {
 476                 /*
 477                  * Set gap limiter/rate limiter/quanity limiter algorithm
 478                  * configuration for interrupt coalesce of queue's interrupt.
 479                  */
 480                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 481                                        HNS3_TQP_INTR_GL_DEFAULT);
 482                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 483                                        HNS3_TQP_INTR_GL_DEFAULT);
 484                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 485                 /*
 486                  * QL(quantity limiter) is not used currently, just set 0 to
 487                  * close it.
 488                  */
 489                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 490
 491                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 492                                                    HNS3_RING_TYPE_TX, i);
 493                 if (ret) {
 494                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 495                                           "vector: %u, ret=%d", i, vec, ret);
 496                         return ret;
 497                 }
 498
 499                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 500                                                    HNS3_RING_TYPE_RX, i);
 501                 if (ret) {
 502                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 503                                           "vector: %u, ret=%d", i, vec, ret);
 504                         return ret;
 505                 }
 506         }
 507
 508         return 0;
 509 }
 510
 511 static int
 512 hns3vf_dev_configure(struct rte_eth_dev *dev)
 513 {
 514         struct hns3_adapter *hns = dev->data->dev_private;
 515         struct hns3_hw *hw = &hns->hw;
 516         struct rte_eth_conf *conf = &dev->data->dev_conf;
 517         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 518         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 519         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 520         struct rte_eth_rss_conf rss_conf;
 521         bool gro_en;
 522         int ret;
 523
 524         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 525
 526         /*
 527          * Some versions of hardware network engine does not support
 528          * individually enable/disable/reset the Tx or Rx queue. These devices
 529          * must enable/disable/reset Tx and Rx queues at the same time. When the
 530          * numbers of Tx queues allocated by upper applications are not equal to
 531          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 532          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 533          * work as usual. But these fake queues are imperceptible, and can not
 534          * be used by upper applications.
 535          */
 536         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 537         if (ret) {
 538                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
 539                 hw->cfg_max_queues = 0;
 540                 return ret;
 541         }
 542
 543         hw->adapter_state = HNS3_NIC_CONFIGURING;
 544         if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
 545                 hns3_err(hw, "setting link speed/duplex not supported");
 546                 ret = -EINVAL;
 547                 goto cfg_err;
 548         }
 549
 550         /* When RSS is not configured, redirect the packet queue 0 */
 551         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
 552                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
 553                 hw->rss_dis_flag = false;
 554                 rss_conf = conf->rx_adv_conf.rss_conf;
 555                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 556                 if (ret)
 557                         goto cfg_err;
 558         }
 559
 560         ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
 561         if (ret != 0)
 562                 goto cfg_err;
 563
 564         ret = hns3vf_dev_configure_vlan(dev);
 565         if (ret)
 566                 goto cfg_err;
 567
 568         /* config hardware GRO */
 569         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
 570         ret = hns3_config_gro(hw, gro_en);
 571         if (ret)
 572                 goto cfg_err;
 573
 574         hns3_init_rx_ptype_tble(dev);
 575
 576         hw->adapter_state = HNS3_NIC_CONFIGURED;
 577         return 0;
 578
 579 cfg_err:
 580         hw->cfg_max_queues = 0;
 581         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 582         hw->adapter_state = HNS3_NIC_INITIALIZED;
 583
 584         return ret;
 585 }
 586
 587 static int
 588 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 589 {
 590         int ret;
 591
 592         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 593                                 sizeof(mtu), true, NULL, 0);
 594         if (ret)
 595                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 596
 597         return ret;
 598 }
 599
 600 static int
 601 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 602 {
 603         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 604         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 605         int ret;
 606
 607         /*
 608          * The hns3 PF/VF devices on the same port share the hardware MTU
 609          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 610          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 611          * driver, there is no need to stop the port for hns3 VF device, and the
 612          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 613          * PF's MTU.
 614          */
 615         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 616                 hns3_err(hw, "Failed to set mtu during resetting");
 617                 return -EIO;
 618         }
 619
 620         /*
 621          * when Rx of scattered packets is off, we have some possibility of
 622          * using vector Rx process function or simple Rx functions in hns3 PMD
 623          * driver. If the input MTU is increased and the maximum length of
 624          * received packets is greater than the length of a buffer for Rx
 625          * packet, the hardware network engine needs to use multiple BDs and
 626          * buffers to store these packets. This will cause problems when still
 627          * using vector Rx process function or simple Rx function to receiving
 628          * packets. So, when Rx of scattered packets is off and device is
 629          * started, it is not permitted to increase MTU so that the maximum
 630          * length of Rx packets is greater than Rx buffer length.
 631          */
 632         if (dev->data->dev_started && !dev->data->scattered_rx &&
 633             frame_size > hw->rx_buf_len) {
 634                 hns3_err(hw, "failed to set mtu because current is "
 635                         "not scattered rx mode");
 636                 return -EOPNOTSUPP;
 637         }
 638
 639         rte_spinlock_lock(&hw->lock);
 640         ret = hns3vf_config_mtu(hw, mtu);
 641         if (ret) {
 642                 rte_spinlock_unlock(&hw->lock);
 643                 return ret;
 644         }
 645         rte_spinlock_unlock(&hw->lock);
 646
 647         return 0;
 648 }
 649
 650 static int
 651 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 652 {
 653         struct hns3_adapter *hns = eth_dev->data->dev_private;
 654         struct hns3_hw *hw = &hns->hw;
 655         uint16_t q_num = hw->tqps_num;
 656
 657         /*
 658          * In interrupt mode, 'max_rx_queues' is set based on the number of
 659          * MSI-X interrupt resources of the hardware.
 660          */
 661         if (hw->data->dev_conf.intr_conf.rxq == 1)
 662                 q_num = hw->intr_tqps_num;
 663
 664         info->max_rx_queues = q_num;
 665         info->max_tx_queues = hw->tqps_num;
 666         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 667         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 668         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 669         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 670         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 671
 672         info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
 673                                  RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
 674                                  RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
 675                                  RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
 676                                  RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 677                                  RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
 678                                  RTE_ETH_RX_OFFLOAD_SCATTER |
 679                                  RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
 680                                  RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
 681                                  RTE_ETH_RX_OFFLOAD_RSS_HASH |
 682                                  RTE_ETH_RX_OFFLOAD_TCP_LRO);
 683         info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 684                                  RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
 685                                  RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
 686                                  RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
 687                                  RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
 688                                  RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
 689                                  RTE_ETH_TX_OFFLOAD_TCP_TSO |
 690                                  RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
 691                                  RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
 692                                  RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
 693                                  RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
 694                                  hns3_txvlan_cap_get(hw));
 695
 696         if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
 697                 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
 698
 699         if (hns3_dev_get_support(hw, INDEP_TXRX))
 700                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 701                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 702
 703         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 704                 .nb_max = HNS3_MAX_RING_DESC,
 705                 .nb_min = HNS3_MIN_RING_DESC,
 706                 .nb_align = HNS3_ALIGN_RING_DESC,
 707         };
 708
 709         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 710                 .nb_max = HNS3_MAX_RING_DESC,
 711                 .nb_min = HNS3_MIN_RING_DESC,
 712                 .nb_align = HNS3_ALIGN_RING_DESC,
 713                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 714                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
 715         };
 716
 717         info->default_rxconf = (struct rte_eth_rxconf) {
 718                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 719                 /*
 720                  * If there are no available Rx buffer descriptors, incoming
 721                  * packets are always dropped by hardware based on hns3 network
 722                  * engine.
 723                  */
 724                 .rx_drop_en = 1,
 725                 .offloads = 0,
 726         };
 727         info->default_txconf = (struct rte_eth_txconf) {
 728                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 729                 .offloads = 0,
 730         };
 731
 732         info->reta_size = hw->rss_ind_tbl_size;
 733         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 734         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 735
 736         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 737         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 738         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 739         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 740         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 741         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 742
 743         return 0;
 744 }
 745
 746 static void
 747 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 748 {
 749         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 750 }
 751
 752 static void
 753 hns3vf_disable_irq0(struct hns3_hw *hw)
 754 {
 755         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 756 }
 757
 758 static void
 759 hns3vf_enable_irq0(struct hns3_hw *hw)
 760 {
 761         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 762 }
 763
 764 static enum hns3vf_evt_cause
 765 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 766 {
 767         struct hns3_hw *hw = &hns->hw;
 768         enum hns3vf_evt_cause ret;
 769         uint32_t cmdq_stat_reg;
 770         uint32_t rst_ing_reg;
 771         uint32_t val;
 772
 773         /* Fetch the events from their corresponding regs */
 774         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 775         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 776                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 777                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 778                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 779                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 780                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 781                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 782                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 783                 if (clearval) {
 784                         hw->reset.stats.global_cnt++;
 785                         hns3_warn(hw, "Global reset detected, clear reset status");
 786                 } else {
 787                         hns3_schedule_delayed_reset(hns);
 788                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 789                 }
 790
 791                 ret = HNS3VF_VECTOR0_EVENT_RST;
 792                 goto out;
 793         }
 794
 795         /* Check for vector0 mailbox(=CMDQ RX) event source */
 796         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
 797                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 798                 ret = HNS3VF_VECTOR0_EVENT_MBX;
 799                 goto out;
 800         }
 801
 802         val = 0;
 803         ret = HNS3VF_VECTOR0_EVENT_OTHER;
 804 out:
 805         if (clearval)
 806                 *clearval = val;
 807         return ret;
 808 }
 809
 810 static void
 811 hns3vf_interrupt_handler(void *param)
 812 {
 813         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 814         struct hns3_adapter *hns = dev->data->dev_private;
 815         struct hns3_hw *hw = &hns->hw;
 816         enum hns3vf_evt_cause event_cause;
 817         uint32_t clearval;
 818
 819         /* Disable interrupt */
 820         hns3vf_disable_irq0(hw);
 821
 822         /* Read out interrupt causes */
 823         event_cause = hns3vf_check_event_cause(hns, &clearval);
 824         /* Clear interrupt causes */
 825         hns3vf_clear_event_cause(hw, clearval);
 826
 827         switch (event_cause) {
 828         case HNS3VF_VECTOR0_EVENT_RST:
 829                 hns3_schedule_reset(hns);
 830                 break;
 831         case HNS3VF_VECTOR0_EVENT_MBX:
 832                 hns3_dev_handle_mbx_msg(hw);
 833                 break;
 834         default:
 835                 break;
 836         }
 837
 838         /* Enable interrupt */
 839         hns3vf_enable_irq0(hw);
 840 }
 841
 842 static void
 843 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
 844 {
 845         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
 846         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
 847         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
 848         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
 849 }
 850
 851 static void
 852 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
 853 {
 854         struct hns3_dev_specs_0_cmd *req0;
 855
 856         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
 857
 858         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
 859         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
 860         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
 861         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
 862 }
 863
 864 static int
 865 hns3vf_check_dev_specifications(struct hns3_hw *hw)
 866 {
 867         if (hw->rss_ind_tbl_size == 0 ||
 868             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
 869                 hns3_warn(hw, "the size of hash lookup table configured (%u)"
 870                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
 871                               HNS3_RSS_IND_TBL_SIZE_MAX);
 872                 return -EINVAL;
 873         }
 874
 875         return 0;
 876 }
 877
 878 static int
 879 hns3vf_query_dev_specifications(struct hns3_hw *hw)
 880 {
 881         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
 882         int ret;
 883         int i;
 884
 885         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
 886                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
 887                                           true);
 888                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 889         }
 890         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
 891
 892         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
 893         if (ret)
 894                 return ret;
 895
 896         hns3vf_parse_dev_specifications(hw, desc);
 897
 898         return hns3vf_check_dev_specifications(hw);
 899 }
 900
 901 void
 902 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
 903 {
 904         uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
 905                                    HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
 906         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
 907         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
 908
 909         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
 910                 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
 911                                           __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
 912 }
 913
 914 static void
 915 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
 916 {
 917 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS      500
 918
 919         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
 920         int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
 921         uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
 922         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
 923         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
 924
 925         __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
 926                          __ATOMIC_RELEASE);
 927
 928         (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
 929                                 NULL, 0);
 930
 931         while (remain_ms > 0) {
 932                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
 933                 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
 934                         HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
 935                         break;
 936                 remain_ms--;
 937         }
 938
 939         /*
 940          * When exit above loop, the pf_push_lsc_cap could be one of the three
 941          * state: unknown (means pf not ack), not_supported, supported.
 942          * Here config it as 'not_supported' when it's 'unknown' state.
 943          */
 944         __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
 945                                   __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
 946
 947         if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
 948                 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
 949                 hns3_info(hw, "detect PF support push link status change!");
 950         } else {
 951                 /*
 952                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
 953                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
 954                  * the RTE_ETH_DEV_INTR_LSC capability.
 955                  */
 956                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
 957         }
 958 }
 959
 960 static int
 961 hns3vf_get_capability(struct hns3_hw *hw)
 962 {
 963         struct rte_pci_device *pci_dev;
 964         struct rte_eth_dev *eth_dev;
 965         uint8_t revision;
 966         int ret;
 967
 968         eth_dev = &rte_eth_devices[hw->data->port_id];
 969         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 970
 971         /* Get PCI revision id */
 972         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
 973                                   HNS3_PCI_REVISION_ID);
 974         if (ret != HNS3_PCI_REVISION_ID_LEN) {
 975                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
 976                              ret);
 977                 return -EIO;
 978         }
 979         hw->revision = revision;
 980
 981         if (revision < PCI_REVISION_ID_HIP09_A) {
 982                 hns3vf_set_default_dev_specifications(hw);
 983                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
 984                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
 985                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
 986                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
 987                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
 988                 hw->rss_info.ipv6_sctp_offload_supported = false;
 989                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
 990                 return 0;
 991         }
 992
 993         ret = hns3vf_query_dev_specifications(hw);
 994         if (ret) {
 995                 PMD_INIT_LOG(ERR,
 996                              "failed to query dev specifications, ret = %d",
 997                              ret);
 998                 return ret;
 999         }
1000
1001         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1002         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1003         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1004         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1005         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1006         hw->rss_info.ipv6_sctp_offload_supported = true;
1007         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1008
1009         return 0;
1010 }
1011
1012 static int
1013 hns3vf_check_tqp_info(struct hns3_hw *hw)
1014 {
1015         if (hw->tqps_num == 0) {
1016                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1017                 return -EINVAL;
1018         }
1019
1020         if (hw->rss_size_max == 0) {
1021                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1022                 return -EINVAL;
1023         }
1024
1025         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1026
1027         return 0;
1028 }
1029
1030 static int
1031 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1032 {
1033         uint8_t resp_msg;
1034         int ret;
1035
1036         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1037                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1038                                 true, &resp_msg, sizeof(resp_msg));
1039         if (ret) {
1040                 if (ret == -ETIME) {
1041                         /*
1042                          * Getting current port based VLAN state from PF driver
1043                          * will not affect VF driver's basic function. Because
1044                          * the VF driver relies on hns3 PF kernel ether driver,
1045                          * to avoid introducing compatibility issues with older
1046                          * version of PF driver, no failure will be returned
1047                          * when the return value is ETIME. This return value has
1048                          * the following scenarios:
1049                          * 1) Firmware didn't return the results in time
1050                          * 2) the result return by firmware is timeout
1051                          * 3) the older version of kernel side PF driver does
1052                          *    not support this mailbox message.
1053                          * For scenarios 1 and 2, it is most likely that a
1054                          * hardware error has occurred, or a hardware reset has
1055                          * occurred. In this case, these errors will be caught
1056                          * by other functions.
1057                          */
1058                         PMD_INIT_LOG(WARNING,
1059                                 "failed to get PVID state for timeout, maybe "
1060                                 "kernel side PF driver doesn't support this "
1061                                 "mailbox message, or firmware didn't respond.");
1062                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1063                 } else {
1064                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1065                                 " ret = %d", ret);
1066                         return ret;
1067                 }
1068         }
1069         hw->port_base_vlan_cfg.state = resp_msg ?
1070                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1071         return 0;
1072 }
1073
1074 static int
1075 hns3vf_get_queue_info(struct hns3_hw *hw)
1076 {
1077 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1078         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1079         int ret;
1080
1081         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1082                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1083         if (ret) {
1084                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1085                 return ret;
1086         }
1087
1088         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1089         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1090
1091         return hns3vf_check_tqp_info(hw);
1092 }
1093
1094 static int
1095 hns3vf_get_queue_depth(struct hns3_hw *hw)
1096 {
1097 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1098         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1099         int ret;
1100
1101         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1102                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1103         if (ret) {
1104                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1105                              ret);
1106                 return ret;
1107         }
1108
1109         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1110         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1111
1112         return 0;
1113 }
1114
1115 static void
1116 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1117 {
1118         if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1119                 hns3_set_bit(hw->capability,
1120                                 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1121 }
1122
1123 static int
1124 hns3vf_get_num_tc(struct hns3_hw *hw)
1125 {
1126         uint8_t num_tc = 0;
1127         uint32_t i;
1128
1129         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1130                 if (hw->hw_tc_map & BIT(i))
1131                         num_tc++;
1132         }
1133         return num_tc;
1134 }
1135
1136 static int
1137 hns3vf_get_basic_info(struct hns3_hw *hw)
1138 {
1139         uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1140         struct hns3_basic_info *basic_info;
1141         int ret;
1142
1143         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1144                                 true, resp_msg, sizeof(resp_msg));
1145         if (ret) {
1146                 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1147                                 ret);
1148                 return ret;
1149         }
1150
1151         basic_info = (struct hns3_basic_info *)resp_msg;
1152         hw->hw_tc_map = basic_info->hw_tc_map;
1153         hw->num_tc = hns3vf_get_num_tc(hw);
1154         hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1155         hns3vf_update_caps(hw, basic_info->caps);
1156
1157         return 0;
1158 }
1159
1160 static int
1161 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1162 {
1163         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1164         int ret;
1165
1166         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1167                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1168         if (ret) {
1169                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1170                 return ret;
1171         }
1172
1173         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1174
1175         return 0;
1176 }
1177
1178 static int
1179 hns3vf_get_configuration(struct hns3_hw *hw)
1180 {
1181         int ret;
1182
1183         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1184         hw->rss_dis_flag = false;
1185
1186         /* Get device capability */
1187         ret = hns3vf_get_capability(hw);
1188         if (ret) {
1189                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1190                 return ret;
1191         }
1192
1193         hns3vf_get_push_lsc_cap(hw);
1194
1195         /* Get basic info from PF */
1196         ret = hns3vf_get_basic_info(hw);
1197         if (ret)
1198                 return ret;
1199
1200         /* Get queue configuration from PF */
1201         ret = hns3vf_get_queue_info(hw);
1202         if (ret)
1203                 return ret;
1204
1205         /* Get queue depth info from PF */
1206         ret = hns3vf_get_queue_depth(hw);
1207         if (ret)
1208                 return ret;
1209
1210         /* Get user defined VF MAC addr from PF */
1211         ret = hns3vf_get_host_mac_addr(hw);
1212         if (ret)
1213                 return ret;
1214
1215         return hns3vf_get_port_base_vlan_filter_state(hw);
1216 }
1217
1218 static int
1219 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1220                             uint16_t nb_tx_q)
1221 {
1222         struct hns3_hw *hw = &hns->hw;
1223
1224         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1225 }
1226
1227 static void
1228 hns3vf_request_link_info(struct hns3_hw *hw)
1229 {
1230         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1231         bool send_req;
1232         int ret;
1233
1234         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1235                 return;
1236
1237         send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1238                    vf->req_link_info_cnt > 0;
1239         if (!send_req)
1240                 return;
1241
1242         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1243                                 NULL, 0);
1244         if (ret) {
1245                 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1246                 return;
1247         }
1248
1249         if (vf->req_link_info_cnt > 0)
1250                 vf->req_link_info_cnt--;
1251 }
1252
1253 void
1254 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1255                           uint32_t link_speed, uint8_t link_duplex)
1256 {
1257         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1258         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1259         struct hns3_mac *mac = &hw->mac;
1260         int ret;
1261
1262         /*
1263          * PF kernel driver may push link status when VF driver is in resetting,
1264          * driver will stop polling job in this case, after resetting done
1265          * driver will start polling job again.
1266          * When polling job started, driver will get initial link status by
1267          * sending request to PF kernel driver, then could update link status by
1268          * process PF kernel driver's link status mailbox message.
1269          */
1270         if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1271                 return;
1272
1273         if (hw->adapter_state != HNS3_NIC_STARTED)
1274                 return;
1275
1276         mac->link_status = link_status;
1277         mac->link_speed = link_speed;
1278         mac->link_duplex = link_duplex;
1279         ret = hns3vf_dev_link_update(dev, 0);
1280         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1281                 hns3_start_report_lse(dev);
1282 }
1283
1284 static int
1285 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1286 {
1287 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1288         struct hns3_hw *hw = &hns->hw;
1289         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1290         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1291         uint8_t is_kill = on ? 0 : 1;
1292
1293         msg_data[0] = is_kill;
1294         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1295         memcpy(&msg_data[3], &proto, sizeof(proto));
1296
1297         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1298                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1299                                  0);
1300 }
1301
1302 static int
1303 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1304 {
1305         struct hns3_adapter *hns = dev->data->dev_private;
1306         struct hns3_hw *hw = &hns->hw;
1307         int ret;
1308
1309         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1310                 hns3_err(hw,
1311                          "vf set vlan id failed during resetting, vlan_id =%u",
1312                          vlan_id);
1313                 return -EIO;
1314         }
1315         rte_spinlock_lock(&hw->lock);
1316         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1317         rte_spinlock_unlock(&hw->lock);
1318         if (ret)
1319                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1320                          vlan_id, ret);
1321
1322         return ret;
1323 }
1324
1325 static int
1326 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1327 {
1328         uint8_t msg_data;
1329         int ret;
1330
1331         if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1332                 return 0;
1333
1334         msg_data = enable ? 1 : 0;
1335         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1336                         HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1337                         sizeof(msg_data), true, NULL, 0);
1338         if (ret)
1339                 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1340                                 enable ? "enable" : "disable", ret);
1341
1342         return ret;
1343 }
1344
1345 static int
1346 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1347 {
1348         uint8_t msg_data;
1349         int ret;
1350
1351         msg_data = enable ? 1 : 0;
1352         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1353                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1354         if (ret)
1355                 hns3_err(hw, "vf %s strip failed, ret = %d.",
1356                                 enable ? "enable" : "disable", ret);
1357
1358         return ret;
1359 }
1360
1361 static int
1362 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1363 {
1364         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1365         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1366         unsigned int tmp_mask;
1367         int ret = 0;
1368
1369         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1370                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1371                              "mask = 0x%x", mask);
1372                 return -EIO;
1373         }
1374
1375         tmp_mask = (unsigned int)mask;
1376
1377         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
1378                 rte_spinlock_lock(&hw->lock);
1379                 /* Enable or disable VLAN filter */
1380                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1381                         ret = hns3vf_en_vlan_filter(hw, true);
1382                 else
1383                         ret = hns3vf_en_vlan_filter(hw, false);
1384                 rte_spinlock_unlock(&hw->lock);
1385                 if (ret)
1386                         return ret;
1387         }
1388
1389         /* Vlan stripping setting */
1390         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
1391                 rte_spinlock_lock(&hw->lock);
1392                 /* Enable or disable VLAN stripping */
1393                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1394                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1395                 else
1396                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1397                 rte_spinlock_unlock(&hw->lock);
1398         }
1399
1400         return ret;
1401 }
1402
1403 static int
1404 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1405 {
1406         struct rte_vlan_filter_conf *vfc;
1407         struct hns3_hw *hw = &hns->hw;
1408         uint16_t vlan_id;
1409         uint64_t vbit;
1410         uint64_t ids;
1411         int ret = 0;
1412         uint32_t i;
1413
1414         vfc = &hw->data->vlan_filter_conf;
1415         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1416                 if (vfc->ids[i] == 0)
1417                         continue;
1418                 ids = vfc->ids[i];
1419                 while (ids) {
1420                         /*
1421                          * 64 means the num bits of ids, one bit corresponds to
1422                          * one vlan id
1423                          */
1424                         vlan_id = 64 * i;
1425                         /* count trailing zeroes */
1426                         vbit = ~ids & (ids - 1);
1427                         /* clear least significant bit set */
1428                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1429                         for (; vbit;) {
1430                                 vbit >>= 1;
1431                                 vlan_id++;
1432                         }
1433                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1434                         if (ret) {
1435                                 hns3_err(hw,
1436                                          "VF handle vlan table failed, ret =%d, on = %d",
1437                                          ret, on);
1438                                 return ret;
1439                         }
1440                 }
1441         }
1442
1443         return ret;
1444 }
1445
1446 static int
1447 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1448 {
1449         return hns3vf_handle_all_vlan_table(hns, 0);
1450 }
1451
1452 static int
1453 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1454 {
1455         struct hns3_hw *hw = &hns->hw;
1456         struct rte_eth_conf *dev_conf;
1457         bool en;
1458         int ret;
1459
1460         dev_conf = &hw->data->dev_conf;
1461         en = dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? true
1462                                                                    : false;
1463         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1464         if (ret)
1465                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1466                          ret);
1467         return ret;
1468 }
1469
1470 static int
1471 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1472 {
1473         struct hns3_adapter *hns = dev->data->dev_private;
1474         struct rte_eth_dev_data *data = dev->data;
1475         struct hns3_hw *hw = &hns->hw;
1476         int ret;
1477
1478         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1479             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1480             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1481                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1482                               "or hw_vlan_insert_pvid is not support!");
1483         }
1484
1485         /* Apply vlan offload setting */
1486         ret = hns3vf_vlan_offload_set(dev, RTE_ETH_VLAN_STRIP_MASK |
1487                                         RTE_ETH_VLAN_FILTER_MASK);
1488         if (ret)
1489                 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1490
1491         return ret;
1492 }
1493
1494 static int
1495 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1496 {
1497         uint8_t msg_data;
1498
1499         msg_data = alive ? 1 : 0;
1500         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1501                                  sizeof(msg_data), false, NULL, 0);
1502 }
1503
1504 static void
1505 hns3vf_keep_alive_handler(void *param)
1506 {
1507         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1508         struct hns3_adapter *hns = eth_dev->data->dev_private;
1509         struct hns3_hw *hw = &hns->hw;
1510         int ret;
1511
1512         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1513                                 false, NULL, 0);
1514         if (ret)
1515                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1516                          ret);
1517
1518         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1519                           eth_dev);
1520 }
1521
1522 static void
1523 hns3vf_service_handler(void *param)
1524 {
1525         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1526         struct hns3_adapter *hns = eth_dev->data->dev_private;
1527         struct hns3_hw *hw = &hns->hw;
1528
1529         /*
1530          * The query link status and reset processing are executed in the
1531          * interrupt thread. When the IMP reset occurs, IMP will not respond,
1532          * and the query operation will timeout after 30ms. In the case of
1533          * multiple PF/VFs, each query failure timeout causes the IMP reset
1534          * interrupt to fail to respond within 100ms.
1535          * Before querying the link status, check whether there is a reset
1536          * pending, and if so, abandon the query.
1537          */
1538         if (!hns3vf_is_reset_pending(hns))
1539                 hns3vf_request_link_info(hw);
1540         else
1541                 hns3_warn(hw, "Cancel the query when reset is pending");
1542
1543         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1544                           eth_dev);
1545 }
1546
1547 static void
1548 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1549 {
1550 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT      3
1551
1552         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1553
1554         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1555                 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1556
1557         __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1558
1559         hns3vf_service_handler(dev);
1560 }
1561
1562 static void
1563 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1564 {
1565         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1566
1567         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1568
1569         __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1570 }
1571
1572 static int
1573 hns3_query_vf_resource(struct hns3_hw *hw)
1574 {
1575         struct hns3_vf_res_cmd *req;
1576         struct hns3_cmd_desc desc;
1577         uint16_t num_msi;
1578         int ret;
1579
1580         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1581         ret = hns3_cmd_send(hw, &desc, 1);
1582         if (ret) {
1583                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1584                 return ret;
1585         }
1586
1587         req = (struct hns3_vf_res_cmd *)desc.data;
1588         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1589                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1590         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1591                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1592                          num_msi, HNS3_MIN_VECTOR_NUM);
1593                 return -EINVAL;
1594         }
1595
1596         hw->num_msi = num_msi;
1597
1598         return 0;
1599 }
1600
1601 static int
1602 hns3vf_init_hardware(struct hns3_adapter *hns)
1603 {
1604         struct hns3_hw *hw = &hns->hw;
1605         uint16_t mtu = hw->data->mtu;
1606         int ret;
1607
1608         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1609         if (ret)
1610                 return ret;
1611
1612         ret = hns3vf_config_mtu(hw, mtu);
1613         if (ret)
1614                 goto err_init_hardware;
1615
1616         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1617         if (ret) {
1618                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1619                 goto err_init_hardware;
1620         }
1621
1622         ret = hns3_config_gro(hw, false);
1623         if (ret) {
1624                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1625                 goto err_init_hardware;
1626         }
1627
1628         /*
1629          * In the initialization clearing the all hardware mapping relationship
1630          * configurations between queues and interrupt vectors is needed, so
1631          * some error caused by the residual configurations, such as the
1632          * unexpected interrupt, can be avoid.
1633          */
1634         ret = hns3vf_init_ring_with_vector(hw);
1635         if (ret) {
1636                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1637                 goto err_init_hardware;
1638         }
1639
1640         return 0;
1641
1642 err_init_hardware:
1643         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1644         return ret;
1645 }
1646
1647 static int
1648 hns3vf_clear_vport_list(struct hns3_hw *hw)
1649 {
1650         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1651                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1652                                  NULL, 0);
1653 }
1654
1655 static int
1656 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1657 {
1658         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1659         struct hns3_adapter *hns = eth_dev->data->dev_private;
1660         struct hns3_hw *hw = &hns->hw;
1661         int ret;
1662
1663         PMD_INIT_FUNC_TRACE();
1664
1665         /* Get hardware io base address from pcie BAR2 IO space */
1666         hw->io_base = pci_dev->mem_resource[2].addr;
1667
1668         /* Firmware command queue initialize */
1669         ret = hns3_cmd_init_queue(hw);
1670         if (ret) {
1671                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1672                 goto err_cmd_init_queue;
1673         }
1674
1675         /* Firmware command initialize */
1676         ret = hns3_cmd_init(hw);
1677         if (ret) {
1678                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1679                 goto err_cmd_init;
1680         }
1681
1682         hns3_tx_push_init(eth_dev);
1683
1684         /* Get VF resource */
1685         ret = hns3_query_vf_resource(hw);
1686         if (ret)
1687                 goto err_cmd_init;
1688
1689         rte_spinlock_init(&hw->mbx_resp.lock);
1690
1691         hns3vf_clear_event_cause(hw, 0);
1692
1693         ret = rte_intr_callback_register(pci_dev->intr_handle,
1694                                          hns3vf_interrupt_handler, eth_dev);
1695         if (ret) {
1696                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1697                 goto err_intr_callback_register;
1698         }
1699
1700         /* Enable interrupt */
1701         rte_intr_enable(pci_dev->intr_handle);
1702         hns3vf_enable_irq0(hw);
1703
1704         /* Get configuration from PF */
1705         ret = hns3vf_get_configuration(hw);
1706         if (ret) {
1707                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1708                 goto err_get_config;
1709         }
1710
1711         ret = hns3_tqp_stats_init(hw);
1712         if (ret)
1713                 goto err_get_config;
1714
1715         /* Hardware statistics of imissed registers cleared. */
1716         ret = hns3_update_imissed_stats(hw, true);
1717         if (ret) {
1718                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1719                 goto err_set_tc_queue;
1720         }
1721
1722         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1723         if (ret) {
1724                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1725                 goto err_set_tc_queue;
1726         }
1727
1728         ret = hns3vf_clear_vport_list(hw);
1729         if (ret) {
1730                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1731                 goto err_set_tc_queue;
1732         }
1733
1734         ret = hns3vf_init_hardware(hns);
1735         if (ret)
1736                 goto err_set_tc_queue;
1737
1738         hns3_rss_set_default_args(hw);
1739
1740         ret = hns3vf_set_alive(hw, true);
1741         if (ret) {
1742                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1743                 goto err_set_tc_queue;
1744         }
1745
1746         return 0;
1747
1748 err_set_tc_queue:
1749         hns3_tqp_stats_uninit(hw);
1750
1751 err_get_config:
1752         hns3vf_disable_irq0(hw);
1753         rte_intr_disable(pci_dev->intr_handle);
1754         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1755                              eth_dev);
1756 err_intr_callback_register:
1757 err_cmd_init:
1758         hns3_cmd_uninit(hw);
1759         hns3_cmd_destroy_queue(hw);
1760 err_cmd_init_queue:
1761         hw->io_base = NULL;
1762
1763         return ret;
1764 }
1765
1766 static void
1767 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1768 {
1769         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1770         struct hns3_adapter *hns = eth_dev->data->dev_private;
1771         struct hns3_hw *hw = &hns->hw;
1772
1773         PMD_INIT_FUNC_TRACE();
1774
1775         hns3_rss_uninit(hns);
1776         (void)hns3_config_gro(hw, false);
1777         (void)hns3vf_set_alive(hw, false);
1778         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1779         hns3_flow_uninit(eth_dev);
1780         hns3_tqp_stats_uninit(hw);
1781         hns3vf_disable_irq0(hw);
1782         rte_intr_disable(pci_dev->intr_handle);
1783         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1784                              eth_dev);
1785         hns3_cmd_uninit(hw);
1786         hns3_cmd_destroy_queue(hw);
1787         hw->io_base = NULL;
1788 }
1789
1790 static int
1791 hns3vf_do_stop(struct hns3_adapter *hns)
1792 {
1793         struct hns3_hw *hw = &hns->hw;
1794         int ret;
1795
1796         hw->mac.link_status = RTE_ETH_LINK_DOWN;
1797
1798         /*
1799          * The "hns3vf_do_stop" function will also be called by .stop_service to
1800          * prepare reset. At the time of global or IMP reset, the command cannot
1801          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
1802          * accessed during the reset process. So the mbuf can not be released
1803          * during reset and is required to be released after the reset is
1804          * completed.
1805          */
1806         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
1807                 hns3_dev_release_mbufs(hns);
1808
1809         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
1810                 hns3_configure_all_mac_addr(hns, true);
1811                 ret = hns3_reset_all_tqps(hns);
1812                 if (ret) {
1813                         hns3_err(hw, "failed to reset all queues ret = %d",
1814                                  ret);
1815                         return ret;
1816                 }
1817         }
1818         return 0;
1819 }
1820
1821 static void
1822 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1823 {
1824         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1826         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1827         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1828         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1829         uint16_t q_id;
1830
1831         if (dev->data->dev_conf.intr_conf.rxq == 0)
1832                 return;
1833
1834         /* unmap the ring with vector */
1835         if (rte_intr_allow_others(intr_handle)) {
1836                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1837                 base = RTE_INTR_VEC_RXTX_OFFSET;
1838         }
1839         if (rte_intr_dp_is_en(intr_handle)) {
1840                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1841                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1842                                                            HNS3_RING_TYPE_RX,
1843                                                            q_id);
1844                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
1845                             - 1)
1846                                 vec++;
1847                 }
1848         }
1849         /* Clean datapath event and queue/vec mapping */
1850         rte_intr_efd_disable(intr_handle);
1851
1852         /* Cleanup vector list */
1853         rte_intr_vec_list_free(intr_handle);
1854 }
1855
1856 static int
1857 hns3vf_dev_stop(struct rte_eth_dev *dev)
1858 {
1859         struct hns3_adapter *hns = dev->data->dev_private;
1860         struct hns3_hw *hw = &hns->hw;
1861
1862         PMD_INIT_FUNC_TRACE();
1863         dev->data->dev_started = 0;
1864
1865         hw->adapter_state = HNS3_NIC_STOPPING;
1866         hns3_set_rxtx_function(dev);
1867         rte_wmb();
1868         /* Disable datapath on secondary process. */
1869         hns3_mp_req_stop_rxtx(dev);
1870         /* Prevent crashes when queues are still in use. */
1871         rte_delay_ms(hw->cfg_max_queues);
1872
1873         rte_spinlock_lock(&hw->lock);
1874         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1875                 hns3_stop_tqps(hw);
1876                 hns3vf_do_stop(hns);
1877                 hns3vf_unmap_rx_interrupt(dev);
1878                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1879         }
1880         hns3_rx_scattered_reset(dev);
1881         hns3vf_stop_poll_job(dev);
1882         hns3_stop_report_lse(dev);
1883         rte_spinlock_unlock(&hw->lock);
1884
1885         return 0;
1886 }
1887
1888 static int
1889 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1890 {
1891         struct hns3_adapter *hns = eth_dev->data->dev_private;
1892         struct hns3_hw *hw = &hns->hw;
1893         int ret = 0;
1894
1895         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1896                 return 0;
1897
1898         if (hw->adapter_state == HNS3_NIC_STARTED)
1899                 ret = hns3vf_dev_stop(eth_dev);
1900
1901         hw->adapter_state = HNS3_NIC_CLOSING;
1902         hns3_reset_abort(hns);
1903         hw->adapter_state = HNS3_NIC_CLOSED;
1904         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1905         hns3_configure_all_mc_mac_addr(hns, true);
1906         hns3vf_remove_all_vlan_table(hns);
1907         hns3vf_uninit_vf(eth_dev);
1908         hns3_free_all_queues(eth_dev);
1909         rte_free(hw->reset.wait_data);
1910         hns3_mp_uninit_primary();
1911         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
1912
1913         return ret;
1914 }
1915
1916 static int
1917 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1918                       size_t fw_size)
1919 {
1920         struct hns3_adapter *hns = eth_dev->data->dev_private;
1921         struct hns3_hw *hw = &hns->hw;
1922         uint32_t version = hw->fw_version;
1923         int ret;
1924
1925         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1926                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1927                                       HNS3_FW_VERSION_BYTE3_S),
1928                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1929                                       HNS3_FW_VERSION_BYTE2_S),
1930                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1931                                       HNS3_FW_VERSION_BYTE1_S),
1932                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1933                                       HNS3_FW_VERSION_BYTE0_S));
1934         if (ret < 0)
1935                 return -EINVAL;
1936
1937         ret += 1; /* add the size of '\0' */
1938         if (fw_size < (size_t)ret)
1939                 return ret;
1940         else
1941                 return 0;
1942 }
1943
1944 static int
1945 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1946                        __rte_unused int wait_to_complete)
1947 {
1948         struct hns3_adapter *hns = eth_dev->data->dev_private;
1949         struct hns3_hw *hw = &hns->hw;
1950         struct hns3_mac *mac = &hw->mac;
1951         struct rte_eth_link new_link;
1952
1953         memset(&new_link, 0, sizeof(new_link));
1954         switch (mac->link_speed) {
1955         case RTE_ETH_SPEED_NUM_10M:
1956         case RTE_ETH_SPEED_NUM_100M:
1957         case RTE_ETH_SPEED_NUM_1G:
1958         case RTE_ETH_SPEED_NUM_10G:
1959         case RTE_ETH_SPEED_NUM_25G:
1960         case RTE_ETH_SPEED_NUM_40G:
1961         case RTE_ETH_SPEED_NUM_50G:
1962         case RTE_ETH_SPEED_NUM_100G:
1963         case RTE_ETH_SPEED_NUM_200G:
1964                 if (mac->link_status)
1965                         new_link.link_speed = mac->link_speed;
1966                 break;
1967         default:
1968                 if (mac->link_status)
1969                         new_link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
1970                 break;
1971         }
1972
1973         if (!mac->link_status)
1974                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
1975
1976         new_link.link_duplex = mac->link_duplex;
1977         new_link.link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
1978         new_link.link_autoneg =
1979             !(eth_dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED);
1980
1981         return rte_eth_linkstatus_set(eth_dev, &new_link);
1982 }
1983
1984 static int
1985 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1986 {
1987         struct hns3_hw *hw = &hns->hw;
1988         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1989         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1990         int ret;
1991
1992         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
1993         if (ret)
1994                 return ret;
1995
1996         hns3_enable_rxd_adv_layout(hw);
1997
1998         ret = hns3_init_queues(hns, reset_queue);
1999         if (ret)
2000                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2001
2002         return ret;
2003 }
2004
2005 static int
2006 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2007 {
2008         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2009         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2010         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2011         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2012         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2013         uint32_t intr_vector;
2014         uint16_t q_id;
2015         int ret;
2016
2017         /*
2018          * hns3 needs a separate interrupt to be used as event interrupt which
2019          * could not be shared with task queue pair, so KERNEL drivers need
2020          * support multiple interrupt vectors.
2021          */
2022         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2023             !rte_intr_cap_multiple(intr_handle))
2024                 return 0;
2025
2026         rte_intr_disable(intr_handle);
2027         intr_vector = hw->used_rx_queues;
2028         /* It creates event fd for each intr vector when MSIX is used */
2029         if (rte_intr_efd_enable(intr_handle, intr_vector))
2030                 return -EINVAL;
2031
2032         /* Allocate vector list */
2033         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
2034                                     hw->used_rx_queues)) {
2035                 hns3_err(hw, "Failed to allocate %u rx_queues"
2036                          " intr_vec", hw->used_rx_queues);
2037                 ret = -ENOMEM;
2038                 goto vf_alloc_intr_vec_error;
2039         }
2040
2041         if (rte_intr_allow_others(intr_handle)) {
2042                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2043                 base = RTE_INTR_VEC_RXTX_OFFSET;
2044         }
2045
2046         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2047                 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2048                                                    HNS3_RING_TYPE_RX, q_id);
2049                 if (ret)
2050                         goto vf_bind_vector_error;
2051
2052                 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
2053                         goto vf_bind_vector_error;
2054
2055                 /*
2056                  * If there are not enough efds (e.g. not enough interrupt),
2057                  * remaining queues will be bond to the last interrupt.
2058                  */
2059                 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
2060                         vec++;
2061         }
2062         rte_intr_enable(intr_handle);
2063         return 0;
2064
2065 vf_bind_vector_error:
2066         rte_intr_vec_list_free(intr_handle);
2067 vf_alloc_intr_vec_error:
2068         rte_intr_efd_disable(intr_handle);
2069         return ret;
2070 }
2071
2072 static int
2073 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2074 {
2075         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2076         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2077         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2078         uint16_t q_id;
2079         int ret;
2080
2081         if (dev->data->dev_conf.intr_conf.rxq == 0)
2082                 return 0;
2083
2084         if (rte_intr_dp_is_en(intr_handle)) {
2085                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2086                         ret = hns3vf_bind_ring_with_vector(hw,
2087                                 rte_intr_vec_list_index_get(intr_handle,
2088                                                                    q_id),
2089                                 true, HNS3_RING_TYPE_RX, q_id);
2090                         if (ret)
2091                                 return ret;
2092                 }
2093         }
2094
2095         return 0;
2096 }
2097
2098 static void
2099 hns3vf_restore_filter(struct rte_eth_dev *dev)
2100 {
2101         hns3_restore_rss_filter(dev);
2102 }
2103
2104 static int
2105 hns3vf_dev_start(struct rte_eth_dev *dev)
2106 {
2107         struct hns3_adapter *hns = dev->data->dev_private;
2108         struct hns3_hw *hw = &hns->hw;
2109         int ret;
2110
2111         PMD_INIT_FUNC_TRACE();
2112         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2113                 return -EBUSY;
2114
2115         rte_spinlock_lock(&hw->lock);
2116         hw->adapter_state = HNS3_NIC_STARTING;
2117         ret = hns3vf_do_start(hns, true);
2118         if (ret) {
2119                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2120                 rte_spinlock_unlock(&hw->lock);
2121                 return ret;
2122         }
2123         ret = hns3vf_map_rx_interrupt(dev);
2124         if (ret)
2125                 goto map_rx_inter_err;
2126
2127         /*
2128          * There are three register used to control the status of a TQP
2129          * (contains a pair of Tx queue and Rx queue) in the new version network
2130          * engine. One is used to control the enabling of Tx queue, the other is
2131          * used to control the enabling of Rx queue, and the last is the master
2132          * switch used to control the enabling of the tqp. The Tx register and
2133          * TQP register must be enabled at the same time to enable a Tx queue.
2134          * The same applies to the Rx queue. For the older network enginem, this
2135          * function only refresh the enabled flag, and it is used to update the
2136          * status of queue in the dpdk framework.
2137          */
2138         ret = hns3_start_all_txqs(dev);
2139         if (ret)
2140                 goto map_rx_inter_err;
2141
2142         ret = hns3_start_all_rxqs(dev);
2143         if (ret)
2144                 goto start_all_rxqs_fail;
2145
2146         hw->adapter_state = HNS3_NIC_STARTED;
2147         rte_spinlock_unlock(&hw->lock);
2148
2149         hns3_rx_scattered_calc(dev);
2150         hns3_set_rxtx_function(dev);
2151         hns3_mp_req_start_rxtx(dev);
2152
2153         hns3vf_restore_filter(dev);
2154
2155         /* Enable interrupt of all rx queues before enabling queues */
2156         hns3_dev_all_rx_queue_intr_enable(hw, true);
2157         hns3_start_tqps(hw);
2158
2159         if (dev->data->dev_conf.intr_conf.lsc != 0)
2160                 hns3vf_dev_link_update(dev, 0);
2161         hns3vf_start_poll_job(dev);
2162
2163         return ret;
2164
2165 start_all_rxqs_fail:
2166         hns3_stop_all_txqs(dev);
2167 map_rx_inter_err:
2168         (void)hns3vf_do_stop(hns);
2169         hw->adapter_state = HNS3_NIC_CONFIGURED;
2170         rte_spinlock_unlock(&hw->lock);
2171
2172         return ret;
2173 }
2174
2175 static bool
2176 is_vf_reset_done(struct hns3_hw *hw)
2177 {
2178 #define HNS3_FUN_RST_ING_BITS \
2179         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2180          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2181          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2182          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2183
2184         uint32_t val;
2185
2186         if (hw->reset.level == HNS3_VF_RESET) {
2187                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2188                 if (val & HNS3_VF_RST_ING_BIT)
2189                         return false;
2190         } else {
2191                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2192                 if (val & HNS3_FUN_RST_ING_BITS)
2193                         return false;
2194         }
2195         return true;
2196 }
2197
2198 bool
2199 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2200 {
2201         struct hns3_hw *hw = &hns->hw;
2202         enum hns3_reset_level reset;
2203
2204         /*
2205          * According to the protocol of PCIe, FLR to a PF device resets the PF
2206          * state as well as the SR-IOV extended capability including VF Enable
2207          * which means that VFs no longer exist.
2208          *
2209          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2210          * is in FLR stage, the register state of VF device is not reliable,
2211          * so register states detection can not be carried out. In this case,
2212          * we just ignore the register states and return false to indicate that
2213          * there are no other reset states that need to be processed by driver.
2214          */
2215         if (hw->reset.level == HNS3_VF_FULL_RESET)
2216                 return false;
2217
2218         /* Check the registers to confirm whether there is reset pending */
2219         hns3vf_check_event_cause(hns, NULL);
2220         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2221         if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2222             hw->reset.level < reset) {
2223                 hns3_warn(hw, "High level reset %d is pending", reset);
2224                 return true;
2225         }
2226         return false;
2227 }
2228
2229 static int
2230 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2231 {
2232         struct hns3_hw *hw = &hns->hw;
2233         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2234         struct timeval tv;
2235
2236         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2237                 /*
2238                  * After vf reset is ready, the PF may not have completed
2239                  * the reset processing. The vf sending mbox to PF may fail
2240                  * during the pf reset, so it is better to add extra delay.
2241                  */
2242                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2243                     hw->reset.level == HNS3_FLR_RESET)
2244                         return 0;
2245                 /* Reset retry process, no need to add extra delay. */
2246                 if (hw->reset.attempts)
2247                         return 0;
2248                 if (wait_data->check_completion == NULL)
2249                         return 0;
2250
2251                 wait_data->check_completion = NULL;
2252                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2253                 wait_data->count = 1;
2254                 wait_data->result = HNS3_WAIT_REQUEST;
2255                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2256                                   wait_data);
2257                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2258                 return -EAGAIN;
2259         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2260                 hns3_clock_gettime(&tv);
2261                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2262                           tv.tv_sec, tv.tv_usec);
2263                 return -ETIME;
2264         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2265                 return -EAGAIN;
2266
2267         wait_data->hns = hns;
2268         wait_data->check_completion = is_vf_reset_done;
2269         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2270                                 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2271         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2272         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2273         wait_data->result = HNS3_WAIT_REQUEST;
2274         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2275         return -EAGAIN;
2276 }
2277
2278 static int
2279 hns3vf_prepare_reset(struct hns3_adapter *hns)
2280 {
2281         struct hns3_hw *hw = &hns->hw;
2282         int ret;
2283
2284         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2285                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2286                                         0, true, NULL, 0);
2287                 if (ret)
2288                         return ret;
2289         }
2290         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2291
2292         return 0;
2293 }
2294
2295 static int
2296 hns3vf_stop_service(struct hns3_adapter *hns)
2297 {
2298         struct hns3_hw *hw = &hns->hw;
2299         struct rte_eth_dev *eth_dev;
2300
2301         eth_dev = &rte_eth_devices[hw->data->port_id];
2302         if (hw->adapter_state == HNS3_NIC_STARTED) {
2303                 /*
2304                  * Make sure call update link status before hns3vf_stop_poll_job
2305                  * because update link status depend on polling job exist.
2306                  */
2307                 hns3vf_update_link_status(hw, RTE_ETH_LINK_DOWN, hw->mac.link_speed,
2308                                           hw->mac.link_duplex);
2309                 hns3vf_stop_poll_job(eth_dev);
2310         }
2311         hw->mac.link_status = RTE_ETH_LINK_DOWN;
2312
2313         hns3_set_rxtx_function(eth_dev);
2314         rte_wmb();
2315         /* Disable datapath on secondary process. */
2316         hns3_mp_req_stop_rxtx(eth_dev);
2317         rte_delay_ms(hw->cfg_max_queues);
2318
2319         rte_spinlock_lock(&hw->lock);
2320         if (hw->adapter_state == HNS3_NIC_STARTED ||
2321             hw->adapter_state == HNS3_NIC_STOPPING) {
2322                 hns3_enable_all_queues(hw, false);
2323                 hns3vf_do_stop(hns);
2324                 hw->reset.mbuf_deferred_free = true;
2325         } else
2326                 hw->reset.mbuf_deferred_free = false;
2327
2328         /*
2329          * It is cumbersome for hardware to pick-and-choose entries for deletion
2330          * from table space. Hence, for function reset software intervention is
2331          * required to delete the entries.
2332          */
2333         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2334                 hns3_configure_all_mc_mac_addr(hns, true);
2335         rte_spinlock_unlock(&hw->lock);
2336
2337         return 0;
2338 }
2339
2340 static int
2341 hns3vf_start_service(struct hns3_adapter *hns)
2342 {
2343         struct hns3_hw *hw = &hns->hw;
2344         struct rte_eth_dev *eth_dev;
2345
2346         eth_dev = &rte_eth_devices[hw->data->port_id];
2347         hns3_set_rxtx_function(eth_dev);
2348         hns3_mp_req_start_rxtx(eth_dev);
2349         if (hw->adapter_state == HNS3_NIC_STARTED) {
2350                 hns3vf_start_poll_job(eth_dev);
2351
2352                 /* Enable interrupt of all rx queues before enabling queues */
2353                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2354                 /*
2355                  * Enable state of each rxq and txq will be recovered after
2356                  * reset, so we need to restore them before enable all tqps;
2357                  */
2358                 hns3_restore_tqp_enable_state(hw);
2359                 /*
2360                  * When finished the initialization, enable queues to receive
2361                  * and transmit packets.
2362                  */
2363                 hns3_enable_all_queues(hw, true);
2364         }
2365
2366         return 0;
2367 }
2368
2369 static int
2370 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2371 {
2372         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2373         struct rte_ether_addr *hw_mac;
2374         int ret;
2375
2376         /*
2377          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2378          * on the host by "ip link set ..." command. If the hns3 PF kernel
2379          * ethdev driver sets the MAC address for VF device after the
2380          * initialization of the related VF device, the PF driver will notify
2381          * VF driver to reset VF device to make the new MAC address effective
2382          * immediately. The hns3 VF PMD driver should check whether the MAC
2383          * address has been changed by the PF kernel ethdev driver, if changed
2384          * VF driver should configure hardware using the new MAC address in the
2385          * recovering hardware configuration stage of the reset process.
2386          */
2387         ret = hns3vf_get_host_mac_addr(hw);
2388         if (ret)
2389                 return ret;
2390
2391         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2392         ret = rte_is_zero_ether_addr(hw_mac);
2393         if (ret) {
2394                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2395         } else {
2396                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2397                 if (!ret) {
2398                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2399                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2400                                               &hw->data->mac_addrs[0]);
2401                         hns3_warn(hw, "Default MAC address has been changed to:"
2402                                   " %s by the host PF kernel ethdev driver",
2403                                   mac_str);
2404                 }
2405         }
2406
2407         return 0;
2408 }
2409
2410 static int
2411 hns3vf_restore_conf(struct hns3_adapter *hns)
2412 {
2413         struct hns3_hw *hw = &hns->hw;
2414         int ret;
2415
2416         ret = hns3vf_check_default_mac_change(hw);
2417         if (ret)
2418                 return ret;
2419
2420         ret = hns3_configure_all_mac_addr(hns, false);
2421         if (ret)
2422                 return ret;
2423
2424         ret = hns3_configure_all_mc_mac_addr(hns, false);
2425         if (ret)
2426                 goto err_mc_mac;
2427
2428         ret = hns3vf_restore_promisc(hns);
2429         if (ret)
2430                 goto err_vlan_table;
2431
2432         ret = hns3vf_restore_vlan_conf(hns);
2433         if (ret)
2434                 goto err_vlan_table;
2435
2436         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2437         if (ret)
2438                 goto err_vlan_table;
2439
2440         ret = hns3vf_restore_rx_interrupt(hw);
2441         if (ret)
2442                 goto err_vlan_table;
2443
2444         ret = hns3_restore_gro_conf(hw);
2445         if (ret)
2446                 goto err_vlan_table;
2447
2448         if (hw->adapter_state == HNS3_NIC_STARTED) {
2449                 ret = hns3vf_do_start(hns, false);
2450                 if (ret)
2451                         goto err_vlan_table;
2452                 hns3_info(hw, "hns3vf dev restart successful!");
2453         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2454                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2455
2456         ret = hns3vf_set_alive(hw, true);
2457         if (ret) {
2458                 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2459                 goto err_vlan_table;
2460         }
2461
2462         return 0;
2463
2464 err_vlan_table:
2465         hns3_configure_all_mc_mac_addr(hns, true);
2466 err_mc_mac:
2467         hns3_configure_all_mac_addr(hns, true);
2468         return ret;
2469 }
2470
2471 static enum hns3_reset_level
2472 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2473 {
2474         enum hns3_reset_level reset_level;
2475
2476         /* return the highest priority reset level amongst all */
2477         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2478                 reset_level = HNS3_VF_RESET;
2479         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2480                 reset_level = HNS3_VF_FULL_RESET;
2481         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2482                 reset_level = HNS3_VF_PF_FUNC_RESET;
2483         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2484                 reset_level = HNS3_VF_FUNC_RESET;
2485         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2486                 reset_level = HNS3_FLR_RESET;
2487         else
2488                 reset_level = HNS3_NONE_RESET;
2489
2490         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2491                 return HNS3_NONE_RESET;
2492
2493         return reset_level;
2494 }
2495
2496 static void
2497 hns3vf_reset_service(void *param)
2498 {
2499         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2500         struct hns3_hw *hw = &hns->hw;
2501         enum hns3_reset_level reset_level;
2502         struct timeval tv_delta;
2503         struct timeval tv_start;
2504         struct timeval tv;
2505         uint64_t msec;
2506
2507         /*
2508          * The interrupt is not triggered within the delay time.
2509          * The interrupt may have been lost. It is necessary to handle
2510          * the interrupt to recover from the error.
2511          */
2512         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2513                             SCHEDULE_DEFERRED) {
2514                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2515                                  __ATOMIC_RELAXED);
2516                 hns3_err(hw, "Handling interrupts in delayed tasks");
2517                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2518                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2519                 if (reset_level == HNS3_NONE_RESET) {
2520                         hns3_err(hw, "No reset level is set, try global reset");
2521                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2522                 }
2523         }
2524         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2525
2526         /*
2527          * Hardware reset has been notified, we now have to poll & check if
2528          * hardware has actually completed the reset sequence.
2529          */
2530         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2531         if (reset_level != HNS3_NONE_RESET) {
2532                 hns3_clock_gettime(&tv_start);
2533                 hns3_reset_process(hns, reset_level);
2534                 hns3_clock_gettime(&tv);
2535                 timersub(&tv, &tv_start, &tv_delta);
2536                 msec = hns3_clock_calctime_ms(&tv_delta);
2537                 if (msec > HNS3_RESET_PROCESS_MS)
2538                         hns3_err(hw, "%d handle long time delta %" PRIu64
2539                                  " ms time=%ld.%.6ld",
2540                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2541         }
2542 }
2543
2544 static int
2545 hns3vf_reinit_dev(struct hns3_adapter *hns)
2546 {
2547         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2548         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2549         struct hns3_hw *hw = &hns->hw;
2550         int ret;
2551
2552         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2553                 rte_intr_disable(pci_dev->intr_handle);
2554                 ret = hns3vf_set_bus_master(pci_dev, true);
2555                 if (ret < 0) {
2556                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2557                         return ret;
2558                 }
2559         }
2560
2561         /* Firmware command initialize */
2562         ret = hns3_cmd_init(hw);
2563         if (ret) {
2564                 hns3_err(hw, "Failed to init cmd: %d", ret);
2565                 return ret;
2566         }
2567
2568         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2569                 /*
2570                  * UIO enables msix by writing the pcie configuration space
2571                  * vfio_pci enables msix in rte_intr_enable.
2572                  */
2573                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2574                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2575                         if (hns3vf_enable_msix(pci_dev, true))
2576                                 hns3_err(hw, "Failed to enable msix");
2577                 }
2578
2579                 rte_intr_enable(pci_dev->intr_handle);
2580         }
2581
2582         ret = hns3_reset_all_tqps(hns);
2583         if (ret) {
2584                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2585                 return ret;
2586         }
2587
2588         ret = hns3vf_init_hardware(hns);
2589         if (ret) {
2590                 hns3_err(hw, "Failed to init hardware: %d", ret);
2591                 return ret;
2592         }
2593
2594         return 0;
2595 }
2596
2597 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2598         .dev_configure      = hns3vf_dev_configure,
2599         .dev_start          = hns3vf_dev_start,
2600         .dev_stop           = hns3vf_dev_stop,
2601         .dev_close          = hns3vf_dev_close,
2602         .mtu_set            = hns3vf_dev_mtu_set,
2603         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2604         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2605         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2606         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2607         .stats_get          = hns3_stats_get,
2608         .stats_reset        = hns3_stats_reset,
2609         .xstats_get         = hns3_dev_xstats_get,
2610         .xstats_get_names   = hns3_dev_xstats_get_names,
2611         .xstats_reset       = hns3_dev_xstats_reset,
2612         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2613         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2614         .dev_infos_get      = hns3vf_dev_infos_get,
2615         .fw_version_get     = hns3vf_fw_version_get,
2616         .rx_queue_setup     = hns3_rx_queue_setup,
2617         .tx_queue_setup     = hns3_tx_queue_setup,
2618         .rx_queue_release   = hns3_dev_rx_queue_release,
2619         .tx_queue_release   = hns3_dev_tx_queue_release,
2620         .rx_queue_start     = hns3_dev_rx_queue_start,
2621         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2622         .tx_queue_start     = hns3_dev_tx_queue_start,
2623         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2624         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2625         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2626         .rxq_info_get       = hns3_rxq_info_get,
2627         .txq_info_get       = hns3_txq_info_get,
2628         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2629         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2630         .mac_addr_add       = hns3_add_mac_addr,
2631         .mac_addr_remove    = hns3_remove_mac_addr,
2632         .mac_addr_set       = hns3vf_set_default_mac_addr,
2633         .set_mc_addr_list   = hns3_set_mc_mac_addr_list,
2634         .link_update        = hns3vf_dev_link_update,
2635         .rss_hash_update    = hns3_dev_rss_hash_update,
2636         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2637         .reta_update        = hns3_dev_rss_reta_update,
2638         .reta_query         = hns3_dev_rss_reta_query,
2639         .flow_ops_get       = hns3_dev_flow_ops_get,
2640         .vlan_filter_set    = hns3vf_vlan_filter_set,
2641         .vlan_offload_set   = hns3vf_vlan_offload_set,
2642         .get_reg            = hns3_get_regs,
2643         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2644         .tx_done_cleanup    = hns3_tx_done_cleanup,
2645 };
2646
2647 static const struct hns3_reset_ops hns3vf_reset_ops = {
2648         .reset_service       = hns3vf_reset_service,
2649         .stop_service        = hns3vf_stop_service,
2650         .prepare_reset       = hns3vf_prepare_reset,
2651         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2652         .reinit_dev          = hns3vf_reinit_dev,
2653         .restore_conf        = hns3vf_restore_conf,
2654         .start_service       = hns3vf_start_service,
2655 };
2656
2657 static void
2658 hns3vf_init_hw_ops(struct hns3_hw *hw)
2659 {
2660         hw->ops.add_mc_mac_addr = hns3vf_add_mc_mac_addr;
2661         hw->ops.del_mc_mac_addr = hns3vf_remove_mc_mac_addr;
2662         hw->ops.add_uc_mac_addr = hns3vf_add_uc_mac_addr;
2663         hw->ops.del_uc_mac_addr = hns3vf_remove_uc_mac_addr;
2664 }
2665
2666 static int
2667 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2668 {
2669         struct hns3_adapter *hns = eth_dev->data->dev_private;
2670         struct hns3_hw *hw = &hns->hw;
2671         int ret;
2672
2673         PMD_INIT_FUNC_TRACE();
2674
2675         hns3_flow_init(eth_dev);
2676
2677         hns3_set_rxtx_function(eth_dev);
2678         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2679         eth_dev->rx_queue_count = hns3_rx_queue_count;
2680         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2681                 ret = hns3_mp_init_secondary();
2682                 if (ret) {
2683                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2684                                           "process, ret = %d", ret);
2685                         goto err_mp_init_secondary;
2686                 }
2687                 hw->secondary_cnt++;
2688                 hns3_tx_push_init(eth_dev);
2689                 return 0;
2690         }
2691
2692         ret = hns3_mp_init_primary();
2693         if (ret) {
2694                 PMD_INIT_LOG(ERR,
2695                              "Failed to init for primary process, ret = %d",
2696                              ret);
2697                 goto err_mp_init_primary;
2698         }
2699
2700         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2701         hns->is_vf = true;
2702         hw->data = eth_dev->data;
2703         hns3_parse_devargs(eth_dev);
2704
2705         ret = hns3_reset_init(hw);
2706         if (ret)
2707                 goto err_init_reset;
2708         hw->reset.ops = &hns3vf_reset_ops;
2709
2710         hns3vf_init_hw_ops(hw);
2711         ret = hns3vf_init_vf(eth_dev);
2712         if (ret) {
2713                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2714                 goto err_init_vf;
2715         }
2716
2717         /* Allocate memory for storing MAC addresses */
2718         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2719                                                sizeof(struct rte_ether_addr) *
2720                                                HNS3_VF_UC_MACADDR_NUM, 0);
2721         if (eth_dev->data->mac_addrs == NULL) {
2722                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2723                              "to store MAC addresses",
2724                              sizeof(struct rte_ether_addr) *
2725                              HNS3_VF_UC_MACADDR_NUM);
2726                 ret = -ENOMEM;
2727                 goto err_rte_zmalloc;
2728         }
2729
2730         /*
2731          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2732          * on the host by "ip link set ..." command. To avoid some incorrect
2733          * scenes, for example, hns3 VF PMD driver fails to receive and send
2734          * packets after user configure the MAC address by using the
2735          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2736          * address strategy as the hns3 kernel ethdev driver in the
2737          * initialization. If user configure a MAC address by the ip command
2738          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2739          * start with a random MAC address in the initialization.
2740          */
2741         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2742                 rte_eth_random_addr(hw->mac.mac_addr);
2743         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2744                             &eth_dev->data->mac_addrs[0]);
2745
2746         hw->adapter_state = HNS3_NIC_INITIALIZED;
2747
2748         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2749                             SCHEDULE_PENDING) {
2750                 hns3_err(hw, "Reschedule reset service after dev_init");
2751                 hns3_schedule_reset(hns);
2752         } else {
2753                 /* IMP will wait ready flag before reset */
2754                 hns3_notify_reset_ready(hw, false);
2755         }
2756         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2757                           eth_dev);
2758         return 0;
2759
2760 err_rte_zmalloc:
2761         hns3vf_uninit_vf(eth_dev);
2762
2763 err_init_vf:
2764         rte_free(hw->reset.wait_data);
2765
2766 err_init_reset:
2767         hns3_mp_uninit_primary();
2768
2769 err_mp_init_primary:
2770 err_mp_init_secondary:
2771         eth_dev->dev_ops = NULL;
2772         eth_dev->rx_pkt_burst = NULL;
2773         eth_dev->rx_descriptor_status = NULL;
2774         eth_dev->tx_pkt_burst = NULL;
2775         eth_dev->tx_pkt_prepare = NULL;
2776         eth_dev->tx_descriptor_status = NULL;
2777
2778         return ret;
2779 }
2780
2781 static int
2782 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2783 {
2784         struct hns3_adapter *hns = eth_dev->data->dev_private;
2785         struct hns3_hw *hw = &hns->hw;
2786
2787         PMD_INIT_FUNC_TRACE();
2788
2789         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2790                 return 0;
2791
2792         if (hw->adapter_state < HNS3_NIC_CLOSING)
2793                 hns3vf_dev_close(eth_dev);
2794
2795         hw->adapter_state = HNS3_NIC_REMOVED;
2796         return 0;
2797 }
2798
2799 static int
2800 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2801                      struct rte_pci_device *pci_dev)
2802 {
2803         return rte_eth_dev_pci_generic_probe(pci_dev,
2804                                              sizeof(struct hns3_adapter),
2805                                              hns3vf_dev_init);
2806 }
2807
2808 static int
2809 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2810 {
2811         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2812 }
2813
2814 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2815         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2816         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2817         { .vendor_id = 0, }, /* sentinel */
2818 };
2819
2820 static struct rte_pci_driver rte_hns3vf_pmd = {
2821         .id_table = pci_id_hns3vf_map,
2822         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2823         .probe = eth_hns3vf_pci_probe,
2824         .remove = eth_hns3vf_pci_remove,
2825 };
2826
2827 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2828 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2829 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
2830 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
2831                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
2832                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
2833                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
2834                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16_t> ");