1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #include <linux/pci_regs.h>
7 #include <ethdev_pci.h>
11 #include "hns3_ethdev.h"
12 #include "hns3_common.h"
13 #include "hns3_logs.h"
14 #include "hns3_rxtx.h"
15 #include "hns3_regs.h"
16 #include "hns3_intr.h"
19 #include "hns3_flow.h"
21 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */
22 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */
24 #define HNS3VF_RESET_WAIT_MS 20
25 #define HNS3VF_RESET_WAIT_CNT 2000
27 /* Reset related Registers */
28 #define HNS3_GLOBAL_RESET_BIT 0
29 #define HNS3_CORE_RESET_BIT 1
30 #define HNS3_IMP_RESET_BIT 2
31 #define HNS3_FUN_RST_ING_B 0
33 enum hns3vf_evt_cause {
34 HNS3VF_VECTOR0_EVENT_RST,
35 HNS3VF_VECTOR0_EVENT_MBX,
36 HNS3VF_VECTOR0_EVENT_OTHER,
39 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
41 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
42 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
44 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
45 struct rte_ether_addr *mac_addr);
46 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
47 struct rte_ether_addr *mac_addr);
48 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
49 __rte_unused int wait_to_complete);
51 /* set PCI bus mastering */
53 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
58 ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND);
60 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
66 /* set the master bit */
67 reg |= PCI_COMMAND_MASTER;
69 reg &= ~(PCI_COMMAND_MASTER);
71 return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND);
75 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
76 * @cap: the capability
78 * Return the address of the given capability within the PCI capability list.
81 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
83 #define MAX_PCIE_CAPABILITY 48
90 ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
92 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
96 if (!(status & PCI_STATUS_CAP_LIST))
99 ttl = MAX_PCIE_CAPABILITY;
100 ret = rte_pci_read_config(device, &pos, sizeof(pos),
101 PCI_CAPABILITY_LIST);
103 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
104 PCI_CAPABILITY_LIST);
108 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
109 ret = rte_pci_read_config(device, &id, sizeof(id),
110 (pos + PCI_CAP_LIST_ID));
112 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
113 (pos + PCI_CAP_LIST_ID));
123 ret = rte_pci_read_config(device, &pos, sizeof(pos),
124 (pos + PCI_CAP_LIST_NEXT));
126 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
127 (pos + PCI_CAP_LIST_NEXT));
135 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
141 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
143 ret = rte_pci_read_config(device, &control, sizeof(control),
144 (pos + PCI_MSIX_FLAGS));
146 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
147 (pos + PCI_MSIX_FLAGS));
152 control |= PCI_MSIX_FLAGS_ENABLE;
154 control &= ~PCI_MSIX_FLAGS_ENABLE;
155 ret = rte_pci_write_config(device, &control, sizeof(control),
156 (pos + PCI_MSIX_FLAGS));
158 PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
159 (pos + PCI_MSIX_FLAGS));
170 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
172 /* mac address was checked by upper level interface */
173 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
176 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
177 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
178 RTE_ETHER_ADDR_LEN, false, NULL, 0);
180 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
182 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
189 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
191 /* mac address was checked by upper level interface */
192 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
195 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
196 HNS3_MBX_MAC_VLAN_UC_REMOVE,
197 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
200 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
202 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
209 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
210 struct rte_ether_addr *mac_addr)
212 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
213 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
214 struct rte_ether_addr *old_addr;
215 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
216 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
220 * It has been guaranteed that input parameter named mac_addr is valid
221 * address in the rte layer of DPDK framework.
223 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
224 rte_spinlock_lock(&hw->lock);
225 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
226 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
229 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
230 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
231 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
234 * The hns3 VF PMD depends on the hns3 PF kernel ethdev
235 * driver. When user has configured a MAC address for VF device
236 * by "ip link set ..." command based on the PF device, the hns3
237 * PF kernel ethdev driver does not allow VF driver to request
238 * reconfiguring a different default MAC address, and return
239 * -EPREM to VF driver through mailbox.
242 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
244 hns3_warn(hw, "Has permanent mac addr(%s) for vf",
247 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
249 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
254 rte_ether_addr_copy(mac_addr,
255 (struct rte_ether_addr *)hw->mac.mac_addr);
256 rte_spinlock_unlock(&hw->lock);
262 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
263 struct rte_ether_addr *mac_addr)
265 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
268 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
269 HNS3_MBX_MAC_VLAN_MC_ADD,
270 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
273 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
275 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
283 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
284 struct rte_ether_addr *mac_addr)
286 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
289 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
290 HNS3_MBX_MAC_VLAN_MC_REMOVE,
291 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
294 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
296 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
304 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
305 bool en_uc_pmc, bool en_mc_pmc)
307 struct hns3_mbx_vf_to_pf_cmd *req;
308 struct hns3_cmd_desc desc;
311 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
314 * The hns3 VF PMD depends on the hns3 PF kernel ethdev driver,
315 * so there are some features for promiscuous/allmulticast mode in hns3
317 * 1. The promiscuous/allmulticast mode can be configured successfully
318 * only based on the trusted VF device. If based on the non trusted
319 * VF device, configuring promiscuous/allmulticast mode will fail.
320 * The hns3 VF device can be configured as trusted device by hns3 PF
321 * kernel ethdev driver on the host by the following command:
322 * "ip link set <eth num> vf <vf id> turst on"
323 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
324 * can receive the ingress and outgoing traffic. This includes
325 * all the ingress packets, all the packets sent from the PF and
326 * other VFs on the same physical port.
327 * 3. Note: Because of the hardware constraints, By default vlan filter
328 * is enabled and couldn't be turned off based on VF device, so vlan
329 * filter is still effective even in promiscuous mode. If upper
330 * applications don't call rte_eth_dev_vlan_filter API function to
331 * set vlan based on VF device, hns3 VF PMD will can't receive
332 * the packets with vlan tag in promiscuous mode.
334 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
335 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
336 req->msg[1] = en_bc_pmc ? 1 : 0;
337 req->msg[2] = en_uc_pmc ? 1 : 0;
338 req->msg[3] = en_mc_pmc ? 1 : 0;
339 req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
341 ret = hns3_cmd_send(hw, &desc, 1);
343 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
349 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
351 struct hns3_adapter *hns = dev->data->dev_private;
352 struct hns3_hw *hw = &hns->hw;
355 ret = hns3vf_set_promisc_mode(hw, true, true, true);
357 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
363 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
365 bool allmulti = dev->data->all_multicast ? true : false;
366 struct hns3_adapter *hns = dev->data->dev_private;
367 struct hns3_hw *hw = &hns->hw;
370 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
372 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
378 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
380 struct hns3_adapter *hns = dev->data->dev_private;
381 struct hns3_hw *hw = &hns->hw;
384 if (dev->data->promiscuous)
387 ret = hns3vf_set_promisc_mode(hw, true, false, true);
389 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
395 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
397 struct hns3_adapter *hns = dev->data->dev_private;
398 struct hns3_hw *hw = &hns->hw;
401 if (dev->data->promiscuous)
404 ret = hns3vf_set_promisc_mode(hw, true, false, false);
406 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
412 hns3vf_restore_promisc(struct hns3_adapter *hns)
414 struct hns3_hw *hw = &hns->hw;
415 bool allmulti = hw->data->all_multicast ? true : false;
417 if (hw->data->promiscuous)
418 return hns3vf_set_promisc_mode(hw, true, true, true);
420 return hns3vf_set_promisc_mode(hw, true, false, allmulti);
424 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id,
425 bool mmap, enum hns3_ring_type queue_type,
428 struct hns3_vf_bind_vector_msg bind_msg;
433 memset(&bind_msg, 0, sizeof(bind_msg));
434 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
435 HNS3_MBX_UNMAP_RING_TO_VECTOR;
436 bind_msg.vector_id = (uint8_t)vector_id;
438 if (queue_type == HNS3_RING_TYPE_RX)
439 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
441 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
443 bind_msg.param[0].ring_type = queue_type;
444 bind_msg.ring_num = 1;
445 bind_msg.param[0].tqp_index = queue_id;
446 op_str = mmap ? "Map" : "Unmap";
447 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
448 sizeof(bind_msg), false, NULL, 0);
450 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
451 op_str, queue_id, bind_msg.vector_id, ret);
457 hns3vf_dev_configure(struct rte_eth_dev *dev)
459 struct hns3_adapter *hns = dev->data->dev_private;
460 struct hns3_hw *hw = &hns->hw;
461 struct rte_eth_conf *conf = &dev->data->dev_conf;
462 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
463 uint16_t nb_rx_q = dev->data->nb_rx_queues;
464 uint16_t nb_tx_q = dev->data->nb_tx_queues;
465 struct rte_eth_rss_conf rss_conf;
469 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
472 * Some versions of hardware network engine does not support
473 * individually enable/disable/reset the Tx or Rx queue. These devices
474 * must enable/disable/reset Tx and Rx queues at the same time. When the
475 * numbers of Tx queues allocated by upper applications are not equal to
476 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
477 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
478 * work as usual. But these fake queues are imperceptible, and can not
479 * be used by upper applications.
481 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
483 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
484 hw->cfg_max_queues = 0;
488 hw->adapter_state = HNS3_NIC_CONFIGURING;
489 if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
490 hns3_err(hw, "setting link speed/duplex not supported");
495 /* When RSS is not configured, redirect the packet queue 0 */
496 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
497 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
498 hw->rss_dis_flag = false;
499 rss_conf = conf->rx_adv_conf.rss_conf;
500 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
505 ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
509 ret = hns3vf_dev_configure_vlan(dev);
513 /* config hardware GRO */
514 gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
515 ret = hns3_config_gro(hw, gro_en);
519 hns3_init_rx_ptype_tble(dev);
521 hw->adapter_state = HNS3_NIC_CONFIGURED;
525 hw->cfg_max_queues = 0;
526 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
527 hw->adapter_state = HNS3_NIC_INITIALIZED;
533 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
537 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
538 sizeof(mtu), true, NULL, 0);
540 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
546 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
548 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
549 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
553 * The hns3 PF/VF devices on the same port share the hardware MTU
554 * configuration. Currently, we send mailbox to inform hns3 PF kernel
555 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD,
556 * there is no need to stop the port for hns3 VF device, and the
557 * MTU value issued by hns3 VF PMD must be less than or equal to
560 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
561 hns3_err(hw, "Failed to set mtu during resetting");
566 * when Rx of scattered packets is off, we have some possibility of
567 * using vector Rx process function or simple Rx functions in hns3 PMD.
568 * If the input MTU is increased and the maximum length of
569 * received packets is greater than the length of a buffer for Rx
570 * packet, the hardware network engine needs to use multiple BDs and
571 * buffers to store these packets. This will cause problems when still
572 * using vector Rx process function or simple Rx function to receiving
573 * packets. So, when Rx of scattered packets is off and device is
574 * started, it is not permitted to increase MTU so that the maximum
575 * length of Rx packets is greater than Rx buffer length.
577 if (dev->data->dev_started && !dev->data->scattered_rx &&
578 frame_size > hw->rx_buf_len) {
579 hns3_err(hw, "failed to set mtu because current is "
580 "not scattered rx mode");
584 rte_spinlock_lock(&hw->lock);
585 ret = hns3vf_config_mtu(hw, mtu);
587 rte_spinlock_unlock(&hw->lock);
590 rte_spinlock_unlock(&hw->lock);
596 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
598 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
602 hns3vf_disable_irq0(struct hns3_hw *hw)
604 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
608 hns3vf_enable_irq0(struct hns3_hw *hw)
610 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
613 static enum hns3vf_evt_cause
614 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
616 struct hns3_hw *hw = &hns->hw;
617 enum hns3vf_evt_cause ret;
618 uint32_t cmdq_stat_reg;
619 uint32_t rst_ing_reg;
622 /* Fetch the events from their corresponding regs */
623 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
624 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
625 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
626 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
627 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
628 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
629 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
630 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
631 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
633 hw->reset.stats.global_cnt++;
634 hns3_warn(hw, "Global reset detected, clear reset status");
636 hns3_schedule_delayed_reset(hns);
637 hns3_warn(hw, "Global reset detected, don't clear reset status");
640 ret = HNS3VF_VECTOR0_EVENT_RST;
644 /* Check for vector0 mailbox(=CMDQ RX) event source */
645 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
646 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
647 ret = HNS3VF_VECTOR0_EVENT_MBX;
652 ret = HNS3VF_VECTOR0_EVENT_OTHER;
660 hns3vf_interrupt_handler(void *param)
662 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
663 struct hns3_adapter *hns = dev->data->dev_private;
664 struct hns3_hw *hw = &hns->hw;
665 enum hns3vf_evt_cause event_cause;
668 /* Disable interrupt */
669 hns3vf_disable_irq0(hw);
671 /* Read out interrupt causes */
672 event_cause = hns3vf_check_event_cause(hns, &clearval);
673 /* Clear interrupt causes */
674 hns3vf_clear_event_cause(hw, clearval);
676 switch (event_cause) {
677 case HNS3VF_VECTOR0_EVENT_RST:
678 hns3_schedule_reset(hns);
680 case HNS3VF_VECTOR0_EVENT_MBX:
681 hns3_dev_handle_mbx_msg(hw);
687 /* Enable interrupt */
688 hns3vf_enable_irq0(hw);
692 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
694 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
695 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
696 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
697 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
701 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
703 struct hns3_dev_specs_0_cmd *req0;
705 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
707 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
708 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
709 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
710 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
714 hns3vf_check_dev_specifications(struct hns3_hw *hw)
716 if (hw->rss_ind_tbl_size == 0 ||
717 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
718 hns3_warn(hw, "the size of hash lookup table configured (%u)"
719 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
720 HNS3_RSS_IND_TBL_SIZE_MAX);
728 hns3vf_query_dev_specifications(struct hns3_hw *hw)
730 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
734 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
735 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
737 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
739 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
741 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
745 hns3vf_parse_dev_specifications(hw, desc);
747 return hns3vf_check_dev_specifications(hw);
751 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
753 uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
754 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
755 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
756 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
758 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
759 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
760 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
764 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
766 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS 500
768 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
769 int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
770 uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
771 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
772 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
774 __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
777 (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
780 while (remain_ms > 0) {
781 rte_delay_ms(HNS3_POLL_RESPONE_MS);
782 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
783 HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
789 * When exit above loop, the pf_push_lsc_cap could be one of the three
790 * state: unknown (means pf not ack), not_supported, supported.
791 * Here config it as 'not_supported' when it's 'unknown' state.
793 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
794 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
796 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
797 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
798 hns3_info(hw, "detect PF support push link status change!");
801 * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
802 * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
803 * the RTE_ETH_DEV_INTR_LSC capability.
805 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
810 hns3vf_get_capability(struct hns3_hw *hw)
814 ret = hns3_get_pci_revision_id(hw, &hw->revision);
818 if (hw->revision < PCI_REVISION_ID_HIP09_A) {
819 hns3vf_set_default_dev_specifications(hw);
820 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
821 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
822 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
823 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
824 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
825 hw->rss_info.ipv6_sctp_offload_supported = false;
826 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
830 ret = hns3vf_query_dev_specifications(hw);
833 "failed to query dev specifications, ret = %d",
838 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
839 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
840 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
841 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
842 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
843 hw->rss_info.ipv6_sctp_offload_supported = true;
844 hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
850 hns3vf_check_tqp_info(struct hns3_hw *hw)
852 if (hw->tqps_num == 0) {
853 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
857 if (hw->rss_size_max == 0) {
858 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
862 hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
868 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
873 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
874 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
875 true, &resp_msg, sizeof(resp_msg));
879 * Getting current port based VLAN state from PF driver
880 * will not affect VF driver's basic function. Because
881 * the VF driver relies on hns3 PF kernel ether driver,
882 * to avoid introducing compatibility issues with older
883 * version of PF driver, no failure will be returned
884 * when the return value is ETIME. This return value has
885 * the following scenarios:
886 * 1) Firmware didn't return the results in time
887 * 2) the result return by firmware is timeout
888 * 3) the older version of kernel side PF driver does
889 * not support this mailbox message.
890 * For scenarios 1 and 2, it is most likely that a
891 * hardware error has occurred, or a hardware reset has
892 * occurred. In this case, these errors will be caught
893 * by other functions.
895 PMD_INIT_LOG(WARNING,
896 "failed to get PVID state for timeout, maybe "
897 "kernel side PF driver doesn't support this "
898 "mailbox message, or firmware didn't respond.");
899 resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
901 PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
906 hw->port_base_vlan_cfg.state = resp_msg ?
907 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
912 hns3vf_get_queue_info(struct hns3_hw *hw)
914 #define HNS3VF_TQPS_RSS_INFO_LEN 6
915 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
918 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
919 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
921 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
925 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
926 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
928 return hns3vf_check_tqp_info(hw);
932 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
934 if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
935 hns3_set_bit(hw->capability,
936 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
940 hns3vf_get_num_tc(struct hns3_hw *hw)
945 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
946 if (hw->hw_tc_map & BIT(i))
953 hns3vf_get_basic_info(struct hns3_hw *hw)
955 uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
956 struct hns3_basic_info *basic_info;
959 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
960 true, resp_msg, sizeof(resp_msg));
962 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
967 basic_info = (struct hns3_basic_info *)resp_msg;
968 hw->hw_tc_map = basic_info->hw_tc_map;
969 hw->num_tc = hns3vf_get_num_tc(hw);
970 hw->pf_vf_if_version = basic_info->pf_vf_if_version;
971 hns3vf_update_caps(hw, basic_info->caps);
977 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
979 uint8_t host_mac[RTE_ETHER_ADDR_LEN];
982 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
983 true, host_mac, RTE_ETHER_ADDR_LEN);
985 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
989 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
995 hns3vf_get_configuration(struct hns3_hw *hw)
999 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1000 hw->rss_dis_flag = false;
1002 /* Get device capability */
1003 ret = hns3vf_get_capability(hw);
1005 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1009 hns3vf_get_push_lsc_cap(hw);
1011 /* Get basic info from PF */
1012 ret = hns3vf_get_basic_info(hw);
1016 /* Get queue configuration from PF */
1017 ret = hns3vf_get_queue_info(hw);
1021 /* Get user defined VF MAC addr from PF */
1022 ret = hns3vf_get_host_mac_addr(hw);
1026 return hns3vf_get_port_base_vlan_filter_state(hw);
1030 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1033 struct hns3_hw *hw = &hns->hw;
1035 return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1039 hns3vf_request_link_info(struct hns3_hw *hw)
1041 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1045 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1048 send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1049 vf->req_link_info_cnt > 0;
1053 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1056 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1060 if (vf->req_link_info_cnt > 0)
1061 vf->req_link_info_cnt--;
1065 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1066 uint32_t link_speed, uint8_t link_duplex)
1068 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1069 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1070 struct hns3_mac *mac = &hw->mac;
1074 * PF kernel driver may push link status when VF driver is in resetting,
1075 * driver will stop polling job in this case, after resetting done
1076 * driver will start polling job again.
1077 * When polling job started, driver will get initial link status by
1078 * sending request to PF kernel driver, then could update link status by
1079 * process PF kernel driver's link status mailbox message.
1081 if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1084 if (hw->adapter_state != HNS3_NIC_STARTED)
1087 mac->link_status = link_status;
1088 mac->link_speed = link_speed;
1089 mac->link_duplex = link_duplex;
1090 ret = hns3vf_dev_link_update(dev, 0);
1091 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1092 hns3_start_report_lse(dev);
1096 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1098 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1099 struct hns3_hw *hw = &hns->hw;
1100 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1101 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1102 uint8_t is_kill = on ? 0 : 1;
1104 msg_data[0] = is_kill;
1105 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1106 memcpy(&msg_data[3], &proto, sizeof(proto));
1108 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1109 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1114 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1116 struct hns3_adapter *hns = dev->data->dev_private;
1117 struct hns3_hw *hw = &hns->hw;
1120 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1122 "vf set vlan id failed during resetting, vlan_id =%u",
1126 rte_spinlock_lock(&hw->lock);
1127 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1128 rte_spinlock_unlock(&hw->lock);
1130 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1137 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1142 if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1145 msg_data = enable ? 1 : 0;
1146 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1147 HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1148 sizeof(msg_data), true, NULL, 0);
1150 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1151 enable ? "enable" : "disable", ret);
1157 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1162 msg_data = enable ? 1 : 0;
1163 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1164 &msg_data, sizeof(msg_data), false, NULL, 0);
1166 hns3_err(hw, "vf %s strip failed, ret = %d.",
1167 enable ? "enable" : "disable", ret);
1173 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1175 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1176 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1177 unsigned int tmp_mask;
1180 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1181 hns3_err(hw, "vf set vlan offload failed during resetting, "
1182 "mask = 0x%x", mask);
1186 tmp_mask = (unsigned int)mask;
1188 if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
1189 rte_spinlock_lock(&hw->lock);
1190 /* Enable or disable VLAN filter */
1191 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1192 ret = hns3vf_en_vlan_filter(hw, true);
1194 ret = hns3vf_en_vlan_filter(hw, false);
1195 rte_spinlock_unlock(&hw->lock);
1200 /* Vlan stripping setting */
1201 if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
1202 rte_spinlock_lock(&hw->lock);
1203 /* Enable or disable VLAN stripping */
1204 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1205 ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1207 ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1208 rte_spinlock_unlock(&hw->lock);
1215 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1217 struct rte_vlan_filter_conf *vfc;
1218 struct hns3_hw *hw = &hns->hw;
1225 vfc = &hw->data->vlan_filter_conf;
1226 for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1227 if (vfc->ids[i] == 0)
1232 * 64 means the num bits of ids, one bit corresponds to
1236 /* count trailing zeroes */
1237 vbit = ~ids & (ids - 1);
1238 /* clear least significant bit set */
1239 ids ^= (ids ^ (ids - 1)) ^ vbit;
1244 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1247 "VF handle vlan table failed, ret =%d, on = %d",
1258 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1260 return hns3vf_handle_all_vlan_table(hns, 0);
1264 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1266 struct hns3_hw *hw = &hns->hw;
1267 struct rte_eth_conf *dev_conf;
1271 dev_conf = &hw->data->dev_conf;
1272 en = dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? true
1274 ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1276 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1282 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1284 struct hns3_adapter *hns = dev->data->dev_private;
1285 struct rte_eth_dev_data *data = dev->data;
1286 struct hns3_hw *hw = &hns->hw;
1289 if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1290 data->dev_conf.txmode.hw_vlan_reject_untagged ||
1291 data->dev_conf.txmode.hw_vlan_insert_pvid) {
1292 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1293 "or hw_vlan_insert_pvid is not support!");
1296 /* Apply vlan offload setting */
1297 ret = hns3vf_vlan_offload_set(dev, RTE_ETH_VLAN_STRIP_MASK |
1298 RTE_ETH_VLAN_FILTER_MASK);
1300 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1306 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1310 msg_data = alive ? 1 : 0;
1311 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1312 sizeof(msg_data), false, NULL, 0);
1316 hns3vf_keep_alive_handler(void *param)
1318 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1319 struct hns3_adapter *hns = eth_dev->data->dev_private;
1320 struct hns3_hw *hw = &hns->hw;
1323 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1326 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1329 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1334 hns3vf_service_handler(void *param)
1336 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1337 struct hns3_adapter *hns = eth_dev->data->dev_private;
1338 struct hns3_hw *hw = &hns->hw;
1341 * The query link status and reset processing are executed in the
1342 * interrupt thread. When the IMP reset occurs, IMP will not respond,
1343 * and the query operation will timeout after 30ms. In the case of
1344 * multiple PF/VFs, each query failure timeout causes the IMP reset
1345 * interrupt to fail to respond within 100ms.
1346 * Before querying the link status, check whether there is a reset
1347 * pending, and if so, abandon the query.
1349 if (!hns3vf_is_reset_pending(hns))
1350 hns3vf_request_link_info(hw);
1352 hns3_warn(hw, "Cancel the query when reset is pending");
1354 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1359 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1361 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT 3
1363 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1365 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1366 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1368 __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1370 hns3vf_service_handler(dev);
1374 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1376 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1378 rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1380 __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1384 hns3_query_vf_resource(struct hns3_hw *hw)
1386 struct hns3_vf_res_cmd *req;
1387 struct hns3_cmd_desc desc;
1391 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1392 ret = hns3_cmd_send(hw, &desc, 1);
1394 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1398 req = (struct hns3_vf_res_cmd *)desc.data;
1399 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1400 HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1401 if (num_msi < HNS3_MIN_VECTOR_NUM) {
1402 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1403 num_msi, HNS3_MIN_VECTOR_NUM);
1407 hw->num_msi = num_msi;
1413 hns3vf_init_hardware(struct hns3_adapter *hns)
1415 struct hns3_hw *hw = &hns->hw;
1416 uint16_t mtu = hw->data->mtu;
1419 ret = hns3vf_set_promisc_mode(hw, true, false, false);
1423 ret = hns3vf_config_mtu(hw, mtu);
1425 goto err_init_hardware;
1427 ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1429 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1430 goto err_init_hardware;
1433 ret = hns3_config_gro(hw, false);
1435 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1436 goto err_init_hardware;
1440 * In the initialization clearing the all hardware mapping relationship
1441 * configurations between queues and interrupt vectors is needed, so
1442 * some error caused by the residual configurations, such as the
1443 * unexpected interrupt, can be avoid.
1445 ret = hns3_init_ring_with_vector(hw);
1447 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1448 goto err_init_hardware;
1454 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1459 hns3vf_clear_vport_list(struct hns3_hw *hw)
1461 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1462 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1467 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1469 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1470 struct hns3_adapter *hns = eth_dev->data->dev_private;
1471 struct hns3_hw *hw = &hns->hw;
1474 PMD_INIT_FUNC_TRACE();
1476 /* Get hardware io base address from pcie BAR2 IO space */
1477 hw->io_base = pci_dev->mem_resource[2].addr;
1479 /* Firmware command queue initialize */
1480 ret = hns3_cmd_init_queue(hw);
1482 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1483 goto err_cmd_init_queue;
1486 /* Firmware command initialize */
1487 ret = hns3_cmd_init(hw);
1489 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1493 hns3_tx_push_init(eth_dev);
1495 /* Get VF resource */
1496 ret = hns3_query_vf_resource(hw);
1500 rte_spinlock_init(&hw->mbx_resp.lock);
1502 hns3vf_clear_event_cause(hw, 0);
1504 ret = rte_intr_callback_register(pci_dev->intr_handle,
1505 hns3vf_interrupt_handler, eth_dev);
1507 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1508 goto err_intr_callback_register;
1511 /* Enable interrupt */
1512 rte_intr_enable(pci_dev->intr_handle);
1513 hns3vf_enable_irq0(hw);
1515 /* Get configuration from PF */
1516 ret = hns3vf_get_configuration(hw);
1518 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1519 goto err_get_config;
1522 ret = hns3_tqp_stats_init(hw);
1524 goto err_get_config;
1526 /* Hardware statistics of imissed registers cleared. */
1527 ret = hns3_update_imissed_stats(hw, true);
1529 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1530 goto err_set_tc_queue;
1533 ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1535 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1536 goto err_set_tc_queue;
1539 ret = hns3vf_clear_vport_list(hw);
1541 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1542 goto err_set_tc_queue;
1545 ret = hns3vf_init_hardware(hns);
1547 goto err_set_tc_queue;
1549 hns3_rss_set_default_args(hw);
1551 ret = hns3vf_set_alive(hw, true);
1553 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1554 goto err_set_tc_queue;
1560 hns3_tqp_stats_uninit(hw);
1563 hns3vf_disable_irq0(hw);
1564 rte_intr_disable(pci_dev->intr_handle);
1565 hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1567 err_intr_callback_register:
1569 hns3_cmd_uninit(hw);
1570 hns3_cmd_destroy_queue(hw);
1578 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1580 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1581 struct hns3_adapter *hns = eth_dev->data->dev_private;
1582 struct hns3_hw *hw = &hns->hw;
1584 PMD_INIT_FUNC_TRACE();
1586 hns3_rss_uninit(hns);
1587 (void)hns3_config_gro(hw, false);
1588 (void)hns3vf_set_alive(hw, false);
1589 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1590 hns3_flow_uninit(eth_dev);
1591 hns3_tqp_stats_uninit(hw);
1592 hns3vf_disable_irq0(hw);
1593 rte_intr_disable(pci_dev->intr_handle);
1594 hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1596 hns3_cmd_uninit(hw);
1597 hns3_cmd_destroy_queue(hw);
1602 hns3vf_do_stop(struct hns3_adapter *hns)
1604 struct hns3_hw *hw = &hns->hw;
1607 hw->mac.link_status = RTE_ETH_LINK_DOWN;
1610 * The "hns3vf_do_stop" function will also be called by .stop_service to
1611 * prepare reset. At the time of global or IMP reset, the command cannot
1612 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
1613 * accessed during the reset process. So the mbuf can not be released
1614 * during reset and is required to be released after the reset is
1617 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)
1618 hns3_dev_release_mbufs(hns);
1620 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
1621 hns3_configure_all_mac_addr(hns, true);
1622 ret = hns3_reset_all_tqps(hns);
1624 hns3_err(hw, "failed to reset all queues ret = %d",
1633 hns3vf_dev_stop(struct rte_eth_dev *dev)
1635 struct hns3_adapter *hns = dev->data->dev_private;
1636 struct hns3_hw *hw = &hns->hw;
1638 PMD_INIT_FUNC_TRACE();
1639 dev->data->dev_started = 0;
1641 hw->adapter_state = HNS3_NIC_STOPPING;
1642 hns3_set_rxtx_function(dev);
1644 /* Disable datapath on secondary process. */
1645 hns3_mp_req_stop_rxtx(dev);
1646 /* Prevent crashes when queues are still in use. */
1647 rte_delay_ms(hw->cfg_max_queues);
1649 rte_spinlock_lock(&hw->lock);
1650 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1652 hns3vf_do_stop(hns);
1653 hns3_unmap_rx_interrupt(dev);
1654 hw->adapter_state = HNS3_NIC_CONFIGURED;
1656 hns3_rx_scattered_reset(dev);
1657 hns3vf_stop_poll_job(dev);
1658 hns3_stop_report_lse(dev);
1659 rte_spinlock_unlock(&hw->lock);
1665 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1667 struct hns3_adapter *hns = eth_dev->data->dev_private;
1668 struct hns3_hw *hw = &hns->hw;
1671 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1672 hns3_mp_uninit(eth_dev);
1676 if (hw->adapter_state == HNS3_NIC_STARTED)
1677 ret = hns3vf_dev_stop(eth_dev);
1679 hw->adapter_state = HNS3_NIC_CLOSING;
1680 hns3_reset_abort(hns);
1681 hw->adapter_state = HNS3_NIC_CLOSED;
1682 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1683 hns3_configure_all_mc_mac_addr(hns, true);
1684 hns3vf_remove_all_vlan_table(hns);
1685 hns3vf_uninit_vf(eth_dev);
1686 hns3_free_all_queues(eth_dev);
1687 rte_free(hw->reset.wait_data);
1688 hns3_mp_uninit(eth_dev);
1689 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
1695 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1696 __rte_unused int wait_to_complete)
1698 struct hns3_adapter *hns = eth_dev->data->dev_private;
1699 struct hns3_hw *hw = &hns->hw;
1700 struct hns3_mac *mac = &hw->mac;
1701 struct rte_eth_link new_link;
1703 memset(&new_link, 0, sizeof(new_link));
1704 switch (mac->link_speed) {
1705 case RTE_ETH_SPEED_NUM_10M:
1706 case RTE_ETH_SPEED_NUM_100M:
1707 case RTE_ETH_SPEED_NUM_1G:
1708 case RTE_ETH_SPEED_NUM_10G:
1709 case RTE_ETH_SPEED_NUM_25G:
1710 case RTE_ETH_SPEED_NUM_40G:
1711 case RTE_ETH_SPEED_NUM_50G:
1712 case RTE_ETH_SPEED_NUM_100G:
1713 case RTE_ETH_SPEED_NUM_200G:
1714 if (mac->link_status)
1715 new_link.link_speed = mac->link_speed;
1718 if (mac->link_status)
1719 new_link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
1723 if (!mac->link_status)
1724 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
1726 new_link.link_duplex = mac->link_duplex;
1727 new_link.link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
1728 new_link.link_autoneg =
1729 !(eth_dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED);
1731 return rte_eth_linkstatus_set(eth_dev, &new_link);
1735 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1737 struct hns3_hw *hw = &hns->hw;
1738 uint16_t nb_rx_q = hw->data->nb_rx_queues;
1739 uint16_t nb_tx_q = hw->data->nb_tx_queues;
1742 ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
1746 hns3_enable_rxd_adv_layout(hw);
1748 ret = hns3_init_queues(hns, reset_queue);
1750 hns3_err(hw, "failed to init queues, ret = %d.", ret);
1756 hns3vf_restore_filter(struct rte_eth_dev *dev)
1758 hns3_restore_rss_filter(dev);
1762 hns3vf_dev_start(struct rte_eth_dev *dev)
1764 struct hns3_adapter *hns = dev->data->dev_private;
1765 struct hns3_hw *hw = &hns->hw;
1768 PMD_INIT_FUNC_TRACE();
1769 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1772 rte_spinlock_lock(&hw->lock);
1773 hw->adapter_state = HNS3_NIC_STARTING;
1774 ret = hns3vf_do_start(hns, true);
1776 hw->adapter_state = HNS3_NIC_CONFIGURED;
1777 rte_spinlock_unlock(&hw->lock);
1780 ret = hns3_map_rx_interrupt(dev);
1782 goto map_rx_inter_err;
1785 * There are three register used to control the status of a TQP
1786 * (contains a pair of Tx queue and Rx queue) in the new version network
1787 * engine. One is used to control the enabling of Tx queue, the other is
1788 * used to control the enabling of Rx queue, and the last is the master
1789 * switch used to control the enabling of the tqp. The Tx register and
1790 * TQP register must be enabled at the same time to enable a Tx queue.
1791 * The same applies to the Rx queue. For the older network enginem, this
1792 * function only refresh the enabled flag, and it is used to update the
1793 * status of queue in the dpdk framework.
1795 ret = hns3_start_all_txqs(dev);
1797 goto map_rx_inter_err;
1799 ret = hns3_start_all_rxqs(dev);
1801 goto start_all_rxqs_fail;
1803 hw->adapter_state = HNS3_NIC_STARTED;
1804 rte_spinlock_unlock(&hw->lock);
1806 hns3_rx_scattered_calc(dev);
1807 hns3_set_rxtx_function(dev);
1808 hns3_mp_req_start_rxtx(dev);
1810 hns3vf_restore_filter(dev);
1812 /* Enable interrupt of all rx queues before enabling queues */
1813 hns3_dev_all_rx_queue_intr_enable(hw, true);
1814 hns3_start_tqps(hw);
1816 if (dev->data->dev_conf.intr_conf.lsc != 0)
1817 hns3vf_dev_link_update(dev, 0);
1818 hns3vf_start_poll_job(dev);
1822 start_all_rxqs_fail:
1823 hns3_stop_all_txqs(dev);
1825 (void)hns3vf_do_stop(hns);
1826 hw->adapter_state = HNS3_NIC_CONFIGURED;
1827 rte_spinlock_unlock(&hw->lock);
1833 is_vf_reset_done(struct hns3_hw *hw)
1835 #define HNS3_FUN_RST_ING_BITS \
1836 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
1837 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
1838 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
1839 BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
1843 if (hw->reset.level == HNS3_VF_RESET) {
1844 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1845 if (val & HNS3_VF_RST_ING_BIT)
1848 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1849 if (val & HNS3_FUN_RST_ING_BITS)
1856 hns3vf_is_reset_pending(struct hns3_adapter *hns)
1858 struct hns3_hw *hw = &hns->hw;
1859 enum hns3_reset_level reset;
1862 * According to the protocol of PCIe, FLR to a PF device resets the PF
1863 * state as well as the SR-IOV extended capability including VF Enable
1864 * which means that VFs no longer exist.
1866 * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
1867 * is in FLR stage, the register state of VF device is not reliable,
1868 * so register states detection can not be carried out. In this case,
1869 * we just ignore the register states and return false to indicate that
1870 * there are no other reset states that need to be processed by driver.
1872 if (hw->reset.level == HNS3_VF_FULL_RESET)
1875 /* Check the registers to confirm whether there is reset pending */
1876 hns3vf_check_event_cause(hns, NULL);
1877 reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
1878 if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
1879 hw->reset.level < reset) {
1880 hns3_warn(hw, "High level reset %d is pending", reset);
1887 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
1889 struct hns3_hw *hw = &hns->hw;
1890 struct hns3_wait_data *wait_data = hw->reset.wait_data;
1893 if (wait_data->result == HNS3_WAIT_SUCCESS) {
1895 * After vf reset is ready, the PF may not have completed
1896 * the reset processing. The vf sending mbox to PF may fail
1897 * during the pf reset, so it is better to add extra delay.
1899 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
1900 hw->reset.level == HNS3_FLR_RESET)
1902 /* Reset retry process, no need to add extra delay. */
1903 if (hw->reset.attempts)
1905 if (wait_data->check_completion == NULL)
1908 wait_data->check_completion = NULL;
1909 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
1910 wait_data->count = 1;
1911 wait_data->result = HNS3_WAIT_REQUEST;
1912 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
1914 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
1916 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
1917 hns3_clock_gettime(&tv);
1918 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
1919 tv.tv_sec, tv.tv_usec);
1921 } else if (wait_data->result == HNS3_WAIT_REQUEST)
1924 wait_data->hns = hns;
1925 wait_data->check_completion = is_vf_reset_done;
1926 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
1927 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
1928 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
1929 wait_data->count = HNS3VF_RESET_WAIT_CNT;
1930 wait_data->result = HNS3_WAIT_REQUEST;
1931 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
1936 hns3vf_prepare_reset(struct hns3_adapter *hns)
1938 struct hns3_hw *hw = &hns->hw;
1941 if (hw->reset.level == HNS3_VF_FUNC_RESET) {
1942 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
1947 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
1953 hns3vf_stop_service(struct hns3_adapter *hns)
1955 struct hns3_hw *hw = &hns->hw;
1956 struct rte_eth_dev *eth_dev;
1958 eth_dev = &rte_eth_devices[hw->data->port_id];
1959 if (hw->adapter_state == HNS3_NIC_STARTED) {
1961 * Make sure call update link status before hns3vf_stop_poll_job
1962 * because update link status depend on polling job exist.
1964 hns3vf_update_link_status(hw, RTE_ETH_LINK_DOWN, hw->mac.link_speed,
1965 hw->mac.link_duplex);
1966 hns3vf_stop_poll_job(eth_dev);
1968 hw->mac.link_status = RTE_ETH_LINK_DOWN;
1970 hns3_set_rxtx_function(eth_dev);
1972 /* Disable datapath on secondary process. */
1973 hns3_mp_req_stop_rxtx(eth_dev);
1974 rte_delay_ms(hw->cfg_max_queues);
1976 rte_spinlock_lock(&hw->lock);
1977 if (hw->adapter_state == HNS3_NIC_STARTED ||
1978 hw->adapter_state == HNS3_NIC_STOPPING) {
1979 hns3_enable_all_queues(hw, false);
1980 hns3vf_do_stop(hns);
1981 hw->reset.mbuf_deferred_free = true;
1983 hw->reset.mbuf_deferred_free = false;
1986 * It is cumbersome for hardware to pick-and-choose entries for deletion
1987 * from table space. Hence, for function reset software intervention is
1988 * required to delete the entries.
1990 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
1991 hns3_configure_all_mc_mac_addr(hns, true);
1992 rte_spinlock_unlock(&hw->lock);
1998 hns3vf_start_service(struct hns3_adapter *hns)
2000 struct hns3_hw *hw = &hns->hw;
2001 struct rte_eth_dev *eth_dev;
2003 eth_dev = &rte_eth_devices[hw->data->port_id];
2004 hns3_set_rxtx_function(eth_dev);
2005 hns3_mp_req_start_rxtx(eth_dev);
2006 if (hw->adapter_state == HNS3_NIC_STARTED) {
2007 hns3vf_start_poll_job(eth_dev);
2009 /* Enable interrupt of all rx queues before enabling queues */
2010 hns3_dev_all_rx_queue_intr_enable(hw, true);
2012 * Enable state of each rxq and txq will be recovered after
2013 * reset, so we need to restore them before enable all tqps;
2015 hns3_restore_tqp_enable_state(hw);
2017 * When finished the initialization, enable queues to receive
2018 * and transmit packets.
2020 hns3_enable_all_queues(hw, true);
2027 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2029 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2030 struct rte_ether_addr *hw_mac;
2034 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2035 * on the host by "ip link set ..." command. If the hns3 PF kernel
2036 * ethdev driver sets the MAC address for VF device after the
2037 * initialization of the related VF device, the PF driver will notify
2038 * VF driver to reset VF device to make the new MAC address effective
2039 * immediately. The hns3 VF PMD should check whether the MAC
2040 * address has been changed by the PF kernel ethdev driver, if changed
2041 * VF driver should configure hardware using the new MAC address in the
2042 * recovering hardware configuration stage of the reset process.
2044 ret = hns3vf_get_host_mac_addr(hw);
2048 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2049 ret = rte_is_zero_ether_addr(hw_mac);
2051 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2053 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2055 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2056 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2057 &hw->data->mac_addrs[0]);
2058 hns3_warn(hw, "Default MAC address has been changed to:"
2059 " %s by the host PF kernel ethdev driver",
2068 hns3vf_restore_conf(struct hns3_adapter *hns)
2070 struct hns3_hw *hw = &hns->hw;
2073 ret = hns3vf_check_default_mac_change(hw);
2077 ret = hns3_configure_all_mac_addr(hns, false);
2081 ret = hns3_configure_all_mc_mac_addr(hns, false);
2085 ret = hns3vf_restore_promisc(hns);
2087 goto err_vlan_table;
2089 ret = hns3vf_restore_vlan_conf(hns);
2091 goto err_vlan_table;
2093 ret = hns3vf_get_port_base_vlan_filter_state(hw);
2095 goto err_vlan_table;
2097 ret = hns3_restore_rx_interrupt(hw);
2099 goto err_vlan_table;
2101 ret = hns3_restore_gro_conf(hw);
2103 goto err_vlan_table;
2105 if (hw->adapter_state == HNS3_NIC_STARTED) {
2106 ret = hns3vf_do_start(hns, false);
2108 goto err_vlan_table;
2109 hns3_info(hw, "hns3vf dev restart successful!");
2110 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2111 hw->adapter_state = HNS3_NIC_CONFIGURED;
2113 ret = hns3vf_set_alive(hw, true);
2115 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2116 goto err_vlan_table;
2122 hns3_configure_all_mc_mac_addr(hns, true);
2124 hns3_configure_all_mac_addr(hns, true);
2128 static enum hns3_reset_level
2129 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2131 enum hns3_reset_level reset_level;
2133 /* return the highest priority reset level amongst all */
2134 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2135 reset_level = HNS3_VF_RESET;
2136 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2137 reset_level = HNS3_VF_FULL_RESET;
2138 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2139 reset_level = HNS3_VF_PF_FUNC_RESET;
2140 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2141 reset_level = HNS3_VF_FUNC_RESET;
2142 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2143 reset_level = HNS3_FLR_RESET;
2145 reset_level = HNS3_NONE_RESET;
2147 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2148 return HNS3_NONE_RESET;
2154 hns3vf_reset_service(void *param)
2156 struct hns3_adapter *hns = (struct hns3_adapter *)param;
2157 struct hns3_hw *hw = &hns->hw;
2158 enum hns3_reset_level reset_level;
2159 struct timeval tv_delta;
2160 struct timeval tv_start;
2165 * The interrupt is not triggered within the delay time.
2166 * The interrupt may have been lost. It is necessary to handle
2167 * the interrupt to recover from the error.
2169 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2170 SCHEDULE_DEFERRED) {
2171 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2173 hns3_err(hw, "Handling interrupts in delayed tasks");
2174 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2175 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2176 if (reset_level == HNS3_NONE_RESET) {
2177 hns3_err(hw, "No reset level is set, try global reset");
2178 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2181 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2184 * Hardware reset has been notified, we now have to poll & check if
2185 * hardware has actually completed the reset sequence.
2187 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2188 if (reset_level != HNS3_NONE_RESET) {
2189 hns3_clock_gettime(&tv_start);
2190 hns3_reset_process(hns, reset_level);
2191 hns3_clock_gettime(&tv);
2192 timersub(&tv, &tv_start, &tv_delta);
2193 msec = hns3_clock_calctime_ms(&tv_delta);
2194 if (msec > HNS3_RESET_PROCESS_MS)
2195 hns3_err(hw, "%d handle long time delta %" PRIu64
2196 " ms time=%ld.%.6ld",
2197 hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2202 hns3vf_reinit_dev(struct hns3_adapter *hns)
2204 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2205 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2206 struct hns3_hw *hw = &hns->hw;
2209 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2210 rte_intr_disable(pci_dev->intr_handle);
2211 ret = hns3vf_set_bus_master(pci_dev, true);
2213 hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2218 /* Firmware command initialize */
2219 ret = hns3_cmd_init(hw);
2221 hns3_err(hw, "Failed to init cmd: %d", ret);
2225 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2227 * UIO enables msix by writing the pcie configuration space
2228 * vfio_pci enables msix in rte_intr_enable.
2230 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2231 pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2232 if (hns3vf_enable_msix(pci_dev, true))
2233 hns3_err(hw, "Failed to enable msix");
2236 rte_intr_enable(pci_dev->intr_handle);
2239 ret = hns3_reset_all_tqps(hns);
2241 hns3_err(hw, "Failed to reset all queues: %d", ret);
2245 ret = hns3vf_init_hardware(hns);
2247 hns3_err(hw, "Failed to init hardware: %d", ret);
2254 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2255 .dev_configure = hns3vf_dev_configure,
2256 .dev_start = hns3vf_dev_start,
2257 .dev_stop = hns3vf_dev_stop,
2258 .dev_close = hns3vf_dev_close,
2259 .mtu_set = hns3vf_dev_mtu_set,
2260 .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2261 .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2262 .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2263 .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2264 .stats_get = hns3_stats_get,
2265 .stats_reset = hns3_stats_reset,
2266 .xstats_get = hns3_dev_xstats_get,
2267 .xstats_get_names = hns3_dev_xstats_get_names,
2268 .xstats_reset = hns3_dev_xstats_reset,
2269 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
2270 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2271 .dev_infos_get = hns3_dev_infos_get,
2272 .fw_version_get = hns3_fw_version_get,
2273 .rx_queue_setup = hns3_rx_queue_setup,
2274 .tx_queue_setup = hns3_tx_queue_setup,
2275 .rx_queue_release = hns3_dev_rx_queue_release,
2276 .tx_queue_release = hns3_dev_tx_queue_release,
2277 .rx_queue_start = hns3_dev_rx_queue_start,
2278 .rx_queue_stop = hns3_dev_rx_queue_stop,
2279 .tx_queue_start = hns3_dev_tx_queue_start,
2280 .tx_queue_stop = hns3_dev_tx_queue_stop,
2281 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
2282 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
2283 .rxq_info_get = hns3_rxq_info_get,
2284 .txq_info_get = hns3_txq_info_get,
2285 .rx_burst_mode_get = hns3_rx_burst_mode_get,
2286 .tx_burst_mode_get = hns3_tx_burst_mode_get,
2287 .mac_addr_add = hns3_add_mac_addr,
2288 .mac_addr_remove = hns3_remove_mac_addr,
2289 .mac_addr_set = hns3vf_set_default_mac_addr,
2290 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
2291 .link_update = hns3vf_dev_link_update,
2292 .rss_hash_update = hns3_dev_rss_hash_update,
2293 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
2294 .reta_update = hns3_dev_rss_reta_update,
2295 .reta_query = hns3_dev_rss_reta_query,
2296 .flow_ops_get = hns3_dev_flow_ops_get,
2297 .vlan_filter_set = hns3vf_vlan_filter_set,
2298 .vlan_offload_set = hns3vf_vlan_offload_set,
2299 .get_reg = hns3_get_regs,
2300 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2301 .tx_done_cleanup = hns3_tx_done_cleanup,
2304 static const struct hns3_reset_ops hns3vf_reset_ops = {
2305 .reset_service = hns3vf_reset_service,
2306 .stop_service = hns3vf_stop_service,
2307 .prepare_reset = hns3vf_prepare_reset,
2308 .wait_hardware_ready = hns3vf_wait_hardware_ready,
2309 .reinit_dev = hns3vf_reinit_dev,
2310 .restore_conf = hns3vf_restore_conf,
2311 .start_service = hns3vf_start_service,
2315 hns3vf_init_hw_ops(struct hns3_hw *hw)
2317 hw->ops.add_mc_mac_addr = hns3vf_add_mc_mac_addr;
2318 hw->ops.del_mc_mac_addr = hns3vf_remove_mc_mac_addr;
2319 hw->ops.add_uc_mac_addr = hns3vf_add_uc_mac_addr;
2320 hw->ops.del_uc_mac_addr = hns3vf_remove_uc_mac_addr;
2321 hw->ops.bind_ring_with_vector = hns3vf_bind_ring_with_vector;
2325 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2327 struct hns3_adapter *hns = eth_dev->data->dev_private;
2328 struct hns3_hw *hw = &hns->hw;
2331 PMD_INIT_FUNC_TRACE();
2333 hns3_flow_init(eth_dev);
2335 hns3_set_rxtx_function(eth_dev);
2336 eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2337 eth_dev->rx_queue_count = hns3_rx_queue_count;
2338 ret = hns3_mp_init(eth_dev);
2342 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2343 hns3_tx_push_init(eth_dev);
2347 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2349 hw->data = eth_dev->data;
2350 hns3_parse_devargs(eth_dev);
2352 ret = hns3_reset_init(hw);
2354 goto err_init_reset;
2355 hw->reset.ops = &hns3vf_reset_ops;
2357 hns3vf_init_hw_ops(hw);
2358 ret = hns3vf_init_vf(eth_dev);
2360 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2364 ret = hns3_init_mac_addrs(eth_dev);
2366 goto err_init_mac_addrs;
2368 hw->adapter_state = HNS3_NIC_INITIALIZED;
2370 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2372 hns3_err(hw, "Reschedule reset service after dev_init");
2373 hns3_schedule_reset(hns);
2375 /* IMP will wait ready flag before reset */
2376 hns3_notify_reset_ready(hw, false);
2378 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2383 hns3vf_uninit_vf(eth_dev);
2386 rte_free(hw->reset.wait_data);
2389 hns3_mp_uninit(eth_dev);
2392 eth_dev->dev_ops = NULL;
2393 eth_dev->rx_pkt_burst = NULL;
2394 eth_dev->rx_descriptor_status = NULL;
2395 eth_dev->tx_pkt_burst = NULL;
2396 eth_dev->tx_pkt_prepare = NULL;
2397 eth_dev->tx_descriptor_status = NULL;
2403 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2405 struct hns3_adapter *hns = eth_dev->data->dev_private;
2406 struct hns3_hw *hw = &hns->hw;
2408 PMD_INIT_FUNC_TRACE();
2410 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2411 __atomic_fetch_sub(&hw->secondary_cnt, 1, __ATOMIC_RELAXED);
2412 hns3_mp_uninit(eth_dev);
2416 if (hw->adapter_state < HNS3_NIC_CLOSING)
2417 hns3vf_dev_close(eth_dev);
2419 hw->adapter_state = HNS3_NIC_REMOVED;
2424 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2425 struct rte_pci_device *pci_dev)
2427 return rte_eth_dev_pci_generic_probe(pci_dev,
2428 sizeof(struct hns3_adapter),
2433 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2435 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2438 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2439 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2440 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2441 { .vendor_id = 0, }, /* sentinel */
2444 static struct rte_pci_driver rte_hns3vf_pmd = {
2445 .id_table = pci_id_hns3vf_map,
2446 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2447 .probe = eth_hns3vf_pci_probe,
2448 .remove = eth_hns3vf_pci_remove,
2451 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2452 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2453 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
2454 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
2455 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
2456 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
2457 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
2458 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16_t> ");