drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
  48                                    __rte_unused int wait_to_complete);
  49
  50 /* set PCI bus mastering */
  51 static int
  52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  53 {
  54         uint16_t reg;
  55         int ret;
  56
  57         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  58         if (ret < 0) {
  59                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  60                              PCI_COMMAND);
  61                 return ret;
  62         }
  63
  64         if (op)
  65                 /* set the master bit */
  66                 reg |= PCI_COMMAND_MASTER;
  67         else
  68                 reg &= ~(PCI_COMMAND_MASTER);
  69
  70         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  71 }
  72
  73 /**
  74  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  75  * @cap: the capability
  76  *
  77  * Return the address of the given capability within the PCI capability list.
  78  */
  79 static int
  80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  81 {
  82 #define MAX_PCIE_CAPABILITY 48
  83         uint16_t status;
  84         uint8_t pos;
  85         uint8_t id;
  86         int ttl;
  87         int ret;
  88
  89         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  90         if (ret < 0) {
  91                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  92                 return 0;
  93         }
  94
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 100                                   PCI_CAPABILITY_LIST);
 101         if (ret < 0) {
 102                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 103                              PCI_CAPABILITY_LIST);
 104                 return 0;
 105         }
 106
 107         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 108                 ret = rte_pci_read_config(device, &id, sizeof(id),
 109                                           (pos + PCI_CAP_LIST_ID));
 110                 if (ret < 0) {
 111                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 112                                      (pos + PCI_CAP_LIST_ID));
 113                         break;
 114                 }
 115
 116                 if (id == 0xFF)
 117                         break;
 118
 119                 if (id == cap)
 120                         return (int)pos;
 121
 122                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 123                                           (pos + PCI_CAP_LIST_NEXT));
 124                 if (ret < 0) {
 125                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 126                                      (pos + PCI_CAP_LIST_NEXT));
 127                         break;
 128                 }
 129         }
 130         return 0;
 131 }
 132
 133 static int
 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 135 {
 136         uint16_t control;
 137         int pos;
 138         int ret;
 139
 140         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 141         if (pos) {
 142                 ret = rte_pci_read_config(device, &control, sizeof(control),
 143                                     (pos + PCI_MSIX_FLAGS));
 144                 if (ret < 0) {
 145                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 146                                      (pos + PCI_MSIX_FLAGS));
 147                         return -ENXIO;
 148                 }
 149
 150                 if (op)
 151                         control |= PCI_MSIX_FLAGS_ENABLE;
 152                 else
 153                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 154                 ret = rte_pci_write_config(device, &control, sizeof(control),
 155                                           (pos + PCI_MSIX_FLAGS));
 156                 if (ret < 0) {
 157                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 158                                     (pos + PCI_MSIX_FLAGS));
 159                         return -ENXIO;
 160                 }
 161
 162                 return 0;
 163         }
 164
 165         return -ENXIO;
 166 }
 167
 168 static int
 169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 170 {
 171         /* mac address was checked by upper level interface */
 172         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 173         int ret;
 174
 175         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 176                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 177                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 178         if (ret) {
 179                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 180                                       mac_addr);
 181                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 182                          mac_str, ret);
 183         }
 184         return ret;
 185 }
 186
 187 static int
 188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 189 {
 190         /* mac address was checked by upper level interface */
 191         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 192         int ret;
 193
 194         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 195                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 196                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 197                                 false, NULL, 0);
 198         if (ret) {
 199                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 200                                       mac_addr);
 201                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 202                          mac_str, ret);
 203         }
 204         return ret;
 205 }
 206
 207 static int
 208 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 209                             struct rte_ether_addr *mac_addr)
 210 {
 211 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 212         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 213         struct rte_ether_addr *old_addr;
 214         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 215         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 216         int ret;
 217
 218         /*
 219          * It has been guaranteed that input parameter named mac_addr is valid
 220          * address in the rte layer of DPDK framework.
 221          */
 222         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 223         rte_spinlock_lock(&hw->lock);
 224         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 225         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 226                RTE_ETHER_ADDR_LEN);
 227
 228         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 229                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 230                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 231         if (ret) {
 232                 /*
 233                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 234                  * driver. When user has configured a MAC address for VF device
 235                  * by "ip link set ..." command based on the PF device, the hns3
 236                  * PF kernel ethdev driver does not allow VF driver to request
 237                  * reconfiguring a different default MAC address, and return
 238                  * -EPREM to VF driver through mailbox.
 239                  */
 240                 if (ret == -EPERM) {
 241                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 242                                               old_addr);
 243                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 244                                   mac_str);
 245                 } else {
 246                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 247                                               mac_addr);
 248                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 249                                  mac_str, ret);
 250                 }
 251         }
 252
 253         rte_ether_addr_copy(mac_addr,
 254                             (struct rte_ether_addr *)hw->mac.mac_addr);
 255         rte_spinlock_unlock(&hw->lock);
 256
 257         return ret;
 258 }
 259
 260 static int
 261 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 262                        struct rte_ether_addr *mac_addr)
 263 {
 264         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 265         int ret;
 266
 267         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 268                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 269                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 270                                 NULL, 0);
 271         if (ret) {
 272                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 273                                       mac_addr);
 274                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 275                          mac_str, ret);
 276         }
 277
 278         return ret;
 279 }
 280
 281 static int
 282 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 283                           struct rte_ether_addr *mac_addr)
 284 {
 285         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 286         int ret;
 287
 288         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 289                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 290                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 291                                 NULL, 0);
 292         if (ret) {
 293                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 294                                       mac_addr);
 295                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 296                          mac_str, ret);
 297         }
 298
 299         return ret;
 300 }
 301
 302 static int
 303 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 304                              struct rte_ether_addr *mc_addr_set,
 305                              uint32_t nb_mc_addr)
 306 {
 307         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 308         struct rte_ether_addr *addr;
 309         uint32_t i;
 310         uint32_t j;
 311
 312         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 313                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
 314                          "invalid. valid range: 0~%d",
 315                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 316                 return -EINVAL;
 317         }
 318
 319         /* Check if input mac addresses are valid */
 320         for (i = 0; i < nb_mc_addr; i++) {
 321                 addr = &mc_addr_set[i];
 322                 if (!rte_is_multicast_ether_addr(addr)) {
 323                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 324                                               addr);
 325                         hns3_err(hw,
 326                                  "failed to set mc mac addr, addr(%s) invalid.",
 327                                  mac_str);
 328                         return -EINVAL;
 329                 }
 330
 331                 /* Check if there are duplicate addresses */
 332                 for (j = i + 1; j < nb_mc_addr; j++) {
 333                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 334                                 hns3_ether_format_addr(mac_str,
 335                                                       RTE_ETHER_ADDR_FMT_SIZE,
 336                                                       addr);
 337                                 hns3_err(hw, "failed to set mc mac addr, "
 338                                          "addrs invalid. two same addrs(%s).",
 339                                          mac_str);
 340                                 return -EINVAL;
 341                         }
 342                 }
 343
 344                 /*
 345                  * Check if there are duplicate addresses between mac_addrs
 346                  * and mc_addr_set
 347                  */
 348                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 349                         if (rte_is_same_ether_addr(addr,
 350                                                    &hw->data->mac_addrs[j])) {
 351                                 hns3_ether_format_addr(mac_str,
 352                                                       RTE_ETHER_ADDR_FMT_SIZE,
 353                                                       addr);
 354                                 hns3_err(hw, "failed to set mc mac addr, "
 355                                          "addrs invalid. addrs(%s) has already "
 356                                          "configured in mac_addr add API",
 357                                          mac_str);
 358                                 return -EINVAL;
 359                         }
 360                 }
 361         }
 362
 363         return 0;
 364 }
 365
 366 static int
 367 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 368                             struct rte_ether_addr *mc_addr_set,
 369                             uint32_t nb_mc_addr)
 370 {
 371         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 372         struct rte_ether_addr *addr;
 373         int cur_addr_num;
 374         int set_addr_num;
 375         int num;
 376         int ret;
 377         int i;
 378
 379         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 380         if (ret)
 381                 return ret;
 382
 383         rte_spinlock_lock(&hw->lock);
 384         cur_addr_num = hw->mc_addrs_num;
 385         for (i = 0; i < cur_addr_num; i++) {
 386                 num = cur_addr_num - i - 1;
 387                 addr = &hw->mc_addrs[num];
 388                 ret = hw->ops.del_mc_mac_addr(hw, addr);
 389                 if (ret) {
 390                         rte_spinlock_unlock(&hw->lock);
 391                         return ret;
 392                 }
 393
 394                 hw->mc_addrs_num--;
 395         }
 396
 397         set_addr_num = (int)nb_mc_addr;
 398         for (i = 0; i < set_addr_num; i++) {
 399                 addr = &mc_addr_set[i];
 400                 ret = hw->ops.add_mc_mac_addr(hw, addr);
 401                 if (ret) {
 402                         rte_spinlock_unlock(&hw->lock);
 403                         return ret;
 404                 }
 405
 406                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 407                 hw->mc_addrs_num++;
 408         }
 409         rte_spinlock_unlock(&hw->lock);
 410
 411         return 0;
 412 }
 413
 414 static int
 415 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 416                         bool en_uc_pmc, bool en_mc_pmc)
 417 {
 418         struct hns3_mbx_vf_to_pf_cmd *req;
 419         struct hns3_cmd_desc desc;
 420         int ret;
 421
 422         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 423
 424         /*
 425          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 426          * so there are some features for promiscuous/allmulticast mode in hns3
 427          * VF PMD driver as below:
 428          * 1. The promiscuous/allmulticast mode can be configured successfully
 429          *    only based on the trusted VF device. If based on the non trusted
 430          *    VF device, configuring promiscuous/allmulticast mode will fail.
 431          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 432          *    kernel ethdev driver on the host by the following command:
 433          *      "ip link set <eth num> vf <vf id> turst on"
 434          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 435          *    driver can receive the ingress and outgoing traffic. In the words,
 436          *    all the ingress packets, all the packets sent from the PF and
 437          *    other VFs on the same physical port.
 438          * 3. Note: Because of the hardware constraints, By default vlan filter
 439          *    is enabled and couldn't be turned off based on VF device, so vlan
 440          *    filter is still effective even in promiscuous mode. If upper
 441          *    applications don't call rte_eth_dev_vlan_filter API function to
 442          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 443          *    the packets with vlan tag in promiscuoue mode.
 444          */
 445         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 446         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 447         req->msg[1] = en_bc_pmc ? 1 : 0;
 448         req->msg[2] = en_uc_pmc ? 1 : 0;
 449         req->msg[3] = en_mc_pmc ? 1 : 0;
 450         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 451
 452         ret = hns3_cmd_send(hw, &desc, 1);
 453         if (ret)
 454                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 455
 456         return ret;
 457 }
 458
 459 static int
 460 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 461 {
 462         struct hns3_adapter *hns = dev->data->dev_private;
 463         struct hns3_hw *hw = &hns->hw;
 464         int ret;
 465
 466         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 467         if (ret)
 468                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 469                         ret);
 470         return ret;
 471 }
 472
 473 static int
 474 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 475 {
 476         bool allmulti = dev->data->all_multicast ? true : false;
 477         struct hns3_adapter *hns = dev->data->dev_private;
 478         struct hns3_hw *hw = &hns->hw;
 479         int ret;
 480
 481         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 482         if (ret)
 483                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 484                         ret);
 485         return ret;
 486 }
 487
 488 static int
 489 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 490 {
 491         struct hns3_adapter *hns = dev->data->dev_private;
 492         struct hns3_hw *hw = &hns->hw;
 493         int ret;
 494
 495         if (dev->data->promiscuous)
 496                 return 0;
 497
 498         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 499         if (ret)
 500                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 501                         ret);
 502         return ret;
 503 }
 504
 505 static int
 506 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 507 {
 508         struct hns3_adapter *hns = dev->data->dev_private;
 509         struct hns3_hw *hw = &hns->hw;
 510         int ret;
 511
 512         if (dev->data->promiscuous)
 513                 return 0;
 514
 515         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 516         if (ret)
 517                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 518                         ret);
 519         return ret;
 520 }
 521
 522 static int
 523 hns3vf_restore_promisc(struct hns3_adapter *hns)
 524 {
 525         struct hns3_hw *hw = &hns->hw;
 526         bool allmulti = hw->data->all_multicast ? true : false;
 527
 528         if (hw->data->promiscuous)
 529                 return hns3vf_set_promisc_mode(hw, true, true, true);
 530
 531         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 532 }
 533
 534 static int
 535 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 536                              bool mmap, enum hns3_ring_type queue_type,
 537                              uint16_t queue_id)
 538 {
 539         struct hns3_vf_bind_vector_msg bind_msg;
 540         const char *op_str;
 541         uint16_t code;
 542         int ret;
 543
 544         memset(&bind_msg, 0, sizeof(bind_msg));
 545         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 546                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 547         bind_msg.vector_id = vector_id;
 548
 549         if (queue_type == HNS3_RING_TYPE_RX)
 550                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 551         else
 552                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 553
 554         bind_msg.param[0].ring_type = queue_type;
 555         bind_msg.ring_num = 1;
 556         bind_msg.param[0].tqp_index = queue_id;
 557         op_str = mmap ? "Map" : "Unmap";
 558         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 559                                 sizeof(bind_msg), false, NULL, 0);
 560         if (ret)
 561                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 562                          op_str, queue_id, bind_msg.vector_id, ret);
 563
 564         return ret;
 565 }
 566
 567 static int
 568 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 569 {
 570         uint16_t vec;
 571         int ret;
 572         int i;
 573
 574         /*
 575          * In hns3 network engine, vector 0 is always the misc interrupt of this
 576          * function, vector 1~N can be used respectively for the queues of the
 577          * function. Tx and Rx queues with the same number share the interrupt
 578          * vector. In the initialization clearing the all hardware mapping
 579          * relationship configurations between queues and interrupt vectors is
 580          * needed, so some error caused by the residual configurations, such as
 581          * the unexpected Tx interrupt, can be avoid.
 582          */
 583         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 584         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 585                 vec = vec - 1; /* the last interrupt is reserved */
 586         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 587         for (i = 0; i < hw->intr_tqps_num; i++) {
 588                 /*
 589                  * Set gap limiter/rate limiter/quanity limiter algorithm
 590                  * configuration for interrupt coalesce of queue's interrupt.
 591                  */
 592                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 593                                        HNS3_TQP_INTR_GL_DEFAULT);
 594                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 595                                        HNS3_TQP_INTR_GL_DEFAULT);
 596                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 597                 /*
 598                  * QL(quantity limiter) is not used currently, just set 0 to
 599                  * close it.
 600                  */
 601                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 602
 603                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 604                                                    HNS3_RING_TYPE_TX, i);
 605                 if (ret) {
 606                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 607                                           "vector: %u, ret=%d", i, vec, ret);
 608                         return ret;
 609                 }
 610
 611                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 612                                                    HNS3_RING_TYPE_RX, i);
 613                 if (ret) {
 614                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 615                                           "vector: %u, ret=%d", i, vec, ret);
 616                         return ret;
 617                 }
 618         }
 619
 620         return 0;
 621 }
 622
 623 static int
 624 hns3vf_dev_configure(struct rte_eth_dev *dev)
 625 {
 626         struct hns3_adapter *hns = dev->data->dev_private;
 627         struct hns3_hw *hw = &hns->hw;
 628         struct rte_eth_conf *conf = &dev->data->dev_conf;
 629         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 630         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 631         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 632         struct rte_eth_rss_conf rss_conf;
 633         bool gro_en;
 634         int ret;
 635
 636         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 637
 638         /*
 639          * Some versions of hardware network engine does not support
 640          * individually enable/disable/reset the Tx or Rx queue. These devices
 641          * must enable/disable/reset Tx and Rx queues at the same time. When the
 642          * numbers of Tx queues allocated by upper applications are not equal to
 643          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 644          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 645          * work as usual. But these fake queues are imperceptible, and can not
 646          * be used by upper applications.
 647          */
 648         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 649         if (ret) {
 650                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
 651                 hw->cfg_max_queues = 0;
 652                 return ret;
 653         }
 654
 655         hw->adapter_state = HNS3_NIC_CONFIGURING;
 656         if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
 657                 hns3_err(hw, "setting link speed/duplex not supported");
 658                 ret = -EINVAL;
 659                 goto cfg_err;
 660         }
 661
 662         /* When RSS is not configured, redirect the packet queue 0 */
 663         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
 664                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
 665                 hw->rss_dis_flag = false;
 666                 rss_conf = conf->rx_adv_conf.rss_conf;
 667                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 668                 if (ret)
 669                         goto cfg_err;
 670         }
 671
 672         ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
 673         if (ret != 0)
 674                 goto cfg_err;
 675
 676         ret = hns3vf_dev_configure_vlan(dev);
 677         if (ret)
 678                 goto cfg_err;
 679
 680         /* config hardware GRO */
 681         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
 682         ret = hns3_config_gro(hw, gro_en);
 683         if (ret)
 684                 goto cfg_err;
 685
 686         hns3_init_rx_ptype_tble(dev);
 687
 688         hw->adapter_state = HNS3_NIC_CONFIGURED;
 689         return 0;
 690
 691 cfg_err:
 692         hw->cfg_max_queues = 0;
 693         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 694         hw->adapter_state = HNS3_NIC_INITIALIZED;
 695
 696         return ret;
 697 }
 698
 699 static int
 700 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 701 {
 702         int ret;
 703
 704         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 705                                 sizeof(mtu), true, NULL, 0);
 706         if (ret)
 707                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 708
 709         return ret;
 710 }
 711
 712 static int
 713 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 714 {
 715         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 716         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 717         int ret;
 718
 719         /*
 720          * The hns3 PF/VF devices on the same port share the hardware MTU
 721          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 722          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 723          * driver, there is no need to stop the port for hns3 VF device, and the
 724          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 725          * PF's MTU.
 726          */
 727         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 728                 hns3_err(hw, "Failed to set mtu during resetting");
 729                 return -EIO;
 730         }
 731
 732         /*
 733          * when Rx of scattered packets is off, we have some possibility of
 734          * using vector Rx process function or simple Rx functions in hns3 PMD
 735          * driver. If the input MTU is increased and the maximum length of
 736          * received packets is greater than the length of a buffer for Rx
 737          * packet, the hardware network engine needs to use multiple BDs and
 738          * buffers to store these packets. This will cause problems when still
 739          * using vector Rx process function or simple Rx function to receiving
 740          * packets. So, when Rx of scattered packets is off and device is
 741          * started, it is not permitted to increase MTU so that the maximum
 742          * length of Rx packets is greater than Rx buffer length.
 743          */
 744         if (dev->data->dev_started && !dev->data->scattered_rx &&
 745             frame_size > hw->rx_buf_len) {
 746                 hns3_err(hw, "failed to set mtu because current is "
 747                         "not scattered rx mode");
 748                 return -EOPNOTSUPP;
 749         }
 750
 751         rte_spinlock_lock(&hw->lock);
 752         ret = hns3vf_config_mtu(hw, mtu);
 753         if (ret) {
 754                 rte_spinlock_unlock(&hw->lock);
 755                 return ret;
 756         }
 757         rte_spinlock_unlock(&hw->lock);
 758
 759         return 0;
 760 }
 761
 762 static int
 763 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 764 {
 765         struct hns3_adapter *hns = eth_dev->data->dev_private;
 766         struct hns3_hw *hw = &hns->hw;
 767         uint16_t q_num = hw->tqps_num;
 768
 769         /*
 770          * In interrupt mode, 'max_rx_queues' is set based on the number of
 771          * MSI-X interrupt resources of the hardware.
 772          */
 773         if (hw->data->dev_conf.intr_conf.rxq == 1)
 774                 q_num = hw->intr_tqps_num;
 775
 776         info->max_rx_queues = q_num;
 777         info->max_tx_queues = hw->tqps_num;
 778         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 779         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 780         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 781         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 782         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 783
 784         info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
 785                                  RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
 786                                  RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
 787                                  RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
 788                                  RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 789                                  RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
 790                                  RTE_ETH_RX_OFFLOAD_SCATTER |
 791                                  RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
 792                                  RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
 793                                  RTE_ETH_RX_OFFLOAD_RSS_HASH |
 794                                  RTE_ETH_RX_OFFLOAD_TCP_LRO);
 795         info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 796                                  RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
 797                                  RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
 798                                  RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
 799                                  RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
 800                                  RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
 801                                  RTE_ETH_TX_OFFLOAD_TCP_TSO |
 802                                  RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
 803                                  RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
 804                                  RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
 805                                  RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
 806                                  hns3_txvlan_cap_get(hw));
 807
 808         if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
 809                 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
 810
 811         if (hns3_dev_get_support(hw, INDEP_TXRX))
 812                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 813                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 814
 815         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 816                 .nb_max = HNS3_MAX_RING_DESC,
 817                 .nb_min = HNS3_MIN_RING_DESC,
 818                 .nb_align = HNS3_ALIGN_RING_DESC,
 819         };
 820
 821         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 822                 .nb_max = HNS3_MAX_RING_DESC,
 823                 .nb_min = HNS3_MIN_RING_DESC,
 824                 .nb_align = HNS3_ALIGN_RING_DESC,
 825                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 826                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
 827         };
 828
 829         info->default_rxconf = (struct rte_eth_rxconf) {
 830                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 831                 /*
 832                  * If there are no available Rx buffer descriptors, incoming
 833                  * packets are always dropped by hardware based on hns3 network
 834                  * engine.
 835                  */
 836                 .rx_drop_en = 1,
 837                 .offloads = 0,
 838         };
 839         info->default_txconf = (struct rte_eth_txconf) {
 840                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 841                 .offloads = 0,
 842         };
 843
 844         info->reta_size = hw->rss_ind_tbl_size;
 845         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 846         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 847
 848         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 849         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 850         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 851         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 852         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 853         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 854
 855         return 0;
 856 }
 857
 858 static void
 859 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 860 {
 861         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 862 }
 863
 864 static void
 865 hns3vf_disable_irq0(struct hns3_hw *hw)
 866 {
 867         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 868 }
 869
 870 static void
 871 hns3vf_enable_irq0(struct hns3_hw *hw)
 872 {
 873         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 874 }
 875
 876 static enum hns3vf_evt_cause
 877 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 878 {
 879         struct hns3_hw *hw = &hns->hw;
 880         enum hns3vf_evt_cause ret;
 881         uint32_t cmdq_stat_reg;
 882         uint32_t rst_ing_reg;
 883         uint32_t val;
 884
 885         /* Fetch the events from their corresponding regs */
 886         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 887         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 888                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 889                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 890                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 891                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 892                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 893                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 894                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 895                 if (clearval) {
 896                         hw->reset.stats.global_cnt++;
 897                         hns3_warn(hw, "Global reset detected, clear reset status");
 898                 } else {
 899                         hns3_schedule_delayed_reset(hns);
 900                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 901                 }
 902
 903                 ret = HNS3VF_VECTOR0_EVENT_RST;
 904                 goto out;
 905         }
 906
 907         /* Check for vector0 mailbox(=CMDQ RX) event source */
 908         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
 909                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 910                 ret = HNS3VF_VECTOR0_EVENT_MBX;
 911                 goto out;
 912         }
 913
 914         val = 0;
 915         ret = HNS3VF_VECTOR0_EVENT_OTHER;
 916 out:
 917         if (clearval)
 918                 *clearval = val;
 919         return ret;
 920 }
 921
 922 static void
 923 hns3vf_interrupt_handler(void *param)
 924 {
 925         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 926         struct hns3_adapter *hns = dev->data->dev_private;
 927         struct hns3_hw *hw = &hns->hw;
 928         enum hns3vf_evt_cause event_cause;
 929         uint32_t clearval;
 930
 931         /* Disable interrupt */
 932         hns3vf_disable_irq0(hw);
 933
 934         /* Read out interrupt causes */
 935         event_cause = hns3vf_check_event_cause(hns, &clearval);
 936         /* Clear interrupt causes */
 937         hns3vf_clear_event_cause(hw, clearval);
 938
 939         switch (event_cause) {
 940         case HNS3VF_VECTOR0_EVENT_RST:
 941                 hns3_schedule_reset(hns);
 942                 break;
 943         case HNS3VF_VECTOR0_EVENT_MBX:
 944                 hns3_dev_handle_mbx_msg(hw);
 945                 break;
 946         default:
 947                 break;
 948         }
 949
 950         /* Enable interrupt */
 951         hns3vf_enable_irq0(hw);
 952 }
 953
 954 static void
 955 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
 956 {
 957         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
 958         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
 959         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
 960         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
 961 }
 962
 963 static void
 964 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
 965 {
 966         struct hns3_dev_specs_0_cmd *req0;
 967
 968         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
 969
 970         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
 971         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
 972         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
 973         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
 974 }
 975
 976 static int
 977 hns3vf_check_dev_specifications(struct hns3_hw *hw)
 978 {
 979         if (hw->rss_ind_tbl_size == 0 ||
 980             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
 981                 hns3_warn(hw, "the size of hash lookup table configured (%u)"
 982                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
 983                               HNS3_RSS_IND_TBL_SIZE_MAX);
 984                 return -EINVAL;
 985         }
 986
 987         return 0;
 988 }
 989
 990 static int
 991 hns3vf_query_dev_specifications(struct hns3_hw *hw)
 992 {
 993         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
 994         int ret;
 995         int i;
 996
 997         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
 998                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
 999                                           true);
1000                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1001         }
1002         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1003
1004         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1005         if (ret)
1006                 return ret;
1007
1008         hns3vf_parse_dev_specifications(hw, desc);
1009
1010         return hns3vf_check_dev_specifications(hw);
1011 }
1012
1013 void
1014 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
1015 {
1016         uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
1017                                    HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1018         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1019         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1020
1021         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1022                 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1023                                           __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1024 }
1025
1026 static void
1027 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
1028 {
1029 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS      500
1030
1031         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1032         int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
1033         uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1034         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1035         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1036
1037         __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
1038                          __ATOMIC_RELEASE);
1039
1040         (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1041                                 NULL, 0);
1042
1043         while (remain_ms > 0) {
1044                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
1045                 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
1046                         HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1047                         break;
1048                 remain_ms--;
1049         }
1050
1051         /*
1052          * When exit above loop, the pf_push_lsc_cap could be one of the three
1053          * state: unknown (means pf not ack), not_supported, supported.
1054          * Here config it as 'not_supported' when it's 'unknown' state.
1055          */
1056         __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1057                                   __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1058
1059         if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
1060                 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
1061                 hns3_info(hw, "detect PF support push link status change!");
1062         } else {
1063                 /*
1064                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
1065                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
1066                  * the RTE_ETH_DEV_INTR_LSC capability.
1067                  */
1068                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1069         }
1070 }
1071
1072 static int
1073 hns3vf_get_capability(struct hns3_hw *hw)
1074 {
1075         struct rte_pci_device *pci_dev;
1076         struct rte_eth_dev *eth_dev;
1077         uint8_t revision;
1078         int ret;
1079
1080         eth_dev = &rte_eth_devices[hw->data->port_id];
1081         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1082
1083         /* Get PCI revision id */
1084         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1085                                   HNS3_PCI_REVISION_ID);
1086         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1087                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1088                              ret);
1089                 return -EIO;
1090         }
1091         hw->revision = revision;
1092
1093         if (revision < PCI_REVISION_ID_HIP09_A) {
1094                 hns3vf_set_default_dev_specifications(hw);
1095                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1096                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1097                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1098                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
1099                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1100                 hw->rss_info.ipv6_sctp_offload_supported = false;
1101                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1102                 return 0;
1103         }
1104
1105         ret = hns3vf_query_dev_specifications(hw);
1106         if (ret) {
1107                 PMD_INIT_LOG(ERR,
1108                              "failed to query dev specifications, ret = %d",
1109                              ret);
1110                 return ret;
1111         }
1112
1113         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1114         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1115         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1116         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1117         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1118         hw->rss_info.ipv6_sctp_offload_supported = true;
1119         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1120
1121         return 0;
1122 }
1123
1124 static int
1125 hns3vf_check_tqp_info(struct hns3_hw *hw)
1126 {
1127         if (hw->tqps_num == 0) {
1128                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1129                 return -EINVAL;
1130         }
1131
1132         if (hw->rss_size_max == 0) {
1133                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1134                 return -EINVAL;
1135         }
1136
1137         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1138
1139         return 0;
1140 }
1141
1142 static int
1143 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1144 {
1145         uint8_t resp_msg;
1146         int ret;
1147
1148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1149                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1150                                 true, &resp_msg, sizeof(resp_msg));
1151         if (ret) {
1152                 if (ret == -ETIME) {
1153                         /*
1154                          * Getting current port based VLAN state from PF driver
1155                          * will not affect VF driver's basic function. Because
1156                          * the VF driver relies on hns3 PF kernel ether driver,
1157                          * to avoid introducing compatibility issues with older
1158                          * version of PF driver, no failure will be returned
1159                          * when the return value is ETIME. This return value has
1160                          * the following scenarios:
1161                          * 1) Firmware didn't return the results in time
1162                          * 2) the result return by firmware is timeout
1163                          * 3) the older version of kernel side PF driver does
1164                          *    not support this mailbox message.
1165                          * For scenarios 1 and 2, it is most likely that a
1166                          * hardware error has occurred, or a hardware reset has
1167                          * occurred. In this case, these errors will be caught
1168                          * by other functions.
1169                          */
1170                         PMD_INIT_LOG(WARNING,
1171                                 "failed to get PVID state for timeout, maybe "
1172                                 "kernel side PF driver doesn't support this "
1173                                 "mailbox message, or firmware didn't respond.");
1174                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1175                 } else {
1176                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1177                                 " ret = %d", ret);
1178                         return ret;
1179                 }
1180         }
1181         hw->port_base_vlan_cfg.state = resp_msg ?
1182                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1183         return 0;
1184 }
1185
1186 static int
1187 hns3vf_get_queue_info(struct hns3_hw *hw)
1188 {
1189 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1190         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1191         int ret;
1192
1193         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1194                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1195         if (ret) {
1196                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1197                 return ret;
1198         }
1199
1200         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1201         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1202
1203         return hns3vf_check_tqp_info(hw);
1204 }
1205
1206 static int
1207 hns3vf_get_queue_depth(struct hns3_hw *hw)
1208 {
1209 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1210         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1211         int ret;
1212
1213         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1214                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1215         if (ret) {
1216                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1217                              ret);
1218                 return ret;
1219         }
1220
1221         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1222         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1223
1224         return 0;
1225 }
1226
1227 static void
1228 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1229 {
1230         if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1231                 hns3_set_bit(hw->capability,
1232                                 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1233 }
1234
1235 static int
1236 hns3vf_get_num_tc(struct hns3_hw *hw)
1237 {
1238         uint8_t num_tc = 0;
1239         uint32_t i;
1240
1241         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1242                 if (hw->hw_tc_map & BIT(i))
1243                         num_tc++;
1244         }
1245         return num_tc;
1246 }
1247
1248 static int
1249 hns3vf_get_basic_info(struct hns3_hw *hw)
1250 {
1251         uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1252         struct hns3_basic_info *basic_info;
1253         int ret;
1254
1255         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1256                                 true, resp_msg, sizeof(resp_msg));
1257         if (ret) {
1258                 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1259                                 ret);
1260                 return ret;
1261         }
1262
1263         basic_info = (struct hns3_basic_info *)resp_msg;
1264         hw->hw_tc_map = basic_info->hw_tc_map;
1265         hw->num_tc = hns3vf_get_num_tc(hw);
1266         hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1267         hns3vf_update_caps(hw, basic_info->caps);
1268
1269         return 0;
1270 }
1271
1272 static int
1273 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1274 {
1275         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1276         int ret;
1277
1278         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1279                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1280         if (ret) {
1281                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1282                 return ret;
1283         }
1284
1285         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1286
1287         return 0;
1288 }
1289
1290 static int
1291 hns3vf_get_configuration(struct hns3_hw *hw)
1292 {
1293         int ret;
1294
1295         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1296         hw->rss_dis_flag = false;
1297
1298         /* Get device capability */
1299         ret = hns3vf_get_capability(hw);
1300         if (ret) {
1301                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1302                 return ret;
1303         }
1304
1305         hns3vf_get_push_lsc_cap(hw);
1306
1307         /* Get basic info from PF */
1308         ret = hns3vf_get_basic_info(hw);
1309         if (ret)
1310                 return ret;
1311
1312         /* Get queue configuration from PF */
1313         ret = hns3vf_get_queue_info(hw);
1314         if (ret)
1315                 return ret;
1316
1317         /* Get queue depth info from PF */
1318         ret = hns3vf_get_queue_depth(hw);
1319         if (ret)
1320                 return ret;
1321
1322         /* Get user defined VF MAC addr from PF */
1323         ret = hns3vf_get_host_mac_addr(hw);
1324         if (ret)
1325                 return ret;
1326
1327         return hns3vf_get_port_base_vlan_filter_state(hw);
1328 }
1329
1330 static int
1331 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1332                             uint16_t nb_tx_q)
1333 {
1334         struct hns3_hw *hw = &hns->hw;
1335
1336         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1337 }
1338
1339 static void
1340 hns3vf_request_link_info(struct hns3_hw *hw)
1341 {
1342         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1343         bool send_req;
1344         int ret;
1345
1346         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1347                 return;
1348
1349         send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1350                    vf->req_link_info_cnt > 0;
1351         if (!send_req)
1352                 return;
1353
1354         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1355                                 NULL, 0);
1356         if (ret) {
1357                 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1358                 return;
1359         }
1360
1361         if (vf->req_link_info_cnt > 0)
1362                 vf->req_link_info_cnt--;
1363 }
1364
1365 void
1366 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1367                           uint32_t link_speed, uint8_t link_duplex)
1368 {
1369         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1370         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1371         struct hns3_mac *mac = &hw->mac;
1372         int ret;
1373
1374         /*
1375          * PF kernel driver may push link status when VF driver is in resetting,
1376          * driver will stop polling job in this case, after resetting done
1377          * driver will start polling job again.
1378          * When polling job started, driver will get initial link status by
1379          * sending request to PF kernel driver, then could update link status by
1380          * process PF kernel driver's link status mailbox message.
1381          */
1382         if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1383                 return;
1384
1385         if (hw->adapter_state != HNS3_NIC_STARTED)
1386                 return;
1387
1388         mac->link_status = link_status;
1389         mac->link_speed = link_speed;
1390         mac->link_duplex = link_duplex;
1391         ret = hns3vf_dev_link_update(dev, 0);
1392         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1393                 hns3_start_report_lse(dev);
1394 }
1395
1396 static int
1397 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1398 {
1399 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1400         struct hns3_hw *hw = &hns->hw;
1401         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1402         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1403         uint8_t is_kill = on ? 0 : 1;
1404
1405         msg_data[0] = is_kill;
1406         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1407         memcpy(&msg_data[3], &proto, sizeof(proto));
1408
1409         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1410                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1411                                  0);
1412 }
1413
1414 static int
1415 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1416 {
1417         struct hns3_adapter *hns = dev->data->dev_private;
1418         struct hns3_hw *hw = &hns->hw;
1419         int ret;
1420
1421         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1422                 hns3_err(hw,
1423                          "vf set vlan id failed during resetting, vlan_id =%u",
1424                          vlan_id);
1425                 return -EIO;
1426         }
1427         rte_spinlock_lock(&hw->lock);
1428         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1429         rte_spinlock_unlock(&hw->lock);
1430         if (ret)
1431                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1432                          vlan_id, ret);
1433
1434         return ret;
1435 }
1436
1437 static int
1438 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1439 {
1440         uint8_t msg_data;
1441         int ret;
1442
1443         if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1444                 return 0;
1445
1446         msg_data = enable ? 1 : 0;
1447         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1448                         HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1449                         sizeof(msg_data), true, NULL, 0);
1450         if (ret)
1451                 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1452                                 enable ? "enable" : "disable", ret);
1453
1454         return ret;
1455 }
1456
1457 static int
1458 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1459 {
1460         uint8_t msg_data;
1461         int ret;
1462
1463         msg_data = enable ? 1 : 0;
1464         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1465                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1466         if (ret)
1467                 hns3_err(hw, "vf %s strip failed, ret = %d.",
1468                                 enable ? "enable" : "disable", ret);
1469
1470         return ret;
1471 }
1472
1473 static int
1474 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1475 {
1476         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1478         unsigned int tmp_mask;
1479         int ret = 0;
1480
1481         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1482                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1483                              "mask = 0x%x", mask);
1484                 return -EIO;
1485         }
1486
1487         tmp_mask = (unsigned int)mask;
1488
1489         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
1490                 rte_spinlock_lock(&hw->lock);
1491                 /* Enable or disable VLAN filter */
1492                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1493                         ret = hns3vf_en_vlan_filter(hw, true);
1494                 else
1495                         ret = hns3vf_en_vlan_filter(hw, false);
1496                 rte_spinlock_unlock(&hw->lock);
1497                 if (ret)
1498                         return ret;
1499         }
1500
1501         /* Vlan stripping setting */
1502         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
1503                 rte_spinlock_lock(&hw->lock);
1504                 /* Enable or disable VLAN stripping */
1505                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1506                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1507                 else
1508                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1509                 rte_spinlock_unlock(&hw->lock);
1510         }
1511
1512         return ret;
1513 }
1514
1515 static int
1516 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1517 {
1518         struct rte_vlan_filter_conf *vfc;
1519         struct hns3_hw *hw = &hns->hw;
1520         uint16_t vlan_id;
1521         uint64_t vbit;
1522         uint64_t ids;
1523         int ret = 0;
1524         uint32_t i;
1525
1526         vfc = &hw->data->vlan_filter_conf;
1527         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1528                 if (vfc->ids[i] == 0)
1529                         continue;
1530                 ids = vfc->ids[i];
1531                 while (ids) {
1532                         /*
1533                          * 64 means the num bits of ids, one bit corresponds to
1534                          * one vlan id
1535                          */
1536                         vlan_id = 64 * i;
1537                         /* count trailing zeroes */
1538                         vbit = ~ids & (ids - 1);
1539                         /* clear least significant bit set */
1540                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1541                         for (; vbit;) {
1542                                 vbit >>= 1;
1543                                 vlan_id++;
1544                         }
1545                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1546                         if (ret) {
1547                                 hns3_err(hw,
1548                                          "VF handle vlan table failed, ret =%d, on = %d",
1549                                          ret, on);
1550                                 return ret;
1551                         }
1552                 }
1553         }
1554
1555         return ret;
1556 }
1557
1558 static int
1559 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1560 {
1561         return hns3vf_handle_all_vlan_table(hns, 0);
1562 }
1563
1564 static int
1565 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1566 {
1567         struct hns3_hw *hw = &hns->hw;
1568         struct rte_eth_conf *dev_conf;
1569         bool en;
1570         int ret;
1571
1572         dev_conf = &hw->data->dev_conf;
1573         en = dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? true
1574                                                                    : false;
1575         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1576         if (ret)
1577                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1578                          ret);
1579         return ret;
1580 }
1581
1582 static int
1583 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1584 {
1585         struct hns3_adapter *hns = dev->data->dev_private;
1586         struct rte_eth_dev_data *data = dev->data;
1587         struct hns3_hw *hw = &hns->hw;
1588         int ret;
1589
1590         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1591             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1592             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1593                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1594                               "or hw_vlan_insert_pvid is not support!");
1595         }
1596
1597         /* Apply vlan offload setting */
1598         ret = hns3vf_vlan_offload_set(dev, RTE_ETH_VLAN_STRIP_MASK |
1599                                         RTE_ETH_VLAN_FILTER_MASK);
1600         if (ret)
1601                 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1602
1603         return ret;
1604 }
1605
1606 static int
1607 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1608 {
1609         uint8_t msg_data;
1610
1611         msg_data = alive ? 1 : 0;
1612         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1613                                  sizeof(msg_data), false, NULL, 0);
1614 }
1615
1616 static void
1617 hns3vf_keep_alive_handler(void *param)
1618 {
1619         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1620         struct hns3_adapter *hns = eth_dev->data->dev_private;
1621         struct hns3_hw *hw = &hns->hw;
1622         int ret;
1623
1624         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1625                                 false, NULL, 0);
1626         if (ret)
1627                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1628                          ret);
1629
1630         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1631                           eth_dev);
1632 }
1633
1634 static void
1635 hns3vf_service_handler(void *param)
1636 {
1637         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1638         struct hns3_adapter *hns = eth_dev->data->dev_private;
1639         struct hns3_hw *hw = &hns->hw;
1640
1641         /*
1642          * The query link status and reset processing are executed in the
1643          * interrupt thread. When the IMP reset occurs, IMP will not respond,
1644          * and the query operation will timeout after 30ms. In the case of
1645          * multiple PF/VFs, each query failure timeout causes the IMP reset
1646          * interrupt to fail to respond within 100ms.
1647          * Before querying the link status, check whether there is a reset
1648          * pending, and if so, abandon the query.
1649          */
1650         if (!hns3vf_is_reset_pending(hns))
1651                 hns3vf_request_link_info(hw);
1652         else
1653                 hns3_warn(hw, "Cancel the query when reset is pending");
1654
1655         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1656                           eth_dev);
1657 }
1658
1659 static void
1660 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1661 {
1662 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT      3
1663
1664         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1665
1666         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1667                 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1668
1669         __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1670
1671         hns3vf_service_handler(dev);
1672 }
1673
1674 static void
1675 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1676 {
1677         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1678
1679         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1680
1681         __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1682 }
1683
1684 static int
1685 hns3_query_vf_resource(struct hns3_hw *hw)
1686 {
1687         struct hns3_vf_res_cmd *req;
1688         struct hns3_cmd_desc desc;
1689         uint16_t num_msi;
1690         int ret;
1691
1692         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1693         ret = hns3_cmd_send(hw, &desc, 1);
1694         if (ret) {
1695                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1696                 return ret;
1697         }
1698
1699         req = (struct hns3_vf_res_cmd *)desc.data;
1700         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1701                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1702         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1703                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1704                          num_msi, HNS3_MIN_VECTOR_NUM);
1705                 return -EINVAL;
1706         }
1707
1708         hw->num_msi = num_msi;
1709
1710         return 0;
1711 }
1712
1713 static int
1714 hns3vf_init_hardware(struct hns3_adapter *hns)
1715 {
1716         struct hns3_hw *hw = &hns->hw;
1717         uint16_t mtu = hw->data->mtu;
1718         int ret;
1719
1720         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1721         if (ret)
1722                 return ret;
1723
1724         ret = hns3vf_config_mtu(hw, mtu);
1725         if (ret)
1726                 goto err_init_hardware;
1727
1728         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1729         if (ret) {
1730                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1731                 goto err_init_hardware;
1732         }
1733
1734         ret = hns3_config_gro(hw, false);
1735         if (ret) {
1736                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1737                 goto err_init_hardware;
1738         }
1739
1740         /*
1741          * In the initialization clearing the all hardware mapping relationship
1742          * configurations between queues and interrupt vectors is needed, so
1743          * some error caused by the residual configurations, such as the
1744          * unexpected interrupt, can be avoid.
1745          */
1746         ret = hns3vf_init_ring_with_vector(hw);
1747         if (ret) {
1748                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1749                 goto err_init_hardware;
1750         }
1751
1752         return 0;
1753
1754 err_init_hardware:
1755         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1756         return ret;
1757 }
1758
1759 static int
1760 hns3vf_clear_vport_list(struct hns3_hw *hw)
1761 {
1762         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1763                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1764                                  NULL, 0);
1765 }
1766
1767 static int
1768 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1769 {
1770         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1771         struct hns3_adapter *hns = eth_dev->data->dev_private;
1772         struct hns3_hw *hw = &hns->hw;
1773         int ret;
1774
1775         PMD_INIT_FUNC_TRACE();
1776
1777         /* Get hardware io base address from pcie BAR2 IO space */
1778         hw->io_base = pci_dev->mem_resource[2].addr;
1779
1780         /* Firmware command queue initialize */
1781         ret = hns3_cmd_init_queue(hw);
1782         if (ret) {
1783                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1784                 goto err_cmd_init_queue;
1785         }
1786
1787         /* Firmware command initialize */
1788         ret = hns3_cmd_init(hw);
1789         if (ret) {
1790                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1791                 goto err_cmd_init;
1792         }
1793
1794         hns3_tx_push_init(eth_dev);
1795
1796         /* Get VF resource */
1797         ret = hns3_query_vf_resource(hw);
1798         if (ret)
1799                 goto err_cmd_init;
1800
1801         rte_spinlock_init(&hw->mbx_resp.lock);
1802
1803         hns3vf_clear_event_cause(hw, 0);
1804
1805         ret = rte_intr_callback_register(pci_dev->intr_handle,
1806                                          hns3vf_interrupt_handler, eth_dev);
1807         if (ret) {
1808                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1809                 goto err_intr_callback_register;
1810         }
1811
1812         /* Enable interrupt */
1813         rte_intr_enable(pci_dev->intr_handle);
1814         hns3vf_enable_irq0(hw);
1815
1816         /* Get configuration from PF */
1817         ret = hns3vf_get_configuration(hw);
1818         if (ret) {
1819                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1820                 goto err_get_config;
1821         }
1822
1823         ret = hns3_tqp_stats_init(hw);
1824         if (ret)
1825                 goto err_get_config;
1826
1827         /* Hardware statistics of imissed registers cleared. */
1828         ret = hns3_update_imissed_stats(hw, true);
1829         if (ret) {
1830                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1831                 goto err_set_tc_queue;
1832         }
1833
1834         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1835         if (ret) {
1836                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1837                 goto err_set_tc_queue;
1838         }
1839
1840         ret = hns3vf_clear_vport_list(hw);
1841         if (ret) {
1842                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1843                 goto err_set_tc_queue;
1844         }
1845
1846         ret = hns3vf_init_hardware(hns);
1847         if (ret)
1848                 goto err_set_tc_queue;
1849
1850         hns3_rss_set_default_args(hw);
1851
1852         ret = hns3vf_set_alive(hw, true);
1853         if (ret) {
1854                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1855                 goto err_set_tc_queue;
1856         }
1857
1858         return 0;
1859
1860 err_set_tc_queue:
1861         hns3_tqp_stats_uninit(hw);
1862
1863 err_get_config:
1864         hns3vf_disable_irq0(hw);
1865         rte_intr_disable(pci_dev->intr_handle);
1866         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1867                              eth_dev);
1868 err_intr_callback_register:
1869 err_cmd_init:
1870         hns3_cmd_uninit(hw);
1871         hns3_cmd_destroy_queue(hw);
1872 err_cmd_init_queue:
1873         hw->io_base = NULL;
1874
1875         return ret;
1876 }
1877
1878 static void
1879 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1880 {
1881         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1882         struct hns3_adapter *hns = eth_dev->data->dev_private;
1883         struct hns3_hw *hw = &hns->hw;
1884
1885         PMD_INIT_FUNC_TRACE();
1886
1887         hns3_rss_uninit(hns);
1888         (void)hns3_config_gro(hw, false);
1889         (void)hns3vf_set_alive(hw, false);
1890         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1891         hns3_flow_uninit(eth_dev);
1892         hns3_tqp_stats_uninit(hw);
1893         hns3vf_disable_irq0(hw);
1894         rte_intr_disable(pci_dev->intr_handle);
1895         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1896                              eth_dev);
1897         hns3_cmd_uninit(hw);
1898         hns3_cmd_destroy_queue(hw);
1899         hw->io_base = NULL;
1900 }
1901
1902 static int
1903 hns3vf_do_stop(struct hns3_adapter *hns)
1904 {
1905         struct hns3_hw *hw = &hns->hw;
1906         int ret;
1907
1908         hw->mac.link_status = RTE_ETH_LINK_DOWN;
1909
1910         /*
1911          * The "hns3vf_do_stop" function will also be called by .stop_service to
1912          * prepare reset. At the time of global or IMP reset, the command cannot
1913          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
1914          * accessed during the reset process. So the mbuf can not be released
1915          * during reset and is required to be released after the reset is
1916          * completed.
1917          */
1918         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
1919                 hns3_dev_release_mbufs(hns);
1920
1921         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
1922                 hns3_configure_all_mac_addr(hns, true);
1923                 ret = hns3_reset_all_tqps(hns);
1924                 if (ret) {
1925                         hns3_err(hw, "failed to reset all queues ret = %d",
1926                                  ret);
1927                         return ret;
1928                 }
1929         }
1930         return 0;
1931 }
1932
1933 static void
1934 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1935 {
1936         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1937         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1938         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1939         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1940         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1941         uint16_t q_id;
1942
1943         if (dev->data->dev_conf.intr_conf.rxq == 0)
1944                 return;
1945
1946         /* unmap the ring with vector */
1947         if (rte_intr_allow_others(intr_handle)) {
1948                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1949                 base = RTE_INTR_VEC_RXTX_OFFSET;
1950         }
1951         if (rte_intr_dp_is_en(intr_handle)) {
1952                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1953                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1954                                                            HNS3_RING_TYPE_RX,
1955                                                            q_id);
1956                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
1957                             - 1)
1958                                 vec++;
1959                 }
1960         }
1961         /* Clean datapath event and queue/vec mapping */
1962         rte_intr_efd_disable(intr_handle);
1963
1964         /* Cleanup vector list */
1965         rte_intr_vec_list_free(intr_handle);
1966 }
1967
1968 static int
1969 hns3vf_dev_stop(struct rte_eth_dev *dev)
1970 {
1971         struct hns3_adapter *hns = dev->data->dev_private;
1972         struct hns3_hw *hw = &hns->hw;
1973
1974         PMD_INIT_FUNC_TRACE();
1975         dev->data->dev_started = 0;
1976
1977         hw->adapter_state = HNS3_NIC_STOPPING;
1978         hns3_set_rxtx_function(dev);
1979         rte_wmb();
1980         /* Disable datapath on secondary process. */
1981         hns3_mp_req_stop_rxtx(dev);
1982         /* Prevent crashes when queues are still in use. */
1983         rte_delay_ms(hw->cfg_max_queues);
1984
1985         rte_spinlock_lock(&hw->lock);
1986         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1987                 hns3_stop_tqps(hw);
1988                 hns3vf_do_stop(hns);
1989                 hns3vf_unmap_rx_interrupt(dev);
1990                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1991         }
1992         hns3_rx_scattered_reset(dev);
1993         hns3vf_stop_poll_job(dev);
1994         hns3_stop_report_lse(dev);
1995         rte_spinlock_unlock(&hw->lock);
1996
1997         return 0;
1998 }
1999
2000 static int
2001 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
2002 {
2003         struct hns3_adapter *hns = eth_dev->data->dev_private;
2004         struct hns3_hw *hw = &hns->hw;
2005         int ret = 0;
2006
2007         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2008                 return 0;
2009
2010         if (hw->adapter_state == HNS3_NIC_STARTED)
2011                 ret = hns3vf_dev_stop(eth_dev);
2012
2013         hw->adapter_state = HNS3_NIC_CLOSING;
2014         hns3_reset_abort(hns);
2015         hw->adapter_state = HNS3_NIC_CLOSED;
2016         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
2017         hns3_configure_all_mc_mac_addr(hns, true);
2018         hns3vf_remove_all_vlan_table(hns);
2019         hns3vf_uninit_vf(eth_dev);
2020         hns3_free_all_queues(eth_dev);
2021         rte_free(hw->reset.wait_data);
2022         hns3_mp_uninit_primary();
2023         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
2024
2025         return ret;
2026 }
2027
2028 static int
2029 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2030                       size_t fw_size)
2031 {
2032         struct hns3_adapter *hns = eth_dev->data->dev_private;
2033         struct hns3_hw *hw = &hns->hw;
2034         uint32_t version = hw->fw_version;
2035         int ret;
2036
2037         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2038                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2039                                       HNS3_FW_VERSION_BYTE3_S),
2040                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2041                                       HNS3_FW_VERSION_BYTE2_S),
2042                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2043                                       HNS3_FW_VERSION_BYTE1_S),
2044                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2045                                       HNS3_FW_VERSION_BYTE0_S));
2046         if (ret < 0)
2047                 return -EINVAL;
2048
2049         ret += 1; /* add the size of '\0' */
2050         if (fw_size < (size_t)ret)
2051                 return ret;
2052         else
2053                 return 0;
2054 }
2055
2056 static int
2057 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2058                        __rte_unused int wait_to_complete)
2059 {
2060         struct hns3_adapter *hns = eth_dev->data->dev_private;
2061         struct hns3_hw *hw = &hns->hw;
2062         struct hns3_mac *mac = &hw->mac;
2063         struct rte_eth_link new_link;
2064
2065         memset(&new_link, 0, sizeof(new_link));
2066         switch (mac->link_speed) {
2067         case RTE_ETH_SPEED_NUM_10M:
2068         case RTE_ETH_SPEED_NUM_100M:
2069         case RTE_ETH_SPEED_NUM_1G:
2070         case RTE_ETH_SPEED_NUM_10G:
2071         case RTE_ETH_SPEED_NUM_25G:
2072         case RTE_ETH_SPEED_NUM_40G:
2073         case RTE_ETH_SPEED_NUM_50G:
2074         case RTE_ETH_SPEED_NUM_100G:
2075         case RTE_ETH_SPEED_NUM_200G:
2076                 if (mac->link_status)
2077                         new_link.link_speed = mac->link_speed;
2078                 break;
2079         default:
2080                 if (mac->link_status)
2081                         new_link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2082                 break;
2083         }
2084
2085         if (!mac->link_status)
2086                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2087
2088         new_link.link_duplex = mac->link_duplex;
2089         new_link.link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2090         new_link.link_autoneg =
2091             !(eth_dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED);
2092
2093         return rte_eth_linkstatus_set(eth_dev, &new_link);
2094 }
2095
2096 static int
2097 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2098 {
2099         struct hns3_hw *hw = &hns->hw;
2100         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2101         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2102         int ret;
2103
2104         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2105         if (ret)
2106                 return ret;
2107
2108         hns3_enable_rxd_adv_layout(hw);
2109
2110         ret = hns3_init_queues(hns, reset_queue);
2111         if (ret)
2112                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2113
2114         return ret;
2115 }
2116
2117 static int
2118 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2119 {
2120         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2121         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2122         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2123         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2124         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2125         uint32_t intr_vector;
2126         uint16_t q_id;
2127         int ret;
2128
2129         /*
2130          * hns3 needs a separate interrupt to be used as event interrupt which
2131          * could not be shared with task queue pair, so KERNEL drivers need
2132          * support multiple interrupt vectors.
2133          */
2134         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2135             !rte_intr_cap_multiple(intr_handle))
2136                 return 0;
2137
2138         rte_intr_disable(intr_handle);
2139         intr_vector = hw->used_rx_queues;
2140         /* It creates event fd for each intr vector when MSIX is used */
2141         if (rte_intr_efd_enable(intr_handle, intr_vector))
2142                 return -EINVAL;
2143
2144         /* Allocate vector list */
2145         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
2146                                     hw->used_rx_queues)) {
2147                 hns3_err(hw, "Failed to allocate %u rx_queues"
2148                          " intr_vec", hw->used_rx_queues);
2149                 ret = -ENOMEM;
2150                 goto vf_alloc_intr_vec_error;
2151         }
2152
2153         if (rte_intr_allow_others(intr_handle)) {
2154                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2155                 base = RTE_INTR_VEC_RXTX_OFFSET;
2156         }
2157
2158         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2159                 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2160                                                    HNS3_RING_TYPE_RX, q_id);
2161                 if (ret)
2162                         goto vf_bind_vector_error;
2163
2164                 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
2165                         goto vf_bind_vector_error;
2166
2167                 /*
2168                  * If there are not enough efds (e.g. not enough interrupt),
2169                  * remaining queues will be bond to the last interrupt.
2170                  */
2171                 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
2172                         vec++;
2173         }
2174         rte_intr_enable(intr_handle);
2175         return 0;
2176
2177 vf_bind_vector_error:
2178         rte_intr_vec_list_free(intr_handle);
2179 vf_alloc_intr_vec_error:
2180         rte_intr_efd_disable(intr_handle);
2181         return ret;
2182 }
2183
2184 static int
2185 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2186 {
2187         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2188         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2189         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2190         uint16_t q_id;
2191         int ret;
2192
2193         if (dev->data->dev_conf.intr_conf.rxq == 0)
2194                 return 0;
2195
2196         if (rte_intr_dp_is_en(intr_handle)) {
2197                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2198                         ret = hns3vf_bind_ring_with_vector(hw,
2199                                 rte_intr_vec_list_index_get(intr_handle,
2200                                                                    q_id),
2201                                 true, HNS3_RING_TYPE_RX, q_id);
2202                         if (ret)
2203                                 return ret;
2204                 }
2205         }
2206
2207         return 0;
2208 }
2209
2210 static void
2211 hns3vf_restore_filter(struct rte_eth_dev *dev)
2212 {
2213         hns3_restore_rss_filter(dev);
2214 }
2215
2216 static int
2217 hns3vf_dev_start(struct rte_eth_dev *dev)
2218 {
2219         struct hns3_adapter *hns = dev->data->dev_private;
2220         struct hns3_hw *hw = &hns->hw;
2221         int ret;
2222
2223         PMD_INIT_FUNC_TRACE();
2224         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2225                 return -EBUSY;
2226
2227         rte_spinlock_lock(&hw->lock);
2228         hw->adapter_state = HNS3_NIC_STARTING;
2229         ret = hns3vf_do_start(hns, true);
2230         if (ret) {
2231                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2232                 rte_spinlock_unlock(&hw->lock);
2233                 return ret;
2234         }
2235         ret = hns3vf_map_rx_interrupt(dev);
2236         if (ret)
2237                 goto map_rx_inter_err;
2238
2239         /*
2240          * There are three register used to control the status of a TQP
2241          * (contains a pair of Tx queue and Rx queue) in the new version network
2242          * engine. One is used to control the enabling of Tx queue, the other is
2243          * used to control the enabling of Rx queue, and the last is the master
2244          * switch used to control the enabling of the tqp. The Tx register and
2245          * TQP register must be enabled at the same time to enable a Tx queue.
2246          * The same applies to the Rx queue. For the older network enginem, this
2247          * function only refresh the enabled flag, and it is used to update the
2248          * status of queue in the dpdk framework.
2249          */
2250         ret = hns3_start_all_txqs(dev);
2251         if (ret)
2252                 goto map_rx_inter_err;
2253
2254         ret = hns3_start_all_rxqs(dev);
2255         if (ret)
2256                 goto start_all_rxqs_fail;
2257
2258         hw->adapter_state = HNS3_NIC_STARTED;
2259         rte_spinlock_unlock(&hw->lock);
2260
2261         hns3_rx_scattered_calc(dev);
2262         hns3_set_rxtx_function(dev);
2263         hns3_mp_req_start_rxtx(dev);
2264
2265         hns3vf_restore_filter(dev);
2266
2267         /* Enable interrupt of all rx queues before enabling queues */
2268         hns3_dev_all_rx_queue_intr_enable(hw, true);
2269         hns3_start_tqps(hw);
2270
2271         if (dev->data->dev_conf.intr_conf.lsc != 0)
2272                 hns3vf_dev_link_update(dev, 0);
2273         hns3vf_start_poll_job(dev);
2274
2275         return ret;
2276
2277 start_all_rxqs_fail:
2278         hns3_stop_all_txqs(dev);
2279 map_rx_inter_err:
2280         (void)hns3vf_do_stop(hns);
2281         hw->adapter_state = HNS3_NIC_CONFIGURED;
2282         rte_spinlock_unlock(&hw->lock);
2283
2284         return ret;
2285 }
2286
2287 static bool
2288 is_vf_reset_done(struct hns3_hw *hw)
2289 {
2290 #define HNS3_FUN_RST_ING_BITS \
2291         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2292          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2293          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2294          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2295
2296         uint32_t val;
2297
2298         if (hw->reset.level == HNS3_VF_RESET) {
2299                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2300                 if (val & HNS3_VF_RST_ING_BIT)
2301                         return false;
2302         } else {
2303                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2304                 if (val & HNS3_FUN_RST_ING_BITS)
2305                         return false;
2306         }
2307         return true;
2308 }
2309
2310 bool
2311 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2312 {
2313         struct hns3_hw *hw = &hns->hw;
2314         enum hns3_reset_level reset;
2315
2316         /*
2317          * According to the protocol of PCIe, FLR to a PF device resets the PF
2318          * state as well as the SR-IOV extended capability including VF Enable
2319          * which means that VFs no longer exist.
2320          *
2321          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2322          * is in FLR stage, the register state of VF device is not reliable,
2323          * so register states detection can not be carried out. In this case,
2324          * we just ignore the register states and return false to indicate that
2325          * there are no other reset states that need to be processed by driver.
2326          */
2327         if (hw->reset.level == HNS3_VF_FULL_RESET)
2328                 return false;
2329
2330         /* Check the registers to confirm whether there is reset pending */
2331         hns3vf_check_event_cause(hns, NULL);
2332         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2333         if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2334             hw->reset.level < reset) {
2335                 hns3_warn(hw, "High level reset %d is pending", reset);
2336                 return true;
2337         }
2338         return false;
2339 }
2340
2341 static int
2342 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2343 {
2344         struct hns3_hw *hw = &hns->hw;
2345         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2346         struct timeval tv;
2347
2348         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2349                 /*
2350                  * After vf reset is ready, the PF may not have completed
2351                  * the reset processing. The vf sending mbox to PF may fail
2352                  * during the pf reset, so it is better to add extra delay.
2353                  */
2354                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2355                     hw->reset.level == HNS3_FLR_RESET)
2356                         return 0;
2357                 /* Reset retry process, no need to add extra delay. */
2358                 if (hw->reset.attempts)
2359                         return 0;
2360                 if (wait_data->check_completion == NULL)
2361                         return 0;
2362
2363                 wait_data->check_completion = NULL;
2364                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2365                 wait_data->count = 1;
2366                 wait_data->result = HNS3_WAIT_REQUEST;
2367                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2368                                   wait_data);
2369                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2370                 return -EAGAIN;
2371         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2372                 hns3_clock_gettime(&tv);
2373                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2374                           tv.tv_sec, tv.tv_usec);
2375                 return -ETIME;
2376         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2377                 return -EAGAIN;
2378
2379         wait_data->hns = hns;
2380         wait_data->check_completion = is_vf_reset_done;
2381         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2382                                 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2383         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2384         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2385         wait_data->result = HNS3_WAIT_REQUEST;
2386         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2387         return -EAGAIN;
2388 }
2389
2390 static int
2391 hns3vf_prepare_reset(struct hns3_adapter *hns)
2392 {
2393         struct hns3_hw *hw = &hns->hw;
2394         int ret;
2395
2396         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2397                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2398                                         0, true, NULL, 0);
2399                 if (ret)
2400                         return ret;
2401         }
2402         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2403
2404         return 0;
2405 }
2406
2407 static int
2408 hns3vf_stop_service(struct hns3_adapter *hns)
2409 {
2410         struct hns3_hw *hw = &hns->hw;
2411         struct rte_eth_dev *eth_dev;
2412
2413         eth_dev = &rte_eth_devices[hw->data->port_id];
2414         if (hw->adapter_state == HNS3_NIC_STARTED) {
2415                 /*
2416                  * Make sure call update link status before hns3vf_stop_poll_job
2417                  * because update link status depend on polling job exist.
2418                  */
2419                 hns3vf_update_link_status(hw, RTE_ETH_LINK_DOWN, hw->mac.link_speed,
2420                                           hw->mac.link_duplex);
2421                 hns3vf_stop_poll_job(eth_dev);
2422         }
2423         hw->mac.link_status = RTE_ETH_LINK_DOWN;
2424
2425         hns3_set_rxtx_function(eth_dev);
2426         rte_wmb();
2427         /* Disable datapath on secondary process. */
2428         hns3_mp_req_stop_rxtx(eth_dev);
2429         rte_delay_ms(hw->cfg_max_queues);
2430
2431         rte_spinlock_lock(&hw->lock);
2432         if (hw->adapter_state == HNS3_NIC_STARTED ||
2433             hw->adapter_state == HNS3_NIC_STOPPING) {
2434                 hns3_enable_all_queues(hw, false);
2435                 hns3vf_do_stop(hns);
2436                 hw->reset.mbuf_deferred_free = true;
2437         } else
2438                 hw->reset.mbuf_deferred_free = false;
2439
2440         /*
2441          * It is cumbersome for hardware to pick-and-choose entries for deletion
2442          * from table space. Hence, for function reset software intervention is
2443          * required to delete the entries.
2444          */
2445         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2446                 hns3_configure_all_mc_mac_addr(hns, true);
2447         rte_spinlock_unlock(&hw->lock);
2448
2449         return 0;
2450 }
2451
2452 static int
2453 hns3vf_start_service(struct hns3_adapter *hns)
2454 {
2455         struct hns3_hw *hw = &hns->hw;
2456         struct rte_eth_dev *eth_dev;
2457
2458         eth_dev = &rte_eth_devices[hw->data->port_id];
2459         hns3_set_rxtx_function(eth_dev);
2460         hns3_mp_req_start_rxtx(eth_dev);
2461         if (hw->adapter_state == HNS3_NIC_STARTED) {
2462                 hns3vf_start_poll_job(eth_dev);
2463
2464                 /* Enable interrupt of all rx queues before enabling queues */
2465                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2466                 /*
2467                  * Enable state of each rxq and txq will be recovered after
2468                  * reset, so we need to restore them before enable all tqps;
2469                  */
2470                 hns3_restore_tqp_enable_state(hw);
2471                 /*
2472                  * When finished the initialization, enable queues to receive
2473                  * and transmit packets.
2474                  */
2475                 hns3_enable_all_queues(hw, true);
2476         }
2477
2478         return 0;
2479 }
2480
2481 static int
2482 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2483 {
2484         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2485         struct rte_ether_addr *hw_mac;
2486         int ret;
2487
2488         /*
2489          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2490          * on the host by "ip link set ..." command. If the hns3 PF kernel
2491          * ethdev driver sets the MAC address for VF device after the
2492          * initialization of the related VF device, the PF driver will notify
2493          * VF driver to reset VF device to make the new MAC address effective
2494          * immediately. The hns3 VF PMD driver should check whether the MAC
2495          * address has been changed by the PF kernel ethdev driver, if changed
2496          * VF driver should configure hardware using the new MAC address in the
2497          * recovering hardware configuration stage of the reset process.
2498          */
2499         ret = hns3vf_get_host_mac_addr(hw);
2500         if (ret)
2501                 return ret;
2502
2503         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2504         ret = rte_is_zero_ether_addr(hw_mac);
2505         if (ret) {
2506                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2507         } else {
2508                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2509                 if (!ret) {
2510                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2511                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2512                                               &hw->data->mac_addrs[0]);
2513                         hns3_warn(hw, "Default MAC address has been changed to:"
2514                                   " %s by the host PF kernel ethdev driver",
2515                                   mac_str);
2516                 }
2517         }
2518
2519         return 0;
2520 }
2521
2522 static int
2523 hns3vf_restore_conf(struct hns3_adapter *hns)
2524 {
2525         struct hns3_hw *hw = &hns->hw;
2526         int ret;
2527
2528         ret = hns3vf_check_default_mac_change(hw);
2529         if (ret)
2530                 return ret;
2531
2532         ret = hns3_configure_all_mac_addr(hns, false);
2533         if (ret)
2534                 return ret;
2535
2536         ret = hns3_configure_all_mc_mac_addr(hns, false);
2537         if (ret)
2538                 goto err_mc_mac;
2539
2540         ret = hns3vf_restore_promisc(hns);
2541         if (ret)
2542                 goto err_vlan_table;
2543
2544         ret = hns3vf_restore_vlan_conf(hns);
2545         if (ret)
2546                 goto err_vlan_table;
2547
2548         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2549         if (ret)
2550                 goto err_vlan_table;
2551
2552         ret = hns3vf_restore_rx_interrupt(hw);
2553         if (ret)
2554                 goto err_vlan_table;
2555
2556         ret = hns3_restore_gro_conf(hw);
2557         if (ret)
2558                 goto err_vlan_table;
2559
2560         if (hw->adapter_state == HNS3_NIC_STARTED) {
2561                 ret = hns3vf_do_start(hns, false);
2562                 if (ret)
2563                         goto err_vlan_table;
2564                 hns3_info(hw, "hns3vf dev restart successful!");
2565         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2566                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2567
2568         ret = hns3vf_set_alive(hw, true);
2569         if (ret) {
2570                 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2571                 goto err_vlan_table;
2572         }
2573
2574         return 0;
2575
2576 err_vlan_table:
2577         hns3_configure_all_mc_mac_addr(hns, true);
2578 err_mc_mac:
2579         hns3_configure_all_mac_addr(hns, true);
2580         return ret;
2581 }
2582
2583 static enum hns3_reset_level
2584 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2585 {
2586         enum hns3_reset_level reset_level;
2587
2588         /* return the highest priority reset level amongst all */
2589         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2590                 reset_level = HNS3_VF_RESET;
2591         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2592                 reset_level = HNS3_VF_FULL_RESET;
2593         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2594                 reset_level = HNS3_VF_PF_FUNC_RESET;
2595         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2596                 reset_level = HNS3_VF_FUNC_RESET;
2597         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2598                 reset_level = HNS3_FLR_RESET;
2599         else
2600                 reset_level = HNS3_NONE_RESET;
2601
2602         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2603                 return HNS3_NONE_RESET;
2604
2605         return reset_level;
2606 }
2607
2608 static void
2609 hns3vf_reset_service(void *param)
2610 {
2611         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2612         struct hns3_hw *hw = &hns->hw;
2613         enum hns3_reset_level reset_level;
2614         struct timeval tv_delta;
2615         struct timeval tv_start;
2616         struct timeval tv;
2617         uint64_t msec;
2618
2619         /*
2620          * The interrupt is not triggered within the delay time.
2621          * The interrupt may have been lost. It is necessary to handle
2622          * the interrupt to recover from the error.
2623          */
2624         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2625                             SCHEDULE_DEFERRED) {
2626                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2627                                  __ATOMIC_RELAXED);
2628                 hns3_err(hw, "Handling interrupts in delayed tasks");
2629                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2630                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2631                 if (reset_level == HNS3_NONE_RESET) {
2632                         hns3_err(hw, "No reset level is set, try global reset");
2633                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2634                 }
2635         }
2636         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2637
2638         /*
2639          * Hardware reset has been notified, we now have to poll & check if
2640          * hardware has actually completed the reset sequence.
2641          */
2642         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2643         if (reset_level != HNS3_NONE_RESET) {
2644                 hns3_clock_gettime(&tv_start);
2645                 hns3_reset_process(hns, reset_level);
2646                 hns3_clock_gettime(&tv);
2647                 timersub(&tv, &tv_start, &tv_delta);
2648                 msec = hns3_clock_calctime_ms(&tv_delta);
2649                 if (msec > HNS3_RESET_PROCESS_MS)
2650                         hns3_err(hw, "%d handle long time delta %" PRIu64
2651                                  " ms time=%ld.%.6ld",
2652                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2653         }
2654 }
2655
2656 static int
2657 hns3vf_reinit_dev(struct hns3_adapter *hns)
2658 {
2659         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2660         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2661         struct hns3_hw *hw = &hns->hw;
2662         int ret;
2663
2664         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2665                 rte_intr_disable(pci_dev->intr_handle);
2666                 ret = hns3vf_set_bus_master(pci_dev, true);
2667                 if (ret < 0) {
2668                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2669                         return ret;
2670                 }
2671         }
2672
2673         /* Firmware command initialize */
2674         ret = hns3_cmd_init(hw);
2675         if (ret) {
2676                 hns3_err(hw, "Failed to init cmd: %d", ret);
2677                 return ret;
2678         }
2679
2680         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2681                 /*
2682                  * UIO enables msix by writing the pcie configuration space
2683                  * vfio_pci enables msix in rte_intr_enable.
2684                  */
2685                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2686                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2687                         if (hns3vf_enable_msix(pci_dev, true))
2688                                 hns3_err(hw, "Failed to enable msix");
2689                 }
2690
2691                 rte_intr_enable(pci_dev->intr_handle);
2692         }
2693
2694         ret = hns3_reset_all_tqps(hns);
2695         if (ret) {
2696                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2697                 return ret;
2698         }
2699
2700         ret = hns3vf_init_hardware(hns);
2701         if (ret) {
2702                 hns3_err(hw, "Failed to init hardware: %d", ret);
2703                 return ret;
2704         }
2705
2706         return 0;
2707 }
2708
2709 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2710         .dev_configure      = hns3vf_dev_configure,
2711         .dev_start          = hns3vf_dev_start,
2712         .dev_stop           = hns3vf_dev_stop,
2713         .dev_close          = hns3vf_dev_close,
2714         .mtu_set            = hns3vf_dev_mtu_set,
2715         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2716         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2717         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2718         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2719         .stats_get          = hns3_stats_get,
2720         .stats_reset        = hns3_stats_reset,
2721         .xstats_get         = hns3_dev_xstats_get,
2722         .xstats_get_names   = hns3_dev_xstats_get_names,
2723         .xstats_reset       = hns3_dev_xstats_reset,
2724         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2725         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2726         .dev_infos_get      = hns3vf_dev_infos_get,
2727         .fw_version_get     = hns3vf_fw_version_get,
2728         .rx_queue_setup     = hns3_rx_queue_setup,
2729         .tx_queue_setup     = hns3_tx_queue_setup,
2730         .rx_queue_release   = hns3_dev_rx_queue_release,
2731         .tx_queue_release   = hns3_dev_tx_queue_release,
2732         .rx_queue_start     = hns3_dev_rx_queue_start,
2733         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2734         .tx_queue_start     = hns3_dev_tx_queue_start,
2735         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2736         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2737         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2738         .rxq_info_get       = hns3_rxq_info_get,
2739         .txq_info_get       = hns3_txq_info_get,
2740         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2741         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2742         .mac_addr_add       = hns3_add_mac_addr,
2743         .mac_addr_remove    = hns3_remove_mac_addr,
2744         .mac_addr_set       = hns3vf_set_default_mac_addr,
2745         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2746         .link_update        = hns3vf_dev_link_update,
2747         .rss_hash_update    = hns3_dev_rss_hash_update,
2748         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2749         .reta_update        = hns3_dev_rss_reta_update,
2750         .reta_query         = hns3_dev_rss_reta_query,
2751         .flow_ops_get       = hns3_dev_flow_ops_get,
2752         .vlan_filter_set    = hns3vf_vlan_filter_set,
2753         .vlan_offload_set   = hns3vf_vlan_offload_set,
2754         .get_reg            = hns3_get_regs,
2755         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2756         .tx_done_cleanup    = hns3_tx_done_cleanup,
2757 };
2758
2759 static const struct hns3_reset_ops hns3vf_reset_ops = {
2760         .reset_service       = hns3vf_reset_service,
2761         .stop_service        = hns3vf_stop_service,
2762         .prepare_reset       = hns3vf_prepare_reset,
2763         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2764         .reinit_dev          = hns3vf_reinit_dev,
2765         .restore_conf        = hns3vf_restore_conf,
2766         .start_service       = hns3vf_start_service,
2767 };
2768
2769 static void
2770 hns3vf_init_hw_ops(struct hns3_hw *hw)
2771 {
2772         hw->ops.add_mc_mac_addr = hns3vf_add_mc_mac_addr;
2773         hw->ops.del_mc_mac_addr = hns3vf_remove_mc_mac_addr;
2774         hw->ops.add_uc_mac_addr = hns3vf_add_uc_mac_addr;
2775         hw->ops.del_uc_mac_addr = hns3vf_remove_uc_mac_addr;
2776 }
2777
2778 static int
2779 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2780 {
2781         struct hns3_adapter *hns = eth_dev->data->dev_private;
2782         struct hns3_hw *hw = &hns->hw;
2783         int ret;
2784
2785         PMD_INIT_FUNC_TRACE();
2786
2787         hns3_flow_init(eth_dev);
2788
2789         hns3_set_rxtx_function(eth_dev);
2790         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2791         eth_dev->rx_queue_count = hns3_rx_queue_count;
2792         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2793                 ret = hns3_mp_init_secondary();
2794                 if (ret) {
2795                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2796                                           "process, ret = %d", ret);
2797                         goto err_mp_init_secondary;
2798                 }
2799                 hw->secondary_cnt++;
2800                 hns3_tx_push_init(eth_dev);
2801                 return 0;
2802         }
2803
2804         ret = hns3_mp_init_primary();
2805         if (ret) {
2806                 PMD_INIT_LOG(ERR,
2807                              "Failed to init for primary process, ret = %d",
2808                              ret);
2809                 goto err_mp_init_primary;
2810         }
2811
2812         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2813         hns->is_vf = true;
2814         hw->data = eth_dev->data;
2815         hns3_parse_devargs(eth_dev);
2816
2817         ret = hns3_reset_init(hw);
2818         if (ret)
2819                 goto err_init_reset;
2820         hw->reset.ops = &hns3vf_reset_ops;
2821
2822         hns3vf_init_hw_ops(hw);
2823         ret = hns3vf_init_vf(eth_dev);
2824         if (ret) {
2825                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2826                 goto err_init_vf;
2827         }
2828
2829         /* Allocate memory for storing MAC addresses */
2830         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2831                                                sizeof(struct rte_ether_addr) *
2832                                                HNS3_VF_UC_MACADDR_NUM, 0);
2833         if (eth_dev->data->mac_addrs == NULL) {
2834                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2835                              "to store MAC addresses",
2836                              sizeof(struct rte_ether_addr) *
2837                              HNS3_VF_UC_MACADDR_NUM);
2838                 ret = -ENOMEM;
2839                 goto err_rte_zmalloc;
2840         }
2841
2842         /*
2843          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2844          * on the host by "ip link set ..." command. To avoid some incorrect
2845          * scenes, for example, hns3 VF PMD driver fails to receive and send
2846          * packets after user configure the MAC address by using the
2847          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2848          * address strategy as the hns3 kernel ethdev driver in the
2849          * initialization. If user configure a MAC address by the ip command
2850          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2851          * start with a random MAC address in the initialization.
2852          */
2853         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2854                 rte_eth_random_addr(hw->mac.mac_addr);
2855         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2856                             &eth_dev->data->mac_addrs[0]);
2857
2858         hw->adapter_state = HNS3_NIC_INITIALIZED;
2859
2860         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2861                             SCHEDULE_PENDING) {
2862                 hns3_err(hw, "Reschedule reset service after dev_init");
2863                 hns3_schedule_reset(hns);
2864         } else {
2865                 /* IMP will wait ready flag before reset */
2866                 hns3_notify_reset_ready(hw, false);
2867         }
2868         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2869                           eth_dev);
2870         return 0;
2871
2872 err_rte_zmalloc:
2873         hns3vf_uninit_vf(eth_dev);
2874
2875 err_init_vf:
2876         rte_free(hw->reset.wait_data);
2877
2878 err_init_reset:
2879         hns3_mp_uninit_primary();
2880
2881 err_mp_init_primary:
2882 err_mp_init_secondary:
2883         eth_dev->dev_ops = NULL;
2884         eth_dev->rx_pkt_burst = NULL;
2885         eth_dev->rx_descriptor_status = NULL;
2886         eth_dev->tx_pkt_burst = NULL;
2887         eth_dev->tx_pkt_prepare = NULL;
2888         eth_dev->tx_descriptor_status = NULL;
2889
2890         return ret;
2891 }
2892
2893 static int
2894 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2895 {
2896         struct hns3_adapter *hns = eth_dev->data->dev_private;
2897         struct hns3_hw *hw = &hns->hw;
2898
2899         PMD_INIT_FUNC_TRACE();
2900
2901         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2902                 return 0;
2903
2904         if (hw->adapter_state < HNS3_NIC_CLOSING)
2905                 hns3vf_dev_close(eth_dev);
2906
2907         hw->adapter_state = HNS3_NIC_REMOVED;
2908         return 0;
2909 }
2910
2911 static int
2912 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2913                      struct rte_pci_device *pci_dev)
2914 {
2915         return rte_eth_dev_pci_generic_probe(pci_dev,
2916                                              sizeof(struct hns3_adapter),
2917                                              hns3vf_dev_init);
2918 }
2919
2920 static int
2921 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2922 {
2923         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2924 }
2925
2926 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2927         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2928         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2929         { .vendor_id = 0, }, /* sentinel */
2930 };
2931
2932 static struct rte_pci_driver rte_hns3vf_pmd = {
2933         .id_table = pci_id_hns3vf_map,
2934         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2935         .probe = eth_hns3vf_pci_probe,
2936         .remove = eth_hns3vf_pci_remove,
2937 };
2938
2939 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2940 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2941 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
2942 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
2943                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
2944                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
2945                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
2946                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16_t> ");