drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint16_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid.
 708          */
 709         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 710         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 711                 vec = vec - 1; /* the last interrupt is reserved */
 712         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 713         for (i = 0; i < hw->intr_tqps_num; i++) {
 714                 /*
 715                  * Set gap limiter/rate limiter/quanity limiter algorithm
 716                  * configuration for interrupt coalesce of queue's interrupt.
 717                  */
 718                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 719                                        HNS3_TQP_INTR_GL_DEFAULT);
 720                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 721                                        HNS3_TQP_INTR_GL_DEFAULT);
 722                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 723                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 724
 725                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 726                                                    HNS3_RING_TYPE_TX, i);
 727                 if (ret) {
 728                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 729                                           "vector: %d, ret=%d", i, vec, ret);
 730                         return ret;
 731                 }
 732
 733                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 734                                                    HNS3_RING_TYPE_RX, i);
 735                 if (ret) {
 736                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 737                                           "vector: %d, ret=%d", i, vec, ret);
 738                         return ret;
 739                 }
 740         }
 741
 742         return 0;
 743 }
 744
 745 static int
 746 hns3vf_dev_configure(struct rte_eth_dev *dev)
 747 {
 748         struct hns3_adapter *hns = dev->data->dev_private;
 749         struct hns3_hw *hw = &hns->hw;
 750         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 751         struct rte_eth_conf *conf = &dev->data->dev_conf;
 752         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 753         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 754         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 755         struct rte_eth_rss_conf rss_conf;
 756         uint16_t mtu;
 757         bool gro_en;
 758         int ret;
 759
 760         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 761
 762         /*
 763          * Some versions of hardware network engine does not support
 764          * individually enable/disable/reset the Tx or Rx queue. These devices
 765          * must enable/disable/reset Tx and Rx queues at the same time. When the
 766          * numbers of Tx queues allocated by upper applications are not equal to
 767          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 768          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 769          * work as usual. But these fake queues are imperceptible, and can not
 770          * be used by upper applications.
 771          */
 772         if (!hns3_dev_indep_txrx_supported(hw)) {
 773                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 774                 if (ret) {
 775                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
 776                                  ret);
 777                         return ret;
 778                 }
 779         }
 780
 781         hw->adapter_state = HNS3_NIC_CONFIGURING;
 782         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 783                 hns3_err(hw, "setting link speed/duplex not supported");
 784                 ret = -EINVAL;
 785                 goto cfg_err;
 786         }
 787
 788         /* When RSS is not configured, redirect the packet queue 0 */
 789         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 790                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 791                 hw->rss_dis_flag = false;
 792                 rss_conf = conf->rx_adv_conf.rss_conf;
 793                 if (rss_conf.rss_key == NULL) {
 794                         rss_conf.rss_key = rss_cfg->key;
 795                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 796                 }
 797
 798                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 799                 if (ret)
 800                         goto cfg_err;
 801         }
 802
 803         /*
 804          * If jumbo frames are enabled, MTU needs to be refreshed
 805          * according to the maximum RX packet length.
 806          */
 807         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 808                 /*
 809                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 810                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 811                  * can safely assign to "uint16_t" type variable.
 812                  */
 813                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 814                 ret = hns3vf_dev_mtu_set(dev, mtu);
 815                 if (ret)
 816                         goto cfg_err;
 817                 dev->data->mtu = mtu;
 818         }
 819
 820         ret = hns3vf_dev_configure_vlan(dev);
 821         if (ret)
 822                 goto cfg_err;
 823
 824         /* config hardware GRO */
 825         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 826         ret = hns3_config_gro(hw, gro_en);
 827         if (ret)
 828                 goto cfg_err;
 829
 830         hns->rx_simple_allowed = true;
 831         hns->rx_vec_allowed = true;
 832         hns->tx_simple_allowed = true;
 833         hns->tx_vec_allowed = true;
 834
 835         hns3_init_rx_ptype_tble(dev);
 836
 837         hw->adapter_state = HNS3_NIC_CONFIGURED;
 838         return 0;
 839
 840 cfg_err:
 841         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 842         hw->adapter_state = HNS3_NIC_INITIALIZED;
 843
 844         return ret;
 845 }
 846
 847 static int
 848 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 849 {
 850         int ret;
 851
 852         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 853                                 sizeof(mtu), true, NULL, 0);
 854         if (ret)
 855                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 856
 857         return ret;
 858 }
 859
 860 static int
 861 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 862 {
 863         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 864         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 865         int ret;
 866
 867         /*
 868          * The hns3 PF/VF devices on the same port share the hardware MTU
 869          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 870          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 871          * driver, there is no need to stop the port for hns3 VF device, and the
 872          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 873          * PF's MTU.
 874          */
 875         if (rte_atomic16_read(&hw->reset.resetting)) {
 876                 hns3_err(hw, "Failed to set mtu during resetting");
 877                 return -EIO;
 878         }
 879
 880         /*
 881          * when Rx of scattered packets is off, we have some possibility of
 882          * using vector Rx process function or simple Rx functions in hns3 PMD
 883          * driver. If the input MTU is increased and the maximum length of
 884          * received packets is greater than the length of a buffer for Rx
 885          * packet, the hardware network engine needs to use multiple BDs and
 886          * buffers to store these packets. This will cause problems when still
 887          * using vector Rx process function or simple Rx function to receiving
 888          * packets. So, when Rx of scattered packets is off and device is
 889          * started, it is not permitted to increase MTU so that the maximum
 890          * length of Rx packets is greater than Rx buffer length.
 891          */
 892         if (dev->data->dev_started && !dev->data->scattered_rx &&
 893             frame_size > hw->rx_buf_len) {
 894                 hns3_err(hw, "failed to set mtu because current is "
 895                         "not scattered rx mode");
 896                 return -EOPNOTSUPP;
 897         }
 898
 899         rte_spinlock_lock(&hw->lock);
 900         ret = hns3vf_config_mtu(hw, mtu);
 901         if (ret) {
 902                 rte_spinlock_unlock(&hw->lock);
 903                 return ret;
 904         }
 905         if (frame_size > RTE_ETHER_MAX_LEN)
 906                 dev->data->dev_conf.rxmode.offloads |=
 907                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 908         else
 909                 dev->data->dev_conf.rxmode.offloads &=
 910                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 911         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 912         rte_spinlock_unlock(&hw->lock);
 913
 914         return 0;
 915 }
 916
 917 static int
 918 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 919 {
 920         struct hns3_adapter *hns = eth_dev->data->dev_private;
 921         struct hns3_hw *hw = &hns->hw;
 922         uint16_t q_num = hw->tqps_num;
 923
 924         /*
 925          * In interrupt mode, 'max_rx_queues' is set based on the number of
 926          * MSI-X interrupt resources of the hardware.
 927          */
 928         if (hw->data->dev_conf.intr_conf.rxq == 1)
 929                 q_num = hw->intr_tqps_num;
 930
 931         info->max_rx_queues = q_num;
 932         info->max_tx_queues = hw->tqps_num;
 933         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 934         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 935         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 936         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 937         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 938
 939         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 940                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 941                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 942                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 943                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 944                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 945                                  DEV_RX_OFFLOAD_SCATTER |
 946                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 947                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 948                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 949                                  DEV_RX_OFFLOAD_RSS_HASH |
 950                                  DEV_RX_OFFLOAD_TCP_LRO);
 951         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 952                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 953                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 954                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 955                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 956                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 957                                  DEV_TX_OFFLOAD_TCP_TSO |
 958                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 959                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 960                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 961                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 962                                  hns3_txvlan_cap_get(hw));
 963
 964         if (hns3_dev_indep_txrx_supported(hw))
 965                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 966                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 967
 968         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 969                 .nb_max = HNS3_MAX_RING_DESC,
 970                 .nb_min = HNS3_MIN_RING_DESC,
 971                 .nb_align = HNS3_ALIGN_RING_DESC,
 972         };
 973
 974         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 975                 .nb_max = HNS3_MAX_RING_DESC,
 976                 .nb_min = HNS3_MIN_RING_DESC,
 977                 .nb_align = HNS3_ALIGN_RING_DESC,
 978                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 979                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
 980         };
 981
 982         info->default_rxconf = (struct rte_eth_rxconf) {
 983                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 984                 /*
 985                  * If there are no available Rx buffer descriptors, incoming
 986                  * packets are always dropped by hardware based on hns3 network
 987                  * engine.
 988                  */
 989                 .rx_drop_en = 1,
 990                 .offloads = 0,
 991         };
 992         info->default_txconf = (struct rte_eth_txconf) {
 993                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 994                 .offloads = 0,
 995         };
 996
 997         info->vmdq_queue_num = 0;
 998
 999         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
1000         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1001         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1002         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1003         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1004
1005         return 0;
1006 }
1007
1008 static void
1009 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1010 {
1011         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1012 }
1013
1014 static void
1015 hns3vf_disable_irq0(struct hns3_hw *hw)
1016 {
1017         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1018 }
1019
1020 static void
1021 hns3vf_enable_irq0(struct hns3_hw *hw)
1022 {
1023         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1024 }
1025
1026 static enum hns3vf_evt_cause
1027 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1028 {
1029         struct hns3_hw *hw = &hns->hw;
1030         enum hns3vf_evt_cause ret;
1031         uint32_t cmdq_stat_reg;
1032         uint32_t rst_ing_reg;
1033         uint32_t val;
1034
1035         /* Fetch the events from their corresponding regs */
1036         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1037
1038         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1039                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1040                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1041                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1042                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1043                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1044                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1045                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1046                 if (clearval) {
1047                         hw->reset.stats.global_cnt++;
1048                         hns3_warn(hw, "Global reset detected, clear reset status");
1049                 } else {
1050                         hns3_schedule_delayed_reset(hns);
1051                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1052                 }
1053
1054                 ret = HNS3VF_VECTOR0_EVENT_RST;
1055                 goto out;
1056         }
1057
1058         /* Check for vector0 mailbox(=CMDQ RX) event source */
1059         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1060                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1061                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1062                 goto out;
1063         }
1064
1065         val = 0;
1066         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1067 out:
1068         if (clearval)
1069                 *clearval = val;
1070         return ret;
1071 }
1072
1073 static void
1074 hns3vf_interrupt_handler(void *param)
1075 {
1076         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1077         struct hns3_adapter *hns = dev->data->dev_private;
1078         struct hns3_hw *hw = &hns->hw;
1079         enum hns3vf_evt_cause event_cause;
1080         uint32_t clearval;
1081
1082         if (hw->irq_thread_id == 0)
1083                 hw->irq_thread_id = pthread_self();
1084
1085         /* Disable interrupt */
1086         hns3vf_disable_irq0(hw);
1087
1088         /* Read out interrupt causes */
1089         event_cause = hns3vf_check_event_cause(hns, &clearval);
1090
1091         switch (event_cause) {
1092         case HNS3VF_VECTOR0_EVENT_RST:
1093                 hns3_schedule_reset(hns);
1094                 break;
1095         case HNS3VF_VECTOR0_EVENT_MBX:
1096                 hns3_dev_handle_mbx_msg(hw);
1097                 break;
1098         default:
1099                 break;
1100         }
1101
1102         /* Clear interrupt causes */
1103         hns3vf_clear_event_cause(hw, clearval);
1104
1105         /* Enable interrupt */
1106         hns3vf_enable_irq0(hw);
1107 }
1108
1109 static void
1110 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1111 {
1112         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1113         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1114         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1115 }
1116
1117 static void
1118 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1119 {
1120         struct hns3_dev_specs_0_cmd *req0;
1121
1122         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1123
1124         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1125         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1126         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1127 }
1128
1129 static int
1130 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1131 {
1132         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1133         int ret;
1134         int i;
1135
1136         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1137                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1138                                           true);
1139                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1140         }
1141         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1142
1143         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1144         if (ret)
1145                 return ret;
1146
1147         hns3vf_parse_dev_specifications(hw, desc);
1148
1149         return 0;
1150 }
1151
1152 static int
1153 hns3vf_get_capability(struct hns3_hw *hw)
1154 {
1155         struct rte_pci_device *pci_dev;
1156         struct rte_eth_dev *eth_dev;
1157         uint8_t revision;
1158         int ret;
1159
1160         eth_dev = &rte_eth_devices[hw->data->port_id];
1161         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1162
1163         /* Get PCI revision id */
1164         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1165                                   HNS3_PCI_REVISION_ID);
1166         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1167                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1168                              ret);
1169                 return -EIO;
1170         }
1171         hw->revision = revision;
1172
1173         if (revision < PCI_REVISION_ID_HIP09_A) {
1174                 hns3vf_set_default_dev_specifications(hw);
1175                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1176                 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
1177                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1178                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1179                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1180                 return 0;
1181         }
1182
1183         ret = hns3vf_query_dev_specifications(hw);
1184         if (ret) {
1185                 PMD_INIT_LOG(ERR,
1186                              "failed to query dev specifications, ret = %d",
1187                              ret);
1188                 return ret;
1189         }
1190
1191         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1192         hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
1193         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1194         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1195         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1196
1197         return 0;
1198 }
1199
1200 static int
1201 hns3vf_check_tqp_info(struct hns3_hw *hw)
1202 {
1203         if (hw->tqps_num == 0) {
1204                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1205                 return -EINVAL;
1206         }
1207
1208         if (hw->rss_size_max == 0) {
1209                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1210                 return -EINVAL;
1211         }
1212
1213         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1214
1215         return 0;
1216 }
1217
1218 static int
1219 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1220 {
1221         uint8_t resp_msg;
1222         int ret;
1223
1224         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1225                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1226                                 true, &resp_msg, sizeof(resp_msg));
1227         if (ret) {
1228                 if (ret == -ETIME) {
1229                         /*
1230                          * Getting current port based VLAN state from PF driver
1231                          * will not affect VF driver's basic function. Because
1232                          * the VF driver relies on hns3 PF kernel ether driver,
1233                          * to avoid introducing compatibility issues with older
1234                          * version of PF driver, no failure will be returned
1235                          * when the return value is ETIME. This return value has
1236                          * the following scenarios:
1237                          * 1) Firmware didn't return the results in time
1238                          * 2) the result return by firmware is timeout
1239                          * 3) the older version of kernel side PF driver does
1240                          *    not support this mailbox message.
1241                          * For scenarios 1 and 2, it is most likely that a
1242                          * hardware error has occurred, or a hardware reset has
1243                          * occurred. In this case, these errors will be caught
1244                          * by other functions.
1245                          */
1246                         PMD_INIT_LOG(WARNING,
1247                                 "failed to get PVID state for timeout, maybe "
1248                                 "kernel side PF driver doesn't support this "
1249                                 "mailbox message, or firmware didn't respond.");
1250                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1251                 } else {
1252                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1253                                 " ret = %d", ret);
1254                         return ret;
1255                 }
1256         }
1257         hw->port_base_vlan_cfg.state = resp_msg ?
1258                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1259         return 0;
1260 }
1261
1262 static int
1263 hns3vf_get_queue_info(struct hns3_hw *hw)
1264 {
1265 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1266         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1267         int ret;
1268
1269         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1270                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1271         if (ret) {
1272                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1273                 return ret;
1274         }
1275
1276         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1277         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1278
1279         return hns3vf_check_tqp_info(hw);
1280 }
1281
1282 static int
1283 hns3vf_get_queue_depth(struct hns3_hw *hw)
1284 {
1285 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1286         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1287         int ret;
1288
1289         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1290                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1291         if (ret) {
1292                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1293                              ret);
1294                 return ret;
1295         }
1296
1297         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1298         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1299
1300         return 0;
1301 }
1302
1303 static int
1304 hns3vf_get_tc_info(struct hns3_hw *hw)
1305 {
1306         uint8_t resp_msg;
1307         int ret;
1308         int i;
1309
1310         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1311                                 true, &resp_msg, sizeof(resp_msg));
1312         if (ret) {
1313                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1314                          ret);
1315                 return ret;
1316         }
1317
1318         hw->hw_tc_map = resp_msg;
1319
1320         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1321                 if (hw->hw_tc_map & BIT(i))
1322                         hw->num_tc++;
1323         }
1324
1325         return 0;
1326 }
1327
1328 static int
1329 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1330 {
1331         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1332         int ret;
1333
1334         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1335                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1336         if (ret) {
1337                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1338                 return ret;
1339         }
1340
1341         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1342
1343         return 0;
1344 }
1345
1346 static int
1347 hns3vf_get_configuration(struct hns3_hw *hw)
1348 {
1349         int ret;
1350
1351         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1352         hw->rss_dis_flag = false;
1353
1354         /* Get device capability */
1355         ret = hns3vf_get_capability(hw);
1356         if (ret) {
1357                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1358                 return ret;
1359         }
1360
1361         /* Get queue configuration from PF */
1362         ret = hns3vf_get_queue_info(hw);
1363         if (ret)
1364                 return ret;
1365
1366         /* Get queue depth info from PF */
1367         ret = hns3vf_get_queue_depth(hw);
1368         if (ret)
1369                 return ret;
1370
1371         /* Get user defined VF MAC addr from PF */
1372         ret = hns3vf_get_host_mac_addr(hw);
1373         if (ret)
1374                 return ret;
1375
1376         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1377         if (ret)
1378                 return ret;
1379
1380         /* Get tc configuration from PF */
1381         return hns3vf_get_tc_info(hw);
1382 }
1383
1384 static int
1385 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1386                             uint16_t nb_tx_q)
1387 {
1388         struct hns3_hw *hw = &hns->hw;
1389
1390         if (nb_rx_q < hw->num_tc) {
1391                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1392                          nb_rx_q, hw->num_tc);
1393                 return -EINVAL;
1394         }
1395
1396         if (nb_tx_q < hw->num_tc) {
1397                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1398                          nb_tx_q, hw->num_tc);
1399                 return -EINVAL;
1400         }
1401
1402         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1403 }
1404
1405 static void
1406 hns3vf_request_link_info(struct hns3_hw *hw)
1407 {
1408         uint8_t resp_msg;
1409         int ret;
1410
1411         if (rte_atomic16_read(&hw->reset.resetting))
1412                 return;
1413         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1414                                 &resp_msg, sizeof(resp_msg));
1415         if (ret)
1416                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1417 }
1418
1419 static int
1420 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1421 {
1422 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1423         struct hns3_hw *hw = &hns->hw;
1424         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1425         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1426         uint8_t is_kill = on ? 0 : 1;
1427
1428         msg_data[0] = is_kill;
1429         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1430         memcpy(&msg_data[3], &proto, sizeof(proto));
1431
1432         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1433                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1434                                  0);
1435 }
1436
1437 static int
1438 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1439 {
1440         struct hns3_adapter *hns = dev->data->dev_private;
1441         struct hns3_hw *hw = &hns->hw;
1442         int ret;
1443
1444         if (rte_atomic16_read(&hw->reset.resetting)) {
1445                 hns3_err(hw,
1446                          "vf set vlan id failed during resetting, vlan_id =%u",
1447                          vlan_id);
1448                 return -EIO;
1449         }
1450         rte_spinlock_lock(&hw->lock);
1451         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1452         rte_spinlock_unlock(&hw->lock);
1453         if (ret)
1454                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1455                          vlan_id, ret);
1456
1457         return ret;
1458 }
1459
1460 static int
1461 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1462 {
1463         uint8_t msg_data;
1464         int ret;
1465
1466         msg_data = enable ? 1 : 0;
1467         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1468                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1469         if (ret)
1470                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1471
1472         return ret;
1473 }
1474
1475 static int
1476 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1477 {
1478         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1479         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1480         unsigned int tmp_mask;
1481         int ret = 0;
1482
1483         if (rte_atomic16_read(&hw->reset.resetting)) {
1484                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1485                              "mask = 0x%x", mask);
1486                 return -EIO;
1487         }
1488
1489         tmp_mask = (unsigned int)mask;
1490         /* Vlan stripping setting */
1491         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1492                 rte_spinlock_lock(&hw->lock);
1493                 /* Enable or disable VLAN stripping */
1494                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1495                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1496                 else
1497                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1498                 rte_spinlock_unlock(&hw->lock);
1499         }
1500
1501         return ret;
1502 }
1503
1504 static int
1505 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1506 {
1507         struct rte_vlan_filter_conf *vfc;
1508         struct hns3_hw *hw = &hns->hw;
1509         uint16_t vlan_id;
1510         uint64_t vbit;
1511         uint64_t ids;
1512         int ret = 0;
1513         uint32_t i;
1514
1515         vfc = &hw->data->vlan_filter_conf;
1516         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1517                 if (vfc->ids[i] == 0)
1518                         continue;
1519                 ids = vfc->ids[i];
1520                 while (ids) {
1521                         /*
1522                          * 64 means the num bits of ids, one bit corresponds to
1523                          * one vlan id
1524                          */
1525                         vlan_id = 64 * i;
1526                         /* count trailing zeroes */
1527                         vbit = ~ids & (ids - 1);
1528                         /* clear least significant bit set */
1529                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1530                         for (; vbit;) {
1531                                 vbit >>= 1;
1532                                 vlan_id++;
1533                         }
1534                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1535                         if (ret) {
1536                                 hns3_err(hw,
1537                                          "VF handle vlan table failed, ret =%d, on = %d",
1538                                          ret, on);
1539                                 return ret;
1540                         }
1541                 }
1542         }
1543
1544         return ret;
1545 }
1546
1547 static int
1548 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1549 {
1550         return hns3vf_handle_all_vlan_table(hns, 0);
1551 }
1552
1553 static int
1554 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1555 {
1556         struct hns3_hw *hw = &hns->hw;
1557         struct rte_eth_conf *dev_conf;
1558         bool en;
1559         int ret;
1560
1561         dev_conf = &hw->data->dev_conf;
1562         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1563                                                                    : false;
1564         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1565         if (ret)
1566                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1567                          ret);
1568         return ret;
1569 }
1570
1571 static int
1572 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1573 {
1574         struct hns3_adapter *hns = dev->data->dev_private;
1575         struct rte_eth_dev_data *data = dev->data;
1576         struct hns3_hw *hw = &hns->hw;
1577         int ret;
1578
1579         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1580             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1581             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1582                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1583                               "or hw_vlan_insert_pvid is not support!");
1584         }
1585
1586         /* Apply vlan offload setting */
1587         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1588         if (ret)
1589                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1590
1591         return ret;
1592 }
1593
1594 static int
1595 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1596 {
1597         uint8_t msg_data;
1598
1599         msg_data = alive ? 1 : 0;
1600         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1601                                  sizeof(msg_data), false, NULL, 0);
1602 }
1603
1604 static void
1605 hns3vf_keep_alive_handler(void *param)
1606 {
1607         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1608         struct hns3_adapter *hns = eth_dev->data->dev_private;
1609         struct hns3_hw *hw = &hns->hw;
1610         uint8_t respmsg;
1611         int ret;
1612
1613         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1614                                 false, &respmsg, sizeof(uint8_t));
1615         if (ret)
1616                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1617                          ret);
1618
1619         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1620                           eth_dev);
1621 }
1622
1623 static void
1624 hns3vf_service_handler(void *param)
1625 {
1626         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1627         struct hns3_adapter *hns = eth_dev->data->dev_private;
1628         struct hns3_hw *hw = &hns->hw;
1629
1630         /*
1631          * The query link status and reset processing are executed in the
1632          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1633          * and the query operation will time out after 30ms. In the case of
1634          * multiple PF/VFs, each query failure timeout causes the IMP reset
1635          * interrupt to fail to respond within 100ms.
1636          * Before querying the link status, check whether there is a reset
1637          * pending, and if so, abandon the query.
1638          */
1639         if (!hns3vf_is_reset_pending(hns))
1640                 hns3vf_request_link_info(hw);
1641         else
1642                 hns3_warn(hw, "Cancel the query when reset is pending");
1643
1644         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1645                           eth_dev);
1646 }
1647
1648 static int
1649 hns3_query_vf_resource(struct hns3_hw *hw)
1650 {
1651         struct hns3_vf_res_cmd *req;
1652         struct hns3_cmd_desc desc;
1653         uint16_t num_msi;
1654         int ret;
1655
1656         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1657         ret = hns3_cmd_send(hw, &desc, 1);
1658         if (ret) {
1659                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1660                 return ret;
1661         }
1662
1663         req = (struct hns3_vf_res_cmd *)desc.data;
1664         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1665                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1666         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1667                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1668                          num_msi, HNS3_MIN_VECTOR_NUM);
1669                 return -EINVAL;
1670         }
1671
1672         hw->num_msi = num_msi;
1673
1674         return 0;
1675 }
1676
1677 static int
1678 hns3vf_init_hardware(struct hns3_adapter *hns)
1679 {
1680         struct hns3_hw *hw = &hns->hw;
1681         uint16_t mtu = hw->data->mtu;
1682         int ret;
1683
1684         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1685         if (ret)
1686                 return ret;
1687
1688         ret = hns3vf_config_mtu(hw, mtu);
1689         if (ret)
1690                 goto err_init_hardware;
1691
1692         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1693         if (ret) {
1694                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1695                 goto err_init_hardware;
1696         }
1697
1698         ret = hns3_config_gro(hw, false);
1699         if (ret) {
1700                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1701                 goto err_init_hardware;
1702         }
1703
1704         /*
1705          * In the initialization clearing the all hardware mapping relationship
1706          * configurations between queues and interrupt vectors is needed, so
1707          * some error caused by the residual configurations, such as the
1708          * unexpected interrupt, can be avoid.
1709          */
1710         ret = hns3vf_init_ring_with_vector(hw);
1711         if (ret) {
1712                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1713                 goto err_init_hardware;
1714         }
1715
1716         ret = hns3vf_set_alive(hw, true);
1717         if (ret) {
1718                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1719                 goto err_init_hardware;
1720         }
1721
1722         hns3vf_request_link_info(hw);
1723         return 0;
1724
1725 err_init_hardware:
1726         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1727         return ret;
1728 }
1729
1730 static int
1731 hns3vf_clear_vport_list(struct hns3_hw *hw)
1732 {
1733         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1734                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1735                                  NULL, 0);
1736 }
1737
1738 static int
1739 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1740 {
1741         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1742         struct hns3_adapter *hns = eth_dev->data->dev_private;
1743         struct hns3_hw *hw = &hns->hw;
1744         int ret;
1745
1746         PMD_INIT_FUNC_TRACE();
1747
1748         /* Get hardware io base address from pcie BAR2 IO space */
1749         hw->io_base = pci_dev->mem_resource[2].addr;
1750
1751         /* Firmware command queue initialize */
1752         ret = hns3_cmd_init_queue(hw);
1753         if (ret) {
1754                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1755                 goto err_cmd_init_queue;
1756         }
1757
1758         /* Firmware command initialize */
1759         ret = hns3_cmd_init(hw);
1760         if (ret) {
1761                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1762                 goto err_cmd_init;
1763         }
1764
1765         /* Get VF resource */
1766         ret = hns3_query_vf_resource(hw);
1767         if (ret)
1768                 goto err_cmd_init;
1769
1770         rte_spinlock_init(&hw->mbx_resp.lock);
1771
1772         hns3vf_clear_event_cause(hw, 0);
1773
1774         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1775                                          hns3vf_interrupt_handler, eth_dev);
1776         if (ret) {
1777                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1778                 goto err_intr_callback_register;
1779         }
1780
1781         /* Enable interrupt */
1782         rte_intr_enable(&pci_dev->intr_handle);
1783         hns3vf_enable_irq0(hw);
1784
1785         /* Get configuration from PF */
1786         ret = hns3vf_get_configuration(hw);
1787         if (ret) {
1788                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1789                 goto err_get_config;
1790         }
1791
1792         ret = hns3_tqp_stats_init(hw);
1793         if (ret)
1794                 goto err_get_config;
1795
1796         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1797         if (ret) {
1798                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1799                 goto err_set_tc_queue;
1800         }
1801
1802         ret = hns3vf_clear_vport_list(hw);
1803         if (ret) {
1804                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1805                 goto err_set_tc_queue;
1806         }
1807
1808         ret = hns3vf_init_hardware(hns);
1809         if (ret)
1810                 goto err_set_tc_queue;
1811
1812         hns3_set_default_rss_args(hw);
1813
1814         return 0;
1815
1816 err_set_tc_queue:
1817         hns3_tqp_stats_uninit(hw);
1818
1819 err_get_config:
1820         hns3vf_disable_irq0(hw);
1821         rte_intr_disable(&pci_dev->intr_handle);
1822         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1823                              eth_dev);
1824 err_intr_callback_register:
1825 err_cmd_init:
1826         hns3_cmd_uninit(hw);
1827         hns3_cmd_destroy_queue(hw);
1828 err_cmd_init_queue:
1829         hw->io_base = NULL;
1830
1831         return ret;
1832 }
1833
1834 static void
1835 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1836 {
1837         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1838         struct hns3_adapter *hns = eth_dev->data->dev_private;
1839         struct hns3_hw *hw = &hns->hw;
1840
1841         PMD_INIT_FUNC_TRACE();
1842
1843         hns3_rss_uninit(hns);
1844         (void)hns3_config_gro(hw, false);
1845         (void)hns3vf_set_alive(hw, false);
1846         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1847         hns3_tqp_stats_uninit(hw);
1848         hns3vf_disable_irq0(hw);
1849         rte_intr_disable(&pci_dev->intr_handle);
1850         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1851                              eth_dev);
1852         hns3_cmd_uninit(hw);
1853         hns3_cmd_destroy_queue(hw);
1854         hw->io_base = NULL;
1855 }
1856
1857 static int
1858 hns3vf_do_stop(struct hns3_adapter *hns)
1859 {
1860         struct hns3_hw *hw = &hns->hw;
1861         int ret;
1862
1863         hw->mac.link_status = ETH_LINK_DOWN;
1864
1865         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1866                 hns3vf_configure_mac_addr(hns, true);
1867                 ret = hns3_reset_all_tqps(hns);
1868                 if (ret) {
1869                         hns3_err(hw, "failed to reset all queues ret = %d",
1870                                  ret);
1871                         return ret;
1872                 }
1873         }
1874         return 0;
1875 }
1876
1877 static void
1878 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1879 {
1880         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1881         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1882         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1883         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1884         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1885         uint16_t q_id;
1886
1887         if (dev->data->dev_conf.intr_conf.rxq == 0)
1888                 return;
1889
1890         /* unmap the ring with vector */
1891         if (rte_intr_allow_others(intr_handle)) {
1892                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1893                 base = RTE_INTR_VEC_RXTX_OFFSET;
1894         }
1895         if (rte_intr_dp_is_en(intr_handle)) {
1896                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1897                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1898                                                            HNS3_RING_TYPE_RX,
1899                                                            q_id);
1900                         if (vec < base + intr_handle->nb_efd - 1)
1901                                 vec++;
1902                 }
1903         }
1904         /* Clean datapath event and queue/vec mapping */
1905         rte_intr_efd_disable(intr_handle);
1906         if (intr_handle->intr_vec) {
1907                 rte_free(intr_handle->intr_vec);
1908                 intr_handle->intr_vec = NULL;
1909         }
1910 }
1911
1912 static void
1913 hns3vf_dev_stop(struct rte_eth_dev *dev)
1914 {
1915         struct hns3_adapter *hns = dev->data->dev_private;
1916         struct hns3_hw *hw = &hns->hw;
1917
1918         PMD_INIT_FUNC_TRACE();
1919
1920         hw->adapter_state = HNS3_NIC_STOPPING;
1921         hns3_set_rxtx_function(dev);
1922         rte_wmb();
1923         /* Disable datapath on secondary process. */
1924         hns3_mp_req_stop_rxtx(dev);
1925         /* Prevent crashes when queues are still in use. */
1926         rte_delay_ms(hw->tqps_num);
1927
1928         rte_spinlock_lock(&hw->lock);
1929         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1930                 hns3_stop_tqps(hw);
1931                 hns3vf_do_stop(hns);
1932                 hns3vf_unmap_rx_interrupt(dev);
1933                 hns3_dev_release_mbufs(hns);
1934                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1935         }
1936         hns3_rx_scattered_reset(dev);
1937         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1938         rte_spinlock_unlock(&hw->lock);
1939 }
1940
1941 static int
1942 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1943 {
1944         struct hns3_adapter *hns = eth_dev->data->dev_private;
1945         struct hns3_hw *hw = &hns->hw;
1946
1947         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1948                 return 0;
1949
1950         if (hw->adapter_state == HNS3_NIC_STARTED)
1951                 hns3vf_dev_stop(eth_dev);
1952
1953         hw->adapter_state = HNS3_NIC_CLOSING;
1954         hns3_reset_abort(hns);
1955         hw->adapter_state = HNS3_NIC_CLOSED;
1956         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1957         hns3vf_configure_all_mc_mac_addr(hns, true);
1958         hns3vf_remove_all_vlan_table(hns);
1959         hns3vf_uninit_vf(eth_dev);
1960         hns3_free_all_queues(eth_dev);
1961         rte_free(hw->reset.wait_data);
1962         rte_free(eth_dev->process_private);
1963         eth_dev->process_private = NULL;
1964         hns3_mp_uninit_primary();
1965         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1966
1967         return 0;
1968 }
1969
1970 static int
1971 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1972                       size_t fw_size)
1973 {
1974         struct hns3_adapter *hns = eth_dev->data->dev_private;
1975         struct hns3_hw *hw = &hns->hw;
1976         uint32_t version = hw->fw_version;
1977         int ret;
1978
1979         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1980                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1981                                       HNS3_FW_VERSION_BYTE3_S),
1982                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1983                                       HNS3_FW_VERSION_BYTE2_S),
1984                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1985                                       HNS3_FW_VERSION_BYTE1_S),
1986                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1987                                       HNS3_FW_VERSION_BYTE0_S));
1988         ret += 1; /* add the size of '\0' */
1989         if (fw_size < (uint32_t)ret)
1990                 return ret;
1991         else
1992                 return 0;
1993 }
1994
1995 static int
1996 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1997                        __rte_unused int wait_to_complete)
1998 {
1999         struct hns3_adapter *hns = eth_dev->data->dev_private;
2000         struct hns3_hw *hw = &hns->hw;
2001         struct hns3_mac *mac = &hw->mac;
2002         struct rte_eth_link new_link;
2003
2004         memset(&new_link, 0, sizeof(new_link));
2005         switch (mac->link_speed) {
2006         case ETH_SPEED_NUM_10M:
2007         case ETH_SPEED_NUM_100M:
2008         case ETH_SPEED_NUM_1G:
2009         case ETH_SPEED_NUM_10G:
2010         case ETH_SPEED_NUM_25G:
2011         case ETH_SPEED_NUM_40G:
2012         case ETH_SPEED_NUM_50G:
2013         case ETH_SPEED_NUM_100G:
2014         case ETH_SPEED_NUM_200G:
2015                 new_link.link_speed = mac->link_speed;
2016                 break;
2017         default:
2018                 new_link.link_speed = ETH_SPEED_NUM_100M;
2019                 break;
2020         }
2021
2022         new_link.link_duplex = mac->link_duplex;
2023         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2024         new_link.link_autoneg =
2025             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2026
2027         return rte_eth_linkstatus_set(eth_dev, &new_link);
2028 }
2029
2030 static int
2031 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2032 {
2033         struct hns3_hw *hw = &hns->hw;
2034         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2035         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2036         int ret;
2037
2038         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2039         if (ret)
2040                 return ret;
2041
2042         ret = hns3_init_queues(hns, reset_queue);
2043         if (ret)
2044                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2045
2046         return ret;
2047 }
2048
2049 static int
2050 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2051 {
2052         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2053         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2054         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2056         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2057         uint32_t intr_vector;
2058         uint16_t q_id;
2059         int ret;
2060
2061         if (dev->data->dev_conf.intr_conf.rxq == 0)
2062                 return 0;
2063
2064         /* disable uio/vfio intr/eventfd mapping */
2065         rte_intr_disable(intr_handle);
2066
2067         /* check and configure queue intr-vector mapping */
2068         if (rte_intr_cap_multiple(intr_handle) ||
2069             !RTE_ETH_DEV_SRIOV(dev).active) {
2070                 intr_vector = hw->used_rx_queues;
2071                 /* It creates event fd for each intr vector when MSIX is used */
2072                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2073                         return -EINVAL;
2074         }
2075         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2076                 intr_handle->intr_vec =
2077                         rte_zmalloc("intr_vec",
2078                                     hw->used_rx_queues * sizeof(int), 0);
2079                 if (intr_handle->intr_vec == NULL) {
2080                         hns3_err(hw, "Failed to allocate %d rx_queues"
2081                                      " intr_vec", hw->used_rx_queues);
2082                         ret = -ENOMEM;
2083                         goto vf_alloc_intr_vec_error;
2084                 }
2085         }
2086
2087         if (rte_intr_allow_others(intr_handle)) {
2088                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2089                 base = RTE_INTR_VEC_RXTX_OFFSET;
2090         }
2091         if (rte_intr_dp_is_en(intr_handle)) {
2092                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2093                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2094                                                            HNS3_RING_TYPE_RX,
2095                                                            q_id);
2096                         if (ret)
2097                                 goto vf_bind_vector_error;
2098                         intr_handle->intr_vec[q_id] = vec;
2099                         if (vec < base + intr_handle->nb_efd - 1)
2100                                 vec++;
2101                 }
2102         }
2103         rte_intr_enable(intr_handle);
2104         return 0;
2105
2106 vf_bind_vector_error:
2107         rte_intr_efd_disable(intr_handle);
2108         if (intr_handle->intr_vec) {
2109                 free(intr_handle->intr_vec);
2110                 intr_handle->intr_vec = NULL;
2111         }
2112         return ret;
2113 vf_alloc_intr_vec_error:
2114         rte_intr_efd_disable(intr_handle);
2115         return ret;
2116 }
2117
2118 static int
2119 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2120 {
2121         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2122         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2123         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2124         uint16_t q_id;
2125         int ret;
2126
2127         if (dev->data->dev_conf.intr_conf.rxq == 0)
2128                 return 0;
2129
2130         if (rte_intr_dp_is_en(intr_handle)) {
2131                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2132                         ret = hns3vf_bind_ring_with_vector(hw,
2133                                         intr_handle->intr_vec[q_id], true,
2134                                         HNS3_RING_TYPE_RX, q_id);
2135                         if (ret)
2136                                 return ret;
2137                 }
2138         }
2139
2140         return 0;
2141 }
2142
2143 static void
2144 hns3vf_restore_filter(struct rte_eth_dev *dev)
2145 {
2146         hns3_restore_rss_filter(dev);
2147 }
2148
2149 static int
2150 hns3vf_dev_start(struct rte_eth_dev *dev)
2151 {
2152         struct hns3_adapter *hns = dev->data->dev_private;
2153         struct hns3_hw *hw = &hns->hw;
2154         int ret;
2155
2156         PMD_INIT_FUNC_TRACE();
2157         if (rte_atomic16_read(&hw->reset.resetting))
2158                 return -EBUSY;
2159
2160         rte_spinlock_lock(&hw->lock);
2161         hw->adapter_state = HNS3_NIC_STARTING;
2162         ret = hns3vf_do_start(hns, true);
2163         if (ret) {
2164                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2165                 rte_spinlock_unlock(&hw->lock);
2166                 return ret;
2167         }
2168         ret = hns3vf_map_rx_interrupt(dev);
2169         if (ret) {
2170                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2171                 rte_spinlock_unlock(&hw->lock);
2172                 return ret;
2173         }
2174
2175         /*
2176          * There are three register used to control the status of a TQP
2177          * (contains a pair of Tx queue and Rx queue) in the new version network
2178          * engine. One is used to control the enabling of Tx queue, the other is
2179          * used to control the enabling of Rx queue, and the last is the master
2180          * switch used to control the enabling of the tqp. The Tx register and
2181          * TQP register must be enabled at the same time to enable a Tx queue.
2182          * The same applies to the Rx queue. For the older network enginem, this
2183          * function only refresh the enabled flag, and it is used to update the
2184          * status of queue in the dpdk framework.
2185          */
2186         ret = hns3_start_all_txqs(dev);
2187         if (ret) {
2188                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2189                 rte_spinlock_unlock(&hw->lock);
2190                 return ret;
2191         }
2192
2193         ret = hns3_start_all_rxqs(dev);
2194         if (ret) {
2195                 hns3_stop_all_txqs(dev);
2196                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2197                 rte_spinlock_unlock(&hw->lock);
2198                 return ret;
2199         }
2200
2201         hw->adapter_state = HNS3_NIC_STARTED;
2202         rte_spinlock_unlock(&hw->lock);
2203
2204         hns3_rx_scattered_calc(dev);
2205         hns3_set_rxtx_function(dev);
2206         hns3_mp_req_start_rxtx(dev);
2207         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2208
2209         hns3vf_restore_filter(dev);
2210
2211         /* Enable interrupt of all rx queues before enabling queues */
2212         hns3_dev_all_rx_queue_intr_enable(hw, true);
2213
2214         /*
2215          * After finished the initialization, start all tqps to receive/transmit
2216          * packets and refresh all queue status.
2217          */
2218         hns3_start_tqps(hw);
2219
2220         return ret;
2221 }
2222
2223 static bool
2224 is_vf_reset_done(struct hns3_hw *hw)
2225 {
2226 #define HNS3_FUN_RST_ING_BITS \
2227         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2228          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2229          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2230          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2231
2232         uint32_t val;
2233
2234         if (hw->reset.level == HNS3_VF_RESET) {
2235                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2236                 if (val & HNS3_VF_RST_ING_BIT)
2237                         return false;
2238         } else {
2239                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2240                 if (val & HNS3_FUN_RST_ING_BITS)
2241                         return false;
2242         }
2243         return true;
2244 }
2245
2246 bool
2247 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2248 {
2249         struct hns3_hw *hw = &hns->hw;
2250         enum hns3_reset_level reset;
2251
2252         /*
2253          * According to the protocol of PCIe, FLR to a PF device resets the PF
2254          * state as well as the SR-IOV extended capability including VF Enable
2255          * which means that VFs no longer exist.
2256          *
2257          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2258          * is in FLR stage, the register state of VF device is not reliable,
2259          * so register states detection can not be carried out. In this case,
2260          * we just ignore the register states and return false to indicate that
2261          * there are no other reset states that need to be processed by driver.
2262          */
2263         if (hw->reset.level == HNS3_VF_FULL_RESET)
2264                 return false;
2265
2266         /* Check the registers to confirm whether there is reset pending */
2267         hns3vf_check_event_cause(hns, NULL);
2268         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2269         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2270                 hns3_warn(hw, "High level reset %d is pending", reset);
2271                 return true;
2272         }
2273         return false;
2274 }
2275
2276 static int
2277 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2278 {
2279         struct hns3_hw *hw = &hns->hw;
2280         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2281         struct timeval tv;
2282
2283         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2284                 /*
2285                  * After vf reset is ready, the PF may not have completed
2286                  * the reset processing. The vf sending mbox to PF may fail
2287                  * during the pf reset, so it is better to add extra delay.
2288                  */
2289                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2290                     hw->reset.level == HNS3_FLR_RESET)
2291                         return 0;
2292                 /* Reset retry process, no need to add extra delay. */
2293                 if (hw->reset.attempts)
2294                         return 0;
2295                 if (wait_data->check_completion == NULL)
2296                         return 0;
2297
2298                 wait_data->check_completion = NULL;
2299                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2300                 wait_data->count = 1;
2301                 wait_data->result = HNS3_WAIT_REQUEST;
2302                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2303                                   wait_data);
2304                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2305                 return -EAGAIN;
2306         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2307                 gettimeofday(&tv, NULL);
2308                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2309                           tv.tv_sec, tv.tv_usec);
2310                 return -ETIME;
2311         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2312                 return -EAGAIN;
2313
2314         wait_data->hns = hns;
2315         wait_data->check_completion = is_vf_reset_done;
2316         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2317                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2318         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2319         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2320         wait_data->result = HNS3_WAIT_REQUEST;
2321         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2322         return -EAGAIN;
2323 }
2324
2325 static int
2326 hns3vf_prepare_reset(struct hns3_adapter *hns)
2327 {
2328         struct hns3_hw *hw = &hns->hw;
2329         int ret = 0;
2330
2331         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2332                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2333                                         0, true, NULL, 0);
2334         }
2335         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2336
2337         return ret;
2338 }
2339
2340 static int
2341 hns3vf_stop_service(struct hns3_adapter *hns)
2342 {
2343         struct hns3_hw *hw = &hns->hw;
2344         struct rte_eth_dev *eth_dev;
2345
2346         eth_dev = &rte_eth_devices[hw->data->port_id];
2347         if (hw->adapter_state == HNS3_NIC_STARTED)
2348                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2349         hw->mac.link_status = ETH_LINK_DOWN;
2350
2351         hns3_set_rxtx_function(eth_dev);
2352         rte_wmb();
2353         /* Disable datapath on secondary process. */
2354         hns3_mp_req_stop_rxtx(eth_dev);
2355         rte_delay_ms(hw->tqps_num);
2356
2357         rte_spinlock_lock(&hw->lock);
2358         if (hw->adapter_state == HNS3_NIC_STARTED ||
2359             hw->adapter_state == HNS3_NIC_STOPPING) {
2360                 hns3_enable_all_queues(hw, false);
2361                 hns3vf_do_stop(hns);
2362                 hw->reset.mbuf_deferred_free = true;
2363         } else
2364                 hw->reset.mbuf_deferred_free = false;
2365
2366         /*
2367          * It is cumbersome for hardware to pick-and-choose entries for deletion
2368          * from table space. Hence, for function reset software intervention is
2369          * required to delete the entries.
2370          */
2371         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2372                 hns3vf_configure_all_mc_mac_addr(hns, true);
2373         rte_spinlock_unlock(&hw->lock);
2374
2375         return 0;
2376 }
2377
2378 static int
2379 hns3vf_start_service(struct hns3_adapter *hns)
2380 {
2381         struct hns3_hw *hw = &hns->hw;
2382         struct rte_eth_dev *eth_dev;
2383
2384         eth_dev = &rte_eth_devices[hw->data->port_id];
2385         hns3_set_rxtx_function(eth_dev);
2386         hns3_mp_req_start_rxtx(eth_dev);
2387         if (hw->adapter_state == HNS3_NIC_STARTED) {
2388                 hns3vf_service_handler(eth_dev);
2389
2390                 /* Enable interrupt of all rx queues before enabling queues */
2391                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2392                 /*
2393                  * When finished the initialization, enable queues to receive
2394                  * and transmit packets.
2395                  */
2396                 hns3_enable_all_queues(hw, true);
2397         }
2398
2399         return 0;
2400 }
2401
2402 static int
2403 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2404 {
2405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2406         struct rte_ether_addr *hw_mac;
2407         int ret;
2408
2409         /*
2410          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2411          * on the host by "ip link set ..." command. If the hns3 PF kernel
2412          * ethdev driver sets the MAC address for VF device after the
2413          * initialization of the related VF device, the PF driver will notify
2414          * VF driver to reset VF device to make the new MAC address effective
2415          * immediately. The hns3 VF PMD driver should check whether the MAC
2416          * address has been changed by the PF kernel ethdev driver, if changed
2417          * VF driver should configure hardware using the new MAC address in the
2418          * recovering hardware configuration stage of the reset process.
2419          */
2420         ret = hns3vf_get_host_mac_addr(hw);
2421         if (ret)
2422                 return ret;
2423
2424         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2425         ret = rte_is_zero_ether_addr(hw_mac);
2426         if (ret) {
2427                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2428         } else {
2429                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2430                 if (!ret) {
2431                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2432                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2433                                               &hw->data->mac_addrs[0]);
2434                         hns3_warn(hw, "Default MAC address has been changed to:"
2435                                   " %s by the host PF kernel ethdev driver",
2436                                   mac_str);
2437                 }
2438         }
2439
2440         return 0;
2441 }
2442
2443 static int
2444 hns3vf_restore_conf(struct hns3_adapter *hns)
2445 {
2446         struct hns3_hw *hw = &hns->hw;
2447         int ret;
2448
2449         ret = hns3vf_check_default_mac_change(hw);
2450         if (ret)
2451                 return ret;
2452
2453         ret = hns3vf_configure_mac_addr(hns, false);
2454         if (ret)
2455                 return ret;
2456
2457         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2458         if (ret)
2459                 goto err_mc_mac;
2460
2461         ret = hns3vf_restore_promisc(hns);
2462         if (ret)
2463                 goto err_vlan_table;
2464
2465         ret = hns3vf_restore_vlan_conf(hns);
2466         if (ret)
2467                 goto err_vlan_table;
2468
2469         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2470         if (ret)
2471                 goto err_vlan_table;
2472
2473         ret = hns3vf_restore_rx_interrupt(hw);
2474         if (ret)
2475                 goto err_vlan_table;
2476
2477         ret = hns3_restore_gro_conf(hw);
2478         if (ret)
2479                 goto err_vlan_table;
2480
2481         if (hw->adapter_state == HNS3_NIC_STARTED) {
2482                 ret = hns3vf_do_start(hns, false);
2483                 if (ret)
2484                         goto err_vlan_table;
2485                 hns3_info(hw, "hns3vf dev restart successful!");
2486         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2487                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2488         return 0;
2489
2490 err_vlan_table:
2491         hns3vf_configure_all_mc_mac_addr(hns, true);
2492 err_mc_mac:
2493         hns3vf_configure_mac_addr(hns, true);
2494         return ret;
2495 }
2496
2497 static enum hns3_reset_level
2498 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2499 {
2500         enum hns3_reset_level reset_level;
2501
2502         /* return the highest priority reset level amongst all */
2503         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2504                 reset_level = HNS3_VF_RESET;
2505         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2506                 reset_level = HNS3_VF_FULL_RESET;
2507         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2508                 reset_level = HNS3_VF_PF_FUNC_RESET;
2509         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2510                 reset_level = HNS3_VF_FUNC_RESET;
2511         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2512                 reset_level = HNS3_FLR_RESET;
2513         else
2514                 reset_level = HNS3_NONE_RESET;
2515
2516         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2517                 return HNS3_NONE_RESET;
2518
2519         return reset_level;
2520 }
2521
2522 static void
2523 hns3vf_reset_service(void *param)
2524 {
2525         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2526         struct hns3_hw *hw = &hns->hw;
2527         enum hns3_reset_level reset_level;
2528         struct timeval tv_delta;
2529         struct timeval tv_start;
2530         struct timeval tv;
2531         uint64_t msec;
2532
2533         /*
2534          * The interrupt is not triggered within the delay time.
2535          * The interrupt may have been lost. It is necessary to handle
2536          * the interrupt to recover from the error.
2537          */
2538         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2539                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2540                 hns3_err(hw, "Handling interrupts in delayed tasks");
2541                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2542                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2543                 if (reset_level == HNS3_NONE_RESET) {
2544                         hns3_err(hw, "No reset level is set, try global reset");
2545                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2546                 }
2547         }
2548         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2549
2550         /*
2551          * Hardware reset has been notified, we now have to poll & check if
2552          * hardware has actually completed the reset sequence.
2553          */
2554         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2555         if (reset_level != HNS3_NONE_RESET) {
2556                 gettimeofday(&tv_start, NULL);
2557                 hns3_reset_process(hns, reset_level);
2558                 gettimeofday(&tv, NULL);
2559                 timersub(&tv, &tv_start, &tv_delta);
2560                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2561                        tv_delta.tv_usec / USEC_PER_MSEC;
2562                 if (msec > HNS3_RESET_PROCESS_MS)
2563                         hns3_err(hw, "%d handle long time delta %" PRIx64
2564                                  " ms time=%ld.%.6ld",
2565                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2566         }
2567 }
2568
2569 static int
2570 hns3vf_reinit_dev(struct hns3_adapter *hns)
2571 {
2572         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2573         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2574         struct hns3_hw *hw = &hns->hw;
2575         int ret;
2576
2577         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2578                 rte_intr_disable(&pci_dev->intr_handle);
2579                 hns3vf_set_bus_master(pci_dev, true);
2580         }
2581
2582         /* Firmware command initialize */
2583         ret = hns3_cmd_init(hw);
2584         if (ret) {
2585                 hns3_err(hw, "Failed to init cmd: %d", ret);
2586                 return ret;
2587         }
2588
2589         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2590                 /*
2591                  * UIO enables msix by writing the pcie configuration space
2592                  * vfio_pci enables msix in rte_intr_enable.
2593                  */
2594                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2595                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2596                         if (hns3vf_enable_msix(pci_dev, true))
2597                                 hns3_err(hw, "Failed to enable msix");
2598                 }
2599
2600                 rte_intr_enable(&pci_dev->intr_handle);
2601         }
2602
2603         ret = hns3_reset_all_tqps(hns);
2604         if (ret) {
2605                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2606                 return ret;
2607         }
2608
2609         ret = hns3vf_init_hardware(hns);
2610         if (ret) {
2611                 hns3_err(hw, "Failed to init hardware: %d", ret);
2612                 return ret;
2613         }
2614
2615         return 0;
2616 }
2617
2618 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2619         .dev_configure      = hns3vf_dev_configure,
2620         .dev_start          = hns3vf_dev_start,
2621         .dev_stop           = hns3vf_dev_stop,
2622         .dev_close          = hns3vf_dev_close,
2623         .mtu_set            = hns3vf_dev_mtu_set,
2624         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2625         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2626         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2627         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2628         .stats_get          = hns3_stats_get,
2629         .stats_reset        = hns3_stats_reset,
2630         .xstats_get         = hns3_dev_xstats_get,
2631         .xstats_get_names   = hns3_dev_xstats_get_names,
2632         .xstats_reset       = hns3_dev_xstats_reset,
2633         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2634         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2635         .dev_infos_get      = hns3vf_dev_infos_get,
2636         .fw_version_get     = hns3vf_fw_version_get,
2637         .rx_queue_setup     = hns3_rx_queue_setup,
2638         .tx_queue_setup     = hns3_tx_queue_setup,
2639         .rx_queue_release   = hns3_dev_rx_queue_release,
2640         .tx_queue_release   = hns3_dev_tx_queue_release,
2641         .rx_queue_start     = hns3_dev_rx_queue_start,
2642         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2643         .tx_queue_start     = hns3_dev_tx_queue_start,
2644         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2645         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2646         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2647         .rxq_info_get       = hns3_rxq_info_get,
2648         .txq_info_get       = hns3_txq_info_get,
2649         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2650         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2651         .mac_addr_add       = hns3vf_add_mac_addr,
2652         .mac_addr_remove    = hns3vf_remove_mac_addr,
2653         .mac_addr_set       = hns3vf_set_default_mac_addr,
2654         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2655         .link_update        = hns3vf_dev_link_update,
2656         .rss_hash_update    = hns3_dev_rss_hash_update,
2657         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2658         .reta_update        = hns3_dev_rss_reta_update,
2659         .reta_query         = hns3_dev_rss_reta_query,
2660         .filter_ctrl        = hns3_dev_filter_ctrl,
2661         .vlan_filter_set    = hns3vf_vlan_filter_set,
2662         .vlan_offload_set   = hns3vf_vlan_offload_set,
2663         .get_reg            = hns3_get_regs,
2664         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2665 };
2666
2667 static const struct hns3_reset_ops hns3vf_reset_ops = {
2668         .reset_service       = hns3vf_reset_service,
2669         .stop_service        = hns3vf_stop_service,
2670         .prepare_reset       = hns3vf_prepare_reset,
2671         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2672         .reinit_dev          = hns3vf_reinit_dev,
2673         .restore_conf        = hns3vf_restore_conf,
2674         .start_service       = hns3vf_start_service,
2675 };
2676
2677 static int
2678 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2679 {
2680         struct hns3_adapter *hns = eth_dev->data->dev_private;
2681         struct hns3_hw *hw = &hns->hw;
2682         int ret;
2683
2684         PMD_INIT_FUNC_TRACE();
2685
2686         eth_dev->process_private = (struct hns3_process_private *)
2687             rte_zmalloc_socket("hns3_filter_list",
2688                                sizeof(struct hns3_process_private),
2689                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2690         if (eth_dev->process_private == NULL) {
2691                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2692                 return -ENOMEM;
2693         }
2694
2695         /* initialize flow filter lists */
2696         hns3_filterlist_init(eth_dev);
2697
2698         hns3_set_rxtx_function(eth_dev);
2699         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2700         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2701                 ret = hns3_mp_init_secondary();
2702                 if (ret) {
2703                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2704                                           "process, ret = %d", ret);
2705                         goto err_mp_init_secondary;
2706                 }
2707
2708                 hw->secondary_cnt++;
2709                 return 0;
2710         }
2711
2712         ret = hns3_mp_init_primary();
2713         if (ret) {
2714                 PMD_INIT_LOG(ERR,
2715                              "Failed to init for primary process, ret = %d",
2716                              ret);
2717                 goto err_mp_init_primary;
2718         }
2719
2720         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2721         hns->is_vf = true;
2722         hw->data = eth_dev->data;
2723
2724         ret = hns3_reset_init(hw);
2725         if (ret)
2726                 goto err_init_reset;
2727         hw->reset.ops = &hns3vf_reset_ops;
2728
2729         ret = hns3vf_init_vf(eth_dev);
2730         if (ret) {
2731                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2732                 goto err_init_vf;
2733         }
2734
2735         /* Allocate memory for storing MAC addresses */
2736         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2737                                                sizeof(struct rte_ether_addr) *
2738                                                HNS3_VF_UC_MACADDR_NUM, 0);
2739         if (eth_dev->data->mac_addrs == NULL) {
2740                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2741                              "to store MAC addresses",
2742                              sizeof(struct rte_ether_addr) *
2743                              HNS3_VF_UC_MACADDR_NUM);
2744                 ret = -ENOMEM;
2745                 goto err_rte_zmalloc;
2746         }
2747
2748         /*
2749          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2750          * on the host by "ip link set ..." command. To avoid some incorrect
2751          * scenes, for example, hns3 VF PMD driver fails to receive and send
2752          * packets after user configure the MAC address by using the
2753          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2754          * address strategy as the hns3 kernel ethdev driver in the
2755          * initialization. If user configure a MAC address by the ip command
2756          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2757          * start with a random MAC address in the initialization.
2758          */
2759         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2760                 rte_eth_random_addr(hw->mac.mac_addr);
2761         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2762                             &eth_dev->data->mac_addrs[0]);
2763
2764         hw->adapter_state = HNS3_NIC_INITIALIZED;
2765
2766         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2767                 hns3_err(hw, "Reschedule reset service after dev_init");
2768                 hns3_schedule_reset(hns);
2769         } else {
2770                 /* IMP will wait ready flag before reset */
2771                 hns3_notify_reset_ready(hw, false);
2772         }
2773         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2774                           eth_dev);
2775         return 0;
2776
2777 err_rte_zmalloc:
2778         hns3vf_uninit_vf(eth_dev);
2779
2780 err_init_vf:
2781         rte_free(hw->reset.wait_data);
2782
2783 err_init_reset:
2784         hns3_mp_uninit_primary();
2785
2786 err_mp_init_primary:
2787 err_mp_init_secondary:
2788         eth_dev->dev_ops = NULL;
2789         eth_dev->rx_pkt_burst = NULL;
2790         eth_dev->tx_pkt_burst = NULL;
2791         eth_dev->tx_pkt_prepare = NULL;
2792         rte_free(eth_dev->process_private);
2793         eth_dev->process_private = NULL;
2794
2795         return ret;
2796 }
2797
2798 static int
2799 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2800 {
2801         struct hns3_adapter *hns = eth_dev->data->dev_private;
2802         struct hns3_hw *hw = &hns->hw;
2803
2804         PMD_INIT_FUNC_TRACE();
2805
2806         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2807                 return -EPERM;
2808
2809         eth_dev->dev_ops = NULL;
2810         eth_dev->rx_pkt_burst = NULL;
2811         eth_dev->tx_pkt_burst = NULL;
2812         eth_dev->tx_pkt_prepare = NULL;
2813
2814         if (hw->adapter_state < HNS3_NIC_CLOSING)
2815                 hns3vf_dev_close(eth_dev);
2816
2817         hw->adapter_state = HNS3_NIC_REMOVED;
2818         return 0;
2819 }
2820
2821 static int
2822 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2823                      struct rte_pci_device *pci_dev)
2824 {
2825         return rte_eth_dev_pci_generic_probe(pci_dev,
2826                                              sizeof(struct hns3_adapter),
2827                                              hns3vf_dev_init);
2828 }
2829
2830 static int
2831 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2832 {
2833         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2834 }
2835
2836 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2837         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2838         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2839         { .vendor_id = 0, /* sentinel */ },
2840 };
2841
2842 static struct rte_pci_driver rte_hns3vf_pmd = {
2843         .id_table = pci_id_hns3vf_map,
2844         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2845         .probe = eth_hns3vf_pci_probe,
2846         .remove = eth_hns3vf_pci_remove,
2847 };
2848
2849 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2850 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2851 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");