drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint8_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid. Because of the hardware
 708          * constraints in hns3 hardware engine, we have to implement clearing
 709          * the mapping relationship configurations by binding all queues to the
 710          * last interrupt vector and reserving the last interrupt vector. This
 711          * method results in a decrease of the maximum queues when upper
 712          * applications call the rte_eth_dev_configure API function to enable
 713          * Rx interrupt.
 714          */
 715         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 716         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
 717         for (i = 0; i < hw->intr_tqps_num; i++) {
 718                 /*
 719                  * Set gap limiter and rate limiter configuration of queue's
 720                  * interrupt.
 721                  */
 722                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 723                                        HNS3_TQP_INTR_GL_DEFAULT);
 724                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 725                                        HNS3_TQP_INTR_GL_DEFAULT);
 726                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 727
 728                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 729                                                    HNS3_RING_TYPE_TX, i);
 730                 if (ret) {
 731                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 732                                           "vector: %d, ret=%d", i, vec, ret);
 733                         return ret;
 734                 }
 735
 736                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 737                                                    HNS3_RING_TYPE_RX, i);
 738                 if (ret) {
 739                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 740                                           "vector: %d, ret=%d", i, vec, ret);
 741                         return ret;
 742                 }
 743         }
 744
 745         return 0;
 746 }
 747
 748 static int
 749 hns3vf_dev_configure(struct rte_eth_dev *dev)
 750 {
 751         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 752         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 753         struct rte_eth_conf *conf = &dev->data->dev_conf;
 754         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 755         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 756         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 757         struct rte_eth_rss_conf rss_conf;
 758         uint16_t mtu;
 759         int ret;
 760
 761         /*
 762          * Hardware does not support individually enable/disable/reset the Tx or
 763          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 764          * and Rx queues at the same time. When the numbers of Tx queues
 765          * allocated by upper applications are not equal to the numbers of Rx
 766          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 767          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 768          * these fake queues are imperceptible, and can not be used by upper
 769          * applications.
 770          */
 771         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 772         if (ret) {
 773                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 774                 return ret;
 775         }
 776
 777         hw->adapter_state = HNS3_NIC_CONFIGURING;
 778         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 779                 hns3_err(hw, "setting link speed/duplex not supported");
 780                 ret = -EINVAL;
 781                 goto cfg_err;
 782         }
 783
 784         /* When RSS is not configured, redirect the packet queue 0 */
 785         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 786                 rss_conf = conf->rx_adv_conf.rss_conf;
 787                 if (rss_conf.rss_key == NULL) {
 788                         rss_conf.rss_key = rss_cfg->key;
 789                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 790                 }
 791
 792                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 793                 if (ret)
 794                         goto cfg_err;
 795         }
 796
 797         /*
 798          * If jumbo frames are enabled, MTU needs to be refreshed
 799          * according to the maximum RX packet length.
 800          */
 801         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 802                 /*
 803                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 804                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 805                  * can safely assign to "uint16_t" type variable.
 806                  */
 807                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 808                 ret = hns3vf_dev_mtu_set(dev, mtu);
 809                 if (ret)
 810                         goto cfg_err;
 811                 dev->data->mtu = mtu;
 812         }
 813
 814         ret = hns3vf_dev_configure_vlan(dev);
 815         if (ret)
 816                 goto cfg_err;
 817
 818         hw->adapter_state = HNS3_NIC_CONFIGURED;
 819         return 0;
 820
 821 cfg_err:
 822         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 823         hw->adapter_state = HNS3_NIC_INITIALIZED;
 824
 825         return ret;
 826 }
 827
 828 static int
 829 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 830 {
 831         int ret;
 832
 833         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 834                                 sizeof(mtu), true, NULL, 0);
 835         if (ret)
 836                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 837
 838         return ret;
 839 }
 840
 841 static int
 842 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 843 {
 844         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 845         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 846         int ret;
 847
 848         /*
 849          * The hns3 PF/VF devices on the same port share the hardware MTU
 850          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 851          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 852          * driver, there is no need to stop the port for hns3 VF device, and the
 853          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 854          * PF's MTU.
 855          */
 856         if (rte_atomic16_read(&hw->reset.resetting)) {
 857                 hns3_err(hw, "Failed to set mtu during resetting");
 858                 return -EIO;
 859         }
 860
 861         rte_spinlock_lock(&hw->lock);
 862         ret = hns3vf_config_mtu(hw, mtu);
 863         if (ret) {
 864                 rte_spinlock_unlock(&hw->lock);
 865                 return ret;
 866         }
 867         if (frame_size > RTE_ETHER_MAX_LEN)
 868                 dev->data->dev_conf.rxmode.offloads |=
 869                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 870         else
 871                 dev->data->dev_conf.rxmode.offloads &=
 872                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 873         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 874         rte_spinlock_unlock(&hw->lock);
 875
 876         return 0;
 877 }
 878
 879 static int
 880 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 881 {
 882         struct hns3_adapter *hns = eth_dev->data->dev_private;
 883         struct hns3_hw *hw = &hns->hw;
 884         uint16_t q_num = hw->tqps_num;
 885
 886         /*
 887          * In interrupt mode, 'max_rx_queues' is set based on the number of
 888          * MSI-X interrupt resources of the hardware.
 889          */
 890         if (hw->data->dev_conf.intr_conf.rxq == 1)
 891                 q_num = hw->intr_tqps_num;
 892
 893         info->max_rx_queues = q_num;
 894         info->max_tx_queues = hw->tqps_num;
 895         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 896         info->min_rx_bufsize = hw->rx_buf_len;
 897         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 898         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 899
 900         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 901                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 902                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 903                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 904                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 905                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 906                                  DEV_RX_OFFLOAD_KEEP_CRC |
 907                                  DEV_RX_OFFLOAD_SCATTER |
 908                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 909                                  DEV_RX_OFFLOAD_QINQ_STRIP |
 910                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 911                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
 912         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 913         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 914                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 915                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 916                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 917                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 918                                  DEV_TX_OFFLOAD_VLAN_INSERT |
 919                                  DEV_TX_OFFLOAD_QINQ_INSERT |
 920                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 921                                  DEV_TX_OFFLOAD_TCP_TSO |
 922                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 923                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 924                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 925                                  info->tx_queue_offload_capa);
 926
 927         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 928                 .nb_max = HNS3_MAX_RING_DESC,
 929                 .nb_min = HNS3_MIN_RING_DESC,
 930                 .nb_align = HNS3_ALIGN_RING_DESC,
 931         };
 932
 933         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 934                 .nb_max = HNS3_MAX_RING_DESC,
 935                 .nb_min = HNS3_MIN_RING_DESC,
 936                 .nb_align = HNS3_ALIGN_RING_DESC,
 937         };
 938
 939         info->vmdq_queue_num = 0;
 940
 941         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 942         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 943         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 944         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 945         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 946
 947         return 0;
 948 }
 949
 950 static void
 951 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 952 {
 953         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 954 }
 955
 956 static void
 957 hns3vf_disable_irq0(struct hns3_hw *hw)
 958 {
 959         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 960 }
 961
 962 static void
 963 hns3vf_enable_irq0(struct hns3_hw *hw)
 964 {
 965         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 966 }
 967
 968 static enum hns3vf_evt_cause
 969 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 970 {
 971         struct hns3_hw *hw = &hns->hw;
 972         enum hns3vf_evt_cause ret;
 973         uint32_t cmdq_stat_reg;
 974         uint32_t rst_ing_reg;
 975         uint32_t val;
 976
 977         /* Fetch the events from their corresponding regs */
 978         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 979
 980         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 981                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 982                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 983                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 984                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 985                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 986                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 987                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 988                 if (clearval) {
 989                         hw->reset.stats.global_cnt++;
 990                         hns3_warn(hw, "Global reset detected, clear reset status");
 991                 } else {
 992                         hns3_schedule_delayed_reset(hns);
 993                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 994                 }
 995
 996                 ret = HNS3VF_VECTOR0_EVENT_RST;
 997                 goto out;
 998         }
 999
1000         /* Check for vector0 mailbox(=CMDQ RX) event source */
1001         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1002                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1003                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1004                 goto out;
1005         }
1006
1007         val = 0;
1008         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1009 out:
1010         if (clearval)
1011                 *clearval = val;
1012         return ret;
1013 }
1014
1015 static void
1016 hns3vf_interrupt_handler(void *param)
1017 {
1018         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1019         struct hns3_adapter *hns = dev->data->dev_private;
1020         struct hns3_hw *hw = &hns->hw;
1021         enum hns3vf_evt_cause event_cause;
1022         uint32_t clearval;
1023
1024         if (hw->irq_thread_id == 0)
1025                 hw->irq_thread_id = pthread_self();
1026
1027         /* Disable interrupt */
1028         hns3vf_disable_irq0(hw);
1029
1030         /* Read out interrupt causes */
1031         event_cause = hns3vf_check_event_cause(hns, &clearval);
1032
1033         switch (event_cause) {
1034         case HNS3VF_VECTOR0_EVENT_RST:
1035                 hns3_schedule_reset(hns);
1036                 break;
1037         case HNS3VF_VECTOR0_EVENT_MBX:
1038                 hns3_dev_handle_mbx_msg(hw);
1039                 break;
1040         default:
1041                 break;
1042         }
1043
1044         /* Clear interrupt causes */
1045         hns3vf_clear_event_cause(hw, clearval);
1046
1047         /* Enable interrupt */
1048         hns3vf_enable_irq0(hw);
1049 }
1050
1051 static int
1052 hns3vf_check_tqp_info(struct hns3_hw *hw)
1053 {
1054         uint16_t tqps_num;
1055
1056         tqps_num = hw->tqps_num;
1057         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1058                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1059                                   "range: 1~%d",
1060                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1061                 return -EINVAL;
1062         }
1063
1064         if (hw->rx_buf_len == 0)
1065                 hw->rx_buf_len = HNS3_DEFAULT_RX_BUF_LEN;
1066         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1067
1068         return 0;
1069 }
1070
1071 static int
1072 hns3vf_get_queue_info(struct hns3_hw *hw)
1073 {
1074 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1075         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1076         int ret;
1077
1078         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1079                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1080         if (ret) {
1081                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1082                 return ret;
1083         }
1084
1085         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1086         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1087         memcpy(&hw->rx_buf_len, &resp_msg[4], sizeof(uint16_t));
1088
1089         return hns3vf_check_tqp_info(hw);
1090 }
1091
1092 static int
1093 hns3vf_get_queue_depth(struct hns3_hw *hw)
1094 {
1095 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1096         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1097         int ret;
1098
1099         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1100                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1101         if (ret) {
1102                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1103                              ret);
1104                 return ret;
1105         }
1106
1107         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1108         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1109
1110         return 0;
1111 }
1112
1113 static int
1114 hns3vf_get_tc_info(struct hns3_hw *hw)
1115 {
1116         uint8_t resp_msg;
1117         int ret;
1118
1119         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1120                                 true, &resp_msg, sizeof(resp_msg));
1121         if (ret) {
1122                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1123                          ret);
1124                 return ret;
1125         }
1126
1127         hw->hw_tc_map = resp_msg;
1128
1129         return 0;
1130 }
1131
1132 static int
1133 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1134 {
1135         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1136         int ret;
1137
1138         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1139                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1140         if (ret) {
1141                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1142                 return ret;
1143         }
1144
1145         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1146
1147         return 0;
1148 }
1149
1150 static int
1151 hns3vf_get_configuration(struct hns3_hw *hw)
1152 {
1153         int ret;
1154
1155         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1156         hw->rss_dis_flag = false;
1157
1158         /* Get queue configuration from PF */
1159         ret = hns3vf_get_queue_info(hw);
1160         if (ret)
1161                 return ret;
1162
1163         /* Get queue depth info from PF */
1164         ret = hns3vf_get_queue_depth(hw);
1165         if (ret)
1166                 return ret;
1167
1168         /* Get user defined VF MAC addr from PF */
1169         ret = hns3vf_get_host_mac_addr(hw);
1170         if (ret)
1171                 return ret;
1172
1173         /* Get tc configuration from PF */
1174         return hns3vf_get_tc_info(hw);
1175 }
1176
1177 static int
1178 hns3vf_set_tc_info(struct hns3_adapter *hns)
1179 {
1180         struct hns3_hw *hw = &hns->hw;
1181         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1182         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1183         uint8_t i;
1184
1185         hw->num_tc = 0;
1186         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1187                 if (hw->hw_tc_map & BIT(i))
1188                         hw->num_tc++;
1189
1190         if (nb_rx_q < hw->num_tc) {
1191                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1192                          nb_rx_q, hw->num_tc);
1193                 return -EINVAL;
1194         }
1195
1196         if (nb_tx_q < hw->num_tc) {
1197                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1198                          nb_tx_q, hw->num_tc);
1199                 return -EINVAL;
1200         }
1201
1202         hns3_set_rss_size(hw, nb_rx_q);
1203         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1204
1205         return 0;
1206 }
1207
1208 static void
1209 hns3vf_request_link_info(struct hns3_hw *hw)
1210 {
1211         uint8_t resp_msg;
1212         int ret;
1213
1214         if (rte_atomic16_read(&hw->reset.resetting))
1215                 return;
1216         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1217                                 &resp_msg, sizeof(resp_msg));
1218         if (ret)
1219                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1220 }
1221
1222 static int
1223 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1224 {
1225 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1226         struct hns3_hw *hw = &hns->hw;
1227         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1228         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1229         uint8_t is_kill = on ? 0 : 1;
1230
1231         msg_data[0] = is_kill;
1232         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1233         memcpy(&msg_data[3], &proto, sizeof(proto));
1234
1235         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1236                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1237                                  0);
1238 }
1239
1240 static int
1241 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1242 {
1243         struct hns3_adapter *hns = dev->data->dev_private;
1244         struct hns3_hw *hw = &hns->hw;
1245         int ret;
1246
1247         if (rte_atomic16_read(&hw->reset.resetting)) {
1248                 hns3_err(hw,
1249                          "vf set vlan id failed during resetting, vlan_id =%u",
1250                          vlan_id);
1251                 return -EIO;
1252         }
1253         rte_spinlock_lock(&hw->lock);
1254         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1255         rte_spinlock_unlock(&hw->lock);
1256         if (ret)
1257                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1258                          vlan_id, ret);
1259
1260         return ret;
1261 }
1262
1263 static int
1264 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1265 {
1266         uint8_t msg_data;
1267         int ret;
1268
1269         msg_data = enable ? 1 : 0;
1270         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1271                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1272         if (ret)
1273                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1274
1275         return ret;
1276 }
1277
1278 static int
1279 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1280 {
1281         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1282         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1283         unsigned int tmp_mask;
1284         int ret = 0;
1285
1286         if (rte_atomic16_read(&hw->reset.resetting)) {
1287                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1288                              "mask = 0x%x", mask);
1289                 return -EIO;
1290         }
1291
1292         tmp_mask = (unsigned int)mask;
1293         /* Vlan stripping setting */
1294         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1295                 rte_spinlock_lock(&hw->lock);
1296                 /* Enable or disable VLAN stripping */
1297                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1298                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1299                 else
1300                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1301                 rte_spinlock_unlock(&hw->lock);
1302         }
1303
1304         return ret;
1305 }
1306
1307 static int
1308 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1309 {
1310         struct rte_vlan_filter_conf *vfc;
1311         struct hns3_hw *hw = &hns->hw;
1312         uint16_t vlan_id;
1313         uint64_t vbit;
1314         uint64_t ids;
1315         int ret = 0;
1316         uint32_t i;
1317
1318         vfc = &hw->data->vlan_filter_conf;
1319         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1320                 if (vfc->ids[i] == 0)
1321                         continue;
1322                 ids = vfc->ids[i];
1323                 while (ids) {
1324                         /*
1325                          * 64 means the num bits of ids, one bit corresponds to
1326                          * one vlan id
1327                          */
1328                         vlan_id = 64 * i;
1329                         /* count trailing zeroes */
1330                         vbit = ~ids & (ids - 1);
1331                         /* clear least significant bit set */
1332                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1333                         for (; vbit;) {
1334                                 vbit >>= 1;
1335                                 vlan_id++;
1336                         }
1337                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1338                         if (ret) {
1339                                 hns3_err(hw,
1340                                          "VF handle vlan table failed, ret =%d, on = %d",
1341                                          ret, on);
1342                                 return ret;
1343                         }
1344                 }
1345         }
1346
1347         return ret;
1348 }
1349
1350 static int
1351 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1352 {
1353         return hns3vf_handle_all_vlan_table(hns, 0);
1354 }
1355
1356 static int
1357 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1358 {
1359         struct hns3_hw *hw = &hns->hw;
1360         struct rte_eth_conf *dev_conf;
1361         bool en;
1362         int ret;
1363
1364         dev_conf = &hw->data->dev_conf;
1365         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1366                                                                    : false;
1367         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1368         if (ret)
1369                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1370                          ret);
1371         return ret;
1372 }
1373
1374 static int
1375 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1376 {
1377         struct hns3_adapter *hns = dev->data->dev_private;
1378         struct rte_eth_dev_data *data = dev->data;
1379         struct hns3_hw *hw = &hns->hw;
1380         int ret;
1381
1382         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1383             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1384             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1385                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1386                               "or hw_vlan_insert_pvid is not support!");
1387         }
1388
1389         /* Apply vlan offload setting */
1390         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1391         if (ret)
1392                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1393
1394         return ret;
1395 }
1396
1397 static int
1398 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1399 {
1400         uint8_t msg_data;
1401
1402         msg_data = alive ? 1 : 0;
1403         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1404                                  sizeof(msg_data), false, NULL, 0);
1405 }
1406
1407 static void
1408 hns3vf_keep_alive_handler(void *param)
1409 {
1410         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1411         struct hns3_adapter *hns = eth_dev->data->dev_private;
1412         struct hns3_hw *hw = &hns->hw;
1413         uint8_t respmsg;
1414         int ret;
1415
1416         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1417                                 false, &respmsg, sizeof(uint8_t));
1418         if (ret)
1419                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1420                          ret);
1421
1422         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1423                           eth_dev);
1424 }
1425
1426 static void
1427 hns3vf_service_handler(void *param)
1428 {
1429         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1430         struct hns3_adapter *hns = eth_dev->data->dev_private;
1431         struct hns3_hw *hw = &hns->hw;
1432
1433         /*
1434          * The query link status and reset processing are executed in the
1435          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1436          * and the query operation will time out after 30ms. In the case of
1437          * multiple PF/VFs, each query failure timeout causes the IMP reset
1438          * interrupt to fail to respond within 100ms.
1439          * Before querying the link status, check whether there is a reset
1440          * pending, and if so, abandon the query.
1441          */
1442         if (!hns3vf_is_reset_pending(hns))
1443                 hns3vf_request_link_info(hw);
1444         else
1445                 hns3_warn(hw, "Cancel the query when reset is pending");
1446
1447         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1448                           eth_dev);
1449 }
1450
1451 static int
1452 hns3_query_vf_resource(struct hns3_hw *hw)
1453 {
1454         struct hns3_vf_res_cmd *req;
1455         struct hns3_cmd_desc desc;
1456         uint16_t num_msi;
1457         int ret;
1458
1459         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1460         ret = hns3_cmd_send(hw, &desc, 1);
1461         if (ret) {
1462                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1463                 return ret;
1464         }
1465
1466         req = (struct hns3_vf_res_cmd *)desc.data;
1467         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1468                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
1469         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1470                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1471                          num_msi, HNS3_MIN_VECTOR_NUM);
1472                 return -EINVAL;
1473         }
1474
1475         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
1476
1477         return 0;
1478 }
1479
1480 static int
1481 hns3vf_init_hardware(struct hns3_adapter *hns)
1482 {
1483         struct hns3_hw *hw = &hns->hw;
1484         uint16_t mtu = hw->data->mtu;
1485         int ret;
1486
1487         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1488         if (ret)
1489                 return ret;
1490
1491         ret = hns3vf_config_mtu(hw, mtu);
1492         if (ret)
1493                 goto err_init_hardware;
1494
1495         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1496         if (ret) {
1497                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1498                 goto err_init_hardware;
1499         }
1500
1501         ret = hns3_config_gro(hw, false);
1502         if (ret) {
1503                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1504                 goto err_init_hardware;
1505         }
1506
1507         ret = hns3vf_set_alive(hw, true);
1508         if (ret) {
1509                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1510                 goto err_init_hardware;
1511         }
1512
1513         hns3vf_request_link_info(hw);
1514         return 0;
1515
1516 err_init_hardware:
1517         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1518         return ret;
1519 }
1520
1521 static int
1522 hns3vf_clear_vport_list(struct hns3_hw *hw)
1523 {
1524         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1525                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1526                                  NULL, 0);
1527 }
1528
1529 static int
1530 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1531 {
1532         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1533         struct hns3_adapter *hns = eth_dev->data->dev_private;
1534         struct hns3_hw *hw = &hns->hw;
1535         int ret;
1536
1537         PMD_INIT_FUNC_TRACE();
1538
1539         /* Get hardware io base address from pcie BAR2 IO space */
1540         hw->io_base = pci_dev->mem_resource[2].addr;
1541
1542         /* Firmware command queue initialize */
1543         ret = hns3_cmd_init_queue(hw);
1544         if (ret) {
1545                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1546                 goto err_cmd_init_queue;
1547         }
1548
1549         /* Firmware command initialize */
1550         ret = hns3_cmd_init(hw);
1551         if (ret) {
1552                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1553                 goto err_cmd_init;
1554         }
1555
1556         /* Get VF resource */
1557         ret = hns3_query_vf_resource(hw);
1558         if (ret)
1559                 goto err_cmd_init;
1560
1561         rte_spinlock_init(&hw->mbx_resp.lock);
1562
1563         hns3vf_clear_event_cause(hw, 0);
1564
1565         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1566                                          hns3vf_interrupt_handler, eth_dev);
1567         if (ret) {
1568                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1569                 goto err_intr_callback_register;
1570         }
1571
1572         /* Enable interrupt */
1573         rte_intr_enable(&pci_dev->intr_handle);
1574         hns3vf_enable_irq0(hw);
1575
1576         /* Get configuration from PF */
1577         ret = hns3vf_get_configuration(hw);
1578         if (ret) {
1579                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1580                 goto err_get_config;
1581         }
1582
1583         /*
1584          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1585          * on the host by "ip link set ..." command. To avoid some incorrect
1586          * scenes, for example, hns3 VF PMD driver fails to receive and send
1587          * packets after user configure the MAC address by using the
1588          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
1589          * address strategy as the hns3 kernel ethdev driver in the
1590          * initialization. If user configure a MAC address by the ip command
1591          * for VF device, then hns3 VF PMD driver will start with it, otherwise
1592          * start with a random MAC address in the initialization.
1593          */
1594         ret = rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr);
1595         if (ret)
1596                 rte_eth_random_addr(hw->mac.mac_addr);
1597
1598         ret = hns3vf_clear_vport_list(hw);
1599         if (ret) {
1600                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1601                 goto err_get_config;
1602         }
1603
1604         ret = hns3vf_init_hardware(hns);
1605         if (ret)
1606                 goto err_get_config;
1607
1608         hns3_set_default_rss_args(hw);
1609
1610         /*
1611          * In the initialization clearing the all hardware mapping relationship
1612          * configurations between queues and interrupt vectors is needed, so
1613          * some error caused by the residual configurations, such as the
1614          * unexpected interrupt, can be avoid.
1615          */
1616         ret = hns3vf_init_ring_with_vector(hw);
1617         if (ret)
1618                 goto err_get_config;
1619
1620         return 0;
1621
1622 err_get_config:
1623         hns3vf_disable_irq0(hw);
1624         rte_intr_disable(&pci_dev->intr_handle);
1625         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1626                              eth_dev);
1627 err_intr_callback_register:
1628 err_cmd_init:
1629         hns3_cmd_uninit(hw);
1630         hns3_cmd_destroy_queue(hw);
1631 err_cmd_init_queue:
1632         hw->io_base = NULL;
1633
1634         return ret;
1635 }
1636
1637 static void
1638 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1639 {
1640         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1641         struct hns3_adapter *hns = eth_dev->data->dev_private;
1642         struct hns3_hw *hw = &hns->hw;
1643
1644         PMD_INIT_FUNC_TRACE();
1645
1646         hns3_rss_uninit(hns);
1647         (void)hns3vf_set_alive(hw, false);
1648         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1649         hns3vf_disable_irq0(hw);
1650         rte_intr_disable(&pci_dev->intr_handle);
1651         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1652                              eth_dev);
1653         hns3_cmd_uninit(hw);
1654         hns3_cmd_destroy_queue(hw);
1655         hw->io_base = NULL;
1656 }
1657
1658 static int
1659 hns3vf_do_stop(struct hns3_adapter *hns)
1660 {
1661         struct hns3_hw *hw = &hns->hw;
1662         bool reset_queue;
1663
1664         hw->mac.link_status = ETH_LINK_DOWN;
1665
1666         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1667                 hns3vf_configure_mac_addr(hns, true);
1668                 reset_queue = true;
1669         } else
1670                 reset_queue = false;
1671         return hns3_stop_queues(hns, reset_queue);
1672 }
1673
1674 static void
1675 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1676 {
1677         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1678         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1679         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1680         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1681         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1682         uint16_t q_id;
1683
1684         if (dev->data->dev_conf.intr_conf.rxq == 0)
1685                 return;
1686
1687         /* unmap the ring with vector */
1688         if (rte_intr_allow_others(intr_handle)) {
1689                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1690                 base = RTE_INTR_VEC_RXTX_OFFSET;
1691         }
1692         if (rte_intr_dp_is_en(intr_handle)) {
1693                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1694                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1695                                                            HNS3_RING_TYPE_RX,
1696                                                            q_id);
1697                         if (vec < base + intr_handle->nb_efd - 1)
1698                                 vec++;
1699                 }
1700         }
1701         /* Clean datapath event and queue/vec mapping */
1702         rte_intr_efd_disable(intr_handle);
1703         if (intr_handle->intr_vec) {
1704                 rte_free(intr_handle->intr_vec);
1705                 intr_handle->intr_vec = NULL;
1706         }
1707 }
1708
1709 static void
1710 hns3vf_dev_stop(struct rte_eth_dev *dev)
1711 {
1712         struct hns3_adapter *hns = dev->data->dev_private;
1713         struct hns3_hw *hw = &hns->hw;
1714
1715         PMD_INIT_FUNC_TRACE();
1716
1717         hw->adapter_state = HNS3_NIC_STOPPING;
1718         hns3_set_rxtx_function(dev);
1719         rte_wmb();
1720         /* Disable datapath on secondary process. */
1721         hns3_mp_req_stop_rxtx(dev);
1722         /* Prevent crashes when queues are still in use. */
1723         rte_delay_ms(hw->tqps_num);
1724
1725         rte_spinlock_lock(&hw->lock);
1726         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1727                 hns3vf_do_stop(hns);
1728                 hns3_dev_release_mbufs(hns);
1729                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1730         }
1731         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1732         rte_spinlock_unlock(&hw->lock);
1733
1734         hns3vf_unmap_rx_interrupt(dev);
1735 }
1736
1737 static void
1738 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1739 {
1740         struct hns3_adapter *hns = eth_dev->data->dev_private;
1741         struct hns3_hw *hw = &hns->hw;
1742
1743         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1744                 return;
1745
1746         if (hw->adapter_state == HNS3_NIC_STARTED)
1747                 hns3vf_dev_stop(eth_dev);
1748
1749         hw->adapter_state = HNS3_NIC_CLOSING;
1750         hns3_reset_abort(hns);
1751         hw->adapter_state = HNS3_NIC_CLOSED;
1752         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1753         hns3vf_configure_all_mc_mac_addr(hns, true);
1754         hns3vf_remove_all_vlan_table(hns);
1755         hns3vf_uninit_vf(eth_dev);
1756         hns3_free_all_queues(eth_dev);
1757         rte_free(hw->reset.wait_data);
1758         rte_free(eth_dev->process_private);
1759         eth_dev->process_private = NULL;
1760         hns3_mp_uninit_primary();
1761         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1762 }
1763
1764 static int
1765 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1766                        __rte_unused int wait_to_complete)
1767 {
1768         struct hns3_adapter *hns = eth_dev->data->dev_private;
1769         struct hns3_hw *hw = &hns->hw;
1770         struct hns3_mac *mac = &hw->mac;
1771         struct rte_eth_link new_link;
1772
1773         memset(&new_link, 0, sizeof(new_link));
1774         switch (mac->link_speed) {
1775         case ETH_SPEED_NUM_10M:
1776         case ETH_SPEED_NUM_100M:
1777         case ETH_SPEED_NUM_1G:
1778         case ETH_SPEED_NUM_10G:
1779         case ETH_SPEED_NUM_25G:
1780         case ETH_SPEED_NUM_40G:
1781         case ETH_SPEED_NUM_50G:
1782         case ETH_SPEED_NUM_100G:
1783                 new_link.link_speed = mac->link_speed;
1784                 break;
1785         default:
1786                 new_link.link_speed = ETH_SPEED_NUM_100M;
1787                 break;
1788         }
1789
1790         new_link.link_duplex = mac->link_duplex;
1791         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1792         new_link.link_autoneg =
1793             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1794
1795         return rte_eth_linkstatus_set(eth_dev, &new_link);
1796 }
1797
1798 static int
1799 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1800 {
1801         struct hns3_hw *hw = &hns->hw;
1802         int ret;
1803
1804         ret = hns3vf_set_tc_info(hns);
1805         if (ret)
1806                 return ret;
1807
1808         ret = hns3_start_queues(hns, reset_queue);
1809         if (ret)
1810                 hns3_err(hw, "Failed to start queues: %d", ret);
1811
1812         return ret;
1813 }
1814
1815 static int
1816 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1817 {
1818         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1819         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1820         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1821         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1822         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1823         uint32_t intr_vector;
1824         uint16_t q_id;
1825         int ret;
1826
1827         if (dev->data->dev_conf.intr_conf.rxq == 0)
1828                 return 0;
1829
1830         /* disable uio/vfio intr/eventfd mapping */
1831         rte_intr_disable(intr_handle);
1832
1833         /* check and configure queue intr-vector mapping */
1834         if (rte_intr_cap_multiple(intr_handle) ||
1835             !RTE_ETH_DEV_SRIOV(dev).active) {
1836                 intr_vector = hw->used_rx_queues;
1837                 /* It creates event fd for each intr vector when MSIX is used */
1838                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1839                         return -EINVAL;
1840         }
1841         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1842                 intr_handle->intr_vec =
1843                         rte_zmalloc("intr_vec",
1844                                     hw->used_rx_queues * sizeof(int), 0);
1845                 if (intr_handle->intr_vec == NULL) {
1846                         hns3_err(hw, "Failed to allocate %d rx_queues"
1847                                      " intr_vec", hw->used_rx_queues);
1848                         ret = -ENOMEM;
1849                         goto vf_alloc_intr_vec_error;
1850                 }
1851         }
1852
1853         if (rte_intr_allow_others(intr_handle)) {
1854                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1855                 base = RTE_INTR_VEC_RXTX_OFFSET;
1856         }
1857         if (rte_intr_dp_is_en(intr_handle)) {
1858                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1859                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
1860                                                            HNS3_RING_TYPE_RX,
1861                                                            q_id);
1862                         if (ret)
1863                                 goto vf_bind_vector_error;
1864                         intr_handle->intr_vec[q_id] = vec;
1865                         if (vec < base + intr_handle->nb_efd - 1)
1866                                 vec++;
1867                 }
1868         }
1869         rte_intr_enable(intr_handle);
1870         return 0;
1871
1872 vf_bind_vector_error:
1873         rte_intr_efd_disable(intr_handle);
1874         if (intr_handle->intr_vec) {
1875                 free(intr_handle->intr_vec);
1876                 intr_handle->intr_vec = NULL;
1877         }
1878         return ret;
1879 vf_alloc_intr_vec_error:
1880         rte_intr_efd_disable(intr_handle);
1881         return ret;
1882 }
1883
1884 static void
1885 hns3vf_restore_filter(struct rte_eth_dev *dev)
1886 {
1887         hns3_restore_rss_filter(dev);
1888 }
1889
1890 static int
1891 hns3vf_dev_start(struct rte_eth_dev *dev)
1892 {
1893         struct hns3_adapter *hns = dev->data->dev_private;
1894         struct hns3_hw *hw = &hns->hw;
1895         int ret;
1896
1897         PMD_INIT_FUNC_TRACE();
1898         if (rte_atomic16_read(&hw->reset.resetting))
1899                 return -EBUSY;
1900
1901         rte_spinlock_lock(&hw->lock);
1902         hw->adapter_state = HNS3_NIC_STARTING;
1903         ret = hns3vf_do_start(hns, true);
1904         if (ret) {
1905                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1906                 rte_spinlock_unlock(&hw->lock);
1907                 return ret;
1908         }
1909         hw->adapter_state = HNS3_NIC_STARTED;
1910         rte_spinlock_unlock(&hw->lock);
1911
1912         ret = hns3vf_map_rx_interrupt(dev);
1913         if (ret)
1914                 return ret;
1915         hns3_set_rxtx_function(dev);
1916         hns3_mp_req_start_rxtx(dev);
1917         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
1918
1919         hns3vf_restore_filter(dev);
1920
1921         return ret;
1922 }
1923
1924 static bool
1925 is_vf_reset_done(struct hns3_hw *hw)
1926 {
1927 #define HNS3_FUN_RST_ING_BITS \
1928         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
1929          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
1930          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
1931          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
1932
1933         uint32_t val;
1934
1935         if (hw->reset.level == HNS3_VF_RESET) {
1936                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1937                 if (val & HNS3_VF_RST_ING_BIT)
1938                         return false;
1939         } else {
1940                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1941                 if (val & HNS3_FUN_RST_ING_BITS)
1942                         return false;
1943         }
1944         return true;
1945 }
1946
1947 bool
1948 hns3vf_is_reset_pending(struct hns3_adapter *hns)
1949 {
1950         struct hns3_hw *hw = &hns->hw;
1951         enum hns3_reset_level reset;
1952
1953         hns3vf_check_event_cause(hns, NULL);
1954         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
1955         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
1956                 hns3_warn(hw, "High level reset %d is pending", reset);
1957                 return true;
1958         }
1959         return false;
1960 }
1961
1962 static int
1963 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
1964 {
1965         struct hns3_hw *hw = &hns->hw;
1966         struct hns3_wait_data *wait_data = hw->reset.wait_data;
1967         struct timeval tv;
1968
1969         if (wait_data->result == HNS3_WAIT_SUCCESS) {
1970                 /*
1971                  * After vf reset is ready, the PF may not have completed
1972                  * the reset processing. The vf sending mbox to PF may fail
1973                  * during the pf reset, so it is better to add extra delay.
1974                  */
1975                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
1976                     hw->reset.level == HNS3_FLR_RESET)
1977                         return 0;
1978                 /* Reset retry process, no need to add extra delay. */
1979                 if (hw->reset.attempts)
1980                         return 0;
1981                 if (wait_data->check_completion == NULL)
1982                         return 0;
1983
1984                 wait_data->check_completion = NULL;
1985                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
1986                 wait_data->count = 1;
1987                 wait_data->result = HNS3_WAIT_REQUEST;
1988                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
1989                                   wait_data);
1990                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
1991                 return -EAGAIN;
1992         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
1993                 gettimeofday(&tv, NULL);
1994                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
1995                           tv.tv_sec, tv.tv_usec);
1996                 return -ETIME;
1997         } else if (wait_data->result == HNS3_WAIT_REQUEST)
1998                 return -EAGAIN;
1999
2000         wait_data->hns = hns;
2001         wait_data->check_completion = is_vf_reset_done;
2002         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2003                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2004         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2005         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2006         wait_data->result = HNS3_WAIT_REQUEST;
2007         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2008         return -EAGAIN;
2009 }
2010
2011 static int
2012 hns3vf_prepare_reset(struct hns3_adapter *hns)
2013 {
2014         struct hns3_hw *hw = &hns->hw;
2015         int ret = 0;
2016
2017         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2018                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2019                                         0, true, NULL, 0);
2020         }
2021         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2022
2023         return ret;
2024 }
2025
2026 static int
2027 hns3vf_stop_service(struct hns3_adapter *hns)
2028 {
2029         struct hns3_hw *hw = &hns->hw;
2030         struct rte_eth_dev *eth_dev;
2031
2032         eth_dev = &rte_eth_devices[hw->data->port_id];
2033         if (hw->adapter_state == HNS3_NIC_STARTED)
2034                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2035         hw->mac.link_status = ETH_LINK_DOWN;
2036
2037         hns3_set_rxtx_function(eth_dev);
2038         rte_wmb();
2039         /* Disable datapath on secondary process. */
2040         hns3_mp_req_stop_rxtx(eth_dev);
2041         rte_delay_ms(hw->tqps_num);
2042
2043         rte_spinlock_lock(&hw->lock);
2044         if (hw->adapter_state == HNS3_NIC_STARTED ||
2045             hw->adapter_state == HNS3_NIC_STOPPING) {
2046                 hns3vf_do_stop(hns);
2047                 hw->reset.mbuf_deferred_free = true;
2048         } else
2049                 hw->reset.mbuf_deferred_free = false;
2050
2051         /*
2052          * It is cumbersome for hardware to pick-and-choose entries for deletion
2053          * from table space. Hence, for function reset software intervention is
2054          * required to delete the entries.
2055          */
2056         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2057                 hns3vf_configure_all_mc_mac_addr(hns, true);
2058         rte_spinlock_unlock(&hw->lock);
2059
2060         return 0;
2061 }
2062
2063 static int
2064 hns3vf_start_service(struct hns3_adapter *hns)
2065 {
2066         struct hns3_hw *hw = &hns->hw;
2067         struct rte_eth_dev *eth_dev;
2068
2069         eth_dev = &rte_eth_devices[hw->data->port_id];
2070         hns3_set_rxtx_function(eth_dev);
2071         hns3_mp_req_start_rxtx(eth_dev);
2072         if (hw->adapter_state == HNS3_NIC_STARTED)
2073                 hns3vf_service_handler(eth_dev);
2074
2075         return 0;
2076 }
2077
2078 static int
2079 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2080 {
2081         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2082         struct rte_ether_addr *hw_mac;
2083         int ret;
2084
2085         /*
2086          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2087          * on the host by "ip link set ..." command. If the hns3 PF kernel
2088          * ethdev driver sets the MAC address for VF device after the
2089          * initialization of the related VF device, the PF driver will notify
2090          * VF driver to reset VF device to make the new MAC address effective
2091          * immediately. The hns3 VF PMD driver should check whether the MAC
2092          * address has been changed by the PF kernel ethdev driver, if changed
2093          * VF driver should configure hardware using the new MAC address in the
2094          * recovering hardware configuration stage of the reset process.
2095          */
2096         ret = hns3vf_get_host_mac_addr(hw);
2097         if (ret)
2098                 return ret;
2099
2100         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2101         ret = rte_is_zero_ether_addr(hw_mac);
2102         if (ret) {
2103                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2104         } else {
2105                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2106                 if (!ret) {
2107                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2108                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2109                                               &hw->data->mac_addrs[0]);
2110                         hns3_warn(hw, "Default MAC address has been changed to:"
2111                                   " %s by the host PF kernel ethdev driver",
2112                                   mac_str);
2113                 }
2114         }
2115
2116         return 0;
2117 }
2118
2119 static int
2120 hns3vf_restore_conf(struct hns3_adapter *hns)
2121 {
2122         struct hns3_hw *hw = &hns->hw;
2123         int ret;
2124
2125         ret = hns3vf_check_default_mac_change(hw);
2126         if (ret)
2127                 return ret;
2128
2129         ret = hns3vf_configure_mac_addr(hns, false);
2130         if (ret)
2131                 return ret;
2132
2133         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2134         if (ret)
2135                 goto err_mc_mac;
2136
2137         ret = hns3vf_restore_promisc(hns);
2138         if (ret)
2139                 goto err_vlan_table;
2140
2141         ret = hns3vf_restore_vlan_conf(hns);
2142         if (ret)
2143                 goto err_vlan_table;
2144
2145         if (hw->adapter_state == HNS3_NIC_STARTED) {
2146                 ret = hns3vf_do_start(hns, false);
2147                 if (ret)
2148                         goto err_vlan_table;
2149                 hns3_info(hw, "hns3vf dev restart successful!");
2150         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2151                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2152         return 0;
2153
2154 err_vlan_table:
2155         hns3vf_configure_all_mc_mac_addr(hns, true);
2156 err_mc_mac:
2157         hns3vf_configure_mac_addr(hns, true);
2158         return ret;
2159 }
2160
2161 static enum hns3_reset_level
2162 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2163 {
2164         enum hns3_reset_level reset_level;
2165
2166         /* return the highest priority reset level amongst all */
2167         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2168                 reset_level = HNS3_VF_RESET;
2169         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2170                 reset_level = HNS3_VF_FULL_RESET;
2171         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2172                 reset_level = HNS3_VF_PF_FUNC_RESET;
2173         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2174                 reset_level = HNS3_VF_FUNC_RESET;
2175         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2176                 reset_level = HNS3_FLR_RESET;
2177         else
2178                 reset_level = HNS3_NONE_RESET;
2179
2180         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2181                 return HNS3_NONE_RESET;
2182
2183         return reset_level;
2184 }
2185
2186 static void
2187 hns3vf_reset_service(void *param)
2188 {
2189         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2190         struct hns3_hw *hw = &hns->hw;
2191         enum hns3_reset_level reset_level;
2192         struct timeval tv_delta;
2193         struct timeval tv_start;
2194         struct timeval tv;
2195         uint64_t msec;
2196
2197         /*
2198          * The interrupt is not triggered within the delay time.
2199          * The interrupt may have been lost. It is necessary to handle
2200          * the interrupt to recover from the error.
2201          */
2202         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2203                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2204                 hns3_err(hw, "Handling interrupts in delayed tasks");
2205                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2206                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2207                 if (reset_level == HNS3_NONE_RESET) {
2208                         hns3_err(hw, "No reset level is set, try global reset");
2209                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2210                 }
2211         }
2212         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2213
2214         /*
2215          * Hardware reset has been notified, we now have to poll & check if
2216          * hardware has actually completed the reset sequence.
2217          */
2218         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2219         if (reset_level != HNS3_NONE_RESET) {
2220                 gettimeofday(&tv_start, NULL);
2221                 hns3_reset_process(hns, reset_level);
2222                 gettimeofday(&tv, NULL);
2223                 timersub(&tv, &tv_start, &tv_delta);
2224                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2225                        tv_delta.tv_usec / USEC_PER_MSEC;
2226                 if (msec > HNS3_RESET_PROCESS_MS)
2227                         hns3_err(hw, "%d handle long time delta %" PRIx64
2228                                  " ms time=%ld.%.6ld",
2229                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2230         }
2231 }
2232
2233 static int
2234 hns3vf_reinit_dev(struct hns3_adapter *hns)
2235 {
2236         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2237         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2238         struct hns3_hw *hw = &hns->hw;
2239         int ret;
2240
2241         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2242                 rte_intr_disable(&pci_dev->intr_handle);
2243                 hns3vf_set_bus_master(pci_dev, true);
2244         }
2245
2246         /* Firmware command initialize */
2247         ret = hns3_cmd_init(hw);
2248         if (ret) {
2249                 hns3_err(hw, "Failed to init cmd: %d", ret);
2250                 return ret;
2251         }
2252
2253         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2254                 /*
2255                  * UIO enables msix by writing the pcie configuration space
2256                  * vfio_pci enables msix in rte_intr_enable.
2257                  */
2258                 if (pci_dev->kdrv == RTE_KDRV_IGB_UIO ||
2259                     pci_dev->kdrv == RTE_KDRV_UIO_GENERIC) {
2260                         if (hns3vf_enable_msix(pci_dev, true))
2261                                 hns3_err(hw, "Failed to enable msix");
2262                 }
2263
2264                 rte_intr_enable(&pci_dev->intr_handle);
2265         }
2266
2267         ret = hns3_reset_all_queues(hns);
2268         if (ret) {
2269                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2270                 return ret;
2271         }
2272
2273         ret = hns3vf_init_hardware(hns);
2274         if (ret) {
2275                 hns3_err(hw, "Failed to init hardware: %d", ret);
2276                 return ret;
2277         }
2278
2279         return 0;
2280 }
2281
2282 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2283         .dev_start          = hns3vf_dev_start,
2284         .dev_stop           = hns3vf_dev_stop,
2285         .dev_close          = hns3vf_dev_close,
2286         .mtu_set            = hns3vf_dev_mtu_set,
2287         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2288         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2289         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2290         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2291         .stats_get          = hns3_stats_get,
2292         .stats_reset        = hns3_stats_reset,
2293         .xstats_get         = hns3_dev_xstats_get,
2294         .xstats_get_names   = hns3_dev_xstats_get_names,
2295         .xstats_reset       = hns3_dev_xstats_reset,
2296         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2297         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2298         .dev_infos_get      = hns3vf_dev_infos_get,
2299         .rx_queue_setup     = hns3_rx_queue_setup,
2300         .tx_queue_setup     = hns3_tx_queue_setup,
2301         .rx_queue_release   = hns3_dev_rx_queue_release,
2302         .tx_queue_release   = hns3_dev_tx_queue_release,
2303         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2304         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2305         .dev_configure      = hns3vf_dev_configure,
2306         .mac_addr_add       = hns3vf_add_mac_addr,
2307         .mac_addr_remove    = hns3vf_remove_mac_addr,
2308         .mac_addr_set       = hns3vf_set_default_mac_addr,
2309         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2310         .link_update        = hns3vf_dev_link_update,
2311         .rss_hash_update    = hns3_dev_rss_hash_update,
2312         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2313         .reta_update        = hns3_dev_rss_reta_update,
2314         .reta_query         = hns3_dev_rss_reta_query,
2315         .filter_ctrl        = hns3_dev_filter_ctrl,
2316         .vlan_filter_set    = hns3vf_vlan_filter_set,
2317         .vlan_offload_set   = hns3vf_vlan_offload_set,
2318         .get_reg            = hns3_get_regs,
2319         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2320 };
2321
2322 static const struct hns3_reset_ops hns3vf_reset_ops = {
2323         .reset_service       = hns3vf_reset_service,
2324         .stop_service        = hns3vf_stop_service,
2325         .prepare_reset       = hns3vf_prepare_reset,
2326         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2327         .reinit_dev          = hns3vf_reinit_dev,
2328         .restore_conf        = hns3vf_restore_conf,
2329         .start_service       = hns3vf_start_service,
2330 };
2331
2332 static int
2333 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2334 {
2335         struct hns3_adapter *hns = eth_dev->data->dev_private;
2336         struct hns3_hw *hw = &hns->hw;
2337         int ret;
2338
2339         PMD_INIT_FUNC_TRACE();
2340
2341         eth_dev->process_private = (struct hns3_process_private *)
2342             rte_zmalloc_socket("hns3_filter_list",
2343                                sizeof(struct hns3_process_private),
2344                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2345         if (eth_dev->process_private == NULL) {
2346                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2347                 return -ENOMEM;
2348         }
2349
2350         /* initialize flow filter lists */
2351         hns3_filterlist_init(eth_dev);
2352
2353         hns3_set_rxtx_function(eth_dev);
2354         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2355         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2356                 hns3_mp_init_secondary();
2357                 hw->secondary_cnt++;
2358                 return 0;
2359         }
2360
2361         hns3_mp_init_primary();
2362
2363         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2364         hns->is_vf = true;
2365         hw->data = eth_dev->data;
2366
2367         ret = hns3_reset_init(hw);
2368         if (ret)
2369                 goto err_init_reset;
2370         hw->reset.ops = &hns3vf_reset_ops;
2371
2372         ret = hns3vf_init_vf(eth_dev);
2373         if (ret) {
2374                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2375                 goto err_init_vf;
2376         }
2377
2378         /* Allocate memory for storing MAC addresses */
2379         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2380                                                sizeof(struct rte_ether_addr) *
2381                                                HNS3_VF_UC_MACADDR_NUM, 0);
2382         if (eth_dev->data->mac_addrs == NULL) {
2383                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2384                              "to store MAC addresses",
2385                              sizeof(struct rte_ether_addr) *
2386                              HNS3_VF_UC_MACADDR_NUM);
2387                 ret = -ENOMEM;
2388                 goto err_rte_zmalloc;
2389         }
2390
2391         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2392                             &eth_dev->data->mac_addrs[0]);
2393         hw->adapter_state = HNS3_NIC_INITIALIZED;
2394         /*
2395          * Pass the information to the rte_eth_dev_close() that it should also
2396          * release the private port resources.
2397          */
2398         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2399
2400         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2401                 hns3_err(hw, "Reschedule reset service after dev_init");
2402                 hns3_schedule_reset(hns);
2403         } else {
2404                 /* IMP will wait ready flag before reset */
2405                 hns3_notify_reset_ready(hw, false);
2406         }
2407         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2408                           eth_dev);
2409         return 0;
2410
2411 err_rte_zmalloc:
2412         hns3vf_uninit_vf(eth_dev);
2413
2414 err_init_vf:
2415         rte_free(hw->reset.wait_data);
2416
2417 err_init_reset:
2418         eth_dev->dev_ops = NULL;
2419         eth_dev->rx_pkt_burst = NULL;
2420         eth_dev->tx_pkt_burst = NULL;
2421         eth_dev->tx_pkt_prepare = NULL;
2422         rte_free(eth_dev->process_private);
2423         eth_dev->process_private = NULL;
2424
2425         return ret;
2426 }
2427
2428 static int
2429 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2430 {
2431         struct hns3_adapter *hns = eth_dev->data->dev_private;
2432         struct hns3_hw *hw = &hns->hw;
2433
2434         PMD_INIT_FUNC_TRACE();
2435
2436         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2437                 return -EPERM;
2438
2439         eth_dev->dev_ops = NULL;
2440         eth_dev->rx_pkt_burst = NULL;
2441         eth_dev->tx_pkt_burst = NULL;
2442         eth_dev->tx_pkt_prepare = NULL;
2443
2444         if (hw->adapter_state < HNS3_NIC_CLOSING)
2445                 hns3vf_dev_close(eth_dev);
2446
2447         hw->adapter_state = HNS3_NIC_REMOVED;
2448         return 0;
2449 }
2450
2451 static int
2452 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2453                      struct rte_pci_device *pci_dev)
2454 {
2455         return rte_eth_dev_pci_generic_probe(pci_dev,
2456                                              sizeof(struct hns3_adapter),
2457                                              hns3vf_dev_init);
2458 }
2459
2460 static int
2461 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2462 {
2463         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2464 }
2465
2466 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2467         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2468         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2469         { .vendor_id = 0, /* sentinel */ },
2470 };
2471
2472 static struct rte_pci_driver rte_hns3vf_pmd = {
2473         .id_table = pci_id_hns3vf_map,
2474         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2475         .probe = eth_hns3vf_pci_probe,
2476         .remove = eth_hns3vf_pci_remove,
2477 };
2478
2479 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2480 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2481 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");