1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
6 #include <rte_atomic.h>
8 #include <rte_cycles.h>
9 #include <rte_ethdev.h>
11 #include <rte_malloc.h>
13 #include <rte_bus_pci.h>
15 #include "hns3_ethdev.h"
16 #include "hns3_logs.h"
17 #include "hns3_intr.h"
18 #include "hns3_regs.h"
19 #include "hns3_rxtx.h"
21 #define SWITCH_CONTEXT_US 10
23 /* offset in MSIX bd */
24 #define MAC_ERROR_OFFSET 1
25 #define PPP_PF_ERROR_OFFSET 2
26 #define PPU_PF_ERROR_OFFSET 3
27 #define RCB_ERROR_OFFSET 5
28 #define RCB_ERROR_STATUS_OFFSET 2
30 #define HNS3_CHECK_MERGE_CNT(val) \
33 hw->reset.stats.merge_cnt++; \
36 const struct hns3_hw_error mac_afifo_tnl_int[] = {
37 { .int_msk = BIT(0), .msg = "egu_cge_afifo_ecc_1bit_err",
38 .reset_level = HNS3_NONE_RESET },
39 { .int_msk = BIT(1), .msg = "egu_cge_afifo_ecc_mbit_err",
40 .reset_level = HNS3_GLOBAL_RESET },
41 { .int_msk = BIT(2), .msg = "egu_lge_afifo_ecc_1bit_err",
42 .reset_level = HNS3_NONE_RESET },
43 { .int_msk = BIT(3), .msg = "egu_lge_afifo_ecc_mbit_err",
44 .reset_level = HNS3_GLOBAL_RESET },
45 { .int_msk = BIT(4), .msg = "cge_igu_afifo_ecc_1bit_err",
46 .reset_level = HNS3_NONE_RESET },
47 { .int_msk = BIT(5), .msg = "cge_igu_afifo_ecc_mbit_err",
48 .reset_level = HNS3_GLOBAL_RESET },
49 { .int_msk = BIT(6), .msg = "lge_igu_afifo_ecc_1bit_err",
50 .reset_level = HNS3_NONE_RESET },
51 { .int_msk = BIT(7), .msg = "lge_igu_afifo_ecc_mbit_err",
52 .reset_level = HNS3_GLOBAL_RESET },
53 { .int_msk = BIT(8), .msg = "cge_igu_afifo_overflow_err",
54 .reset_level = HNS3_GLOBAL_RESET },
55 { .int_msk = BIT(9), .msg = "lge_igu_afifo_overflow_err",
56 .reset_level = HNS3_GLOBAL_RESET },
57 { .int_msk = BIT(10), .msg = "egu_cge_afifo_underrun_err",
58 .reset_level = HNS3_GLOBAL_RESET },
59 { .int_msk = BIT(11), .msg = "egu_lge_afifo_underrun_err",
60 .reset_level = HNS3_GLOBAL_RESET },
61 { .int_msk = BIT(12), .msg = "egu_ge_afifo_underrun_err",
62 .reset_level = HNS3_GLOBAL_RESET },
63 { .int_msk = BIT(13), .msg = "ge_igu_afifo_overflow_err",
64 .reset_level = HNS3_GLOBAL_RESET },
65 { .int_msk = 0, .msg = NULL,
66 .reset_level = HNS3_NONE_RESET}
69 const struct hns3_hw_error ppu_mpf_abnormal_int_st2[] = {
70 { .int_msk = BIT(13), .msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
71 .reset_level = HNS3_GLOBAL_RESET },
72 { .int_msk = BIT(14), .msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
73 .reset_level = HNS3_GLOBAL_RESET },
74 { .int_msk = BIT(15), .msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
75 .reset_level = HNS3_GLOBAL_RESET },
76 { .int_msk = BIT(16), .msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
77 .reset_level = HNS3_GLOBAL_RESET },
78 { .int_msk = BIT(17), .msg = "rcb_tx_ring_ecc_mbit_err",
79 .reset_level = HNS3_GLOBAL_RESET },
80 { .int_msk = BIT(18), .msg = "rcb_rx_ring_ecc_mbit_err",
81 .reset_level = HNS3_GLOBAL_RESET },
82 { .int_msk = BIT(19), .msg = "rcb_tx_fbd_ecc_mbit_err",
83 .reset_level = HNS3_GLOBAL_RESET },
84 { .int_msk = BIT(20), .msg = "rcb_rx_ebd_ecc_mbit_err",
85 .reset_level = HNS3_GLOBAL_RESET },
86 { .int_msk = BIT(21), .msg = "rcb_tso_info_ecc_mbit_err",
87 .reset_level = HNS3_GLOBAL_RESET },
88 { .int_msk = BIT(22), .msg = "rcb_tx_int_info_ecc_mbit_err",
89 .reset_level = HNS3_GLOBAL_RESET },
90 { .int_msk = BIT(23), .msg = "rcb_rx_int_info_ecc_mbit_err",
91 .reset_level = HNS3_GLOBAL_RESET },
92 { .int_msk = BIT(24), .msg = "tpu_tx_pkt_0_ecc_mbit_err",
93 .reset_level = HNS3_GLOBAL_RESET },
94 { .int_msk = BIT(25), .msg = "tpu_tx_pkt_1_ecc_mbit_err",
95 .reset_level = HNS3_GLOBAL_RESET },
96 { .int_msk = BIT(26), .msg = "rd_bus_err",
97 .reset_level = HNS3_GLOBAL_RESET },
98 { .int_msk = BIT(27), .msg = "wr_bus_err",
99 .reset_level = HNS3_GLOBAL_RESET },
100 { .int_msk = BIT(28), .msg = "reg_search_miss",
101 .reset_level = HNS3_GLOBAL_RESET },
102 { .int_msk = BIT(29), .msg = "rx_q_search_miss",
103 .reset_level = HNS3_NONE_RESET },
104 { .int_msk = BIT(30), .msg = "ooo_ecc_err_detect",
105 .reset_level = HNS3_NONE_RESET },
106 { .int_msk = BIT(31), .msg = "ooo_ecc_err_multpl",
107 .reset_level = HNS3_GLOBAL_RESET },
108 { .int_msk = 0, .msg = NULL,
109 .reset_level = HNS3_NONE_RESET}
112 const struct hns3_hw_error ssu_port_based_pf_int[] = {
113 { .int_msk = BIT(0), .msg = "roc_pkt_without_key_port",
114 .reset_level = HNS3_GLOBAL_RESET },
115 { .int_msk = BIT(9), .msg = "low_water_line_err_port",
116 .reset_level = HNS3_NONE_RESET },
117 { .int_msk = BIT(10), .msg = "hi_water_line_err_port",
118 .reset_level = HNS3_GLOBAL_RESET },
119 { .int_msk = 0, .msg = NULL,
120 .reset_level = HNS3_NONE_RESET}
123 const struct hns3_hw_error ppp_pf_abnormal_int[] = {
124 { .int_msk = BIT(0), .msg = "tx_vlan_tag_err",
125 .reset_level = HNS3_NONE_RESET },
126 { .int_msk = BIT(1), .msg = "rss_list_tc_unassigned_queue_err",
127 .reset_level = HNS3_NONE_RESET },
128 { .int_msk = 0, .msg = NULL,
129 .reset_level = HNS3_NONE_RESET}
132 const struct hns3_hw_error ppu_pf_abnormal_int[] = {
133 { .int_msk = BIT(0), .msg = "over_8bd_no_fe",
134 .reset_level = HNS3_FUNC_RESET },
135 { .int_msk = BIT(1), .msg = "tso_mss_cmp_min_err",
136 .reset_level = HNS3_NONE_RESET },
137 { .int_msk = BIT(2), .msg = "tso_mss_cmp_max_err",
138 .reset_level = HNS3_NONE_RESET },
139 { .int_msk = BIT(3), .msg = "tx_rd_fbd_poison",
140 .reset_level = HNS3_FUNC_RESET },
141 { .int_msk = BIT(4), .msg = "rx_rd_ebd_poison",
142 .reset_level = HNS3_FUNC_RESET },
143 { .int_msk = BIT(5), .msg = "buf_wait_timeout",
144 .reset_level = HNS3_NONE_RESET },
145 { .int_msk = 0, .msg = NULL,
146 .reset_level = HNS3_NONE_RESET}
150 config_ppp_err_intr(struct hns3_adapter *hns, uint32_t cmd, bool en)
152 struct hns3_hw *hw = &hns->hw;
153 struct hns3_cmd_desc desc[2];
156 /* configure PPP error interrupts */
157 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
158 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
159 hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
161 if (cmd == HNS3_PPP_CMD0_INT_CMD) {
164 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN);
166 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN);
168 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN);
172 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK);
174 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK);
176 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN_MASK);
177 } else if (cmd == HNS3_PPP_CMD1_INT_CMD) {
180 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN);
182 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN);
186 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK);
188 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK);
191 ret = hns3_cmd_send(hw, &desc[0], 2);
193 hns3_err(hw, "fail to configure PPP error int: %d", ret);
199 enable_ppp_err_intr(struct hns3_adapter *hns, bool en)
203 ret = config_ppp_err_intr(hns, HNS3_PPP_CMD0_INT_CMD, en);
207 return config_ppp_err_intr(hns, HNS3_PPP_CMD1_INT_CMD, en);
211 enable_ssu_err_intr(struct hns3_adapter *hns, bool en)
213 struct hns3_hw *hw = &hns->hw;
214 struct hns3_cmd_desc desc[2];
217 /* configure SSU ecc error interrupts */
218 hns3_cmd_setup_basic_desc(&desc[0], HNS3_SSU_ECC_INT_CMD, false);
219 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
220 hns3_cmd_setup_basic_desc(&desc[1], HNS3_SSU_ECC_INT_CMD, false);
223 rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN);
225 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN);
227 rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN);
230 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK);
232 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK);
233 desc[1].data[2] = rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK);
235 ret = hns3_cmd_send(hw, &desc[0], 2);
237 hns3_err(hw, "fail to configure SSU ECC error interrupt: %d",
242 /* configure SSU common error interrupts */
243 hns3_cmd_setup_basic_desc(&desc[0], HNS3_SSU_COMMON_INT_CMD, false);
244 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
245 hns3_cmd_setup_basic_desc(&desc[1], HNS3_SSU_COMMON_INT_CMD, false);
248 desc[0].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN);
250 rte_cpu_to_le_32(HNS3_SSU_PORT_BASED_ERR_INT_EN);
252 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN);
255 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN_MASK |
256 HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK);
258 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK);
260 ret = hns3_cmd_send(hw, &desc[0], 2);
262 hns3_err(hw, "fail to configure SSU COMMON error intr: %d",
269 config_ppu_err_intrs(struct hns3_adapter *hns, uint32_t cmd, bool en)
271 struct hns3_hw *hw = &hns->hw;
272 struct hns3_cmd_desc desc[2];
275 /* configure PPU error interrupts */
277 case HNS3_PPU_MPF_ECC_INT_CMD:
278 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
279 desc[0].flag |= HNS3_CMD_FLAG_NEXT;
280 hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
282 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN;
283 desc[0].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN;
284 desc[1].data[3] = HNS3_PPU_MPF_ABNORMAL_INT3_EN;
285 desc[1].data[4] = HNS3_PPU_MPF_ABNORMAL_INT2_EN;
288 desc[1].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK;
289 desc[1].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK;
290 desc[1].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK;
291 desc[1].data[3] |= HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK;
294 case HNS3_PPU_MPF_OTHER_INT_CMD:
295 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
297 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2;
299 desc[0].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK;
301 case HNS3_PPU_PF_OTHER_INT_CMD:
302 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
304 desc[0].data[0] = HNS3_PPU_PF_ABNORMAL_INT_EN;
306 desc[0].data[2] = HNS3_PPU_PF_ABNORMAL_INT_EN_MASK;
310 "Invalid cmd(%u) to configure PPU error interrupts.",
315 return hns3_cmd_send(hw, &desc[0], num);
319 enable_ppu_err_intr(struct hns3_adapter *hns, bool en)
321 struct hns3_hw *hw = &hns->hw;
324 ret = config_ppu_err_intrs(hns, HNS3_PPU_MPF_ECC_INT_CMD, en);
326 hns3_err(hw, "fail to configure PPU MPF ECC error intr: %d",
331 ret = config_ppu_err_intrs(hns, HNS3_PPU_MPF_OTHER_INT_CMD, en);
333 hns3_err(hw, "fail to configure PPU MPF other intr: %d",
338 ret = config_ppu_err_intrs(hns, HNS3_PPU_PF_OTHER_INT_CMD, en);
340 hns3_err(hw, "fail to configure PPU PF error interrupts: %d",
346 enable_mac_err_intr(struct hns3_adapter *hns, bool en)
348 struct hns3_hw *hw = &hns->hw;
349 struct hns3_cmd_desc desc;
352 /* configure MAC common error interrupts */
353 hns3_cmd_setup_basic_desc(&desc, HNS3_MAC_COMMON_INT_EN, false);
355 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN);
357 desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN_MASK);
359 ret = hns3_cmd_send(hw, &desc, 1);
361 hns3_err(hw, "fail to configure MAC COMMON error intr: %d",
367 static const struct hns3_hw_blk hw_blk[] = {
370 .enable_err_intr = enable_ppp_err_intr,
374 .enable_err_intr = enable_ssu_err_intr,
378 .enable_err_intr = enable_ppu_err_intr,
382 .enable_err_intr = enable_mac_err_intr,
386 .enable_err_intr = NULL,
391 hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool en)
393 const struct hns3_hw_blk *module = hw_blk;
396 while (module->enable_err_intr) {
397 ret = module->enable_err_intr(hns, en);
407 static enum hns3_reset_level
408 hns3_find_highest_level(struct hns3_adapter *hns, const char *reg,
409 const struct hns3_hw_error *err, uint32_t err_sts)
411 enum hns3_reset_level reset_level = HNS3_FUNC_RESET;
412 struct hns3_hw *hw = &hns->hw;
413 bool need_reset = false;
416 if (err->int_msk & err_sts) {
417 hns3_warn(hw, "%s %s found [error status=0x%x]",
418 reg, err->msg, err_sts);
419 if (err->reset_level != HNS3_NONE_RESET &&
420 err->reset_level >= reset_level) {
421 reset_level = err->reset_level;
430 return HNS3_NONE_RESET;
434 query_num_bds_in_msix(struct hns3_hw *hw, struct hns3_cmd_desc *desc_bd)
438 hns3_cmd_setup_basic_desc(desc_bd, HNS3_QUERY_MSIX_INT_STS_BD_NUM,
440 ret = hns3_cmd_send(hw, desc_bd, 1);
442 hns3_err(hw, "query num bds in msix failed: %d", ret);
448 query_all_mpf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
453 hns3_cmd_setup_basic_desc(desc, HNS3_QUERY_CLEAR_ALL_MPF_MSIX_INT,
455 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
457 ret = hns3_cmd_send(hw, &desc[0], mpf_bd_num);
459 hns3_err(hw, "query all mpf msix err failed: %d", ret);
465 clear_all_mpf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
470 hns3_cmd_reuse_desc(desc, false);
471 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
473 ret = hns3_cmd_send(hw, desc, mpf_bd_num);
475 hns3_err(hw, "clear all mpf msix err failed: %d", ret);
481 query_all_pf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
486 hns3_cmd_setup_basic_desc(desc, HNS3_QUERY_CLEAR_ALL_PF_MSIX_INT, true);
487 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
489 ret = hns3_cmd_send(hw, desc, pf_bd_num);
491 hns3_err(hw, "query all pf msix int cmd failed: %d", ret);
497 clear_all_pf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
502 hns3_cmd_reuse_desc(desc, false);
503 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
505 ret = hns3_cmd_send(hw, desc, pf_bd_num);
507 hns3_err(hw, "clear all pf msix err failed: %d", ret);
513 hns3_intr_unregister(const struct rte_intr_handle *hdl,
514 rte_intr_callback_fn cb_fn, void *cb_arg)
520 ret = rte_intr_callback_unregister(hdl, cb_fn, cb_arg);
523 } else if (ret != -EAGAIN) {
524 PMD_INIT_LOG(ERR, "Failed to unregister intr: %d", ret);
527 rte_delay_ms(HNS3_INTR_UNREG_FAIL_DELAY_MS);
528 } while (retry_cnt++ < HNS3_INTR_UNREG_FAIL_RETRY_CNT);
532 hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels)
534 uint32_t mpf_bd_num, pf_bd_num, bd_num;
535 enum hns3_reset_level req_level;
536 struct hns3_hw *hw = &hns->hw;
537 struct hns3_pf *pf = &hns->pf;
538 struct hns3_cmd_desc desc_bd;
539 struct hns3_cmd_desc *desc;
544 /* query the number of bds for the MSIx int status */
545 ret = query_num_bds_in_msix(hw, &desc_bd);
547 hns3_err(hw, "fail to query msix int status bd num: %d", ret);
551 mpf_bd_num = rte_le_to_cpu_32(desc_bd.data[0]);
552 pf_bd_num = rte_le_to_cpu_32(desc_bd.data[1]);
553 bd_num = max_t(uint32_t, mpf_bd_num, pf_bd_num);
554 if (bd_num < RCB_ERROR_OFFSET) {
555 hns3_err(hw, "bd_num is less than RCB_ERROR_OFFSET: %u",
560 desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0);
562 hns3_err(hw, "fail to zmalloc desc");
566 /* query all main PF MSIx errors */
567 ret = query_all_mpf_msix_err(hw, &desc[0], mpf_bd_num);
569 hns3_err(hw, "query all mpf msix int cmd failed: %d", ret);
574 desc_data = (uint32_t *)&desc[MAC_ERROR_OFFSET];
575 status = rte_le_to_cpu_32(*desc_data);
577 req_level = hns3_find_highest_level(hns, "MAC_AFIFO_TNL_INT_R",
580 hns3_atomic_set_bit(req_level, levels);
581 pf->abn_int_stats.mac_afifo_tnl_intr_cnt++;
584 /* log PPU(RCB) errors */
585 desc_data = (uint32_t *)&desc[RCB_ERROR_OFFSET];
586 status = rte_le_to_cpu_32(*(desc_data + RCB_ERROR_STATUS_OFFSET)) &
587 HNS3_PPU_MPF_INT_ST2_MSIX_MASK;
589 req_level = hns3_find_highest_level(hns,
590 "PPU_MPF_ABNORMAL_INT_ST2",
591 ppu_mpf_abnormal_int_st2,
593 hns3_atomic_set_bit(req_level, levels);
594 pf->abn_int_stats.ppu_mpf_abnormal_intr_st2_cnt++;
597 /* clear all main PF MSIx errors */
598 ret = clear_all_mpf_msix_err(hw, desc, mpf_bd_num);
600 hns3_err(hw, "clear all mpf msix int cmd failed: %d", ret);
604 /* query all PF MSIx errors */
605 memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc));
606 ret = query_all_pf_msix_err(hw, &desc[0], pf_bd_num);
608 hns3_err(hw, "query all pf msix int cmd failed (%d)", ret);
612 /* log SSU PF errors */
613 status = rte_le_to_cpu_32(desc[0].data[0]) &
614 HNS3_SSU_PORT_INT_MSIX_MASK;
616 req_level = hns3_find_highest_level(hns,
617 "SSU_PORT_BASED_ERR_INT",
618 ssu_port_based_pf_int,
620 hns3_atomic_set_bit(req_level, levels);
621 pf->abn_int_stats.ssu_port_based_pf_intr_cnt++;
624 /* log PPP PF errors */
625 desc_data = (uint32_t *)&desc[PPP_PF_ERROR_OFFSET];
626 status = rte_le_to_cpu_32(*desc_data);
628 req_level = hns3_find_highest_level(hns,
629 "PPP_PF_ABNORMAL_INT_ST0",
632 hns3_atomic_set_bit(req_level, levels);
633 pf->abn_int_stats.ppp_pf_abnormal_intr_cnt++;
636 /* log PPU(RCB) PF errors */
637 desc_data = (uint32_t *)&desc[PPU_PF_ERROR_OFFSET];
638 status = rte_le_to_cpu_32(*desc_data) & HNS3_PPU_PF_INT_MSIX_MASK;
640 req_level = hns3_find_highest_level(hns,
641 "PPU_PF_ABNORMAL_INT_ST",
644 hns3_atomic_set_bit(req_level, levels);
645 pf->abn_int_stats.ppu_pf_abnormal_intr_cnt++;
648 /* clear all PF MSIx errors */
649 ret = clear_all_pf_msix_err(hw, desc, pf_bd_num);
651 hns3_err(hw, "clear all pf msix int cmd failed: %d", ret);