1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
6 #include <rte_cycles.h>
7 #include <rte_ethdev.h>
9 #include <rte_malloc.h>
11 #include "hns3_ethdev.h"
12 #include "hns3_logs.h"
13 #include "hns3_intr.h"
14 #include "hns3_regs.h"
15 #include "hns3_rxtx.h"
17 #define SWITCH_CONTEXT_US 10
19 #define HNS3_CHECK_MERGE_CNT(val) \
22 hw->reset.stats.merge_cnt++; \
25 static const char *reset_string[HNS3_MAX_RESET] = {
26 "flr", "vf_func", "vf_pf_func", "vf_full", "vf_global",
27 "pf_func", "global", "IMP", "none",
30 static const struct hns3_hw_error mac_afifo_tnl_int[] = {
33 .msg = "egu_cge_afifo_ecc_1bit_err",
34 .reset_level = HNS3_NONE_RESET
37 .msg = "egu_cge_afifo_ecc_mbit_err",
38 .reset_level = HNS3_GLOBAL_RESET
41 .msg = "egu_lge_afifo_ecc_1bit_err",
42 .reset_level = HNS3_NONE_RESET
45 .msg = "egu_lge_afifo_ecc_mbit_err",
46 .reset_level = HNS3_GLOBAL_RESET
49 .msg = "cge_igu_afifo_ecc_1bit_err",
50 .reset_level = HNS3_NONE_RESET
53 .msg = "cge_igu_afifo_ecc_mbit_err",
54 .reset_level = HNS3_GLOBAL_RESET
57 .msg = "lge_igu_afifo_ecc_1bit_err",
58 .reset_level = HNS3_NONE_RESET
61 .msg = "lge_igu_afifo_ecc_mbit_err",
62 .reset_level = HNS3_GLOBAL_RESET
65 .msg = "cge_igu_afifo_overflow_err",
66 .reset_level = HNS3_GLOBAL_RESET
69 .msg = "lge_igu_afifo_overflow_err",
70 .reset_level = HNS3_GLOBAL_RESET
73 .msg = "egu_cge_afifo_underrun_err",
74 .reset_level = HNS3_GLOBAL_RESET
77 .msg = "egu_lge_afifo_underrun_err",
78 .reset_level = HNS3_GLOBAL_RESET
81 .msg = "egu_ge_afifo_underrun_err",
82 .reset_level = HNS3_GLOBAL_RESET
85 .msg = "ge_igu_afifo_overflow_err",
86 .reset_level = HNS3_GLOBAL_RESET
90 .reset_level = HNS3_NONE_RESET
94 static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = {
96 .int_msk = 0xFFFFFFFF,
97 .msg = "rpu_rx_pkt_ecc_mbit_err",
98 .reset_level = HNS3_GLOBAL_RESET
102 .reset_level = HNS3_NONE_RESET
106 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = {
109 .msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
110 .reset_level = HNS3_GLOBAL_RESET
113 .msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
114 .reset_level = HNS3_GLOBAL_RESET
117 .msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
118 .reset_level = HNS3_GLOBAL_RESET
121 .msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
122 .reset_level = HNS3_GLOBAL_RESET
125 .msg = "rcb_tx_ring_ecc_mbit_err",
126 .reset_level = HNS3_GLOBAL_RESET
129 .msg = "rcb_rx_ring_ecc_mbit_err",
130 .reset_level = HNS3_GLOBAL_RESET
133 .msg = "rcb_tx_fbd_ecc_mbit_err",
134 .reset_level = HNS3_GLOBAL_RESET
137 .msg = "rcb_rx_ebd_ecc_mbit_err",
138 .reset_level = HNS3_GLOBAL_RESET
141 .msg = "rcb_tso_info_ecc_mbit_err",
142 .reset_level = HNS3_GLOBAL_RESET
145 .msg = "rcb_tx_int_info_ecc_mbit_err",
146 .reset_level = HNS3_GLOBAL_RESET
149 .msg = "rcb_rx_int_info_ecc_mbit_err",
150 .reset_level = HNS3_GLOBAL_RESET
153 .msg = "tpu_tx_pkt_0_ecc_mbit_err",
154 .reset_level = HNS3_GLOBAL_RESET
157 .msg = "tpu_tx_pkt_1_ecc_mbit_err",
158 .reset_level = HNS3_GLOBAL_RESET
162 .reset_level = HNS3_GLOBAL_RESET
166 .reset_level = HNS3_GLOBAL_RESET
169 .msg = "ooo_ecc_err_detect",
170 .reset_level = HNS3_NONE_RESET
173 .msg = "ooo_ecc_err_multpl",
174 .reset_level = HNS3_GLOBAL_RESET
178 .reset_level = HNS3_NONE_RESET
182 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = {
185 .msg = "rx_q_search_miss",
186 .reset_level = HNS3_NONE_RESET
190 .reset_level = HNS3_NONE_RESET
194 static const struct hns3_hw_error ssu_port_based_pf_int[] = {
197 .msg = "roc_pkt_without_key_port",
198 .reset_level = HNS3_GLOBAL_RESET
201 .msg = "low_water_line_err_port",
202 .reset_level = HNS3_NONE_RESET
206 .reset_level = HNS3_NONE_RESET
210 static const struct hns3_hw_error ppp_pf_abnormal_int[] = {
213 .msg = "tx_vlan_tag_err",
214 .reset_level = HNS3_NONE_RESET
217 .msg = "rss_list_tc_unassigned_queue_err",
218 .reset_level = HNS3_NONE_RESET
222 .reset_level = HNS3_NONE_RESET
226 static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = {
229 .msg = "tx_rd_fbd_poison",
230 .reset_level = HNS3_FUNC_RESET
233 .msg = "rx_rd_ebd_poison",
234 .reset_level = HNS3_FUNC_RESET
238 .reset_level = HNS3_NONE_RESET
242 static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = {
245 .msg = "over_8bd_no_fe",
246 .reset_level = HNS3_FUNC_RESET
249 .msg = "tso_mss_cmp_min_err",
250 .reset_level = HNS3_NONE_RESET
253 .msg = "tso_mss_cmp_max_err",
254 .reset_level = HNS3_NONE_RESET
257 .msg = "buf_wait_timeout",
258 .reset_level = HNS3_NONE_RESET
262 .reset_level = HNS3_NONE_RESET
266 static const struct hns3_hw_error imp_tcm_ecc_int[] = {
269 .msg = "imp_itcm0_ecc_mbit_err",
270 .reset_level = HNS3_NONE_RESET
273 .msg = "imp_itcm1_ecc_mbit_err",
274 .reset_level = HNS3_NONE_RESET
277 .msg = "imp_itcm2_ecc_mbit_err",
278 .reset_level = HNS3_NONE_RESET
281 .msg = "imp_itcm3_ecc_mbit_err",
282 .reset_level = HNS3_NONE_RESET
285 .msg = "imp_dtcm0_mem0_ecc_mbit_err",
286 .reset_level = HNS3_NONE_RESET
289 .msg = "imp_dtcm0_mem1_ecc_mbit_err",
290 .reset_level = HNS3_NONE_RESET
293 .msg = "imp_dtcm1_mem0_ecc_mbit_err",
294 .reset_level = HNS3_NONE_RESET
297 .msg = "imp_dtcm1_mem1_ecc_mbit_err",
298 .reset_level = HNS3_NONE_RESET
301 .msg = "imp_itcm4_ecc_mbit_err",
302 .reset_level = HNS3_NONE_RESET
306 .reset_level = HNS3_NONE_RESET
310 static const struct hns3_hw_error cmdq_mem_ecc_int[] = {
313 .msg = "cmdq_nic_rx_depth_ecc_mbit_err",
314 .reset_level = HNS3_NONE_RESET
317 .msg = "cmdq_nic_tx_depth_ecc_mbit_err",
318 .reset_level = HNS3_NONE_RESET
321 .msg = "cmdq_nic_rx_tail_ecc_mbit_err",
322 .reset_level = HNS3_NONE_RESET
325 .msg = "cmdq_nic_tx_tail_ecc_mbit_err",
326 .reset_level = HNS3_NONE_RESET
329 .msg = "cmdq_nic_rx_head_ecc_mbit_err",
330 .reset_level = HNS3_NONE_RESET
333 .msg = "cmdq_nic_tx_head_ecc_mbit_err",
334 .reset_level = HNS3_NONE_RESET
337 .msg = "cmdq_nic_rx_addr_ecc_mbit_err",
338 .reset_level = HNS3_NONE_RESET
341 .msg = "cmdq_nic_tx_addr_ecc_mbit_err",
342 .reset_level = HNS3_NONE_RESET
346 .reset_level = HNS3_NONE_RESET
350 static const struct hns3_hw_error tqp_int_ecc_int[] = {
353 .msg = "tqp_int_cfg_even_ecc_mbit_err",
354 .reset_level = HNS3_NONE_RESET
357 .msg = "tqp_int_cfg_odd_ecc_mbit_err",
358 .reset_level = HNS3_NONE_RESET
361 .msg = "tqp_int_ctrl_even_ecc_mbit_err",
362 .reset_level = HNS3_NONE_RESET
365 .msg = "tqp_int_ctrl_odd_ecc_mbit_err",
366 .reset_level = HNS3_NONE_RESET
369 .msg = "tx_queue_scan_int_ecc_mbit_err",
370 .reset_level = HNS3_NONE_RESET
373 .msg = "rx_queue_scan_int_ecc_mbit_err",
374 .reset_level = HNS3_NONE_RESET
378 .reset_level = HNS3_NONE_RESET
382 static const struct hns3_hw_error imp_rd_poison_int[] = {
385 .msg = "imp_rd_poison_int",
386 .reset_level = HNS3_NONE_RESET
390 .reset_level = HNS3_NONE_RESET
394 #define HNS3_SSU_MEM_ECC_ERR(x) \
397 .msg = "ssu_mem" #x "_ecc_mbit_err", \
398 .reset_level = HNS3_GLOBAL_RESET \
401 static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = {
402 HNS3_SSU_MEM_ECC_ERR(0),
403 HNS3_SSU_MEM_ECC_ERR(1),
404 HNS3_SSU_MEM_ECC_ERR(2),
405 HNS3_SSU_MEM_ECC_ERR(3),
406 HNS3_SSU_MEM_ECC_ERR(4),
407 HNS3_SSU_MEM_ECC_ERR(5),
408 HNS3_SSU_MEM_ECC_ERR(6),
409 HNS3_SSU_MEM_ECC_ERR(7),
410 HNS3_SSU_MEM_ECC_ERR(8),
411 HNS3_SSU_MEM_ECC_ERR(9),
412 HNS3_SSU_MEM_ECC_ERR(10),
413 HNS3_SSU_MEM_ECC_ERR(11),
414 HNS3_SSU_MEM_ECC_ERR(12),
415 HNS3_SSU_MEM_ECC_ERR(13),
416 HNS3_SSU_MEM_ECC_ERR(14),
417 HNS3_SSU_MEM_ECC_ERR(15),
418 HNS3_SSU_MEM_ECC_ERR(16),
419 HNS3_SSU_MEM_ECC_ERR(17),
420 HNS3_SSU_MEM_ECC_ERR(18),
421 HNS3_SSU_MEM_ECC_ERR(19),
422 HNS3_SSU_MEM_ECC_ERR(20),
423 HNS3_SSU_MEM_ECC_ERR(21),
424 HNS3_SSU_MEM_ECC_ERR(22),
425 HNS3_SSU_MEM_ECC_ERR(23),
426 HNS3_SSU_MEM_ECC_ERR(24),
427 HNS3_SSU_MEM_ECC_ERR(25),
428 HNS3_SSU_MEM_ECC_ERR(26),
429 HNS3_SSU_MEM_ECC_ERR(27),
430 HNS3_SSU_MEM_ECC_ERR(28),
431 HNS3_SSU_MEM_ECC_ERR(29),
432 HNS3_SSU_MEM_ECC_ERR(30),
433 HNS3_SSU_MEM_ECC_ERR(31),
436 .reset_level = HNS3_NONE_RESET}
439 static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = {
442 .msg = "ssu_mem32_ecc_mbit_err",
443 .reset_level = HNS3_GLOBAL_RESET
447 .reset_level = HNS3_NONE_RESET
451 static const struct hns3_hw_error ssu_common_ecc_int[] = {
454 .msg = "buf_sum_err",
455 .reset_level = HNS3_NONE_RESET
458 .msg = "ppp_mb_num_err",
459 .reset_level = HNS3_NONE_RESET
462 .msg = "ppp_mbid_err",
463 .reset_level = HNS3_GLOBAL_RESET
466 .msg = "ppp_rlt_mac_err",
467 .reset_level = HNS3_GLOBAL_RESET
470 .msg = "ppp_rlt_host_err",
471 .reset_level = HNS3_GLOBAL_RESET
474 .msg = "cks_edit_position_err",
475 .reset_level = HNS3_GLOBAL_RESET
478 .msg = "cks_edit_condition_err",
479 .reset_level = HNS3_GLOBAL_RESET
482 .msg = "vlan_edit_condition_err",
483 .reset_level = HNS3_GLOBAL_RESET
486 .msg = "vlan_num_ot_err",
487 .reset_level = HNS3_GLOBAL_RESET
490 .msg = "vlan_num_in_err",
491 .reset_level = HNS3_GLOBAL_RESET
495 .reset_level = HNS3_NONE_RESET
499 static const struct hns3_hw_error igu_int[] = {
502 .msg = "igu_rx_buf0_ecc_mbit_err",
503 .reset_level = HNS3_GLOBAL_RESET
506 .msg = "igu_rx_buf1_ecc_mbit_err",
507 .reset_level = HNS3_GLOBAL_RESET
511 .reset_level = HNS3_NONE_RESET
515 static const struct hns3_hw_error msix_ecc_int[] = {
518 .msg = "msix_nic_ecc_mbit_err",
519 .reset_level = HNS3_NONE_RESET
523 .reset_level = HNS3_NONE_RESET
527 static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = {
530 .msg = "vf_vlan_ad_mem_ecc_mbit_err",
531 .reset_level = HNS3_GLOBAL_RESET
534 .msg = "umv_mcast_group_mem_ecc_mbit_err",
535 .reset_level = HNS3_GLOBAL_RESET
538 .msg = "umv_key_mem0_ecc_mbit_err",
539 .reset_level = HNS3_GLOBAL_RESET
542 .msg = "umv_key_mem1_ecc_mbit_err",
543 .reset_level = HNS3_GLOBAL_RESET
546 .msg = "umv_key_mem2_ecc_mbit_err",
547 .reset_level = HNS3_GLOBAL_RESET
550 .msg = "umv_key_mem3_ecc_mbit_err",
551 .reset_level = HNS3_GLOBAL_RESET
554 .msg = "umv_ad_mem_ecc_mbit_err",
555 .reset_level = HNS3_GLOBAL_RESET
558 .msg = "rss_tc_mode_mem_ecc_mbit_err",
559 .reset_level = HNS3_GLOBAL_RESET
562 .msg = "rss_idt_mem0_ecc_mbit_err",
563 .reset_level = HNS3_GLOBAL_RESET
566 .msg = "rss_idt_mem1_ecc_mbit_err",
567 .reset_level = HNS3_GLOBAL_RESET
570 .msg = "rss_idt_mem2_ecc_mbit_err",
571 .reset_level = HNS3_GLOBAL_RESET
574 .msg = "rss_idt_mem3_ecc_mbit_err",
575 .reset_level = HNS3_GLOBAL_RESET
578 .msg = "rss_idt_mem4_ecc_mbit_err",
579 .reset_level = HNS3_GLOBAL_RESET
582 .msg = "rss_idt_mem5_ecc_mbit_err",
583 .reset_level = HNS3_GLOBAL_RESET
586 .msg = "rss_idt_mem6_ecc_mbit_err",
587 .reset_level = HNS3_GLOBAL_RESET
590 .msg = "rss_idt_mem7_ecc_mbit_err",
591 .reset_level = HNS3_GLOBAL_RESET
594 .msg = "rss_idt_mem8_ecc_mbit_err",
595 .reset_level = HNS3_GLOBAL_RESET
598 .msg = "rss_idt_mem9_ecc_mbit_err",
599 .reset_level = HNS3_GLOBAL_RESET
602 .msg = "rss_idt_mem10_ecc_m1bit_err",
603 .reset_level = HNS3_GLOBAL_RESET
606 .msg = "rss_idt_mem11_ecc_mbit_err",
607 .reset_level = HNS3_GLOBAL_RESET
610 .msg = "rss_idt_mem12_ecc_mbit_err",
611 .reset_level = HNS3_GLOBAL_RESET
614 .msg = "rss_idt_mem13_ecc_mbit_err",
615 .reset_level = HNS3_GLOBAL_RESET
618 .msg = "rss_idt_mem14_ecc_mbit_err",
619 .reset_level = HNS3_GLOBAL_RESET
622 .msg = "rss_idt_mem15_ecc_mbit_err",
623 .reset_level = HNS3_GLOBAL_RESET
626 .msg = "port_vlan_mem_ecc_mbit_err",
627 .reset_level = HNS3_GLOBAL_RESET
630 .msg = "mcast_linear_table_mem_ecc_mbit_err",
631 .reset_level = HNS3_GLOBAL_RESET
634 .msg = "mcast_result_mem_ecc_mbit_err",
635 .reset_level = HNS3_GLOBAL_RESET
638 .msg = "flow_director_ad_mem0_ecc_mbit_err",
639 .reset_level = HNS3_GLOBAL_RESET
642 .msg = "flow_director_ad_mem1_ecc_mbit_err",
643 .reset_level = HNS3_GLOBAL_RESET
646 .msg = "rx_vlan_tag_memory_ecc_mbit_err",
647 .reset_level = HNS3_GLOBAL_RESET
650 .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
651 .reset_level = HNS3_GLOBAL_RESET
655 .reset_level = HNS3_NONE_RESET
659 static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = {
662 .msg = "hfs_fifo_mem_ecc_mbit_err",
663 .reset_level = HNS3_GLOBAL_RESET
666 .msg = "rslt_descr_fifo_mem_ecc_mbit_err",
667 .reset_level = HNS3_GLOBAL_RESET
670 .msg = "tx_vlan_tag_mem_ecc_mbit_err",
671 .reset_level = HNS3_GLOBAL_RESET
674 .msg = "FD_CN0_memory_ecc_mbit_err",
675 .reset_level = HNS3_GLOBAL_RESET
678 .msg = "FD_CN1_memory_ecc_mbit_err",
679 .reset_level = HNS3_GLOBAL_RESET
682 .msg = "GRO_AD_memory_ecc_mbit_err",
683 .reset_level = HNS3_GLOBAL_RESET
687 .reset_level = HNS3_NONE_RESET
691 static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = {
694 .msg = "gro_bd_ecc_mbit_err",
695 .reset_level = HNS3_GLOBAL_RESET
698 .msg = "gro_context_ecc_mbit_err",
699 .reset_level = HNS3_GLOBAL_RESET
702 .msg = "rx_stash_cfg_ecc_mbit_err",
703 .reset_level = HNS3_GLOBAL_RESET
706 .msg = "axi_rd_fbd_ecc_mbit_err",
707 .reset_level = HNS3_GLOBAL_RESET
711 .reset_level = HNS3_NONE_RESET
715 static const struct hns3_hw_error tm_sch_int[] = {
718 .msg = "tm_sch_ecc_mbit_err",
719 .reset_level = HNS3_GLOBAL_RESET
722 .msg = "tm_sch_port_shap_sub_fifo_wr_err",
723 .reset_level = HNS3_GLOBAL_RESET
726 .msg = "tm_sch_port_shap_sub_fifo_rd_err",
727 .reset_level = HNS3_GLOBAL_RESET
730 .msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
731 .reset_level = HNS3_GLOBAL_RESET
734 .msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
735 .reset_level = HNS3_GLOBAL_RESET
738 .msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
739 .reset_level = HNS3_GLOBAL_RESET
742 .msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
743 .reset_level = HNS3_GLOBAL_RESET
746 .msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
747 .reset_level = HNS3_GLOBAL_RESET
750 .msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
751 .reset_level = HNS3_GLOBAL_RESET
754 .msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
755 .reset_level = HNS3_GLOBAL_RESET
758 .msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
759 .reset_level = HNS3_GLOBAL_RESET
762 .msg = "tm_sch_port_shap_offset_fifo_wr_err",
763 .reset_level = HNS3_GLOBAL_RESET
766 .msg = "tm_sch_port_shap_offset_fifo_rd_err",
767 .reset_level = HNS3_GLOBAL_RESET
770 .msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
771 .reset_level = HNS3_GLOBAL_RESET
774 .msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
775 .reset_level = HNS3_GLOBAL_RESET
778 .msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
779 .reset_level = HNS3_GLOBAL_RESET
782 .msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
783 .reset_level = HNS3_GLOBAL_RESET
786 .msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
787 .reset_level = HNS3_GLOBAL_RESET
790 .msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
791 .reset_level = HNS3_GLOBAL_RESET
794 .msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
795 .reset_level = HNS3_GLOBAL_RESET
798 .msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
799 .reset_level = HNS3_GLOBAL_RESET
802 .msg = "tm_sch_rq_fifo_wr_err",
803 .reset_level = HNS3_GLOBAL_RESET
806 .msg = "tm_sch_rq_fifo_rd_err",
807 .reset_level = HNS3_GLOBAL_RESET
810 .msg = "tm_sch_nq_fifo_wr_err",
811 .reset_level = HNS3_GLOBAL_RESET
814 .msg = "tm_sch_nq_fifo_rd_err",
815 .reset_level = HNS3_GLOBAL_RESET
818 .msg = "tm_sch_roce_up_fifo_wr_err",
819 .reset_level = HNS3_GLOBAL_RESET
822 .msg = "tm_sch_roce_up_fifo_rd_err",
823 .reset_level = HNS3_GLOBAL_RESET
826 .msg = "tm_sch_rcb_byte_fifo_wr_err",
827 .reset_level = HNS3_GLOBAL_RESET
830 .msg = "tm_sch_rcb_byte_fifo_rd_err",
831 .reset_level = HNS3_GLOBAL_RESET
834 .msg = "tm_sch_ssu_byte_fifo_wr_err",
835 .reset_level = HNS3_GLOBAL_RESET
838 .msg = "tm_sch_ssu_byte_fifo_rd_err",
839 .reset_level = HNS3_GLOBAL_RESET
843 .reset_level = HNS3_NONE_RESET
847 static const struct hns3_hw_error qcn_fifo_int[] = {
850 .msg = "qcn_shap_gp0_sch_fifo_rd_err",
851 .reset_level = HNS3_GLOBAL_RESET
854 .msg = "qcn_shap_gp0_sch_fifo_wr_err",
855 .reset_level = HNS3_GLOBAL_RESET
858 .msg = "qcn_shap_gp1_sch_fifo_rd_err",
859 .reset_level = HNS3_GLOBAL_RESET
862 .msg = "qcn_shap_gp1_sch_fifo_wr_err",
863 .reset_level = HNS3_GLOBAL_RESET
866 .msg = "qcn_shap_gp2_sch_fifo_rd_err",
867 .reset_level = HNS3_GLOBAL_RESET
870 .msg = "qcn_shap_gp2_sch_fifo_wr_err",
871 .reset_level = HNS3_GLOBAL_RESET
874 .msg = "qcn_shap_gp3_sch_fifo_rd_err",
875 .reset_level = HNS3_GLOBAL_RESET
878 .msg = "qcn_shap_gp3_sch_fifo_wr_err",
879 .reset_level = HNS3_GLOBAL_RESET
882 .msg = "qcn_shap_gp0_offset_fifo_rd_err",
883 .reset_level = HNS3_GLOBAL_RESET
886 .msg = "qcn_shap_gp0_offset_fifo_wr_err",
887 .reset_level = HNS3_GLOBAL_RESET
890 .msg = "qcn_shap_gp1_offset_fifo_rd_err",
891 .reset_level = HNS3_GLOBAL_RESET
894 .msg = "qcn_shap_gp1_offset_fifo_wr_err",
895 .reset_level = HNS3_GLOBAL_RESET
898 .msg = "qcn_shap_gp2_offset_fifo_rd_err",
899 .reset_level = HNS3_GLOBAL_RESET
902 .msg = "qcn_shap_gp2_offset_fifo_wr_err",
903 .reset_level = HNS3_GLOBAL_RESET
906 .msg = "qcn_shap_gp3_offset_fifo_rd_err",
907 .reset_level = HNS3_GLOBAL_RESET
910 .msg = "qcn_shap_gp3_offset_fifo_wr_err",
911 .reset_level = HNS3_GLOBAL_RESET
914 .msg = "qcn_byte_info_fifo_rd_err",
915 .reset_level = HNS3_GLOBAL_RESET
918 .msg = "qcn_byte_info_fifo_wr_err",
919 .reset_level = HNS3_GLOBAL_RESET
923 .reset_level = HNS3_NONE_RESET
927 static const struct hns3_hw_error qcn_ecc_int[] = {
930 .msg = "qcn_byte_mem_ecc_mbit_err",
931 .reset_level = HNS3_GLOBAL_RESET
934 .msg = "qcn_time_mem_ecc_mbit_err",
935 .reset_level = HNS3_GLOBAL_RESET
938 .msg = "qcn_fb_mem_ecc_mbit_err",
939 .reset_level = HNS3_GLOBAL_RESET
942 .msg = "qcn_link_mem_ecc_mbit_err",
943 .reset_level = HNS3_GLOBAL_RESET
946 .msg = "qcn_rate_mem_ecc_mbit_err",
947 .reset_level = HNS3_GLOBAL_RESET
950 .msg = "qcn_tmplt_mem_ecc_mbit_err",
951 .reset_level = HNS3_GLOBAL_RESET
954 .msg = "qcn_shap_cfg_mem_ecc_mbit_err",
955 .reset_level = HNS3_GLOBAL_RESET
958 .msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
959 .reset_level = HNS3_GLOBAL_RESET
962 .msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
963 .reset_level = HNS3_GLOBAL_RESET
966 .msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
967 .reset_level = HNS3_GLOBAL_RESET
970 .msg = "qcn_gp3_barral_mem_ecc_mbit_err",
971 .reset_level = HNS3_GLOBAL_RESET
975 .reset_level = HNS3_NONE_RESET
979 static const struct hns3_hw_error ncsi_ecc_int[] = {
982 .msg = "ncsi_tx_ecc_mbit_err",
983 .reset_level = HNS3_NONE_RESET
987 .reset_level = HNS3_NONE_RESET
991 static const struct hns3_hw_error ssu_fifo_overflow_int[] = {
994 .msg = "ig_mac_inf_int",
995 .reset_level = HNS3_GLOBAL_RESET
998 .msg = "ig_host_inf_int",
999 .reset_level = HNS3_GLOBAL_RESET
1002 .msg = "ig_roc_buf_int",
1003 .reset_level = HNS3_GLOBAL_RESET
1006 .msg = "ig_host_data_fifo_int",
1007 .reset_level = HNS3_GLOBAL_RESET
1010 .msg = "ig_host_key_fifo_int",
1011 .reset_level = HNS3_GLOBAL_RESET
1014 .msg = "tx_qcn_fifo_int",
1015 .reset_level = HNS3_GLOBAL_RESET
1018 .msg = "rx_qcn_fifo_int",
1019 .reset_level = HNS3_GLOBAL_RESET
1022 .msg = "tx_pf_rd_fifo_int",
1023 .reset_level = HNS3_GLOBAL_RESET
1026 .msg = "rx_pf_rd_fifo_int",
1027 .reset_level = HNS3_GLOBAL_RESET
1030 .msg = "qm_eof_fifo_int",
1031 .reset_level = HNS3_GLOBAL_RESET
1034 .msg = "mb_rlt_fifo_int",
1035 .reset_level = HNS3_GLOBAL_RESET
1038 .msg = "dup_uncopy_fifo_int",
1039 .reset_level = HNS3_GLOBAL_RESET
1042 .msg = "dup_cnt_rd_fifo_int",
1043 .reset_level = HNS3_GLOBAL_RESET
1046 .msg = "dup_cnt_drop_fifo_int",
1047 .reset_level = HNS3_GLOBAL_RESET
1050 .msg = "dup_cnt_wrb_fifo_int",
1051 .reset_level = HNS3_GLOBAL_RESET
1054 .msg = "host_cmd_fifo_int",
1055 .reset_level = HNS3_GLOBAL_RESET
1058 .msg = "mac_cmd_fifo_int",
1059 .reset_level = HNS3_GLOBAL_RESET
1062 .msg = "host_cmd_bitmap_empty_int",
1063 .reset_level = HNS3_GLOBAL_RESET
1066 .msg = "mac_cmd_bitmap_empty_int",
1067 .reset_level = HNS3_GLOBAL_RESET
1070 .msg = "dup_bitmap_empty_int",
1071 .reset_level = HNS3_GLOBAL_RESET
1074 .msg = "out_queue_bitmap_empty_int",
1075 .reset_level = HNS3_GLOBAL_RESET
1078 .msg = "bank2_bitmap_empty_int",
1079 .reset_level = HNS3_GLOBAL_RESET
1082 .msg = "bank1_bitmap_empty_int",
1083 .reset_level = HNS3_GLOBAL_RESET
1086 .msg = "bank0_bitmap_empty_int",
1087 .reset_level = HNS3_GLOBAL_RESET
1091 .reset_level = HNS3_NONE_RESET
1095 static const struct hns3_hw_error ssu_ets_tcg_int[] = {
1098 .msg = "ets_rd_int_rx_tcg",
1099 .reset_level = HNS3_GLOBAL_RESET
1102 .msg = "ets_wr_int_rx_tcg",
1103 .reset_level = HNS3_GLOBAL_RESET
1106 .msg = "ets_rd_int_tx_tcg",
1107 .reset_level = HNS3_GLOBAL_RESET
1110 .msg = "ets_wr_int_tx_tcg",
1111 .reset_level = HNS3_GLOBAL_RESET
1115 .reset_level = HNS3_NONE_RESET
1119 static const struct hns3_hw_error igu_egu_tnl_int[] = {
1122 .msg = "rx_buf_overflow",
1123 .reset_level = HNS3_GLOBAL_RESET
1126 .msg = "rx_stp_fifo_overflow",
1127 .reset_level = HNS3_GLOBAL_RESET
1130 .msg = "rx_stp_fifo_underflow",
1131 .reset_level = HNS3_GLOBAL_RESET
1134 .msg = "tx_buf_overflow",
1135 .reset_level = HNS3_GLOBAL_RESET
1138 .msg = "tx_buf_underrun",
1139 .reset_level = HNS3_GLOBAL_RESET
1142 .msg = "rx_stp_buf_overflow",
1143 .reset_level = HNS3_GLOBAL_RESET
1147 .reset_level = HNS3_NONE_RESET
1151 static const struct hns3_hw_error ssu_port_based_err_int[] = {
1154 .msg = "roc_pkt_without_key_port",
1155 .reset_level = HNS3_FUNC_RESET
1158 .msg = "tpu_pkt_without_key_port",
1159 .reset_level = HNS3_GLOBAL_RESET
1162 .msg = "igu_pkt_without_key_port",
1163 .reset_level = HNS3_GLOBAL_RESET
1166 .msg = "roc_eof_mis_match_port",
1167 .reset_level = HNS3_GLOBAL_RESET
1170 .msg = "tpu_eof_mis_match_port",
1171 .reset_level = HNS3_GLOBAL_RESET
1174 .msg = "igu_eof_mis_match_port",
1175 .reset_level = HNS3_GLOBAL_RESET
1178 .msg = "roc_sof_mis_match_port",
1179 .reset_level = HNS3_GLOBAL_RESET
1182 .msg = "tpu_sof_mis_match_port",
1183 .reset_level = HNS3_GLOBAL_RESET
1186 .msg = "igu_sof_mis_match_port",
1187 .reset_level = HNS3_GLOBAL_RESET
1190 .msg = "ets_rd_int_rx_port",
1191 .reset_level = HNS3_GLOBAL_RESET
1194 .msg = "ets_wr_int_rx_port",
1195 .reset_level = HNS3_GLOBAL_RESET
1198 .msg = "ets_rd_int_tx_port",
1199 .reset_level = HNS3_GLOBAL_RESET
1202 .msg = "ets_wr_int_tx_port",
1203 .reset_level = HNS3_GLOBAL_RESET
1207 .reset_level = HNS3_NONE_RESET
1211 static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = {
1215 .msg = "IMP_TCM_ECC_INT_STS",
1216 .hw_err = imp_tcm_ecc_int
1220 .msg = "CMDQ_MEM_ECC_INT_STS",
1221 .hw_err = cmdq_mem_ecc_int
1225 .msg = "IMP_RD_POISON_INT_STS",
1226 .hw_err = imp_rd_poison_int
1230 .msg = "TQP_INT_ECC_INT_STS",
1231 .hw_err = tqp_int_ecc_int
1235 .msg = "MSIX_ECC_INT_STS",
1236 .hw_err = msix_ecc_int
1240 .msg = "SSU_ECC_MULTI_BIT_INT_0",
1241 .hw_err = ssu_ecc_multi_bit_int_0
1245 .msg = "SSU_ECC_MULTI_BIT_INT_1",
1246 .hw_err = ssu_ecc_multi_bit_int_1
1250 .msg = "SSU_COMMON_ERR_INT",
1251 .hw_err = ssu_common_ecc_int
1255 .msg = "IGU_INT_STS",
1260 .msg = "PPP_MPF_ABNORMAL_INT_ST1",
1261 .hw_err = ppp_mpf_abnormal_int_st1
1265 .msg = "PPP_MPF_ABNORMAL_INT_ST3",
1266 .hw_err = ppp_mpf_abnormal_int_st3
1270 .msg = "PPU_MPF_ABNORMAL_INT_ST1",
1271 .hw_err = ppu_mpf_abnormal_int_st1
1275 .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS",
1276 .hw_err = ppu_mpf_abnormal_int_st2_ras
1280 .msg = "PPU_MPF_ABNORMAL_INT_ST3",
1281 .hw_err = ppu_mpf_abnormal_int_st3
1285 .msg = "TM_SCH_RINT",
1286 .hw_err = tm_sch_int
1290 .msg = "QCN_FIFO_RINT",
1291 .hw_err = qcn_fifo_int
1295 .msg = "QCN_ECC_RINT",
1296 .hw_err = qcn_ecc_int
1300 .msg = "NCSI_ECC_INT_RPT",
1301 .hw_err = ncsi_ecc_int
1310 static const struct hns3_hw_error_desc pf_ras_err_tbl[] = {
1314 .msg = "SSU_PORT_BASED_ERR_INT_RAS",
1315 .hw_err = ssu_port_based_err_int
1319 .msg = "SSU_FIFO_OVERFLOW_INT",
1320 .hw_err = ssu_fifo_overflow_int
1324 .msg = "SSU_ETS_TCG_INT",
1325 .hw_err = ssu_ets_tcg_int
1329 .msg = "IGU_EGU_TNL_INT_STS",
1330 .hw_err = igu_egu_tnl_int
1334 .msg = "PPU_PF_ABNORMAL_INT_ST_RAS",
1335 .hw_err = ppu_pf_abnormal_int_ras
1344 static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = {
1348 .msg = "MAC_AFIFO_TNL_INT_R",
1349 .hw_err = mac_afifo_tnl_int
1353 .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX",
1354 .hw_err = ppu_mpf_abnormal_int_st2_msix
1363 static const struct hns3_hw_error_desc pf_msix_err_tbl[] = {
1367 .msg = "SSU_PORT_BASED_ERR_INT_MSIX",
1368 .hw_err = ssu_port_based_pf_int
1372 .msg = "PPP_PF_ABNORMAL_INT_ST0",
1373 .hw_err = ppp_pf_abnormal_int
1377 .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX",
1378 .hw_err = ppu_pf_abnormal_int_msix
1387 enum hns3_hw_err_report_type {
1394 static const struct hns3_hw_mod_name hns3_hw_module_name[] = {
1396 .module_name = MODULE_NONE,
1397 .msg = "MODULE_NONE"
1399 .module_name = MODULE_BIOS_COMMON,
1400 .msg = "MODULE_BIOS_COMMON"
1402 .module_name = MODULE_GE,
1405 .module_name = MODULE_IGU_EGU,
1406 .msg = "MODULE_IGU_EGU"
1408 .module_name = MODULE_LGE,
1411 .module_name = MODULE_NCSI,
1412 .msg = "MODULE_NCSI"
1414 .module_name = MODULE_PPP,
1417 .module_name = MODULE_QCN,
1420 .module_name = MODULE_RCB_RX,
1421 .msg = "MODULE_RCB_RX"
1423 .module_name = MODULE_RTC,
1426 .module_name = MODULE_SSU,
1429 .module_name = MODULE_TM,
1432 .module_name = MODULE_RCB_TX,
1433 .msg = "MODULE_RCB_TX"
1435 .module_name = MODULE_TXDMA,
1436 .msg = "MODULE_TXDMA"
1438 .module_name = MODULE_MASTER,
1439 .msg = "MODULE_MASTER"
1441 .module_name = MODULE_ROH_MAC,
1442 .msg = "MODULE_ROH_MAC"
1446 static const struct hns3_hw_err_type hns3_hw_error_type[] = {
1448 .error_type = NONE_ERROR,
1451 .error_type = FIFO_ERROR,
1454 .error_type = MEMORY_ERROR,
1455 .msg = "memory_error"
1457 .error_type = POISION_ERROR,
1458 .msg = "poision_error"
1460 .error_type = MSIX_ECC_ERROR,
1461 .msg = "msix_ecc_error"
1463 .error_type = TQP_INT_ECC_ERROR,
1464 .msg = "tqp_int_ecc_error"
1466 .error_type = PF_ABNORMAL_INT_ERROR,
1467 .msg = "pf_abnormal_int_error"
1469 .error_type = MPF_ABNORMAL_INT_ERROR,
1470 .msg = "mpf_abnormal_int_error"
1472 .error_type = COMMON_ERROR,
1473 .msg = "common_error"
1475 .error_type = PORT_ERROR,
1478 .error_type = ETS_ERROR,
1481 .error_type = NCSI_ERROR,
1484 .error_type = GLB_ERROR,
1490 hns3_config_ncsi_hw_err_int(struct hns3_adapter *hns, bool en)
1492 struct hns3_hw *hw = &hns->hw;
1493 struct hns3_cmd_desc desc;
1496 /* configure NCSI error interrupts */
1497 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_NCSI_INT_EN, false);
1499 desc.data[0] = rte_cpu_to_le_32(HNS3_NCSI_ERR_INT_EN);
1501 ret = hns3_cmd_send(hw, &desc, 1);
1503 hns3_err(hw, "fail to %s NCSI error interrupts, ret = %d",
1504 en ? "enable" : "disable", ret);
1510 enable_igu_egu_err_intr(struct hns3_adapter *hns, bool en)
1512 struct hns3_hw *hw = &hns->hw;
1513 struct hns3_cmd_desc desc;
1516 /* configure IGU,EGU error interrupts */
1517 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_COMMON_INT_EN, false);
1519 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_ENABLE);
1521 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_DISABLE);
1523 desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_EN_MASK);
1525 ret = hns3_cmd_send(hw, &desc, 1);
1527 hns3_err(hw, "fail to %s IGU common interrupts, ret = %d",
1528 en ? "enable" : "disable", ret);
1532 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_EGU_TNL_INT_EN, false);
1534 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN);
1536 desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN_MASK);
1538 ret = hns3_cmd_send(hw, &desc, 1);
1540 hns3_err(hw, "fail to %s IGU-EGU TNL interrupts, ret = %d",
1541 en ? "enable" : "disable", ret);
1545 return hns3_config_ncsi_hw_err_int(hns, en);
1549 config_ppp_err_intr(struct hns3_adapter *hns, uint32_t cmd, bool en)
1551 struct hns3_hw *hw = &hns->hw;
1552 struct hns3_cmd_desc desc[2];
1555 /* configure PPP error interrupts */
1556 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1557 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1558 hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
1560 if (cmd == HNS3_OPC_PPP_CMD0_INT_CMD) {
1563 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN);
1565 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN);
1567 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN);
1571 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK);
1573 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK);
1575 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN_MASK);
1576 } else if (cmd == HNS3_OPC_PPP_CMD1_INT_CMD) {
1579 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN);
1581 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN);
1585 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK);
1587 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK);
1590 ret = hns3_cmd_send(hw, &desc[0], 2);
1592 hns3_err(hw, "fail to %s PPP error int, ret = %d",
1593 en ? "enable" : "disable", ret);
1599 enable_ppp_err_intr(struct hns3_adapter *hns, bool en)
1603 ret = config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD0_INT_CMD, en);
1607 return config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD1_INT_CMD, en);
1611 enable_ssu_err_intr(struct hns3_adapter *hns, bool en)
1613 struct hns3_hw *hw = &hns->hw;
1614 struct hns3_cmd_desc desc[2];
1617 /* configure SSU ecc error interrupts */
1618 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_ECC_INT_CMD, false);
1619 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1620 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_ECC_INT_CMD, false);
1623 rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN);
1625 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN);
1627 rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN);
1630 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK);
1632 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK);
1633 desc[1].data[2] = rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK);
1635 ret = hns3_cmd_send(hw, &desc[0], 2);
1637 hns3_err(hw, "fail to %s SSU ECC error interrupt, ret = %d",
1638 en ? "enable" : "disable", ret);
1642 /* configure SSU common error interrupts */
1643 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_COMMON_INT_CMD, false);
1644 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1645 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_COMMON_INT_CMD, false);
1648 desc[0].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN);
1650 rte_cpu_to_le_32(HNS3_SSU_PORT_BASED_ERR_INT_EN);
1652 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN);
1655 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN_MASK |
1656 HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK);
1658 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK);
1660 ret = hns3_cmd_send(hw, &desc[0], 2);
1662 hns3_err(hw, "fail to %s SSU COMMON error intr, ret = %d",
1663 en ? "enable" : "disable", ret);
1669 hns3_config_mac_tnl_int(struct hns3_hw *hw, bool en)
1671 struct hns3_cmd_desc desc;
1674 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_TNL_INT_EN, false);
1676 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_EN);
1680 desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_EN_MASK);
1682 ret = hns3_cmd_send(hw, &desc, 1);
1684 hns3_err(hw, "fail to %s mac tnl intr, ret = %d",
1685 en ? "enable" : "disable", ret);
1689 config_ppu_err_intrs(struct hns3_adapter *hns, uint32_t cmd, bool en)
1691 struct hns3_hw *hw = &hns->hw;
1692 struct hns3_cmd_desc desc[2];
1695 /* configure PPU error interrupts */
1697 case HNS3_OPC_PPU_MPF_ECC_INT_CMD:
1698 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1699 desc[0].flag |= HNS3_CMD_FLAG_NEXT;
1700 hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
1702 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN;
1703 desc[0].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN;
1704 desc[1].data[3] = HNS3_PPU_MPF_ABNORMAL_INT3_EN;
1705 desc[1].data[4] = HNS3_PPU_MPF_ABNORMAL_INT2_EN;
1708 desc[1].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK;
1709 desc[1].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK;
1710 desc[1].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK;
1711 desc[1].data[3] |= HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK;
1714 case HNS3_OPC_PPU_MPF_OTHER_INT_CMD:
1715 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1717 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2;
1719 desc[0].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK;
1721 case HNS3_OPC_PPU_PF_OTHER_INT_CMD:
1722 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1724 desc[0].data[0] = HNS3_PPU_PF_ABNORMAL_INT_EN;
1726 desc[0].data[2] = HNS3_PPU_PF_ABNORMAL_INT_EN_MASK;
1730 "Invalid cmd(%u) to configure PPU error interrupts.",
1735 return hns3_cmd_send(hw, &desc[0], num);
1739 enable_ppu_err_intr(struct hns3_adapter *hns, bool en)
1741 struct hns3_hw *hw = &hns->hw;
1744 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_MPF_ECC_INT_CMD, en);
1746 hns3_err(hw, "fail to %s PPU MPF ECC error intr, ret = %d",
1747 en ? "enable" : "disable", ret);
1751 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_MPF_OTHER_INT_CMD, en);
1753 hns3_err(hw, "fail to %s PPU MPF other intr, ret = %d",
1754 en ? "enable" : "disable", ret);
1758 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_PF_OTHER_INT_CMD, en);
1760 hns3_err(hw, "fail to %s PPU PF error interrupts, ret = %d",
1761 en ? "enable" : "disable", ret);
1766 enable_tm_err_intr(struct hns3_adapter *hns, bool en)
1768 struct hns3_hw *hw = &hns->hw;
1769 struct hns3_cmd_desc desc;
1772 /* configure TM SCH error interrupts */
1773 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_SCH_ECC_INT_EN, false);
1775 desc.data[0] = rte_cpu_to_le_32(HNS3_TM_SCH_ECC_ERR_INT_EN);
1777 ret = hns3_cmd_send(hw, &desc, 1);
1779 hns3_err(hw, "fail to %s TM SCH interrupts, ret = %d",
1780 en ? "enable" : "disable", ret);
1784 /* configure TM QCN hw errors */
1785 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QCN_MEM_INT_CFG, false);
1787 desc.data[1] = rte_cpu_to_le_32(HNS3_TM_QCN_MEM_ERR_INT_EN);
1789 ret = hns3_cmd_send(hw, &desc, 1);
1791 hns3_err(hw, "fail to %s TM QCN mem errors, ret = %d\n",
1792 en ? "enable" : "disable", ret);
1798 enable_common_err_intr(struct hns3_adapter *hns, bool en)
1800 struct hns3_hw *hw = &hns->hw;
1801 struct hns3_cmd_desc desc[2];
1804 /* configure common error interrupts */
1805 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_COMMON_ECC_INT_CFG, false);
1806 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1807 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_COMMON_ECC_INT_CFG, false);
1811 rte_cpu_to_le_32(HNS3_IMP_TCM_ECC_ERR_INT_EN);
1813 rte_cpu_to_le_32(HNS3_CMDQ_NIC_ECC_ERR_INT_EN);
1815 rte_cpu_to_le_32(HNS3_IMP_RD_POISON_ERR_INT_EN);
1817 rte_cpu_to_le_32(HNS3_TQP_ECC_ERR_INT_EN |
1818 HNS3_MSIX_SRAM_ECC_ERR_INT_EN);
1820 rte_cpu_to_le_32(HNS3_IMP_ITCM4_ECC_ERR_INT_EN);
1823 desc[1].data[0] = rte_cpu_to_le_32(HNS3_IMP_TCM_ECC_ERR_INT_EN_MASK);
1824 desc[1].data[2] = rte_cpu_to_le_32(HNS3_CMDQ_NIC_ECC_ERR_INT_EN_MASK);
1825 desc[1].data[3] = rte_cpu_to_le_32(HNS3_IMP_RD_POISON_ERR_INT_EN_MASK);
1826 desc[1].data[4] = rte_cpu_to_le_32(HNS3_TQP_ECC_ERR_INT_EN_MASK |
1827 HNS3_MSIX_SRAM_ECC_ERR_INT_EN_MASK);
1828 desc[1].data[5] = rte_cpu_to_le_32(HNS3_IMP_ITCM4_ECC_ERR_INT_EN_MASK);
1830 ret = hns3_cmd_send(hw, &desc[0], RTE_DIM(desc));
1832 hns3_err(hw, "fail to %s common err interrupts, ret = %d\n",
1833 en ? "enable" : "disable", ret);
1839 enable_mac_err_intr(struct hns3_adapter *hns, bool en)
1841 struct hns3_hw *hw = &hns->hw;
1842 struct hns3_cmd_desc desc;
1845 /* configure MAC common error interrupts */
1846 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_COMMON_INT_EN, false);
1848 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN);
1850 desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN_MASK);
1852 ret = hns3_cmd_send(hw, &desc, 1);
1854 hns3_err(hw, "fail to %s MAC COMMON error intr: %d",
1855 en ? "enable" : "disable", ret);
1860 static const struct hns3_hw_blk hw_blk[] = {
1863 .enable_err_intr = enable_igu_egu_err_intr,
1867 .enable_err_intr = enable_ppp_err_intr,
1871 .enable_err_intr = enable_ssu_err_intr,
1875 .enable_err_intr = enable_ppu_err_intr,
1879 .enable_err_intr = enable_tm_err_intr,
1883 .enable_err_intr = enable_common_err_intr,
1887 .enable_err_intr = enable_mac_err_intr,
1891 .enable_err_intr = NULL,
1896 hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool en)
1898 const struct hns3_hw_blk *module = hw_blk;
1901 while (module->enable_err_intr) {
1902 ret = module->enable_err_intr(hns, en);
1912 static enum hns3_reset_level
1913 hns3_find_highest_level(struct hns3_adapter *hns, const char *reg,
1914 const struct hns3_hw_error *err, uint32_t err_sts)
1916 enum hns3_reset_level reset_level = HNS3_FUNC_RESET;
1917 struct hns3_hw *hw = &hns->hw;
1918 bool need_reset = false;
1921 if (err->int_msk & err_sts) {
1922 hns3_warn(hw, "%s %s found [error status=0x%x]",
1923 reg, err->msg, err_sts);
1924 if (err->reset_level != HNS3_NONE_RESET &&
1925 err->reset_level >= reset_level) {
1926 reset_level = err->reset_level;
1935 return HNS3_NONE_RESET;
1939 query_num_bds(struct hns3_hw *hw, bool is_ras, uint32_t *mpf_bd_num,
1940 uint32_t *pf_bd_num)
1942 uint32_t mpf_min_bd_num, pf_min_bd_num;
1943 uint32_t mpf_bd_num_val, pf_bd_num_val;
1944 enum hns3_opcode_type opcode;
1945 struct hns3_cmd_desc desc;
1949 opcode = HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM;
1950 mpf_min_bd_num = HNS3_MPF_RAS_INT_MIN_BD_NUM;
1951 pf_min_bd_num = HNS3_PF_RAS_INT_MIN_BD_NUM;
1953 opcode = HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM;
1954 mpf_min_bd_num = HNS3_MPF_MSIX_INT_MIN_BD_NUM;
1955 pf_min_bd_num = HNS3_PF_MSIX_INT_MIN_BD_NUM;
1958 hns3_cmd_setup_basic_desc(&desc, opcode, true);
1959 ret = hns3_cmd_send(hw, &desc, 1);
1961 hns3_err(hw, "query num bds in msix failed, ret = %d", ret);
1965 mpf_bd_num_val = rte_le_to_cpu_32(desc.data[0]);
1966 pf_bd_num_val = rte_le_to_cpu_32(desc.data[1]);
1967 if (mpf_bd_num_val < mpf_min_bd_num || pf_bd_num_val < pf_min_bd_num) {
1968 hns3_err(hw, "error bd num: mpf(%u), min_mpf(%u), "
1969 "pf(%u), min_pf(%u)\n", mpf_bd_num_val, mpf_min_bd_num,
1970 pf_bd_num_val, pf_min_bd_num);
1974 *mpf_bd_num = mpf_bd_num_val;
1975 *pf_bd_num = pf_bd_num_val;
1981 hns3_intr_unregister(const struct rte_intr_handle *hdl,
1982 rte_intr_callback_fn cb_fn, void *cb_arg)
1988 ret = rte_intr_callback_unregister(hdl, cb_fn, cb_arg);
1991 } else if (ret != -EAGAIN) {
1992 PMD_INIT_LOG(ERR, "Failed to unregister intr: %d", ret);
1995 rte_delay_ms(HNS3_INTR_UNREG_FAIL_DELAY_MS);
1996 } while (retry_cnt++ < HNS3_INTR_UNREG_FAIL_RETRY_CNT);
2000 hns3_get_hw_error_status(struct hns3_cmd_desc *desc, uint8_t desc_offset,
2001 uint8_t data_offset)
2004 uint32_t *desc_data;
2006 if (desc_offset == 0)
2007 status = rte_le_to_cpu_32(desc[desc_offset].data[data_offset]);
2009 desc_data = (uint32_t *)&desc[desc_offset];
2010 status = rte_le_to_cpu_32(*(desc_data + data_offset));
2017 hns3_handle_hw_error(struct hns3_adapter *hns, struct hns3_cmd_desc *desc,
2018 int num, uint64_t *levels,
2019 enum hns3_hw_err_report_type err_type)
2021 const struct hns3_hw_error_desc *err = pf_ras_err_tbl;
2022 enum hns3_opcode_type opcode;
2023 enum hns3_reset_level req_level;
2024 struct hns3_hw *hw = &hns->hw;
2030 err = mpf_msix_err_tbl;
2031 opcode = HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT;
2034 err = pf_msix_err_tbl;
2035 opcode = HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT;
2038 err = mpf_ras_err_tbl;
2039 opcode = HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT;
2042 err = pf_ras_err_tbl;
2043 opcode = HNS3_OPC_QUERY_CLEAR_PF_RAS_INT;
2046 hns3_err(hw, "error hardware err_type = %d\n", err_type);
2050 /* query all hardware errors */
2051 hns3_cmd_setup_basic_desc(&desc[0], opcode, true);
2052 ret = hns3_cmd_send(hw, &desc[0], num);
2054 hns3_err(hw, "query hw err int 0x%x cmd failed, ret = %d\n",
2059 /* traverses the error table and process based on the error type */
2061 status = hns3_get_hw_error_status(desc, err->desc_offset,
2065 * set the reset_level or non_reset flag based on
2066 * the error type and add error statistics. here just
2067 * set the flag, the actual reset action is in
2068 * hns3_msix_process.
2070 req_level = hns3_find_highest_level(hns, err->msg,
2073 hns3_atomic_set_bit(req_level, levels);
2078 /* clear all hardware errors */
2079 hns3_cmd_reuse_desc(&desc[0], false);
2080 ret = hns3_cmd_send(hw, &desc[0], num);
2082 hns3_err(hw, "clear all hw err int cmd failed, ret = %d\n",
2089 hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels)
2091 uint32_t mpf_bd_num, pf_bd_num, bd_num;
2092 struct hns3_hw *hw = &hns->hw;
2093 struct hns3_cmd_desc *desc;
2096 /* query the number of bds for the MSIx int status */
2097 ret = query_num_bds(hw, false, &mpf_bd_num, &pf_bd_num);
2099 hns3_err(hw, "fail to query msix int status bd num: ret = %d",
2104 bd_num = RTE_MAX(mpf_bd_num, pf_bd_num);
2105 desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0);
2108 "fail to zmalloc desc for handling msix error, size = %zu",
2109 bd_num * sizeof(struct hns3_cmd_desc));
2113 /* handle all main PF MSIx errors */
2114 ret = hns3_handle_hw_error(hns, desc, mpf_bd_num, levels, MPF_MSIX_ERR);
2116 hns3_err(hw, "fail to handle all main pf msix errors, ret = %d",
2121 memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc));
2123 /* handle all PF MSIx errors */
2124 ret = hns3_handle_hw_error(hns, desc, pf_bd_num, levels, PF_MSIX_ERR);
2126 hns3_err(hw, "fail to handle all pf msix errors, ret = %d",
2136 hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels)
2138 uint32_t mpf_bd_num, pf_bd_num, bd_num;
2139 struct hns3_hw *hw = &hns->hw;
2140 struct hns3_cmd_desc *desc;
2144 status = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
2145 if ((status & HNS3_RAS_REG_NFE_MASK) == 0)
2148 /* query the number of bds for the RAS int status */
2149 ret = query_num_bds(hw, true, &mpf_bd_num, &pf_bd_num);
2151 hns3_err(hw, "fail to query ras int status bd num: ret = %d",
2156 bd_num = RTE_MAX(mpf_bd_num, pf_bd_num);
2157 desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0);
2160 "fail to zmalloc desc for handing ras error, size = %zu",
2161 bd_num * sizeof(struct hns3_cmd_desc));
2165 /* handle all main PF RAS errors */
2166 ret = hns3_handle_hw_error(hns, desc, mpf_bd_num, levels, MPF_RAS_ERR);
2168 hns3_err(hw, "fail to handle all main pf ras errors, ret = %d",
2173 memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc));
2175 /* handle all PF RAS errors */
2176 ret = hns3_handle_hw_error(hns, desc, pf_bd_num, levels, PF_RAS_ERR);
2178 hns3_err(hw, "fail to handle all pf ras errors, ret = %d", ret);
2187 hns3_handle_type_reg_error_data(struct hns3_hw *hw,
2188 struct hns3_mod_err_info *mod_err_info,
2189 struct hns3_type_reg_err_info *err_info)
2191 #define HNS3_ERR_TYPE_MASK 0x7F
2192 #define HNS3_ERR_TYPE_IS_RAS_OFFSET 7
2194 uint8_t mod_id, total_module, type_id, total_type;
2198 mod_id = mod_err_info->mod_id;
2199 type_id = err_info->type_id & HNS3_ERR_TYPE_MASK;
2200 is_ras = err_info->type_id >> HNS3_ERR_TYPE_IS_RAS_OFFSET;
2202 total_module = RTE_DIM(hns3_hw_module_name);
2203 total_type = RTE_DIM(hns3_hw_error_type);
2205 hns3_err(hw, "total_module:%u, total_type:%u",
2206 total_module, total_type);
2208 if (mod_id < total_module && type_id < total_type)
2209 hns3_err(hw, "found %s %s, is %s error.",
2210 hns3_hw_module_name[mod_id].msg,
2211 hns3_hw_error_type[type_id].msg,
2212 is_ras ? "ras" : "msix");
2214 hns3_err(hw, "unknown module[%u] or type[%u].",
2217 hns3_err(hw, "reg_value:");
2218 for (i = 0; i < err_info->reg_num; i++)
2219 hns3_err(hw, "0x%08x", err_info->reg[i]);
2223 hns3_handle_module_error_data(struct hns3_hw *hw, uint32_t *buf,
2226 struct hns3_type_reg_err_info *type_reg_err_info;
2227 struct hns3_mod_err_info *mod_err_info;
2228 struct hns3_sum_err_info *sum_err_info;
2229 uint8_t mod_num, reset_type;
2230 uint32_t offset = 0;
2234 sum_err_info = (struct hns3_sum_err_info *)&buf[offset++];
2235 mod_num = sum_err_info->mod_num;
2236 reset_type = sum_err_info->reset_type;
2237 if (reset_type && reset_type != HNS3_NONE_RESET)
2238 hns3_atomic_set_bit(reset_type, &hw->reset.request);
2240 hns3_err(hw, "reset_type = %s, mod_num = %u.",
2241 reset_string[reset_type], mod_num);
2244 if (offset >= buf_size) {
2245 hns3_err(hw, "offset(%u) exceeds buf's size(%u).",
2249 mod_err_info = (struct hns3_mod_err_info *)&buf[offset++];
2250 err_num = mod_err_info->err_num;
2251 for (i = 0; i < err_num; i++) {
2252 if (offset >= buf_size) {
2254 "offset(%u) exceeds buf size(%u).",
2259 type_reg_err_info = (struct hns3_type_reg_err_info *)
2261 hns3_handle_type_reg_error_data(hw, mod_err_info,
2264 offset += type_reg_err_info->reg_num;
2270 hns3_query_all_err_bd_num(struct hns3_hw *hw, uint32_t *bd_num)
2272 struct hns3_cmd_desc desc;
2273 uint32_t bd_num_data;
2276 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_ALL_ERR_BD_NUM, true);
2277 ret = hns3_cmd_send(hw, &desc, 1);
2279 hns3_err(hw, "failed to query error bd_num, ret = %d.", ret);
2283 bd_num_data = rte_le_to_cpu_32(desc.data[0]);
2284 *bd_num = bd_num_data;
2285 if (bd_num_data == 0) {
2286 hns3_err(hw, "the value of bd_num is 0!");
2294 hns3_query_all_err_info(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
2299 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_QUERY_ALL_ERR_INFO, true);
2300 ret = hns3_cmd_send(hw, desc, bd_num);
2302 hns3_err(hw, "failed to query error info, ret = %d.", ret);
2310 hns3_handle_hw_error_v2(struct hns3_hw *hw)
2312 uint32_t bd_num, buf_len, i, buf_size;
2313 struct hns3_cmd_desc *desc;
2314 uint32_t *desc_data;
2318 ret = hns3_query_all_err_bd_num(hw, &bd_num);
2322 desc = rte_zmalloc("hns3_ras", bd_num * sizeof(struct hns3_cmd_desc),
2325 hns3_err(hw, "failed to malloc hns3 ras cmd desc.");
2329 ret = hns3_query_all_err_info(hw, desc, bd_num);
2333 buf_len = bd_num * sizeof(struct hns3_cmd_desc) - HNS3_DESC_NO_DATA_LEN;
2334 buf_size = buf_len / HNS3_DESC_DATA_UNIT_SIZE;
2336 desc_data = rte_zmalloc("hns3_ras", buf_len, 0);
2337 if (desc_data == NULL) {
2338 hns3_err(hw, "failed to malloc hns3 ras desc data.");
2342 buf = rte_zmalloc("hns3_ras", buf_len, 0);
2344 hns3_err(hw, "failed to malloc hns3 ras buf data.");
2348 memcpy(desc_data, &desc[0].data[0], buf_len);
2349 for (i = 0; i < buf_size; i++)
2350 buf[i] = rte_le_to_cpu_32(desc_data[i]);
2352 hns3_handle_module_error_data(hw, buf, buf_size);
2356 rte_free(desc_data);
2364 hns3_handle_error(struct hns3_adapter *hns)
2366 struct hns3_hw *hw = &hns->hw;
2368 if (hns3_dev_ras_imp_supported(hw)) {
2369 hns3_handle_hw_error_v2(hw);
2370 hns3_schedule_reset(hns);
2372 hns3_handle_msix_error(hns, &hw->reset.request);
2373 hns3_handle_ras_error(hns, &hw->reset.request);
2374 hns3_schedule_reset(hns);
2379 hns3_reset_init(struct hns3_hw *hw)
2381 rte_spinlock_init(&hw->lock);
2382 hw->reset.level = HNS3_NONE_RESET;
2383 hw->reset.stage = RESET_STAGE_NONE;
2384 hw->reset.request = 0;
2385 hw->reset.pending = 0;
2386 hw->reset.resetting = 0;
2387 __atomic_store_n(&hw->reset.disable_cmd, 0, __ATOMIC_RELAXED);
2388 hw->reset.wait_data = rte_zmalloc("wait_data",
2389 sizeof(struct hns3_wait_data), 0);
2390 if (!hw->reset.wait_data) {
2391 PMD_INIT_LOG(ERR, "Failed to allocate memory for wait_data");
2398 hns3_schedule_reset(struct hns3_adapter *hns)
2400 struct hns3_hw *hw = &hns->hw;
2402 /* Reschedule the reset process after successful initialization */
2403 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {
2404 __atomic_store_n(&hw->reset.schedule, SCHEDULE_PENDING,
2409 if (hw->adapter_state >= HNS3_NIC_CLOSED)
2412 /* Schedule restart alarm if it is not scheduled yet */
2413 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2416 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2418 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);
2420 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2423 rte_eal_alarm_set(SWITCH_CONTEXT_US, hw->reset.ops->reset_service, hns);
2427 hns3_schedule_delayed_reset(struct hns3_adapter *hns)
2429 #define DEFERRED_SCHED_US (3 * MSEC_PER_SEC * USEC_PER_MSEC)
2430 struct hns3_hw *hw = &hns->hw;
2432 /* Do nothing if it is uninited or closed */
2433 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED ||
2434 hw->adapter_state >= HNS3_NIC_CLOSED) {
2438 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) !=
2441 __atomic_store_n(&hw->reset.schedule, SCHEDULE_DEFERRED,
2443 rte_eal_alarm_set(DEFERRED_SCHED_US, hw->reset.ops->reset_service, hns);
2447 hns3_wait_callback(void *param)
2449 struct hns3_wait_data *data = (struct hns3_wait_data *)param;
2450 struct hns3_adapter *hns = data->hns;
2451 struct hns3_hw *hw = &hns->hw;
2456 if (data->check_completion) {
2458 * Check if the current time exceeds the deadline
2459 * or a pending reset coming, or reset during close.
2461 msec = hns3_clock_gettime_ms();
2462 if (msec > data->end_ms || is_reset_pending(hns) ||
2463 hw->adapter_state == HNS3_NIC_CLOSING) {
2467 done = data->check_completion(hw);
2471 if (!done && data->count > 0) {
2472 rte_eal_alarm_set(data->interval, hns3_wait_callback, data);
2476 data->result = HNS3_WAIT_SUCCESS;
2478 hns3_err(hw, "%s wait timeout at stage %d",
2479 reset_string[hw->reset.level], hw->reset.stage);
2480 data->result = HNS3_WAIT_TIMEOUT;
2482 hns3_schedule_reset(hns);
2486 hns3_notify_reset_ready(struct hns3_hw *hw, bool enable)
2490 reg_val = hns3_read_dev(hw, HNS3_CMDQ_TX_DEPTH_REG);
2492 reg_val |= HNS3_NIC_SW_RST_RDY;
2494 reg_val &= ~HNS3_NIC_SW_RST_RDY;
2496 hns3_write_dev(hw, HNS3_CMDQ_TX_DEPTH_REG, reg_val);
2500 hns3_reset_req_hw_reset(struct hns3_adapter *hns)
2502 struct hns3_hw *hw = &hns->hw;
2504 if (hw->reset.wait_data->result == HNS3_WAIT_UNKNOWN) {
2505 hw->reset.wait_data->hns = hns;
2506 hw->reset.wait_data->check_completion = NULL;
2507 hw->reset.wait_data->interval = HNS3_RESET_SYNC_US;
2508 hw->reset.wait_data->count = 1;
2509 hw->reset.wait_data->result = HNS3_WAIT_REQUEST;
2510 rte_eal_alarm_set(hw->reset.wait_data->interval,
2511 hns3_wait_callback, hw->reset.wait_data);
2513 } else if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)
2516 /* inform hardware that preparatory work is done */
2517 hns3_notify_reset_ready(hw, true);
2522 hns3_clear_reset_level(struct hns3_hw *hw, uint64_t *levels)
2524 uint64_t merge_cnt = hw->reset.stats.merge_cnt;
2527 switch (hw->reset.level) {
2528 case HNS3_IMP_RESET:
2529 hns3_atomic_clear_bit(HNS3_IMP_RESET, levels);
2530 tmp = hns3_test_and_clear_bit(HNS3_GLOBAL_RESET, levels);
2531 HNS3_CHECK_MERGE_CNT(tmp);
2532 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);
2533 HNS3_CHECK_MERGE_CNT(tmp);
2535 case HNS3_GLOBAL_RESET:
2536 hns3_atomic_clear_bit(HNS3_GLOBAL_RESET, levels);
2537 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);
2538 HNS3_CHECK_MERGE_CNT(tmp);
2540 case HNS3_FUNC_RESET:
2541 hns3_atomic_clear_bit(HNS3_FUNC_RESET, levels);
2544 hns3_atomic_clear_bit(HNS3_VF_RESET, levels);
2545 tmp = hns3_test_and_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);
2546 HNS3_CHECK_MERGE_CNT(tmp);
2547 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
2548 HNS3_CHECK_MERGE_CNT(tmp);
2550 case HNS3_VF_FULL_RESET:
2551 hns3_atomic_clear_bit(HNS3_VF_FULL_RESET, levels);
2552 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
2553 HNS3_CHECK_MERGE_CNT(tmp);
2555 case HNS3_VF_PF_FUNC_RESET:
2556 hns3_atomic_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);
2557 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
2558 HNS3_CHECK_MERGE_CNT(tmp);
2560 case HNS3_VF_FUNC_RESET:
2561 hns3_atomic_clear_bit(HNS3_VF_FUNC_RESET, levels);
2563 case HNS3_FLR_RESET:
2564 hns3_atomic_clear_bit(HNS3_FLR_RESET, levels);
2566 case HNS3_NONE_RESET:
2570 if (merge_cnt != hw->reset.stats.merge_cnt)
2572 "No need to do low-level reset after %s reset. "
2573 "merge cnt: %" PRIx64 " total merge cnt: %" PRIx64,
2574 reset_string[hw->reset.level],
2575 hw->reset.stats.merge_cnt - merge_cnt,
2576 hw->reset.stats.merge_cnt);
2580 hns3_reset_err_handle(struct hns3_adapter *hns)
2582 #define MAX_RESET_FAIL_CNT 5
2584 struct hns3_hw *hw = &hns->hw;
2586 if (hw->adapter_state == HNS3_NIC_CLOSING)
2589 if (is_reset_pending(hns)) {
2590 hw->reset.attempts = 0;
2591 hw->reset.stats.fail_cnt++;
2592 hns3_warn(hw, "%s reset fail because new Reset is pending "
2593 "attempts:%" PRIx64,
2594 reset_string[hw->reset.level],
2595 hw->reset.stats.fail_cnt);
2596 hw->reset.level = HNS3_NONE_RESET;
2600 hw->reset.attempts++;
2601 if (hw->reset.attempts < MAX_RESET_FAIL_CNT) {
2602 hns3_atomic_set_bit(hw->reset.level, &hw->reset.pending);
2603 hns3_warn(hw, "%s retry to reset attempts: %d",
2604 reset_string[hw->reset.level],
2605 hw->reset.attempts);
2610 * Failure to reset does not mean that the network port is
2611 * completely unavailable, so cmd still needs to be initialized.
2612 * Regardless of whether the execution is successful or not, the
2613 * flow after execution must be continued.
2615 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED))
2616 (void)hns3_cmd_init(hw);
2618 hw->reset.attempts = 0;
2619 hw->reset.stats.fail_cnt++;
2620 hns3_warn(hw, "%s reset fail fail_cnt:%" PRIx64 " success_cnt:%" PRIx64
2621 " global_cnt:%" PRIx64 " imp_cnt:%" PRIx64
2622 " request_cnt:%" PRIx64 " exec_cnt:%" PRIx64
2623 " merge_cnt:%" PRIx64 "adapter_state:%d",
2624 reset_string[hw->reset.level], hw->reset.stats.fail_cnt,
2625 hw->reset.stats.success_cnt, hw->reset.stats.global_cnt,
2626 hw->reset.stats.imp_cnt, hw->reset.stats.request_cnt,
2627 hw->reset.stats.exec_cnt, hw->reset.stats.merge_cnt,
2630 /* IMP no longer waiting the ready flag */
2631 hns3_notify_reset_ready(hw, true);
2636 hns3_reset_pre(struct hns3_adapter *hns)
2638 struct hns3_hw *hw = &hns->hw;
2642 if (hw->reset.stage == RESET_STAGE_NONE) {
2643 __atomic_store_n(&hns->hw.reset.resetting, 1, __ATOMIC_RELAXED);
2644 hw->reset.stage = RESET_STAGE_DOWN;
2645 ret = hw->reset.ops->stop_service(hns);
2646 hns3_clock_gettime(&tv);
2648 hns3_warn(hw, "Reset step1 down fail=%d time=%ld.%.6ld",
2649 ret, tv.tv_sec, tv.tv_usec);
2652 hns3_warn(hw, "Reset step1 down success time=%ld.%.6ld",
2653 tv.tv_sec, tv.tv_usec);
2654 hw->reset.stage = RESET_STAGE_PREWAIT;
2656 if (hw->reset.stage == RESET_STAGE_PREWAIT) {
2657 ret = hw->reset.ops->prepare_reset(hns);
2658 hns3_clock_gettime(&tv);
2661 "Reset step2 prepare wait fail=%d time=%ld.%.6ld",
2662 ret, tv.tv_sec, tv.tv_usec);
2665 hns3_warn(hw, "Reset step2 prepare wait success time=%ld.%.6ld",
2666 tv.tv_sec, tv.tv_usec);
2667 hw->reset.stage = RESET_STAGE_REQ_HW_RESET;
2668 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;
2674 hns3_reset_post(struct hns3_adapter *hns)
2676 #define TIMEOUT_RETRIES_CNT 5
2677 struct hns3_hw *hw = &hns->hw;
2678 struct timeval tv_delta;
2682 if (hw->adapter_state == HNS3_NIC_CLOSING) {
2683 hns3_warn(hw, "Don't do reset_post during closing, just uninit cmd");
2684 hns3_cmd_uninit(hw);
2688 if (hw->reset.stage == RESET_STAGE_DEV_INIT) {
2689 rte_spinlock_lock(&hw->lock);
2690 if (hw->reset.mbuf_deferred_free) {
2691 hns3_dev_release_mbufs(hns);
2692 hw->reset.mbuf_deferred_free = false;
2694 ret = hw->reset.ops->reinit_dev(hns);
2695 rte_spinlock_unlock(&hw->lock);
2696 hns3_clock_gettime(&tv);
2698 hns3_warn(hw, "Reset step5 devinit fail=%d retries=%d",
2699 ret, hw->reset.retries);
2702 hns3_warn(hw, "Reset step5 devinit success time=%ld.%.6ld",
2703 tv.tv_sec, tv.tv_usec);
2704 hw->reset.retries = 0;
2705 hw->reset.stage = RESET_STAGE_RESTORE;
2706 rte_eal_alarm_set(SWITCH_CONTEXT_US,
2707 hw->reset.ops->reset_service, hns);
2710 if (hw->reset.stage == RESET_STAGE_RESTORE) {
2711 rte_spinlock_lock(&hw->lock);
2712 ret = hw->reset.ops->restore_conf(hns);
2713 rte_spinlock_unlock(&hw->lock);
2714 hns3_clock_gettime(&tv);
2717 "Reset step6 restore fail=%d retries=%d",
2718 ret, hw->reset.retries);
2721 hns3_warn(hw, "Reset step6 restore success time=%ld.%.6ld",
2722 tv.tv_sec, tv.tv_usec);
2723 hw->reset.retries = 0;
2724 hw->reset.stage = RESET_STAGE_DONE;
2726 if (hw->reset.stage == RESET_STAGE_DONE) {
2727 /* IMP will wait ready flag before reset */
2728 hns3_notify_reset_ready(hw, false);
2729 hns3_clear_reset_level(hw, &hw->reset.pending);
2730 __atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED);
2731 hw->reset.attempts = 0;
2732 hw->reset.stats.success_cnt++;
2733 hw->reset.stage = RESET_STAGE_NONE;
2734 rte_spinlock_lock(&hw->lock);
2735 hw->reset.ops->start_service(hns);
2736 rte_spinlock_unlock(&hw->lock);
2737 hns3_clock_gettime(&tv);
2738 timersub(&tv, &hw->reset.start_time, &tv_delta);
2739 hns3_warn(hw, "%s reset done fail_cnt:%" PRIx64
2740 " success_cnt:%" PRIx64 " global_cnt:%" PRIx64
2741 " imp_cnt:%" PRIx64 " request_cnt:%" PRIx64
2742 " exec_cnt:%" PRIx64 " merge_cnt:%" PRIx64,
2743 reset_string[hw->reset.level],
2744 hw->reset.stats.fail_cnt, hw->reset.stats.success_cnt,
2745 hw->reset.stats.global_cnt, hw->reset.stats.imp_cnt,
2746 hw->reset.stats.request_cnt, hw->reset.stats.exec_cnt,
2747 hw->reset.stats.merge_cnt);
2749 "%s reset done delta %" PRIu64 " ms time=%ld.%.6ld",
2750 reset_string[hw->reset.level],
2751 hns3_clock_calctime_ms(&tv_delta),
2752 tv.tv_sec, tv.tv_usec);
2753 hw->reset.level = HNS3_NONE_RESET;
2758 if (ret == -ETIME) {
2759 hw->reset.retries++;
2760 if (hw->reset.retries < TIMEOUT_RETRIES_CNT) {
2761 rte_eal_alarm_set(HNS3_RESET_SYNC_US,
2762 hw->reset.ops->reset_service, hns);
2766 hw->reset.retries = 0;
2771 * There are three scenarios as follows:
2772 * When the reset is not in progress, the reset process starts.
2773 * During the reset process, if the reset level has not changed,
2774 * the reset process continues; otherwise, the reset process is aborted.
2775 * hw->reset.level new_level action
2776 * HNS3_NONE_RESET HNS3_XXXX_RESET start reset
2777 * HNS3_XXXX_RESET HNS3_XXXX_RESET continue reset
2778 * HNS3_LOW_RESET HNS3_HIGH_RESET abort
2781 hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level)
2783 struct hns3_hw *hw = &hns->hw;
2784 struct timeval tv_delta;
2788 if (hw->reset.level == HNS3_NONE_RESET) {
2789 hw->reset.level = new_level;
2790 hw->reset.stats.exec_cnt++;
2791 hns3_clock_gettime(&hw->reset.start_time);
2792 hns3_warn(hw, "Start %s reset time=%ld.%.6ld",
2793 reset_string[hw->reset.level],
2794 hw->reset.start_time.tv_sec,
2795 hw->reset.start_time.tv_usec);
2798 if (is_reset_pending(hns)) {
2799 hns3_clock_gettime(&tv);
2801 "%s reset is aborted by high level time=%ld.%.6ld",
2802 reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);
2803 if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)
2804 rte_eal_alarm_cancel(hns3_wait_callback,
2805 hw->reset.wait_data);
2809 ret = hns3_reset_pre(hns);
2813 if (hw->reset.stage == RESET_STAGE_REQ_HW_RESET) {
2814 ret = hns3_reset_req_hw_reset(hns);
2817 hns3_clock_gettime(&tv);
2819 "Reset step3 request IMP reset success time=%ld.%.6ld",
2820 tv.tv_sec, tv.tv_usec);
2821 hw->reset.stage = RESET_STAGE_WAIT;
2822 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;
2824 if (hw->reset.stage == RESET_STAGE_WAIT) {
2825 ret = hw->reset.ops->wait_hardware_ready(hns);
2828 hns3_clock_gettime(&tv);
2829 hns3_warn(hw, "Reset step4 reset wait success time=%ld.%.6ld",
2830 tv.tv_sec, tv.tv_usec);
2831 hw->reset.stage = RESET_STAGE_DEV_INIT;
2834 ret = hns3_reset_post(hns);
2843 hns3_clear_reset_level(hw, &hw->reset.pending);
2844 if (hns3_reset_err_handle(hns)) {
2845 hw->reset.stage = RESET_STAGE_PREWAIT;
2846 hns3_schedule_reset(hns);
2848 rte_spinlock_lock(&hw->lock);
2849 if (hw->reset.mbuf_deferred_free) {
2850 hns3_dev_release_mbufs(hns);
2851 hw->reset.mbuf_deferred_free = false;
2853 rte_spinlock_unlock(&hw->lock);
2854 __atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED);
2855 hw->reset.stage = RESET_STAGE_NONE;
2856 hns3_clock_gettime(&tv);
2857 timersub(&tv, &hw->reset.start_time, &tv_delta);
2858 hns3_warn(hw, "%s reset fail delta %" PRIu64 " ms time=%ld.%.6ld",
2859 reset_string[hw->reset.level],
2860 hns3_clock_calctime_ms(&tv_delta),
2861 tv.tv_sec, tv.tv_usec);
2862 hw->reset.level = HNS3_NONE_RESET;
2869 * The reset process can only be terminated after handshake with IMP(step3),
2870 * so that IMP can complete the reset process normally.
2873 hns3_reset_abort(struct hns3_adapter *hns)
2875 struct hns3_hw *hw = &hns->hw;
2879 for (i = 0; i < HNS3_QUIT_RESET_CNT; i++) {
2880 if (hw->reset.level == HNS3_NONE_RESET)
2882 rte_delay_ms(HNS3_QUIT_RESET_DELAY_MS);
2885 /* IMP no longer waiting the ready flag */
2886 hns3_notify_reset_ready(hw, true);
2888 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);
2889 rte_eal_alarm_cancel(hns3_wait_callback, hw->reset.wait_data);
2891 if (hw->reset.level != HNS3_NONE_RESET) {
2892 hns3_clock_gettime(&tv);
2893 hns3_err(hw, "Failed to terminate reset: %s time=%ld.%.6ld",
2894 reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);
2899 hns3_report_lse(void *arg)
2901 struct rte_eth_dev *dev = (struct rte_eth_dev *)arg;
2902 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2904 if (hw->adapter_state == HNS3_NIC_STARTED)
2905 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2909 hns3_start_report_lse(struct rte_eth_dev *dev)
2911 #define DELAY_REPORT_LSE_US 1
2913 * When this function called, the context may hold hns3_hw.lock, if
2914 * report lse right now, in some application such as bonding, it will
2915 * trigger call driver's ops which may acquire hns3_hw.lock again, so
2917 * Here we use delay report to avoid the deadlock.
2919 rte_eal_alarm_set(DELAY_REPORT_LSE_US, hns3_report_lse, dev);
2923 hns3_stop_report_lse(struct rte_eth_dev *dev)
2925 rte_eal_alarm_cancel(hns3_report_lse, dev);