1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
6 #include <rte_atomic.h>
8 #include <rte_cycles.h>
9 #include <rte_ethdev.h>
11 #include <rte_malloc.h>
13 #include <rte_bus_pci.h>
15 #include "hns3_ethdev.h"
16 #include "hns3_logs.h"
17 #include "hns3_intr.h"
18 #include "hns3_regs.h"
19 #include "hns3_rxtx.h"
21 #define SWITCH_CONTEXT_US 10
23 /* offset in MSIX bd */
24 #define MAC_ERROR_OFFSET 1
25 #define PPP_PF_ERROR_OFFSET 2
26 #define PPU_PF_ERROR_OFFSET 3
27 #define RCB_ERROR_OFFSET 5
28 #define RCB_ERROR_STATUS_OFFSET 2
30 #define HNS3_CHECK_MERGE_CNT(val) \
33 hw->reset.stats.merge_cnt++; \
36 static const char *reset_string[HNS3_MAX_RESET] = {
37 "none", "vf_func", "vf_pf_func", "vf_full", "flr",
38 "vf_global", "pf_func", "global", "IMP",
41 const struct hns3_hw_error mac_afifo_tnl_int[] = {
42 { .int_msk = BIT(0), .msg = "egu_cge_afifo_ecc_1bit_err",
43 .reset_level = HNS3_NONE_RESET },
44 { .int_msk = BIT(1), .msg = "egu_cge_afifo_ecc_mbit_err",
45 .reset_level = HNS3_GLOBAL_RESET },
46 { .int_msk = BIT(2), .msg = "egu_lge_afifo_ecc_1bit_err",
47 .reset_level = HNS3_NONE_RESET },
48 { .int_msk = BIT(3), .msg = "egu_lge_afifo_ecc_mbit_err",
49 .reset_level = HNS3_GLOBAL_RESET },
50 { .int_msk = BIT(4), .msg = "cge_igu_afifo_ecc_1bit_err",
51 .reset_level = HNS3_NONE_RESET },
52 { .int_msk = BIT(5), .msg = "cge_igu_afifo_ecc_mbit_err",
53 .reset_level = HNS3_GLOBAL_RESET },
54 { .int_msk = BIT(6), .msg = "lge_igu_afifo_ecc_1bit_err",
55 .reset_level = HNS3_NONE_RESET },
56 { .int_msk = BIT(7), .msg = "lge_igu_afifo_ecc_mbit_err",
57 .reset_level = HNS3_GLOBAL_RESET },
58 { .int_msk = BIT(8), .msg = "cge_igu_afifo_overflow_err",
59 .reset_level = HNS3_GLOBAL_RESET },
60 { .int_msk = BIT(9), .msg = "lge_igu_afifo_overflow_err",
61 .reset_level = HNS3_GLOBAL_RESET },
62 { .int_msk = BIT(10), .msg = "egu_cge_afifo_underrun_err",
63 .reset_level = HNS3_GLOBAL_RESET },
64 { .int_msk = BIT(11), .msg = "egu_lge_afifo_underrun_err",
65 .reset_level = HNS3_GLOBAL_RESET },
66 { .int_msk = BIT(12), .msg = "egu_ge_afifo_underrun_err",
67 .reset_level = HNS3_GLOBAL_RESET },
68 { .int_msk = BIT(13), .msg = "ge_igu_afifo_overflow_err",
69 .reset_level = HNS3_GLOBAL_RESET },
70 { .int_msk = 0, .msg = NULL,
71 .reset_level = HNS3_NONE_RESET}
74 const struct hns3_hw_error ppu_mpf_abnormal_int_st2[] = {
75 { .int_msk = BIT(13), .msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
76 .reset_level = HNS3_GLOBAL_RESET },
77 { .int_msk = BIT(14), .msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
78 .reset_level = HNS3_GLOBAL_RESET },
79 { .int_msk = BIT(15), .msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
80 .reset_level = HNS3_GLOBAL_RESET },
81 { .int_msk = BIT(16), .msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
82 .reset_level = HNS3_GLOBAL_RESET },
83 { .int_msk = BIT(17), .msg = "rcb_tx_ring_ecc_mbit_err",
84 .reset_level = HNS3_GLOBAL_RESET },
85 { .int_msk = BIT(18), .msg = "rcb_rx_ring_ecc_mbit_err",
86 .reset_level = HNS3_GLOBAL_RESET },
87 { .int_msk = BIT(19), .msg = "rcb_tx_fbd_ecc_mbit_err",
88 .reset_level = HNS3_GLOBAL_RESET },
89 { .int_msk = BIT(20), .msg = "rcb_rx_ebd_ecc_mbit_err",
90 .reset_level = HNS3_GLOBAL_RESET },
91 { .int_msk = BIT(21), .msg = "rcb_tso_info_ecc_mbit_err",
92 .reset_level = HNS3_GLOBAL_RESET },
93 { .int_msk = BIT(22), .msg = "rcb_tx_int_info_ecc_mbit_err",
94 .reset_level = HNS3_GLOBAL_RESET },
95 { .int_msk = BIT(23), .msg = "rcb_rx_int_info_ecc_mbit_err",
96 .reset_level = HNS3_GLOBAL_RESET },
97 { .int_msk = BIT(24), .msg = "tpu_tx_pkt_0_ecc_mbit_err",
98 .reset_level = HNS3_GLOBAL_RESET },
99 { .int_msk = BIT(25), .msg = "tpu_tx_pkt_1_ecc_mbit_err",
100 .reset_level = HNS3_GLOBAL_RESET },
101 { .int_msk = BIT(26), .msg = "rd_bus_err",
102 .reset_level = HNS3_GLOBAL_RESET },
103 { .int_msk = BIT(27), .msg = "wr_bus_err",
104 .reset_level = HNS3_GLOBAL_RESET },
105 { .int_msk = BIT(28), .msg = "reg_search_miss",
106 .reset_level = HNS3_GLOBAL_RESET },
107 { .int_msk = BIT(29), .msg = "rx_q_search_miss",
108 .reset_level = HNS3_NONE_RESET },
109 { .int_msk = BIT(30), .msg = "ooo_ecc_err_detect",
110 .reset_level = HNS3_NONE_RESET },
111 { .int_msk = BIT(31), .msg = "ooo_ecc_err_multpl",
112 .reset_level = HNS3_GLOBAL_RESET },
113 { .int_msk = 0, .msg = NULL,
114 .reset_level = HNS3_NONE_RESET}
117 const struct hns3_hw_error ssu_port_based_pf_int[] = {
118 { .int_msk = BIT(0), .msg = "roc_pkt_without_key_port",
119 .reset_level = HNS3_GLOBAL_RESET },
120 { .int_msk = BIT(9), .msg = "low_water_line_err_port",
121 .reset_level = HNS3_NONE_RESET },
122 { .int_msk = BIT(10), .msg = "hi_water_line_err_port",
123 .reset_level = HNS3_GLOBAL_RESET },
124 { .int_msk = 0, .msg = NULL,
125 .reset_level = HNS3_NONE_RESET}
128 const struct hns3_hw_error ppp_pf_abnormal_int[] = {
129 { .int_msk = BIT(0), .msg = "tx_vlan_tag_err",
130 .reset_level = HNS3_NONE_RESET },
131 { .int_msk = BIT(1), .msg = "rss_list_tc_unassigned_queue_err",
132 .reset_level = HNS3_NONE_RESET },
133 { .int_msk = 0, .msg = NULL,
134 .reset_level = HNS3_NONE_RESET}
137 const struct hns3_hw_error ppu_pf_abnormal_int[] = {
138 { .int_msk = BIT(0), .msg = "over_8bd_no_fe",
139 .reset_level = HNS3_FUNC_RESET },
140 { .int_msk = BIT(1), .msg = "tso_mss_cmp_min_err",
141 .reset_level = HNS3_NONE_RESET },
142 { .int_msk = BIT(2), .msg = "tso_mss_cmp_max_err",
143 .reset_level = HNS3_NONE_RESET },
144 { .int_msk = BIT(3), .msg = "tx_rd_fbd_poison",
145 .reset_level = HNS3_FUNC_RESET },
146 { .int_msk = BIT(4), .msg = "rx_rd_ebd_poison",
147 .reset_level = HNS3_FUNC_RESET },
148 { .int_msk = BIT(5), .msg = "buf_wait_timeout",
149 .reset_level = HNS3_NONE_RESET },
150 { .int_msk = 0, .msg = NULL,
151 .reset_level = HNS3_NONE_RESET}
155 config_ppp_err_intr(struct hns3_adapter *hns, uint32_t cmd, bool en)
157 struct hns3_hw *hw = &hns->hw;
158 struct hns3_cmd_desc desc[2];
161 /* configure PPP error interrupts */
162 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
163 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
164 hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
166 if (cmd == HNS3_PPP_CMD0_INT_CMD) {
169 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN);
171 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN);
173 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN);
177 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK);
179 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK);
181 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN_MASK);
182 } else if (cmd == HNS3_PPP_CMD1_INT_CMD) {
185 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN);
187 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN);
191 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK);
193 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK);
196 ret = hns3_cmd_send(hw, &desc[0], 2);
198 hns3_err(hw, "fail to configure PPP error int: %d", ret);
204 enable_ppp_err_intr(struct hns3_adapter *hns, bool en)
208 ret = config_ppp_err_intr(hns, HNS3_PPP_CMD0_INT_CMD, en);
212 return config_ppp_err_intr(hns, HNS3_PPP_CMD1_INT_CMD, en);
216 enable_ssu_err_intr(struct hns3_adapter *hns, bool en)
218 struct hns3_hw *hw = &hns->hw;
219 struct hns3_cmd_desc desc[2];
222 /* configure SSU ecc error interrupts */
223 hns3_cmd_setup_basic_desc(&desc[0], HNS3_SSU_ECC_INT_CMD, false);
224 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
225 hns3_cmd_setup_basic_desc(&desc[1], HNS3_SSU_ECC_INT_CMD, false);
228 rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN);
230 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN);
232 rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN);
235 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK);
237 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK);
238 desc[1].data[2] = rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK);
240 ret = hns3_cmd_send(hw, &desc[0], 2);
242 hns3_err(hw, "fail to configure SSU ECC error interrupt: %d",
247 /* configure SSU common error interrupts */
248 hns3_cmd_setup_basic_desc(&desc[0], HNS3_SSU_COMMON_INT_CMD, false);
249 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
250 hns3_cmd_setup_basic_desc(&desc[1], HNS3_SSU_COMMON_INT_CMD, false);
253 desc[0].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN);
255 rte_cpu_to_le_32(HNS3_SSU_PORT_BASED_ERR_INT_EN);
257 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN);
260 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN_MASK |
261 HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK);
263 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK);
265 ret = hns3_cmd_send(hw, &desc[0], 2);
267 hns3_err(hw, "fail to configure SSU COMMON error intr: %d",
274 config_ppu_err_intrs(struct hns3_adapter *hns, uint32_t cmd, bool en)
276 struct hns3_hw *hw = &hns->hw;
277 struct hns3_cmd_desc desc[2];
280 /* configure PPU error interrupts */
282 case HNS3_PPU_MPF_ECC_INT_CMD:
283 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
284 desc[0].flag |= HNS3_CMD_FLAG_NEXT;
285 hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
287 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN;
288 desc[0].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN;
289 desc[1].data[3] = HNS3_PPU_MPF_ABNORMAL_INT3_EN;
290 desc[1].data[4] = HNS3_PPU_MPF_ABNORMAL_INT2_EN;
293 desc[1].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK;
294 desc[1].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK;
295 desc[1].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK;
296 desc[1].data[3] |= HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK;
299 case HNS3_PPU_MPF_OTHER_INT_CMD:
300 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
302 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2;
304 desc[0].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK;
306 case HNS3_PPU_PF_OTHER_INT_CMD:
307 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
309 desc[0].data[0] = HNS3_PPU_PF_ABNORMAL_INT_EN;
311 desc[0].data[2] = HNS3_PPU_PF_ABNORMAL_INT_EN_MASK;
315 "Invalid cmd(%u) to configure PPU error interrupts.",
320 return hns3_cmd_send(hw, &desc[0], num);
324 enable_ppu_err_intr(struct hns3_adapter *hns, bool en)
326 struct hns3_hw *hw = &hns->hw;
329 ret = config_ppu_err_intrs(hns, HNS3_PPU_MPF_ECC_INT_CMD, en);
331 hns3_err(hw, "fail to configure PPU MPF ECC error intr: %d",
336 ret = config_ppu_err_intrs(hns, HNS3_PPU_MPF_OTHER_INT_CMD, en);
338 hns3_err(hw, "fail to configure PPU MPF other intr: %d",
343 ret = config_ppu_err_intrs(hns, HNS3_PPU_PF_OTHER_INT_CMD, en);
345 hns3_err(hw, "fail to configure PPU PF error interrupts: %d",
351 enable_mac_err_intr(struct hns3_adapter *hns, bool en)
353 struct hns3_hw *hw = &hns->hw;
354 struct hns3_cmd_desc desc;
357 /* configure MAC common error interrupts */
358 hns3_cmd_setup_basic_desc(&desc, HNS3_MAC_COMMON_INT_EN, false);
360 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN);
362 desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN_MASK);
364 ret = hns3_cmd_send(hw, &desc, 1);
366 hns3_err(hw, "fail to configure MAC COMMON error intr: %d",
372 static const struct hns3_hw_blk hw_blk[] = {
375 .enable_err_intr = enable_ppp_err_intr,
379 .enable_err_intr = enable_ssu_err_intr,
383 .enable_err_intr = enable_ppu_err_intr,
387 .enable_err_intr = enable_mac_err_intr,
391 .enable_err_intr = NULL,
396 hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool en)
398 const struct hns3_hw_blk *module = hw_blk;
401 while (module->enable_err_intr) {
402 ret = module->enable_err_intr(hns, en);
412 static enum hns3_reset_level
413 hns3_find_highest_level(struct hns3_adapter *hns, const char *reg,
414 const struct hns3_hw_error *err, uint32_t err_sts)
416 enum hns3_reset_level reset_level = HNS3_FUNC_RESET;
417 struct hns3_hw *hw = &hns->hw;
418 bool need_reset = false;
421 if (err->int_msk & err_sts) {
422 hns3_warn(hw, "%s %s found [error status=0x%x]",
423 reg, err->msg, err_sts);
424 if (err->reset_level != HNS3_NONE_RESET &&
425 err->reset_level >= reset_level) {
426 reset_level = err->reset_level;
435 return HNS3_NONE_RESET;
439 query_num_bds_in_msix(struct hns3_hw *hw, struct hns3_cmd_desc *desc_bd)
443 hns3_cmd_setup_basic_desc(desc_bd, HNS3_QUERY_MSIX_INT_STS_BD_NUM,
445 ret = hns3_cmd_send(hw, desc_bd, 1);
447 hns3_err(hw, "query num bds in msix failed: %d", ret);
453 query_all_mpf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
458 hns3_cmd_setup_basic_desc(desc, HNS3_QUERY_CLEAR_ALL_MPF_MSIX_INT,
460 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
462 ret = hns3_cmd_send(hw, &desc[0], mpf_bd_num);
464 hns3_err(hw, "query all mpf msix err failed: %d", ret);
470 clear_all_mpf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
475 hns3_cmd_reuse_desc(desc, false);
476 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
478 ret = hns3_cmd_send(hw, desc, mpf_bd_num);
480 hns3_err(hw, "clear all mpf msix err failed: %d", ret);
486 query_all_pf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
491 hns3_cmd_setup_basic_desc(desc, HNS3_QUERY_CLEAR_ALL_PF_MSIX_INT, true);
492 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
494 ret = hns3_cmd_send(hw, desc, pf_bd_num);
496 hns3_err(hw, "query all pf msix int cmd failed: %d", ret);
502 clear_all_pf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
507 hns3_cmd_reuse_desc(desc, false);
508 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
510 ret = hns3_cmd_send(hw, desc, pf_bd_num);
512 hns3_err(hw, "clear all pf msix err failed: %d", ret);
518 hns3_intr_unregister(const struct rte_intr_handle *hdl,
519 rte_intr_callback_fn cb_fn, void *cb_arg)
525 ret = rte_intr_callback_unregister(hdl, cb_fn, cb_arg);
528 } else if (ret != -EAGAIN) {
529 PMD_INIT_LOG(ERR, "Failed to unregister intr: %d", ret);
532 rte_delay_ms(HNS3_INTR_UNREG_FAIL_DELAY_MS);
533 } while (retry_cnt++ < HNS3_INTR_UNREG_FAIL_RETRY_CNT);
537 hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels)
539 uint32_t mpf_bd_num, pf_bd_num, bd_num;
540 enum hns3_reset_level req_level;
541 struct hns3_hw *hw = &hns->hw;
542 struct hns3_pf *pf = &hns->pf;
543 struct hns3_cmd_desc desc_bd;
544 struct hns3_cmd_desc *desc;
549 /* query the number of bds for the MSIx int status */
550 ret = query_num_bds_in_msix(hw, &desc_bd);
552 hns3_err(hw, "fail to query msix int status bd num: %d", ret);
556 mpf_bd_num = rte_le_to_cpu_32(desc_bd.data[0]);
557 pf_bd_num = rte_le_to_cpu_32(desc_bd.data[1]);
558 bd_num = max_t(uint32_t, mpf_bd_num, pf_bd_num);
559 if (bd_num < RCB_ERROR_OFFSET) {
560 hns3_err(hw, "bd_num is less than RCB_ERROR_OFFSET: %u",
565 desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0);
567 hns3_err(hw, "fail to zmalloc desc");
571 /* query all main PF MSIx errors */
572 ret = query_all_mpf_msix_err(hw, &desc[0], mpf_bd_num);
574 hns3_err(hw, "query all mpf msix int cmd failed: %d", ret);
579 desc_data = (uint32_t *)&desc[MAC_ERROR_OFFSET];
580 status = rte_le_to_cpu_32(*desc_data);
582 req_level = hns3_find_highest_level(hns, "MAC_AFIFO_TNL_INT_R",
585 hns3_atomic_set_bit(req_level, levels);
586 pf->abn_int_stats.mac_afifo_tnl_intr_cnt++;
589 /* log PPU(RCB) errors */
590 desc_data = (uint32_t *)&desc[RCB_ERROR_OFFSET];
591 status = rte_le_to_cpu_32(*(desc_data + RCB_ERROR_STATUS_OFFSET)) &
592 HNS3_PPU_MPF_INT_ST2_MSIX_MASK;
594 req_level = hns3_find_highest_level(hns,
595 "PPU_MPF_ABNORMAL_INT_ST2",
596 ppu_mpf_abnormal_int_st2,
598 hns3_atomic_set_bit(req_level, levels);
599 pf->abn_int_stats.ppu_mpf_abnormal_intr_st2_cnt++;
602 /* clear all main PF MSIx errors */
603 ret = clear_all_mpf_msix_err(hw, desc, mpf_bd_num);
605 hns3_err(hw, "clear all mpf msix int cmd failed: %d", ret);
609 /* query all PF MSIx errors */
610 memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc));
611 ret = query_all_pf_msix_err(hw, &desc[0], pf_bd_num);
613 hns3_err(hw, "query all pf msix int cmd failed (%d)", ret);
617 /* log SSU PF errors */
618 status = rte_le_to_cpu_32(desc[0].data[0]) &
619 HNS3_SSU_PORT_INT_MSIX_MASK;
621 req_level = hns3_find_highest_level(hns,
622 "SSU_PORT_BASED_ERR_INT",
623 ssu_port_based_pf_int,
625 hns3_atomic_set_bit(req_level, levels);
626 pf->abn_int_stats.ssu_port_based_pf_intr_cnt++;
629 /* log PPP PF errors */
630 desc_data = (uint32_t *)&desc[PPP_PF_ERROR_OFFSET];
631 status = rte_le_to_cpu_32(*desc_data);
633 req_level = hns3_find_highest_level(hns,
634 "PPP_PF_ABNORMAL_INT_ST0",
637 hns3_atomic_set_bit(req_level, levels);
638 pf->abn_int_stats.ppp_pf_abnormal_intr_cnt++;
641 /* log PPU(RCB) PF errors */
642 desc_data = (uint32_t *)&desc[PPU_PF_ERROR_OFFSET];
643 status = rte_le_to_cpu_32(*desc_data) & HNS3_PPU_PF_INT_MSIX_MASK;
645 req_level = hns3_find_highest_level(hns,
646 "PPU_PF_ABNORMAL_INT_ST",
649 hns3_atomic_set_bit(req_level, levels);
650 pf->abn_int_stats.ppu_pf_abnormal_intr_cnt++;
653 /* clear all PF MSIx errors */
654 ret = clear_all_pf_msix_err(hw, desc, pf_bd_num);
656 hns3_err(hw, "clear all pf msix int cmd failed: %d", ret);
662 hns3_reset_init(struct hns3_hw *hw)
664 rte_spinlock_init(&hw->lock);
665 hw->reset.level = HNS3_NONE_RESET;
666 hw->reset.stage = RESET_STAGE_NONE;
667 hw->reset.request = 0;
668 hw->reset.pending = 0;
669 rte_atomic16_init(&hw->reset.resetting);
670 rte_atomic16_init(&hw->reset.disable_cmd);
671 hw->reset.wait_data = rte_zmalloc("wait_data",
672 sizeof(struct hns3_wait_data), 0);
673 if (!hw->reset.wait_data) {
674 PMD_INIT_LOG(ERR, "Failed to allocate memory for wait_data");
681 hns3_schedule_reset(struct hns3_adapter *hns)
683 struct hns3_hw *hw = &hns->hw;
685 /* Reschedule the reset process after successful initialization */
686 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {
687 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_PENDING);
691 if (hw->adapter_state >= HNS3_NIC_CLOSED)
694 /* Schedule restart alarm if it is not scheduled yet */
695 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_REQUESTED)
697 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED)
698 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);
699 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
701 rte_eal_alarm_set(SWITCH_CONTEXT_US, hw->reset.ops->reset_service, hns);
705 hns3_schedule_delayed_reset(struct hns3_adapter *hns)
707 #define DEFERRED_SCHED_US (3 * MSEC_PER_SEC * USEC_PER_MSEC)
708 struct hns3_hw *hw = &hns->hw;
710 /* Do nothing if it is uninited or closed */
711 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED ||
712 hw->adapter_state >= HNS3_NIC_CLOSED) {
716 if (rte_atomic16_read(&hns->hw.reset.schedule) != SCHEDULE_NONE)
718 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_DEFERRED);
719 rte_eal_alarm_set(DEFERRED_SCHED_US, hw->reset.ops->reset_service, hns);
723 hns3_wait_callback(void *param)
725 struct hns3_wait_data *data = (struct hns3_wait_data *)param;
726 struct hns3_adapter *hns = data->hns;
727 struct hns3_hw *hw = &hns->hw;
732 if (data->check_completion) {
734 * Check if the current time exceeds the deadline
735 * or a pending reset coming, or reset during close.
737 msec = get_timeofday_ms();
738 if (msec > data->end_ms || is_reset_pending(hns) ||
739 hw->adapter_state == HNS3_NIC_CLOSING) {
743 done = data->check_completion(hw);
747 if (!done && data->count > 0) {
748 rte_eal_alarm_set(data->interval, hns3_wait_callback, data);
752 data->result = HNS3_WAIT_SUCCESS;
754 hns3_err(hw, "%s wait timeout at stage %d",
755 reset_string[hw->reset.level], hw->reset.stage);
756 data->result = HNS3_WAIT_TIMEOUT;
758 hns3_schedule_reset(hns);
762 hns3_notify_reset_ready(struct hns3_hw *hw, bool enable)
766 reg_val = hns3_read_dev(hw, HNS3_CMDQ_TX_DEPTH_REG);
768 reg_val |= HNS3_NIC_SW_RST_RDY;
770 reg_val &= ~HNS3_NIC_SW_RST_RDY;
772 hns3_write_dev(hw, HNS3_CMDQ_TX_DEPTH_REG, reg_val);
776 hns3_reset_req_hw_reset(struct hns3_adapter *hns)
778 struct hns3_hw *hw = &hns->hw;
780 if (hw->reset.wait_data->result == HNS3_WAIT_UNKNOWN) {
781 hw->reset.wait_data->hns = hns;
782 hw->reset.wait_data->check_completion = NULL;
783 hw->reset.wait_data->interval = HNS3_RESET_SYNC_US;
784 hw->reset.wait_data->count = 1;
785 hw->reset.wait_data->result = HNS3_WAIT_REQUEST;
786 rte_eal_alarm_set(hw->reset.wait_data->interval,
787 hns3_wait_callback, hw->reset.wait_data);
789 } else if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)
792 /* inform hardware that preparatory work is done */
793 hns3_notify_reset_ready(hw, true);
798 hns3_clear_reset_level(struct hns3_hw *hw, uint64_t *levels)
800 uint64_t merge_cnt = hw->reset.stats.merge_cnt;
803 switch (hw->reset.level) {
805 hns3_atomic_clear_bit(HNS3_IMP_RESET, levels);
806 tmp = hns3_test_and_clear_bit(HNS3_GLOBAL_RESET, levels);
807 HNS3_CHECK_MERGE_CNT(tmp);
808 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);
809 HNS3_CHECK_MERGE_CNT(tmp);
811 case HNS3_GLOBAL_RESET:
812 hns3_atomic_clear_bit(HNS3_GLOBAL_RESET, levels);
813 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);
814 HNS3_CHECK_MERGE_CNT(tmp);
816 case HNS3_FUNC_RESET:
817 hns3_atomic_clear_bit(HNS3_FUNC_RESET, levels);
820 hns3_atomic_clear_bit(HNS3_VF_RESET, levels);
821 tmp = hns3_test_and_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);
822 HNS3_CHECK_MERGE_CNT(tmp);
823 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
824 HNS3_CHECK_MERGE_CNT(tmp);
826 case HNS3_VF_FULL_RESET:
827 hns3_atomic_clear_bit(HNS3_VF_FULL_RESET, levels);
828 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
829 HNS3_CHECK_MERGE_CNT(tmp);
831 case HNS3_VF_PF_FUNC_RESET:
832 hns3_atomic_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);
833 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
834 HNS3_CHECK_MERGE_CNT(tmp);
836 case HNS3_VF_FUNC_RESET:
837 hns3_atomic_clear_bit(HNS3_VF_FUNC_RESET, levels);
840 hns3_atomic_clear_bit(HNS3_FLR_RESET, levels);
842 case HNS3_NONE_RESET:
846 if (merge_cnt != hw->reset.stats.merge_cnt)
848 "No need to do low-level reset after %s reset. "
849 "merge cnt: %" PRIx64 " total merge cnt: %" PRIx64,
850 reset_string[hw->reset.level],
851 hw->reset.stats.merge_cnt - merge_cnt,
852 hw->reset.stats.merge_cnt);
856 hns3_reset_err_handle(struct hns3_adapter *hns)
858 #define MAX_RESET_FAIL_CNT 5
860 struct hns3_hw *hw = &hns->hw;
862 if (hw->adapter_state == HNS3_NIC_CLOSING)
865 if (is_reset_pending(hns)) {
866 hw->reset.attempts = 0;
867 hw->reset.stats.fail_cnt++;
868 hns3_warn(hw, "%s reset fail because new Reset is pending "
870 reset_string[hw->reset.level],
871 hw->reset.stats.fail_cnt);
872 hw->reset.level = HNS3_NONE_RESET;
876 hw->reset.attempts++;
877 if (hw->reset.attempts < MAX_RESET_FAIL_CNT) {
878 hns3_atomic_set_bit(hw->reset.level, &hw->reset.pending);
879 hns3_warn(hw, "%s retry to reset attempts: %d",
880 reset_string[hw->reset.level],
885 if (rte_atomic16_read(&hw->reset.disable_cmd))
888 hw->reset.attempts = 0;
889 hw->reset.stats.fail_cnt++;
890 hns3_warn(hw, "%s reset fail fail_cnt:%" PRIx64 " success_cnt:%" PRIx64
891 " global_cnt:%" PRIx64 " imp_cnt:%" PRIx64
892 " request_cnt:%" PRIx64 " exec_cnt:%" PRIx64
893 " merge_cnt:%" PRIx64,
894 reset_string[hw->reset.level], hw->reset.stats.fail_cnt,
895 hw->reset.stats.success_cnt, hw->reset.stats.global_cnt,
896 hw->reset.stats.imp_cnt, hw->reset.stats.request_cnt,
897 hw->reset.stats.exec_cnt, hw->reset.stats.merge_cnt);
899 /* IMP no longer waiting the ready flag */
900 hns3_notify_reset_ready(hw, true);
905 hns3_reset_pre(struct hns3_adapter *hns)
907 struct hns3_hw *hw = &hns->hw;
911 if (hw->reset.stage == RESET_STAGE_NONE) {
912 rte_atomic16_set(&hns->hw.reset.resetting, 1);
913 hw->reset.stage = RESET_STAGE_DOWN;
914 ret = hw->reset.ops->stop_service(hns);
915 gettimeofday(&tv, NULL);
917 hns3_warn(hw, "Reset step1 down fail=%d time=%ld.%.6ld",
918 ret, tv.tv_sec, tv.tv_usec);
921 hns3_warn(hw, "Reset step1 down success time=%ld.%.6ld",
922 tv.tv_sec, tv.tv_usec);
923 hw->reset.stage = RESET_STAGE_PREWAIT;
925 if (hw->reset.stage == RESET_STAGE_PREWAIT) {
926 ret = hw->reset.ops->prepare_reset(hns);
927 gettimeofday(&tv, NULL);
930 "Reset step2 prepare wait fail=%d time=%ld.%.6ld",
931 ret, tv.tv_sec, tv.tv_usec);
934 hns3_warn(hw, "Reset step2 prepare wait success time=%ld.%.6ld",
935 tv.tv_sec, tv.tv_usec);
936 hw->reset.stage = RESET_STAGE_REQ_HW_RESET;
937 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;
943 hns3_reset_post(struct hns3_adapter *hns)
945 #define TIMEOUT_RETRIES_CNT 5
946 struct hns3_hw *hw = &hns->hw;
947 struct timeval tv_delta;
951 if (hw->adapter_state == HNS3_NIC_CLOSING) {
952 hns3_warn(hw, "Don't do reset_post during closing, just uninit cmd");
957 if (hw->reset.stage == RESET_STAGE_DEV_INIT) {
958 rte_spinlock_lock(&hw->lock);
959 if (hw->reset.mbuf_deferred_free) {
960 hns3_dev_release_mbufs(hns);
961 hw->reset.mbuf_deferred_free = false;
963 ret = hw->reset.ops->reinit_dev(hns);
964 rte_spinlock_unlock(&hw->lock);
965 gettimeofday(&tv, NULL);
967 hns3_warn(hw, "Reset step5 devinit fail=%d retries=%d",
968 ret, hw->reset.retries);
971 hns3_warn(hw, "Reset step5 devinit success time=%ld.%.6ld",
972 tv.tv_sec, tv.tv_usec);
973 hw->reset.retries = 0;
974 hw->reset.stage = RESET_STAGE_RESTORE;
975 rte_eal_alarm_set(SWITCH_CONTEXT_US,
976 hw->reset.ops->reset_service, hns);
979 if (hw->reset.stage == RESET_STAGE_RESTORE) {
980 rte_spinlock_lock(&hw->lock);
981 ret = hw->reset.ops->restore_conf(hns);
982 rte_spinlock_unlock(&hw->lock);
983 gettimeofday(&tv, NULL);
986 "Reset step6 restore fail=%d retries=%d",
987 ret, hw->reset.retries);
990 hns3_warn(hw, "Reset step6 restore success time=%ld.%.6ld",
991 tv.tv_sec, tv.tv_usec);
992 hw->reset.retries = 0;
993 hw->reset.stage = RESET_STAGE_DONE;
995 if (hw->reset.stage == RESET_STAGE_DONE) {
996 /* IMP will wait ready flag before reset */
997 hns3_notify_reset_ready(hw, false);
998 hns3_clear_reset_level(hw, &hw->reset.pending);
999 rte_atomic16_clear(&hns->hw.reset.resetting);
1000 hw->reset.attempts = 0;
1001 hw->reset.stats.success_cnt++;
1002 hw->reset.stage = RESET_STAGE_NONE;
1003 hw->reset.ops->start_service(hns);
1004 gettimeofday(&tv, NULL);
1005 timersub(&tv, &hw->reset.start_time, &tv_delta);
1006 hns3_warn(hw, "%s reset done fail_cnt:%" PRIx64
1007 " success_cnt:%" PRIx64 " global_cnt:%" PRIx64
1008 " imp_cnt:%" PRIx64 " request_cnt:%" PRIx64
1009 " exec_cnt:%" PRIx64 " merge_cnt:%" PRIx64,
1010 reset_string[hw->reset.level],
1011 hw->reset.stats.fail_cnt, hw->reset.stats.success_cnt,
1012 hw->reset.stats.global_cnt, hw->reset.stats.imp_cnt,
1013 hw->reset.stats.request_cnt, hw->reset.stats.exec_cnt,
1014 hw->reset.stats.merge_cnt);
1016 "%s reset done delta %ld ms time=%ld.%.6ld",
1017 reset_string[hw->reset.level],
1018 tv_delta.tv_sec * MSEC_PER_SEC +
1019 tv_delta.tv_usec / USEC_PER_MSEC,
1020 tv.tv_sec, tv.tv_usec);
1021 hw->reset.level = HNS3_NONE_RESET;
1026 if (ret == -ETIME) {
1027 hw->reset.retries++;
1028 if (hw->reset.retries < TIMEOUT_RETRIES_CNT) {
1029 rte_eal_alarm_set(HNS3_RESET_SYNC_US,
1030 hw->reset.ops->reset_service, hns);
1034 hw->reset.retries = 0;
1039 * There are three scenarios as follows:
1040 * When the reset is not in progress, the reset process starts.
1041 * During the reset process, if the reset level has not changed,
1042 * the reset process continues; otherwise, the reset process is aborted.
1043 * hw->reset.level new_level action
1044 * HNS3_NONE_RESET HNS3_XXXX_RESET start reset
1045 * HNS3_XXXX_RESET HNS3_XXXX_RESET continue reset
1046 * HNS3_LOW_RESET HNS3_HIGH_RESET abort
1049 hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level)
1051 struct hns3_hw *hw = &hns->hw;
1052 struct timeval tv_delta;
1056 if (hw->reset.level == HNS3_NONE_RESET) {
1057 hw->reset.level = new_level;
1058 hw->reset.stats.exec_cnt++;
1059 gettimeofday(&hw->reset.start_time, NULL);
1060 hns3_warn(hw, "Start %s reset time=%ld.%.6ld",
1061 reset_string[hw->reset.level],
1062 hw->reset.start_time.tv_sec,
1063 hw->reset.start_time.tv_usec);
1066 if (is_reset_pending(hns)) {
1067 gettimeofday(&tv, NULL);
1069 "%s reset is aborted by high level time=%ld.%.6ld",
1070 reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);
1071 if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)
1072 rte_eal_alarm_cancel(hns3_wait_callback,
1073 hw->reset.wait_data);
1078 ret = hns3_reset_pre(hns);
1082 if (hw->reset.stage == RESET_STAGE_REQ_HW_RESET) {
1083 ret = hns3_reset_req_hw_reset(hns);
1086 gettimeofday(&tv, NULL);
1088 "Reset step3 request IMP reset success time=%ld.%.6ld",
1089 tv.tv_sec, tv.tv_usec);
1090 hw->reset.stage = RESET_STAGE_WAIT;
1091 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;
1093 if (hw->reset.stage == RESET_STAGE_WAIT) {
1094 ret = hw->reset.ops->wait_hardware_ready(hns);
1097 gettimeofday(&tv, NULL);
1098 hns3_warn(hw, "Reset step4 reset wait success time=%ld.%.6ld",
1099 tv.tv_sec, tv.tv_usec);
1100 hw->reset.stage = RESET_STAGE_DEV_INIT;
1103 ret = hns3_reset_post(hns);
1112 hns3_clear_reset_level(hw, &hw->reset.pending);
1113 if (hns3_reset_err_handle(hns)) {
1114 hw->reset.stage = RESET_STAGE_PREWAIT;
1115 hns3_schedule_reset(hns);
1117 rte_spinlock_lock(&hw->lock);
1118 if (hw->reset.mbuf_deferred_free) {
1119 hns3_dev_release_mbufs(hns);
1120 hw->reset.mbuf_deferred_free = false;
1122 rte_spinlock_unlock(&hw->lock);
1123 rte_atomic16_clear(&hns->hw.reset.resetting);
1124 hw->reset.stage = RESET_STAGE_NONE;
1125 gettimeofday(&tv, NULL);
1126 timersub(&tv, &hw->reset.start_time, &tv_delta);
1127 hns3_warn(hw, "%s reset fail delta %ld ms time=%ld.%.6ld",
1128 reset_string[hw->reset.level],
1129 tv_delta.tv_sec * MSEC_PER_SEC +
1130 tv_delta.tv_usec / USEC_PER_MSEC,
1131 tv.tv_sec, tv.tv_usec);
1132 hw->reset.level = HNS3_NONE_RESET;
1139 * The reset process can only be terminated after handshake with IMP(step3),
1140 * so that IMP can complete the reset process normally.
1143 hns3_reset_abort(struct hns3_adapter *hns)
1145 struct hns3_hw *hw = &hns->hw;
1149 for (i = 0; i < HNS3_QUIT_RESET_CNT; i++) {
1150 if (hw->reset.level == HNS3_NONE_RESET)
1152 rte_delay_ms(HNS3_QUIT_RESET_DELAY_MS);
1155 /* IMP no longer waiting the ready flag */
1156 hns3_notify_reset_ready(hw, true);
1158 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);
1159 rte_eal_alarm_cancel(hns3_wait_callback, hw->reset.wait_data);
1161 if (hw->reset.level != HNS3_NONE_RESET) {
1162 gettimeofday(&tv, NULL);
1163 hns3_err(hw, "Failed to terminate reset: %s time=%ld.%.6ld",
1164 reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);