1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
6 #include <rte_cycles.h>
7 #include <rte_ethdev.h>
9 #include <rte_malloc.h>
11 #include "hns3_ethdev.h"
12 #include "hns3_logs.h"
13 #include "hns3_intr.h"
14 #include "hns3_regs.h"
15 #include "hns3_rxtx.h"
17 #define SWITCH_CONTEXT_US 10
19 #define HNS3_CHECK_MERGE_CNT(val) \
22 hw->reset.stats.merge_cnt++; \
25 static const char *reset_string[HNS3_MAX_RESET] = {
26 "none", "vf_func", "vf_pf_func", "vf_full", "flr",
27 "vf_global", "pf_func", "global", "IMP",
30 static const struct hns3_hw_error mac_afifo_tnl_int[] = {
31 { .int_msk = BIT(0), .msg = "egu_cge_afifo_ecc_1bit_err",
32 .reset_level = HNS3_NONE_RESET },
33 { .int_msk = BIT(1), .msg = "egu_cge_afifo_ecc_mbit_err",
34 .reset_level = HNS3_GLOBAL_RESET },
35 { .int_msk = BIT(2), .msg = "egu_lge_afifo_ecc_1bit_err",
36 .reset_level = HNS3_NONE_RESET },
37 { .int_msk = BIT(3), .msg = "egu_lge_afifo_ecc_mbit_err",
38 .reset_level = HNS3_GLOBAL_RESET },
39 { .int_msk = BIT(4), .msg = "cge_igu_afifo_ecc_1bit_err",
40 .reset_level = HNS3_NONE_RESET },
41 { .int_msk = BIT(5), .msg = "cge_igu_afifo_ecc_mbit_err",
42 .reset_level = HNS3_GLOBAL_RESET },
43 { .int_msk = BIT(6), .msg = "lge_igu_afifo_ecc_1bit_err",
44 .reset_level = HNS3_NONE_RESET },
45 { .int_msk = BIT(7), .msg = "lge_igu_afifo_ecc_mbit_err",
46 .reset_level = HNS3_GLOBAL_RESET },
47 { .int_msk = BIT(8), .msg = "cge_igu_afifo_overflow_err",
48 .reset_level = HNS3_GLOBAL_RESET },
49 { .int_msk = BIT(9), .msg = "lge_igu_afifo_overflow_err",
50 .reset_level = HNS3_GLOBAL_RESET },
51 { .int_msk = BIT(10), .msg = "egu_cge_afifo_underrun_err",
52 .reset_level = HNS3_GLOBAL_RESET },
53 { .int_msk = BIT(11), .msg = "egu_lge_afifo_underrun_err",
54 .reset_level = HNS3_GLOBAL_RESET },
55 { .int_msk = BIT(12), .msg = "egu_ge_afifo_underrun_err",
56 .reset_level = HNS3_GLOBAL_RESET },
57 { .int_msk = BIT(13), .msg = "ge_igu_afifo_overflow_err",
58 .reset_level = HNS3_GLOBAL_RESET },
59 { .int_msk = 0, .msg = NULL,
60 .reset_level = HNS3_NONE_RESET}
63 static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = {
64 { .int_msk = 0xFFFFFFFF, .msg = "rpu_rx_pkt_ecc_mbit_err",
65 .reset_level = HNS3_GLOBAL_RESET },
66 { .int_msk = 0, .msg = NULL,
67 .reset_level = HNS3_NONE_RESET}
70 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = {
71 { .int_msk = BIT(13), .msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
72 .reset_level = HNS3_GLOBAL_RESET },
73 { .int_msk = BIT(14), .msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
74 .reset_level = HNS3_GLOBAL_RESET },
75 { .int_msk = BIT(15), .msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
76 .reset_level = HNS3_GLOBAL_RESET },
77 { .int_msk = BIT(16), .msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
78 .reset_level = HNS3_GLOBAL_RESET },
79 { .int_msk = BIT(17), .msg = "rcb_tx_ring_ecc_mbit_err",
80 .reset_level = HNS3_GLOBAL_RESET },
81 { .int_msk = BIT(18), .msg = "rcb_rx_ring_ecc_mbit_err",
82 .reset_level = HNS3_GLOBAL_RESET },
83 { .int_msk = BIT(19), .msg = "rcb_tx_fbd_ecc_mbit_err",
84 .reset_level = HNS3_GLOBAL_RESET },
85 { .int_msk = BIT(20), .msg = "rcb_rx_ebd_ecc_mbit_err",
86 .reset_level = HNS3_GLOBAL_RESET },
87 { .int_msk = BIT(21), .msg = "rcb_tso_info_ecc_mbit_err",
88 .reset_level = HNS3_GLOBAL_RESET },
89 { .int_msk = BIT(22), .msg = "rcb_tx_int_info_ecc_mbit_err",
90 .reset_level = HNS3_GLOBAL_RESET },
91 { .int_msk = BIT(23), .msg = "rcb_rx_int_info_ecc_mbit_err",
92 .reset_level = HNS3_GLOBAL_RESET },
93 { .int_msk = BIT(24), .msg = "tpu_tx_pkt_0_ecc_mbit_err",
94 .reset_level = HNS3_GLOBAL_RESET },
95 { .int_msk = BIT(25), .msg = "tpu_tx_pkt_1_ecc_mbit_err",
96 .reset_level = HNS3_GLOBAL_RESET },
97 { .int_msk = BIT(26), .msg = "rd_bus_err",
98 .reset_level = HNS3_GLOBAL_RESET },
99 { .int_msk = BIT(27), .msg = "wr_bus_err",
100 .reset_level = HNS3_GLOBAL_RESET },
101 { .int_msk = BIT(30), .msg = "ooo_ecc_err_detect",
102 .reset_level = HNS3_NONE_RESET },
103 { .int_msk = BIT(31), .msg = "ooo_ecc_err_multpl",
104 .reset_level = HNS3_GLOBAL_RESET },
105 { .int_msk = 0, .msg = NULL,
106 .reset_level = HNS3_NONE_RESET}
109 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = {
110 { .int_msk = BIT(29), .msg = "rx_q_search_miss",
111 .reset_level = HNS3_NONE_RESET },
112 { .int_msk = 0, .msg = NULL,
113 .reset_level = HNS3_NONE_RESET}
116 static const struct hns3_hw_error ssu_port_based_pf_int[] = {
117 { .int_msk = BIT(0), .msg = "roc_pkt_without_key_port",
118 .reset_level = HNS3_GLOBAL_RESET },
119 { .int_msk = BIT(9), .msg = "low_water_line_err_port",
120 .reset_level = HNS3_NONE_RESET },
121 { .int_msk = 0, .msg = NULL,
122 .reset_level = HNS3_NONE_RESET}
125 static const struct hns3_hw_error ppp_pf_abnormal_int[] = {
126 { .int_msk = BIT(0), .msg = "tx_vlan_tag_err",
127 .reset_level = HNS3_NONE_RESET },
128 { .int_msk = BIT(1), .msg = "rss_list_tc_unassigned_queue_err",
129 .reset_level = HNS3_NONE_RESET },
130 { .int_msk = 0, .msg = NULL,
131 .reset_level = HNS3_NONE_RESET}
134 static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = {
135 { .int_msk = BIT(3), .msg = "tx_rd_fbd_poison",
136 .reset_level = HNS3_FUNC_RESET },
137 { .int_msk = BIT(4), .msg = "rx_rd_ebd_poison",
138 .reset_level = HNS3_FUNC_RESET },
139 { .int_msk = 0, .msg = NULL,
140 .reset_level = HNS3_NONE_RESET}
143 static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = {
144 { .int_msk = BIT(0), .msg = "over_8bd_no_fe",
145 .reset_level = HNS3_FUNC_RESET },
146 { .int_msk = BIT(1), .msg = "tso_mss_cmp_min_err",
147 .reset_level = HNS3_NONE_RESET },
148 { .int_msk = BIT(2), .msg = "tso_mss_cmp_max_err",
149 .reset_level = HNS3_NONE_RESET },
150 { .int_msk = BIT(5), .msg = "buf_wait_timeout",
151 .reset_level = HNS3_NONE_RESET },
152 { .int_msk = 0, .msg = NULL,
153 .reset_level = HNS3_NONE_RESET}
156 static const struct hns3_hw_error imp_tcm_ecc_int[] = {
157 { .int_msk = BIT(1), .msg = "imp_itcm0_ecc_mbit_err",
158 .reset_level = HNS3_NONE_RESET },
159 { .int_msk = BIT(3), .msg = "imp_itcm1_ecc_mbit_err",
160 .reset_level = HNS3_NONE_RESET },
161 { .int_msk = BIT(5), .msg = "imp_itcm2_ecc_mbit_err",
162 .reset_level = HNS3_NONE_RESET },
163 { .int_msk = BIT(7), .msg = "imp_itcm3_ecc_mbit_err",
164 .reset_level = HNS3_NONE_RESET },
165 { .int_msk = BIT(9), .msg = "imp_dtcm0_mem0_ecc_mbit_err",
166 .reset_level = HNS3_NONE_RESET },
167 { .int_msk = BIT(11), .msg = "imp_dtcm0_mem1_ecc_mbit_err",
168 .reset_level = HNS3_NONE_RESET },
169 { .int_msk = BIT(13), .msg = "imp_dtcm1_mem0_ecc_mbit_err",
170 .reset_level = HNS3_NONE_RESET },
171 { .int_msk = BIT(15), .msg = "imp_dtcm1_mem1_ecc_mbit_err",
172 .reset_level = HNS3_NONE_RESET },
173 { .int_msk = BIT(17), .msg = "imp_itcm4_ecc_mbit_err",
174 .reset_level = HNS3_NONE_RESET },
175 { .int_msk = 0, .msg = NULL,
176 .reset_level = HNS3_NONE_RESET}
179 static const struct hns3_hw_error cmdq_mem_ecc_int[] = {
180 { .int_msk = BIT(1), .msg = "cmdq_nic_rx_depth_ecc_mbit_err",
181 .reset_level = HNS3_NONE_RESET },
182 { .int_msk = BIT(3), .msg = "cmdq_nic_tx_depth_ecc_mbit_err",
183 .reset_level = HNS3_NONE_RESET },
184 { .int_msk = BIT(5), .msg = "cmdq_nic_rx_tail_ecc_mbit_err",
185 .reset_level = HNS3_NONE_RESET },
186 { .int_msk = BIT(7), .msg = "cmdq_nic_tx_tail_ecc_mbit_err",
187 .reset_level = HNS3_NONE_RESET },
188 { .int_msk = BIT(9), .msg = "cmdq_nic_rx_head_ecc_mbit_err",
189 .reset_level = HNS3_NONE_RESET },
190 { .int_msk = BIT(11), .msg = "cmdq_nic_tx_head_ecc_mbit_err",
191 .reset_level = HNS3_NONE_RESET },
192 { .int_msk = BIT(13), .msg = "cmdq_nic_rx_addr_ecc_mbit_err",
193 .reset_level = HNS3_NONE_RESET },
194 { .int_msk = BIT(15), .msg = "cmdq_nic_tx_addr_ecc_mbit_err",
195 .reset_level = HNS3_NONE_RESET },
196 { .int_msk = 0, .msg = NULL,
197 .reset_level = HNS3_NONE_RESET}
200 static const struct hns3_hw_error tqp_int_ecc_int[] = {
201 { .int_msk = BIT(6), .msg = "tqp_int_cfg_even_ecc_mbit_err",
202 .reset_level = HNS3_NONE_RESET },
203 { .int_msk = BIT(7), .msg = "tqp_int_cfg_odd_ecc_mbit_err",
204 .reset_level = HNS3_NONE_RESET },
205 { .int_msk = BIT(8), .msg = "tqp_int_ctrl_even_ecc_mbit_err",
206 .reset_level = HNS3_NONE_RESET },
207 { .int_msk = BIT(9), .msg = "tqp_int_ctrl_odd_ecc_mbit_err",
208 .reset_level = HNS3_NONE_RESET },
209 { .int_msk = BIT(10), .msg = "tx_que_scan_int_ecc_mbit_err",
210 .reset_level = HNS3_NONE_RESET },
211 { .int_msk = BIT(11), .msg = "rx_que_scan_int_ecc_mbit_err",
212 .reset_level = HNS3_NONE_RESET },
213 { .int_msk = 0, .msg = NULL,
214 .reset_level = HNS3_NONE_RESET}
217 static const struct hns3_hw_error imp_rd_poison_int[] = {
218 { .int_msk = BIT(0), .msg = "imp_rd_poison_int",
219 .reset_level = HNS3_NONE_RESET },
220 { .int_msk = 0, .msg = NULL,
221 .reset_level = HNS3_NONE_RESET}
224 #define HNS3_SSU_MEM_ECC_ERR(x) \
225 { .int_msk = BIT(x), .msg = "ssu_mem" #x "_ecc_mbit_err", \
226 .reset_level = HNS3_GLOBAL_RESET }
228 static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = {
229 HNS3_SSU_MEM_ECC_ERR(0),
230 HNS3_SSU_MEM_ECC_ERR(1),
231 HNS3_SSU_MEM_ECC_ERR(2),
232 HNS3_SSU_MEM_ECC_ERR(3),
233 HNS3_SSU_MEM_ECC_ERR(4),
234 HNS3_SSU_MEM_ECC_ERR(5),
235 HNS3_SSU_MEM_ECC_ERR(6),
236 HNS3_SSU_MEM_ECC_ERR(7),
237 HNS3_SSU_MEM_ECC_ERR(8),
238 HNS3_SSU_MEM_ECC_ERR(9),
239 HNS3_SSU_MEM_ECC_ERR(10),
240 HNS3_SSU_MEM_ECC_ERR(11),
241 HNS3_SSU_MEM_ECC_ERR(12),
242 HNS3_SSU_MEM_ECC_ERR(13),
243 HNS3_SSU_MEM_ECC_ERR(14),
244 HNS3_SSU_MEM_ECC_ERR(15),
245 HNS3_SSU_MEM_ECC_ERR(16),
246 HNS3_SSU_MEM_ECC_ERR(17),
247 HNS3_SSU_MEM_ECC_ERR(18),
248 HNS3_SSU_MEM_ECC_ERR(19),
249 HNS3_SSU_MEM_ECC_ERR(20),
250 HNS3_SSU_MEM_ECC_ERR(21),
251 HNS3_SSU_MEM_ECC_ERR(22),
252 HNS3_SSU_MEM_ECC_ERR(23),
253 HNS3_SSU_MEM_ECC_ERR(24),
254 HNS3_SSU_MEM_ECC_ERR(25),
255 HNS3_SSU_MEM_ECC_ERR(26),
256 HNS3_SSU_MEM_ECC_ERR(27),
257 HNS3_SSU_MEM_ECC_ERR(28),
258 HNS3_SSU_MEM_ECC_ERR(29),
259 HNS3_SSU_MEM_ECC_ERR(30),
260 HNS3_SSU_MEM_ECC_ERR(31),
261 { .int_msk = 0, .msg = NULL,
262 .reset_level = HNS3_NONE_RESET}
265 static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = {
266 { .int_msk = BIT(0), .msg = "ssu_mem32_ecc_mbit_err",
267 .reset_level = HNS3_GLOBAL_RESET },
268 { .int_msk = 0, .msg = NULL,
269 .reset_level = HNS3_NONE_RESET}
272 static const struct hns3_hw_error ssu_common_ecc_int[] = {
273 { .int_msk = BIT(0), .msg = "buf_sum_err",
274 .reset_level = HNS3_NONE_RESET },
275 { .int_msk = BIT(1), .msg = "ppp_mb_num_err",
276 .reset_level = HNS3_NONE_RESET },
277 { .int_msk = BIT(2), .msg = "ppp_mbid_err",
278 .reset_level = HNS3_GLOBAL_RESET },
279 { .int_msk = BIT(3), .msg = "ppp_rlt_mac_err",
280 .reset_level = HNS3_GLOBAL_RESET },
281 { .int_msk = BIT(4), .msg = "ppp_rlt_host_err",
282 .reset_level = HNS3_GLOBAL_RESET },
283 { .int_msk = BIT(5), .msg = "cks_edit_position_err",
284 .reset_level = HNS3_GLOBAL_RESET },
285 { .int_msk = BIT(6), .msg = "cks_edit_condition_err",
286 .reset_level = HNS3_GLOBAL_RESET },
287 { .int_msk = BIT(7), .msg = "vlan_edit_condition_err",
288 .reset_level = HNS3_GLOBAL_RESET },
289 { .int_msk = BIT(8), .msg = "vlan_num_ot_err",
290 .reset_level = HNS3_GLOBAL_RESET },
291 { .int_msk = BIT(9), .msg = "vlan_num_in_err",
292 .reset_level = HNS3_GLOBAL_RESET },
293 { .int_msk = 0, .msg = NULL,
294 .reset_level = HNS3_NONE_RESET}
297 static const struct hns3_hw_error igu_int[] = {
298 { .int_msk = BIT(0), .msg = "igu_rx_buf0_ecc_mbit_err",
299 .reset_level = HNS3_GLOBAL_RESET },
300 { .int_msk = BIT(2), .msg = "igu_rx_buf1_ecc_mbit_err",
301 .reset_level = HNS3_GLOBAL_RESET },
302 { .int_msk = 0, .msg = NULL,
303 .reset_level = HNS3_NONE_RESET}
306 static const struct hns3_hw_error msix_ecc_int[] = {
307 { .int_msk = BIT(1), .msg = "msix_nic_ecc_mbit_err",
308 .reset_level = HNS3_NONE_RESET },
309 { .int_msk = 0, .msg = NULL,
310 .reset_level = HNS3_NONE_RESET}
313 static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = {
314 { .int_msk = BIT(0), .msg = "vf_vlan_ad_mem_ecc_mbit_err",
315 .reset_level = HNS3_GLOBAL_RESET },
316 { .int_msk = BIT(1), .msg = "umv_mcast_group_mem_ecc_mbit_err",
317 .reset_level = HNS3_GLOBAL_RESET },
318 { .int_msk = BIT(2), .msg = "umv_key_mem0_ecc_mbit_err",
319 .reset_level = HNS3_GLOBAL_RESET },
320 { .int_msk = BIT(3), .msg = "umv_key_mem1_ecc_mbit_err",
321 .reset_level = HNS3_GLOBAL_RESET },
322 { .int_msk = BIT(4), .msg = "umv_key_mem2_ecc_mbit_err",
323 .reset_level = HNS3_GLOBAL_RESET },
324 { .int_msk = BIT(5), .msg = "umv_key_mem3_ecc_mbit_err",
325 .reset_level = HNS3_GLOBAL_RESET },
326 { .int_msk = BIT(6), .msg = "umv_ad_mem_ecc_mbit_err",
327 .reset_level = HNS3_GLOBAL_RESET },
328 { .int_msk = BIT(7), .msg = "rss_tc_mode_mem_ecc_mbit_err",
329 .reset_level = HNS3_GLOBAL_RESET },
330 { .int_msk = BIT(8), .msg = "rss_idt_mem0_ecc_mbit_err",
331 .reset_level = HNS3_GLOBAL_RESET },
332 { .int_msk = BIT(9), .msg = "rss_idt_mem1_ecc_mbit_err",
333 .reset_level = HNS3_GLOBAL_RESET },
334 { .int_msk = BIT(10), .msg = "rss_idt_mem2_ecc_mbit_err",
335 .reset_level = HNS3_GLOBAL_RESET },
336 { .int_msk = BIT(11), .msg = "rss_idt_mem3_ecc_mbit_err",
337 .reset_level = HNS3_GLOBAL_RESET },
338 { .int_msk = BIT(12), .msg = "rss_idt_mem4_ecc_mbit_err",
339 .reset_level = HNS3_GLOBAL_RESET },
340 { .int_msk = BIT(13), .msg = "rss_idt_mem5_ecc_mbit_err",
341 .reset_level = HNS3_GLOBAL_RESET },
342 { .int_msk = BIT(14), .msg = "rss_idt_mem6_ecc_mbit_err",
343 .reset_level = HNS3_GLOBAL_RESET },
344 { .int_msk = BIT(15), .msg = "rss_idt_mem7_ecc_mbit_err",
345 .reset_level = HNS3_GLOBAL_RESET },
346 { .int_msk = BIT(16), .msg = "rss_idt_mem8_ecc_mbit_err",
347 .reset_level = HNS3_GLOBAL_RESET },
348 { .int_msk = BIT(17), .msg = "rss_idt_mem9_ecc_mbit_err",
349 .reset_level = HNS3_GLOBAL_RESET },
350 { .int_msk = BIT(18), .msg = "rss_idt_mem10_ecc_m1bit_err",
351 .reset_level = HNS3_GLOBAL_RESET },
352 { .int_msk = BIT(19), .msg = "rss_idt_mem11_ecc_mbit_err",
353 .reset_level = HNS3_GLOBAL_RESET },
354 { .int_msk = BIT(20), .msg = "rss_idt_mem12_ecc_mbit_err",
355 .reset_level = HNS3_GLOBAL_RESET },
356 { .int_msk = BIT(21), .msg = "rss_idt_mem13_ecc_mbit_err",
357 .reset_level = HNS3_GLOBAL_RESET },
358 { .int_msk = BIT(22), .msg = "rss_idt_mem14_ecc_mbit_err",
359 .reset_level = HNS3_GLOBAL_RESET },
360 { .int_msk = BIT(23), .msg = "rss_idt_mem15_ecc_mbit_err",
361 .reset_level = HNS3_GLOBAL_RESET },
362 { .int_msk = BIT(24), .msg = "port_vlan_mem_ecc_mbit_err",
363 .reset_level = HNS3_GLOBAL_RESET },
364 { .int_msk = BIT(25), .msg = "mcast_linear_table_mem_ecc_mbit_err",
365 .reset_level = HNS3_GLOBAL_RESET },
366 { .int_msk = BIT(26), .msg = "mcast_result_mem_ecc_mbit_err",
367 .reset_level = HNS3_GLOBAL_RESET },
368 { .int_msk = BIT(27), .msg = "flow_director_ad_mem0_ecc_mbit_err",
369 .reset_level = HNS3_GLOBAL_RESET },
370 { .int_msk = BIT(28), .msg = "flow_director_ad_mem1_ecc_mbit_err",
371 .reset_level = HNS3_GLOBAL_RESET },
372 { .int_msk = BIT(29), .msg = "rx_vlan_tag_memory_ecc_mbit_err",
373 .reset_level = HNS3_GLOBAL_RESET },
374 { .int_msk = BIT(30), .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
375 .reset_level = HNS3_GLOBAL_RESET },
376 { .int_msk = 0, .msg = NULL,
377 .reset_level = HNS3_NONE_RESET}
380 static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = {
381 { .int_msk = BIT(0), .msg = "hfs_fifo_mem_ecc_mbit_err",
382 .reset_level = HNS3_GLOBAL_RESET },
383 { .int_msk = BIT(1), .msg = "rslt_descr_fifo_mem_ecc_mbit_err",
384 .reset_level = HNS3_GLOBAL_RESET },
385 { .int_msk = BIT(2), .msg = "tx_vlan_tag_mem_ecc_mbit_err",
386 .reset_level = HNS3_GLOBAL_RESET },
387 { .int_msk = BIT(3), .msg = "FD_CN0_memory_ecc_mbit_err",
388 .reset_level = HNS3_GLOBAL_RESET },
389 { .int_msk = BIT(4), .msg = "FD_CN1_memory_ecc_mbit_err",
390 .reset_level = HNS3_GLOBAL_RESET },
391 { .int_msk = BIT(5), .msg = "GRO_AD_memory_ecc_mbit_err",
392 .reset_level = HNS3_GLOBAL_RESET },
393 { .int_msk = 0, .msg = NULL,
394 .reset_level = HNS3_NONE_RESET}
397 static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = {
398 { .int_msk = BIT(4), .msg = "gro_bd_ecc_mbit_err",
399 .reset_level = HNS3_GLOBAL_RESET },
400 { .int_msk = BIT(5), .msg = "gro_context_ecc_mbit_err",
401 .reset_level = HNS3_GLOBAL_RESET },
402 { .int_msk = BIT(6), .msg = "rx_stash_cfg_ecc_mbit_err",
403 .reset_level = HNS3_GLOBAL_RESET },
404 { .int_msk = BIT(7), .msg = "axi_rd_fbd_ecc_mbit_err",
405 .reset_level = HNS3_GLOBAL_RESET },
406 { .int_msk = 0, .msg = NULL,
407 .reset_level = HNS3_NONE_RESET}
410 static const struct hns3_hw_error tm_sch_int[] = {
411 { .int_msk = BIT(1), .msg = "tm_sch_ecc_mbit_err",
412 .reset_level = HNS3_GLOBAL_RESET },
413 { .int_msk = BIT(2), .msg = "tm_sch_port_shap_sub_fifo_wr_err",
414 .reset_level = HNS3_GLOBAL_RESET },
415 { .int_msk = BIT(3), .msg = "tm_sch_port_shap_sub_fifo_rd_err",
416 .reset_level = HNS3_GLOBAL_RESET },
417 { .int_msk = BIT(4), .msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
418 .reset_level = HNS3_GLOBAL_RESET },
419 { .int_msk = BIT(5), .msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
420 .reset_level = HNS3_GLOBAL_RESET },
421 { .int_msk = BIT(6), .msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
422 .reset_level = HNS3_GLOBAL_RESET },
423 { .int_msk = BIT(7), .msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
424 .reset_level = HNS3_GLOBAL_RESET },
425 { .int_msk = BIT(8), .msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
426 .reset_level = HNS3_GLOBAL_RESET },
427 { .int_msk = BIT(9), .msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
428 .reset_level = HNS3_GLOBAL_RESET },
429 { .int_msk = BIT(10), .msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
430 .reset_level = HNS3_GLOBAL_RESET },
431 { .int_msk = BIT(11), .msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
432 .reset_level = HNS3_GLOBAL_RESET },
433 { .int_msk = BIT(12), .msg = "tm_sch_port_shap_offset_fifo_wr_err",
434 .reset_level = HNS3_GLOBAL_RESET },
435 { .int_msk = BIT(13), .msg = "tm_sch_port_shap_offset_fifo_rd_err",
436 .reset_level = HNS3_GLOBAL_RESET },
437 { .int_msk = BIT(14), .msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
438 .reset_level = HNS3_GLOBAL_RESET },
439 { .int_msk = BIT(15), .msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
440 .reset_level = HNS3_GLOBAL_RESET },
441 { .int_msk = BIT(16), .msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
442 .reset_level = HNS3_GLOBAL_RESET },
443 { .int_msk = BIT(17), .msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
444 .reset_level = HNS3_GLOBAL_RESET },
445 { .int_msk = BIT(18), .msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
446 .reset_level = HNS3_GLOBAL_RESET },
447 { .int_msk = BIT(19), .msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
448 .reset_level = HNS3_GLOBAL_RESET },
449 { .int_msk = BIT(20), .msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
450 .reset_level = HNS3_GLOBAL_RESET },
451 { .int_msk = BIT(21), .msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
452 .reset_level = HNS3_GLOBAL_RESET },
453 { .int_msk = BIT(22), .msg = "tm_sch_rq_fifo_wr_err",
454 .reset_level = HNS3_GLOBAL_RESET },
455 { .int_msk = BIT(23), .msg = "tm_sch_rq_fifo_rd_err",
456 .reset_level = HNS3_GLOBAL_RESET },
457 { .int_msk = BIT(24), .msg = "tm_sch_nq_fifo_wr_err",
458 .reset_level = HNS3_GLOBAL_RESET },
459 { .int_msk = BIT(25), .msg = "tm_sch_nq_fifo_rd_err",
460 .reset_level = HNS3_GLOBAL_RESET },
461 { .int_msk = BIT(26), .msg = "tm_sch_roce_up_fifo_wr_err",
462 .reset_level = HNS3_GLOBAL_RESET },
463 { .int_msk = BIT(27), .msg = "tm_sch_roce_up_fifo_rd_err",
464 .reset_level = HNS3_GLOBAL_RESET },
465 { .int_msk = BIT(28), .msg = "tm_sch_rcb_byte_fifo_wr_err",
466 .reset_level = HNS3_GLOBAL_RESET },
467 { .int_msk = BIT(29), .msg = "tm_sch_rcb_byte_fifo_rd_err",
468 .reset_level = HNS3_GLOBAL_RESET },
469 { .int_msk = BIT(30), .msg = "tm_sch_ssu_byte_fifo_wr_err",
470 .reset_level = HNS3_GLOBAL_RESET },
471 { .int_msk = BIT(31), .msg = "tm_sch_ssu_byte_fifo_rd_err",
472 .reset_level = HNS3_GLOBAL_RESET },
473 { .int_msk = 0, .msg = NULL,
474 .reset_level = HNS3_NONE_RESET}
477 static const struct hns3_hw_error qcn_fifo_int[] = {
478 { .int_msk = BIT(0), .msg = "qcn_shap_gp0_sch_fifo_rd_err",
479 .reset_level = HNS3_GLOBAL_RESET },
480 { .int_msk = BIT(1), .msg = "qcn_shap_gp0_sch_fifo_wr_err",
481 .reset_level = HNS3_GLOBAL_RESET },
482 { .int_msk = BIT(2), .msg = "qcn_shap_gp1_sch_fifo_rd_err",
483 .reset_level = HNS3_GLOBAL_RESET },
484 { .int_msk = BIT(3), .msg = "qcn_shap_gp1_sch_fifo_wr_err",
485 .reset_level = HNS3_GLOBAL_RESET },
486 { .int_msk = BIT(4), .msg = "qcn_shap_gp2_sch_fifo_rd_err",
487 .reset_level = HNS3_GLOBAL_RESET },
488 { .int_msk = BIT(5), .msg = "qcn_shap_gp2_sch_fifo_wr_err",
489 .reset_level = HNS3_GLOBAL_RESET },
490 { .int_msk = BIT(6), .msg = "qcn_shap_gp3_sch_fifo_rd_err",
491 .reset_level = HNS3_GLOBAL_RESET },
492 { .int_msk = BIT(7), .msg = "qcn_shap_gp3_sch_fifo_wr_err",
493 .reset_level = HNS3_GLOBAL_RESET },
494 { .int_msk = BIT(8), .msg = "qcn_shap_gp0_offset_fifo_rd_err",
495 .reset_level = HNS3_GLOBAL_RESET },
496 { .int_msk = BIT(9), .msg = "qcn_shap_gp0_offset_fifo_wr_err",
497 .reset_level = HNS3_GLOBAL_RESET },
498 { .int_msk = BIT(10), .msg = "qcn_shap_gp1_offset_fifo_rd_err",
499 .reset_level = HNS3_GLOBAL_RESET },
500 { .int_msk = BIT(11), .msg = "qcn_shap_gp1_offset_fifo_wr_err",
501 .reset_level = HNS3_GLOBAL_RESET },
502 { .int_msk = BIT(12), .msg = "qcn_shap_gp2_offset_fifo_rd_err",
503 .reset_level = HNS3_GLOBAL_RESET },
504 { .int_msk = BIT(13), .msg = "qcn_shap_gp2_offset_fifo_wr_err",
505 .reset_level = HNS3_GLOBAL_RESET },
506 { .int_msk = BIT(14), .msg = "qcn_shap_gp3_offset_fifo_rd_err",
507 .reset_level = HNS3_GLOBAL_RESET },
508 { .int_msk = BIT(15), .msg = "qcn_shap_gp3_offset_fifo_wr_err",
509 .reset_level = HNS3_GLOBAL_RESET },
510 { .int_msk = BIT(16), .msg = "qcn_byte_info_fifo_rd_err",
511 .reset_level = HNS3_GLOBAL_RESET },
512 { .int_msk = BIT(17), .msg = "qcn_byte_info_fifo_wr_err",
513 .reset_level = HNS3_GLOBAL_RESET },
514 { .int_msk = 0, .msg = NULL,
515 .reset_level = HNS3_NONE_RESET}
518 static const struct hns3_hw_error qcn_ecc_int[] = {
519 { .int_msk = BIT(1), .msg = "qcn_byte_mem_ecc_mbit_err",
520 .reset_level = HNS3_GLOBAL_RESET },
521 { .int_msk = BIT(3), .msg = "qcn_time_mem_ecc_mbit_err",
522 .reset_level = HNS3_GLOBAL_RESET },
523 { .int_msk = BIT(5), .msg = "qcn_fb_mem_ecc_mbit_err",
524 .reset_level = HNS3_GLOBAL_RESET },
525 { .int_msk = BIT(7), .msg = "qcn_link_mem_ecc_mbit_err",
526 .reset_level = HNS3_GLOBAL_RESET },
527 { .int_msk = BIT(9), .msg = "qcn_rate_mem_ecc_mbit_err",
528 .reset_level = HNS3_GLOBAL_RESET },
529 { .int_msk = BIT(11), .msg = "qcn_tmplt_mem_ecc_mbit_err",
530 .reset_level = HNS3_GLOBAL_RESET },
531 { .int_msk = BIT(13), .msg = "qcn_shap_cfg_mem_ecc_mbit_err",
532 .reset_level = HNS3_GLOBAL_RESET },
533 { .int_msk = BIT(15), .msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
534 .reset_level = HNS3_GLOBAL_RESET },
535 { .int_msk = BIT(17), .msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
536 .reset_level = HNS3_GLOBAL_RESET },
537 { .int_msk = BIT(19), .msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
538 .reset_level = HNS3_GLOBAL_RESET },
539 { .int_msk = BIT(21), .msg = "qcn_gp3_barral_mem_ecc_mbit_err",
540 .reset_level = HNS3_GLOBAL_RESET },
541 { .int_msk = 0, .msg = NULL,
542 .reset_level = HNS3_NONE_RESET}
545 static const struct hns3_hw_error ncsi_ecc_int[] = {
546 { .int_msk = BIT(1), .msg = "ncsi_tx_ecc_mbit_err",
547 .reset_level = HNS3_NONE_RESET },
548 { .int_msk = 0, .msg = NULL,
549 .reset_level = HNS3_NONE_RESET}
552 static const struct hns3_hw_error ssu_fifo_overflow_int[] = {
553 { .int_msk = BIT(0), .msg = "ig_mac_inf_int",
554 .reset_level = HNS3_GLOBAL_RESET },
555 { .int_msk = BIT(1), .msg = "ig_host_inf_int",
556 .reset_level = HNS3_GLOBAL_RESET },
557 { .int_msk = BIT(2), .msg = "ig_roc_buf_int",
558 .reset_level = HNS3_GLOBAL_RESET },
559 { .int_msk = BIT(3), .msg = "ig_host_data_fifo_int",
560 .reset_level = HNS3_GLOBAL_RESET },
561 { .int_msk = BIT(4), .msg = "ig_host_key_fifo_int",
562 .reset_level = HNS3_GLOBAL_RESET },
563 { .int_msk = BIT(5), .msg = "tx_qcn_fifo_int",
564 .reset_level = HNS3_GLOBAL_RESET },
565 { .int_msk = BIT(6), .msg = "rx_qcn_fifo_int",
566 .reset_level = HNS3_GLOBAL_RESET },
567 { .int_msk = BIT(7), .msg = "tx_pf_rd_fifo_int",
568 .reset_level = HNS3_GLOBAL_RESET },
569 { .int_msk = BIT(8), .msg = "rx_pf_rd_fifo_int",
570 .reset_level = HNS3_GLOBAL_RESET },
571 { .int_msk = BIT(9), .msg = "qm_eof_fifo_int",
572 .reset_level = HNS3_GLOBAL_RESET },
573 { .int_msk = BIT(10), .msg = "mb_rlt_fifo_int",
574 .reset_level = HNS3_GLOBAL_RESET },
575 { .int_msk = BIT(11), .msg = "dup_uncopy_fifo_int",
576 .reset_level = HNS3_GLOBAL_RESET },
577 { .int_msk = BIT(12), .msg = "dup_cnt_rd_fifo_int",
578 .reset_level = HNS3_GLOBAL_RESET },
579 { .int_msk = BIT(13), .msg = "dup_cnt_drop_fifo_int",
580 .reset_level = HNS3_GLOBAL_RESET },
581 { .int_msk = BIT(14), .msg = "dup_cnt_wrb_fifo_int",
582 .reset_level = HNS3_GLOBAL_RESET },
583 { .int_msk = BIT(15), .msg = "host_cmd_fifo_int",
584 .reset_level = HNS3_GLOBAL_RESET },
585 { .int_msk = BIT(16), .msg = "mac_cmd_fifo_int",
586 .reset_level = HNS3_GLOBAL_RESET },
587 { .int_msk = BIT(17), .msg = "host_cmd_bitmap_empty_int",
588 .reset_level = HNS3_GLOBAL_RESET },
589 { .int_msk = BIT(18), .msg = "mac_cmd_bitmap_empty_int",
590 .reset_level = HNS3_GLOBAL_RESET },
591 { .int_msk = BIT(19), .msg = "dup_bitmap_empty_int",
592 .reset_level = HNS3_GLOBAL_RESET },
593 { .int_msk = BIT(20), .msg = "out_queue_bitmap_empty_int",
594 .reset_level = HNS3_GLOBAL_RESET },
595 { .int_msk = BIT(21), .msg = "bank2_bitmap_empty_int",
596 .reset_level = HNS3_GLOBAL_RESET },
597 { .int_msk = BIT(22), .msg = "bank1_bitmap_empty_int",
598 .reset_level = HNS3_GLOBAL_RESET },
599 { .int_msk = BIT(23), .msg = "bank0_bitmap_empty_int",
600 .reset_level = HNS3_GLOBAL_RESET },
601 { .int_msk = 0, .msg = NULL,
602 .reset_level = HNS3_NONE_RESET}
605 static const struct hns3_hw_error ssu_ets_tcg_int[] = {
606 { .int_msk = BIT(0), .msg = "ets_rd_int_rx_tcg",
607 .reset_level = HNS3_GLOBAL_RESET },
608 { .int_msk = BIT(1), .msg = "ets_wr_int_rx_tcg",
609 .reset_level = HNS3_GLOBAL_RESET },
610 { .int_msk = BIT(2), .msg = "ets_rd_int_tx_tcg",
611 .reset_level = HNS3_GLOBAL_RESET },
612 { .int_msk = BIT(3), .msg = "ets_wr_int_tx_tcg",
613 .reset_level = HNS3_GLOBAL_RESET },
614 { .int_msk = 0, .msg = NULL,
615 .reset_level = HNS3_NONE_RESET}
618 static const struct hns3_hw_error igu_egu_tnl_int[] = {
619 { .int_msk = BIT(0), .msg = "rx_buf_overflow",
620 .reset_level = HNS3_GLOBAL_RESET },
621 { .int_msk = BIT(1), .msg = "rx_stp_fifo_overflow",
622 .reset_level = HNS3_GLOBAL_RESET },
623 { .int_msk = BIT(2), .msg = "rx_stp_fifo_underflow",
624 .reset_level = HNS3_GLOBAL_RESET },
625 { .int_msk = BIT(3), .msg = "tx_buf_overflow",
626 .reset_level = HNS3_GLOBAL_RESET },
627 { .int_msk = BIT(4), .msg = "tx_buf_underrun",
628 .reset_level = HNS3_GLOBAL_RESET },
629 { .int_msk = BIT(5), .msg = "rx_stp_buf_overflow",
630 .reset_level = HNS3_GLOBAL_RESET },
631 { .int_msk = 0, .msg = NULL,
632 .reset_level = HNS3_NONE_RESET}
635 static const struct hns3_hw_error ssu_port_based_err_int[] = {
636 { .int_msk = BIT(0), .msg = "roc_pkt_without_key_port",
637 .reset_level = HNS3_FUNC_RESET },
638 { .int_msk = BIT(1), .msg = "tpu_pkt_without_key_port",
639 .reset_level = HNS3_GLOBAL_RESET },
640 { .int_msk = BIT(2), .msg = "igu_pkt_without_key_port",
641 .reset_level = HNS3_GLOBAL_RESET },
642 { .int_msk = BIT(3), .msg = "roc_eof_mis_match_port",
643 .reset_level = HNS3_GLOBAL_RESET },
644 { .int_msk = BIT(4), .msg = "tpu_eof_mis_match_port",
645 .reset_level = HNS3_GLOBAL_RESET },
646 { .int_msk = BIT(5), .msg = "igu_eof_mis_match_port",
647 .reset_level = HNS3_GLOBAL_RESET },
648 { .int_msk = BIT(6), .msg = "roc_sof_mis_match_port",
649 .reset_level = HNS3_GLOBAL_RESET },
650 { .int_msk = BIT(7), .msg = "tpu_sof_mis_match_port",
651 .reset_level = HNS3_GLOBAL_RESET },
652 { .int_msk = BIT(8), .msg = "igu_sof_mis_match_port",
653 .reset_level = HNS3_GLOBAL_RESET },
654 { .int_msk = BIT(11), .msg = "ets_rd_int_rx_port",
655 .reset_level = HNS3_GLOBAL_RESET },
656 { .int_msk = BIT(12), .msg = "ets_wr_int_rx_port",
657 .reset_level = HNS3_GLOBAL_RESET },
658 { .int_msk = BIT(13), .msg = "ets_rd_int_tx_port",
659 .reset_level = HNS3_GLOBAL_RESET },
660 { .int_msk = BIT(14), .msg = "ets_wr_int_tx_port",
661 .reset_level = HNS3_GLOBAL_RESET },
662 { .int_msk = 0, .msg = NULL,
663 .reset_level = HNS3_NONE_RESET}
666 static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = {
667 { .desc_offset = 0, .data_offset = 0,
668 .msg = "IMP_TCM_ECC_INT_STS",
669 .hw_err = imp_tcm_ecc_int },
670 { .desc_offset = 0, .data_offset = 1,
671 .msg = "CMDQ_MEM_ECC_INT_STS",
672 .hw_err = cmdq_mem_ecc_int },
673 { .desc_offset = 0, .data_offset = 2,
674 .msg = "IMP_RD_POISON_INT_STS",
675 .hw_err = imp_rd_poison_int },
676 { .desc_offset = 0, .data_offset = 3,
677 .msg = "TQP_INT_ECC_INT_STS",
678 .hw_err = tqp_int_ecc_int },
679 { .desc_offset = 0, .data_offset = 4,
680 .msg = "MSIX_ECC_INT_STS",
681 .hw_err = msix_ecc_int },
682 { .desc_offset = 2, .data_offset = 2,
683 .msg = "SSU_ECC_MULTI_BIT_INT_0",
684 .hw_err = ssu_ecc_multi_bit_int_0 },
685 { .desc_offset = 2, .data_offset = 3,
686 .msg = "SSU_ECC_MULTI_BIT_INT_1",
687 .hw_err = ssu_ecc_multi_bit_int_1 },
688 { .desc_offset = 2, .data_offset = 4,
689 .msg = "SSU_COMMON_ERR_INT",
690 .hw_err = ssu_common_ecc_int },
691 { .desc_offset = 3, .data_offset = 0,
692 .msg = "IGU_INT_STS",
694 { .desc_offset = 4, .data_offset = 1,
695 .msg = "PPP_MPF_ABNORMAL_INT_ST1",
696 .hw_err = ppp_mpf_abnormal_int_st1 },
697 { .desc_offset = 4, .data_offset = 3,
698 .msg = "PPP_MPF_ABNORMAL_INT_ST3",
699 .hw_err = ppp_mpf_abnormal_int_st3 },
700 { .desc_offset = 5, .data_offset = 1,
701 .msg = "PPU_MPF_ABNORMAL_INT_ST1",
702 .hw_err = ppu_mpf_abnormal_int_st1 },
703 { .desc_offset = 5, .data_offset = 2,
704 .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS",
705 .hw_err = ppu_mpf_abnormal_int_st2_ras },
706 { .desc_offset = 5, .data_offset = 3,
707 .msg = "PPU_MPF_ABNORMAL_INT_ST3",
708 .hw_err = ppu_mpf_abnormal_int_st3 },
709 { .desc_offset = 6, .data_offset = 0,
710 .msg = "TM_SCH_RINT",
711 .hw_err = tm_sch_int },
712 { .desc_offset = 7, .data_offset = 0,
713 .msg = "QCN_FIFO_RINT",
714 .hw_err = qcn_fifo_int },
715 { .desc_offset = 7, .data_offset = 1,
716 .msg = "QCN_ECC_RINT",
717 .hw_err = qcn_ecc_int },
718 { .desc_offset = 9, .data_offset = 0,
719 .msg = "NCSI_ECC_INT_RPT",
720 .hw_err = ncsi_ecc_int },
721 { .desc_offset = 0, .data_offset = 0,
726 static const struct hns3_hw_error_desc pf_ras_err_tbl[] = {
727 { .desc_offset = 0, .data_offset = 0,
728 .msg = "SSU_PORT_BASED_ERR_INT_RAS",
729 .hw_err = ssu_port_based_err_int },
730 { .desc_offset = 0, .data_offset = 1,
731 .msg = "SSU_FIFO_OVERFLOW_INT",
732 .hw_err = ssu_fifo_overflow_int },
733 { .desc_offset = 0, .data_offset = 2,
734 .msg = "SSU_ETS_TCG_INT",
735 .hw_err = ssu_ets_tcg_int },
736 { .desc_offset = 1, .data_offset = 0,
737 .msg = "IGU_EGU_TNL_INT_STS",
738 .hw_err = igu_egu_tnl_int },
739 { .desc_offset = 3, .data_offset = 0,
740 .msg = "PPU_PF_ABNORMAL_INT_ST_RAS",
741 .hw_err = ppu_pf_abnormal_int_ras },
742 { .desc_offset = 0, .data_offset = 0,
747 static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = {
748 { .desc_offset = 1, .data_offset = 0,
749 .msg = "MAC_AFIFO_TNL_INT_R",
750 .hw_err = mac_afifo_tnl_int },
751 { .desc_offset = 5, .data_offset = 2,
752 .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX",
753 .hw_err = ppu_mpf_abnormal_int_st2_msix },
754 { .desc_offset = 0, .data_offset = 0,
759 static const struct hns3_hw_error_desc pf_msix_err_tbl[] = {
760 { .desc_offset = 0, .data_offset = 0,
761 .msg = "SSU_PORT_BASED_ERR_INT_MSIX",
762 .hw_err = ssu_port_based_pf_int },
763 { .desc_offset = 2, .data_offset = 0,
764 .msg = "PPP_PF_ABNORMAL_INT_ST0",
765 .hw_err = ppp_pf_abnormal_int },
766 { .desc_offset = 3, .data_offset = 0,
767 .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX",
768 .hw_err = ppu_pf_abnormal_int_msix },
769 { .desc_offset = 0, .data_offset = 0,
774 enum hns3_hw_err_type {
782 hns3_config_ncsi_hw_err_int(struct hns3_adapter *hns, bool en)
784 struct hns3_hw *hw = &hns->hw;
785 struct hns3_cmd_desc desc;
788 /* configure NCSI error interrupts */
789 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_NCSI_INT_EN, false);
791 desc.data[0] = rte_cpu_to_le_32(HNS3_NCSI_ERR_INT_EN);
793 ret = hns3_cmd_send(hw, &desc, 1);
795 hns3_err(hw, "fail to %s NCSI error interrupts, ret = %d",
796 en ? "enable" : "disable", ret);
802 enable_igu_egu_err_intr(struct hns3_adapter *hns, bool en)
804 struct hns3_hw *hw = &hns->hw;
805 struct hns3_cmd_desc desc;
808 /* configure IGU,EGU error interrupts */
809 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_COMMON_INT_EN, false);
811 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_ENABLE);
813 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_DISABLE);
815 desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_EN_MASK);
817 ret = hns3_cmd_send(hw, &desc, 1);
819 hns3_err(hw, "fail to %s IGU common interrupts, ret = %d",
820 en ? "enable" : "disable", ret);
824 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_EGU_TNL_INT_EN, false);
826 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN);
828 desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN_MASK);
830 ret = hns3_cmd_send(hw, &desc, 1);
832 hns3_err(hw, "fail to %s IGU-EGU TNL interrupts, ret = %d",
833 en ? "enable" : "disable", ret);
837 return hns3_config_ncsi_hw_err_int(hns, en);
841 config_ppp_err_intr(struct hns3_adapter *hns, uint32_t cmd, bool en)
843 struct hns3_hw *hw = &hns->hw;
844 struct hns3_cmd_desc desc[2];
847 /* configure PPP error interrupts */
848 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
849 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
850 hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
852 if (cmd == HNS3_OPC_PPP_CMD0_INT_CMD) {
855 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN);
857 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN);
859 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN);
863 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK);
865 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK);
867 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN_MASK);
868 } else if (cmd == HNS3_OPC_PPP_CMD1_INT_CMD) {
871 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN);
873 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN);
877 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK);
879 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK);
882 ret = hns3_cmd_send(hw, &desc[0], 2);
884 hns3_err(hw, "fail to %s PPP error int, ret = %d",
885 en ? "enable" : "disable", ret);
891 enable_ppp_err_intr(struct hns3_adapter *hns, bool en)
895 ret = config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD0_INT_CMD, en);
899 return config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD1_INT_CMD, en);
903 enable_ssu_err_intr(struct hns3_adapter *hns, bool en)
905 struct hns3_hw *hw = &hns->hw;
906 struct hns3_cmd_desc desc[2];
909 /* configure SSU ecc error interrupts */
910 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_ECC_INT_CMD, false);
911 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
912 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_ECC_INT_CMD, false);
915 rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN);
917 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN);
919 rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN);
922 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK);
924 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK);
925 desc[1].data[2] = rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK);
927 ret = hns3_cmd_send(hw, &desc[0], 2);
929 hns3_err(hw, "fail to %s SSU ECC error interrupt, ret = %d",
930 en ? "enable" : "disable", ret);
934 /* configure SSU common error interrupts */
935 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_COMMON_INT_CMD, false);
936 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
937 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_COMMON_INT_CMD, false);
940 desc[0].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN);
942 rte_cpu_to_le_32(HNS3_SSU_PORT_BASED_ERR_INT_EN);
944 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN);
947 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN_MASK |
948 HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK);
950 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK);
952 ret = hns3_cmd_send(hw, &desc[0], 2);
954 hns3_err(hw, "fail to %s SSU COMMON error intr, ret = %d",
955 en ? "enable" : "disable", ret);
961 config_ppu_err_intrs(struct hns3_adapter *hns, uint32_t cmd, bool en)
963 struct hns3_hw *hw = &hns->hw;
964 struct hns3_cmd_desc desc[2];
967 /* configure PPU error interrupts */
969 case HNS3_OPC_PPU_MPF_ECC_INT_CMD:
970 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
971 desc[0].flag |= HNS3_CMD_FLAG_NEXT;
972 hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
974 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN;
975 desc[0].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN;
976 desc[1].data[3] = HNS3_PPU_MPF_ABNORMAL_INT3_EN;
977 desc[1].data[4] = HNS3_PPU_MPF_ABNORMAL_INT2_EN;
980 desc[1].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK;
981 desc[1].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK;
982 desc[1].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK;
983 desc[1].data[3] |= HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK;
986 case HNS3_OPC_PPU_MPF_OTHER_INT_CMD:
987 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
989 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2;
991 desc[0].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK;
993 case HNS3_OPC_PPU_PF_OTHER_INT_CMD:
994 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
996 desc[0].data[0] = HNS3_PPU_PF_ABNORMAL_INT_EN;
998 desc[0].data[2] = HNS3_PPU_PF_ABNORMAL_INT_EN_MASK;
1002 "Invalid cmd(%u) to configure PPU error interrupts.",
1007 return hns3_cmd_send(hw, &desc[0], num);
1011 enable_ppu_err_intr(struct hns3_adapter *hns, bool en)
1013 struct hns3_hw *hw = &hns->hw;
1016 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_MPF_ECC_INT_CMD, en);
1018 hns3_err(hw, "fail to %s PPU MPF ECC error intr, ret = %d",
1019 en ? "enable" : "disable", ret);
1023 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_MPF_OTHER_INT_CMD, en);
1025 hns3_err(hw, "fail to %s PPU MPF other intr, ret = %d",
1026 en ? "enable" : "disable", ret);
1030 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_PF_OTHER_INT_CMD, en);
1032 hns3_err(hw, "fail to %s PPU PF error interrupts, ret = %d",
1033 en ? "enable" : "disable", ret);
1038 enable_tm_err_intr(struct hns3_adapter *hns, bool en)
1040 struct hns3_hw *hw = &hns->hw;
1041 struct hns3_cmd_desc desc;
1044 /* configure TM SCH error interrupts */
1045 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_SCH_ECC_INT_EN, false);
1047 desc.data[0] = rte_cpu_to_le_32(HNS3_TM_SCH_ECC_ERR_INT_EN);
1049 ret = hns3_cmd_send(hw, &desc, 1);
1051 hns3_err(hw, "fail to %s TM SCH interrupts, ret = %d",
1052 en ? "enable" : "disable", ret);
1056 /* configure TM QCN hw errors */
1057 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QCN_MEM_INT_CFG, true);
1058 ret = hns3_cmd_send(hw, &desc, 1);
1060 hns3_err(hw, "fail to read TM QCN CFG status, ret = %d\n", ret);
1064 hns3_cmd_reuse_desc(&desc, false);
1066 desc.data[1] = rte_cpu_to_le_32(HNS3_TM_QCN_MEM_ERR_INT_EN);
1068 ret = hns3_cmd_send(hw, &desc, 1);
1070 hns3_err(hw, "fail to %s TM QCN mem errors, ret = %d\n",
1071 en ? "enable" : "disable", ret);
1077 enable_common_err_intr(struct hns3_adapter *hns, bool en)
1079 struct hns3_hw *hw = &hns->hw;
1080 struct hns3_cmd_desc desc[2];
1083 /* configure common error interrupts */
1084 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_COMMON_ECC_INT_CFG, false);
1085 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1086 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_COMMON_ECC_INT_CFG, false);
1090 rte_cpu_to_le_32(HNS3_IMP_TCM_ECC_ERR_INT_EN);
1092 rte_cpu_to_le_32(HNS3_CMDQ_NIC_ECC_ERR_INT_EN);
1094 rte_cpu_to_le_32(HNS3_IMP_RD_POISON_ERR_INT_EN);
1096 rte_cpu_to_le_32(HNS3_TQP_ECC_ERR_INT_EN |
1097 HNS3_MSIX_SRAM_ECC_ERR_INT_EN);
1099 rte_cpu_to_le_32(HNS3_IMP_ITCM4_ECC_ERR_INT_EN);
1102 desc[1].data[0] = rte_cpu_to_le_32(HNS3_IMP_TCM_ECC_ERR_INT_EN_MASK);
1103 desc[1].data[2] = rte_cpu_to_le_32(HNS3_CMDQ_NIC_ECC_ERR_INT_EN_MASK);
1104 desc[1].data[3] = rte_cpu_to_le_32(HNS3_IMP_RD_POISON_ERR_INT_EN_MASK);
1105 desc[1].data[4] = rte_cpu_to_le_32(HNS3_TQP_ECC_ERR_INT_EN_MASK |
1106 HNS3_MSIX_SRAM_ECC_ERR_INT_EN_MASK);
1107 desc[1].data[5] = rte_cpu_to_le_32(HNS3_IMP_ITCM4_ECC_ERR_INT_EN_MASK);
1109 ret = hns3_cmd_send(hw, &desc[0], RTE_DIM(desc));
1111 hns3_err(hw, "fail to %s common err interrupts, ret = %d\n",
1112 en ? "enable" : "disable", ret);
1118 enable_mac_err_intr(struct hns3_adapter *hns, bool en)
1120 struct hns3_hw *hw = &hns->hw;
1121 struct hns3_cmd_desc desc;
1124 /* configure MAC common error interrupts */
1125 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_COMMON_INT_EN, false);
1127 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN);
1129 desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN_MASK);
1131 ret = hns3_cmd_send(hw, &desc, 1);
1133 hns3_err(hw, "fail to %s MAC COMMON error intr: %d",
1134 en ? "enable" : "disable", ret);
1139 static const struct hns3_hw_blk hw_blk[] = {
1142 .enable_err_intr = enable_igu_egu_err_intr,
1146 .enable_err_intr = enable_ppp_err_intr,
1150 .enable_err_intr = enable_ssu_err_intr,
1154 .enable_err_intr = enable_ppu_err_intr,
1158 .enable_err_intr = enable_tm_err_intr,
1162 .enable_err_intr = enable_common_err_intr,
1166 .enable_err_intr = enable_mac_err_intr,
1170 .enable_err_intr = NULL,
1175 hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool en)
1177 const struct hns3_hw_blk *module = hw_blk;
1180 while (module->enable_err_intr) {
1181 ret = module->enable_err_intr(hns, en);
1191 static enum hns3_reset_level
1192 hns3_find_highest_level(struct hns3_adapter *hns, const char *reg,
1193 const struct hns3_hw_error *err, uint32_t err_sts)
1195 enum hns3_reset_level reset_level = HNS3_FUNC_RESET;
1196 struct hns3_hw *hw = &hns->hw;
1197 bool need_reset = false;
1200 if (err->int_msk & err_sts) {
1201 hns3_warn(hw, "%s %s found [error status=0x%x]",
1202 reg, err->msg, err_sts);
1203 if (err->reset_level != HNS3_NONE_RESET &&
1204 err->reset_level >= reset_level) {
1205 reset_level = err->reset_level;
1208 hns3_error_int_stats_add(hns, reg);
1215 return HNS3_NONE_RESET;
1219 query_num_bds(struct hns3_hw *hw, bool is_ras, uint32_t *mpf_bd_num,
1220 uint32_t *pf_bd_num)
1222 uint32_t mpf_min_bd_num, pf_min_bd_num;
1223 uint32_t mpf_bd_num_val, pf_bd_num_val;
1224 enum hns3_opcode_type opcode;
1225 struct hns3_cmd_desc desc;
1229 opcode = HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM;
1230 mpf_min_bd_num = HNS3_MPF_RAS_INT_MIN_BD_NUM;
1231 pf_min_bd_num = HNS3_PF_RAS_INT_MIN_BD_NUM;
1233 opcode = HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM;
1234 mpf_min_bd_num = HNS3_MPF_MSIX_INT_MIN_BD_NUM;
1235 pf_min_bd_num = HNS3_PF_MSIX_INT_MIN_BD_NUM;
1238 hns3_cmd_setup_basic_desc(&desc, opcode, true);
1239 ret = hns3_cmd_send(hw, &desc, 1);
1241 hns3_err(hw, "query num bds in msix failed, ret = %d", ret);
1245 mpf_bd_num_val = rte_le_to_cpu_32(desc.data[0]);
1246 pf_bd_num_val = rte_le_to_cpu_32(desc.data[1]);
1247 if (mpf_bd_num_val < mpf_min_bd_num || pf_bd_num_val < pf_min_bd_num) {
1248 hns3_err(hw, "error bd num: mpf(%u), min_mpf(%u), "
1249 "pf(%u), min_pf(%u)\n", mpf_bd_num_val, mpf_min_bd_num,
1250 pf_bd_num_val, pf_min_bd_num);
1254 *mpf_bd_num = mpf_bd_num_val;
1255 *pf_bd_num = pf_bd_num_val;
1261 hns3_intr_unregister(const struct rte_intr_handle *hdl,
1262 rte_intr_callback_fn cb_fn, void *cb_arg)
1268 ret = rte_intr_callback_unregister(hdl, cb_fn, cb_arg);
1271 } else if (ret != -EAGAIN) {
1272 PMD_INIT_LOG(ERR, "Failed to unregister intr: %d", ret);
1275 rte_delay_ms(HNS3_INTR_UNREG_FAIL_DELAY_MS);
1276 } while (retry_cnt++ < HNS3_INTR_UNREG_FAIL_RETRY_CNT);
1280 hns3_get_hw_error_status(struct hns3_cmd_desc *desc, uint8_t desc_offset,
1281 uint8_t data_offset)
1284 uint32_t *desc_data;
1286 if (desc_offset == 0)
1287 status = rte_le_to_cpu_32(desc[desc_offset].data[data_offset]);
1289 desc_data = (uint32_t *)&desc[desc_offset];
1290 status = rte_le_to_cpu_32(*(desc_data + data_offset));
1297 hns3_handle_hw_error(struct hns3_adapter *hns, struct hns3_cmd_desc *desc,
1298 int num, uint64_t *levels, enum hns3_hw_err_type err_type)
1300 const struct hns3_hw_error_desc *err = pf_ras_err_tbl;
1301 enum hns3_opcode_type opcode;
1302 enum hns3_reset_level req_level;
1303 struct hns3_hw *hw = &hns->hw;
1309 err = mpf_msix_err_tbl;
1310 opcode = HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT;
1313 err = pf_msix_err_tbl;
1314 opcode = HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT;
1317 err = mpf_ras_err_tbl;
1318 opcode = HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT;
1321 err = pf_ras_err_tbl;
1322 opcode = HNS3_OPC_QUERY_CLEAR_PF_RAS_INT;
1325 hns3_err(hw, "error hardware err_type = %d\n", err_type);
1329 /* query all hardware errors */
1330 hns3_cmd_setup_basic_desc(&desc[0], opcode, true);
1331 ret = hns3_cmd_send(hw, &desc[0], num);
1333 hns3_err(hw, "query hw err int 0x%x cmd failed, ret = %d\n",
1338 /* traverses the error table and process based on the error type */
1340 status = hns3_get_hw_error_status(desc, err->desc_offset,
1344 * set the reset_level or non_reset flag based on
1345 * the error type and add error statistics. here just
1346 * set the flag, the actual reset action is in
1347 * hns3_msix_process.
1349 req_level = hns3_find_highest_level(hns, err->msg,
1352 hns3_atomic_set_bit(req_level, levels);
1357 /* clear all hardware errors */
1358 hns3_cmd_reuse_desc(&desc[0], false);
1359 ret = hns3_cmd_send(hw, &desc[0], num);
1361 hns3_err(hw, "clear all hw err int cmd failed, ret = %d\n",
1368 hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels)
1370 uint32_t mpf_bd_num, pf_bd_num, bd_num;
1371 struct hns3_hw *hw = &hns->hw;
1372 struct hns3_cmd_desc *desc;
1375 /* query the number of bds for the MSIx int status */
1376 ret = query_num_bds(hw, false, &mpf_bd_num, &pf_bd_num);
1378 hns3_err(hw, "fail to query msix int status bd num: ret = %d",
1383 bd_num = RTE_MAX(mpf_bd_num, pf_bd_num);
1384 desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0);
1387 "fail to zmalloc desc for handling msix error, size = %zu",
1388 bd_num * sizeof(struct hns3_cmd_desc));
1392 /* handle all main PF MSIx errors */
1393 ret = hns3_handle_hw_error(hns, desc, mpf_bd_num, levels, MPF_MSIX_ERR);
1395 hns3_err(hw, "fail to handle all main pf msix errors, ret = %d",
1400 memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc));
1402 /* handle all PF MSIx errors */
1403 ret = hns3_handle_hw_error(hns, desc, pf_bd_num, levels, PF_MSIX_ERR);
1405 hns3_err(hw, "fail to handle all pf msix errors, ret = %d",
1415 hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels)
1417 uint32_t mpf_bd_num, pf_bd_num, bd_num;
1418 struct hns3_hw *hw = &hns->hw;
1419 struct hns3_cmd_desc *desc;
1423 status = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
1424 if ((status & HNS3_RAS_REG_NFE_MASK) == 0)
1427 /* query the number of bds for the RAS int status */
1428 ret = query_num_bds(hw, true, &mpf_bd_num, &pf_bd_num);
1430 hns3_err(hw, "fail to query ras int status bd num: ret = %d",
1435 bd_num = RTE_MAX(mpf_bd_num, pf_bd_num);
1436 desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0);
1439 "fail to zmalloc desc for handing ras error, size = %zu",
1440 bd_num * sizeof(struct hns3_cmd_desc));
1444 /* handle all main PF RAS errors */
1445 ret = hns3_handle_hw_error(hns, desc, mpf_bd_num, levels, MPF_RAS_ERR);
1447 hns3_err(hw, "fail to handle all main pf ras errors, ret = %d",
1452 memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc));
1454 /* handle all PF RAS errors */
1455 ret = hns3_handle_hw_error(hns, desc, pf_bd_num, levels, PF_RAS_ERR);
1457 hns3_err(hw, "fail to handle all pf ras errors, ret = %d", ret);
1466 hns3_reset_init(struct hns3_hw *hw)
1468 rte_spinlock_init(&hw->lock);
1469 hw->reset.level = HNS3_NONE_RESET;
1470 hw->reset.stage = RESET_STAGE_NONE;
1471 hw->reset.request = 0;
1472 hw->reset.pending = 0;
1473 rte_atomic16_init(&hw->reset.resetting);
1474 rte_atomic16_init(&hw->reset.disable_cmd);
1475 hw->reset.wait_data = rte_zmalloc("wait_data",
1476 sizeof(struct hns3_wait_data), 0);
1477 if (!hw->reset.wait_data) {
1478 PMD_INIT_LOG(ERR, "Failed to allocate memory for wait_data");
1485 hns3_schedule_reset(struct hns3_adapter *hns)
1487 struct hns3_hw *hw = &hns->hw;
1489 /* Reschedule the reset process after successful initialization */
1490 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {
1491 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_PENDING);
1495 if (hw->adapter_state >= HNS3_NIC_CLOSED)
1498 /* Schedule restart alarm if it is not scheduled yet */
1499 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_REQUESTED)
1501 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED)
1502 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);
1503 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
1505 rte_eal_alarm_set(SWITCH_CONTEXT_US, hw->reset.ops->reset_service, hns);
1509 hns3_schedule_delayed_reset(struct hns3_adapter *hns)
1511 #define DEFERRED_SCHED_US (3 * MSEC_PER_SEC * USEC_PER_MSEC)
1512 struct hns3_hw *hw = &hns->hw;
1514 /* Do nothing if it is uninited or closed */
1515 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED ||
1516 hw->adapter_state >= HNS3_NIC_CLOSED) {
1520 if (rte_atomic16_read(&hns->hw.reset.schedule) != SCHEDULE_NONE)
1522 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_DEFERRED);
1523 rte_eal_alarm_set(DEFERRED_SCHED_US, hw->reset.ops->reset_service, hns);
1527 hns3_wait_callback(void *param)
1529 struct hns3_wait_data *data = (struct hns3_wait_data *)param;
1530 struct hns3_adapter *hns = data->hns;
1531 struct hns3_hw *hw = &hns->hw;
1536 if (data->check_completion) {
1538 * Check if the current time exceeds the deadline
1539 * or a pending reset coming, or reset during close.
1541 msec = get_timeofday_ms();
1542 if (msec > data->end_ms || is_reset_pending(hns) ||
1543 hw->adapter_state == HNS3_NIC_CLOSING) {
1547 done = data->check_completion(hw);
1551 if (!done && data->count > 0) {
1552 rte_eal_alarm_set(data->interval, hns3_wait_callback, data);
1556 data->result = HNS3_WAIT_SUCCESS;
1558 hns3_err(hw, "%s wait timeout at stage %d",
1559 reset_string[hw->reset.level], hw->reset.stage);
1560 data->result = HNS3_WAIT_TIMEOUT;
1562 hns3_schedule_reset(hns);
1566 hns3_notify_reset_ready(struct hns3_hw *hw, bool enable)
1570 reg_val = hns3_read_dev(hw, HNS3_CMDQ_TX_DEPTH_REG);
1572 reg_val |= HNS3_NIC_SW_RST_RDY;
1574 reg_val &= ~HNS3_NIC_SW_RST_RDY;
1576 hns3_write_dev(hw, HNS3_CMDQ_TX_DEPTH_REG, reg_val);
1580 hns3_reset_req_hw_reset(struct hns3_adapter *hns)
1582 struct hns3_hw *hw = &hns->hw;
1584 if (hw->reset.wait_data->result == HNS3_WAIT_UNKNOWN) {
1585 hw->reset.wait_data->hns = hns;
1586 hw->reset.wait_data->check_completion = NULL;
1587 hw->reset.wait_data->interval = HNS3_RESET_SYNC_US;
1588 hw->reset.wait_data->count = 1;
1589 hw->reset.wait_data->result = HNS3_WAIT_REQUEST;
1590 rte_eal_alarm_set(hw->reset.wait_data->interval,
1591 hns3_wait_callback, hw->reset.wait_data);
1593 } else if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)
1596 /* inform hardware that preparatory work is done */
1597 hns3_notify_reset_ready(hw, true);
1602 hns3_clear_reset_level(struct hns3_hw *hw, uint64_t *levels)
1604 uint64_t merge_cnt = hw->reset.stats.merge_cnt;
1607 switch (hw->reset.level) {
1608 case HNS3_IMP_RESET:
1609 hns3_atomic_clear_bit(HNS3_IMP_RESET, levels);
1610 tmp = hns3_test_and_clear_bit(HNS3_GLOBAL_RESET, levels);
1611 HNS3_CHECK_MERGE_CNT(tmp);
1612 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);
1613 HNS3_CHECK_MERGE_CNT(tmp);
1615 case HNS3_GLOBAL_RESET:
1616 hns3_atomic_clear_bit(HNS3_GLOBAL_RESET, levels);
1617 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);
1618 HNS3_CHECK_MERGE_CNT(tmp);
1620 case HNS3_FUNC_RESET:
1621 hns3_atomic_clear_bit(HNS3_FUNC_RESET, levels);
1624 hns3_atomic_clear_bit(HNS3_VF_RESET, levels);
1625 tmp = hns3_test_and_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);
1626 HNS3_CHECK_MERGE_CNT(tmp);
1627 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
1628 HNS3_CHECK_MERGE_CNT(tmp);
1630 case HNS3_VF_FULL_RESET:
1631 hns3_atomic_clear_bit(HNS3_VF_FULL_RESET, levels);
1632 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
1633 HNS3_CHECK_MERGE_CNT(tmp);
1635 case HNS3_VF_PF_FUNC_RESET:
1636 hns3_atomic_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);
1637 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
1638 HNS3_CHECK_MERGE_CNT(tmp);
1640 case HNS3_VF_FUNC_RESET:
1641 hns3_atomic_clear_bit(HNS3_VF_FUNC_RESET, levels);
1643 case HNS3_FLR_RESET:
1644 hns3_atomic_clear_bit(HNS3_FLR_RESET, levels);
1646 case HNS3_NONE_RESET:
1650 if (merge_cnt != hw->reset.stats.merge_cnt)
1652 "No need to do low-level reset after %s reset. "
1653 "merge cnt: %" PRIx64 " total merge cnt: %" PRIx64,
1654 reset_string[hw->reset.level],
1655 hw->reset.stats.merge_cnt - merge_cnt,
1656 hw->reset.stats.merge_cnt);
1660 hns3_reset_err_handle(struct hns3_adapter *hns)
1662 #define MAX_RESET_FAIL_CNT 5
1664 struct hns3_hw *hw = &hns->hw;
1666 if (hw->adapter_state == HNS3_NIC_CLOSING)
1669 if (is_reset_pending(hns)) {
1670 hw->reset.attempts = 0;
1671 hw->reset.stats.fail_cnt++;
1672 hns3_warn(hw, "%s reset fail because new Reset is pending "
1673 "attempts:%" PRIx64,
1674 reset_string[hw->reset.level],
1675 hw->reset.stats.fail_cnt);
1676 hw->reset.level = HNS3_NONE_RESET;
1680 hw->reset.attempts++;
1681 if (hw->reset.attempts < MAX_RESET_FAIL_CNT) {
1682 hns3_atomic_set_bit(hw->reset.level, &hw->reset.pending);
1683 hns3_warn(hw, "%s retry to reset attempts: %d",
1684 reset_string[hw->reset.level],
1685 hw->reset.attempts);
1690 * Failure to reset does not mean that the network port is
1691 * completely unavailable, so cmd still needs to be initialized.
1692 * Regardless of whether the execution is successful or not, the
1693 * flow after execution must be continued.
1695 if (rte_atomic16_read(&hw->reset.disable_cmd))
1696 (void)hns3_cmd_init(hw);
1698 hw->reset.attempts = 0;
1699 hw->reset.stats.fail_cnt++;
1700 hns3_warn(hw, "%s reset fail fail_cnt:%" PRIx64 " success_cnt:%" PRIx64
1701 " global_cnt:%" PRIx64 " imp_cnt:%" PRIx64
1702 " request_cnt:%" PRIx64 " exec_cnt:%" PRIx64
1703 " merge_cnt:%" PRIx64 "adapter_state:%d",
1704 reset_string[hw->reset.level], hw->reset.stats.fail_cnt,
1705 hw->reset.stats.success_cnt, hw->reset.stats.global_cnt,
1706 hw->reset.stats.imp_cnt, hw->reset.stats.request_cnt,
1707 hw->reset.stats.exec_cnt, hw->reset.stats.merge_cnt,
1710 /* IMP no longer waiting the ready flag */
1711 hns3_notify_reset_ready(hw, true);
1716 hns3_reset_pre(struct hns3_adapter *hns)
1718 struct hns3_hw *hw = &hns->hw;
1722 if (hw->reset.stage == RESET_STAGE_NONE) {
1723 rte_atomic16_set(&hns->hw.reset.resetting, 1);
1724 hw->reset.stage = RESET_STAGE_DOWN;
1725 ret = hw->reset.ops->stop_service(hns);
1726 gettimeofday(&tv, NULL);
1728 hns3_warn(hw, "Reset step1 down fail=%d time=%ld.%.6ld",
1729 ret, tv.tv_sec, tv.tv_usec);
1732 hns3_warn(hw, "Reset step1 down success time=%ld.%.6ld",
1733 tv.tv_sec, tv.tv_usec);
1734 hw->reset.stage = RESET_STAGE_PREWAIT;
1736 if (hw->reset.stage == RESET_STAGE_PREWAIT) {
1737 ret = hw->reset.ops->prepare_reset(hns);
1738 gettimeofday(&tv, NULL);
1741 "Reset step2 prepare wait fail=%d time=%ld.%.6ld",
1742 ret, tv.tv_sec, tv.tv_usec);
1745 hns3_warn(hw, "Reset step2 prepare wait success time=%ld.%.6ld",
1746 tv.tv_sec, tv.tv_usec);
1747 hw->reset.stage = RESET_STAGE_REQ_HW_RESET;
1748 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;
1754 hns3_reset_post(struct hns3_adapter *hns)
1756 #define TIMEOUT_RETRIES_CNT 5
1757 struct hns3_hw *hw = &hns->hw;
1758 struct timeval tv_delta;
1762 if (hw->adapter_state == HNS3_NIC_CLOSING) {
1763 hns3_warn(hw, "Don't do reset_post during closing, just uninit cmd");
1764 hns3_cmd_uninit(hw);
1768 if (hw->reset.stage == RESET_STAGE_DEV_INIT) {
1769 rte_spinlock_lock(&hw->lock);
1770 if (hw->reset.mbuf_deferred_free) {
1771 hns3_dev_release_mbufs(hns);
1772 hw->reset.mbuf_deferred_free = false;
1774 ret = hw->reset.ops->reinit_dev(hns);
1775 rte_spinlock_unlock(&hw->lock);
1776 gettimeofday(&tv, NULL);
1778 hns3_warn(hw, "Reset step5 devinit fail=%d retries=%d",
1779 ret, hw->reset.retries);
1782 hns3_warn(hw, "Reset step5 devinit success time=%ld.%.6ld",
1783 tv.tv_sec, tv.tv_usec);
1784 hw->reset.retries = 0;
1785 hw->reset.stage = RESET_STAGE_RESTORE;
1786 rte_eal_alarm_set(SWITCH_CONTEXT_US,
1787 hw->reset.ops->reset_service, hns);
1790 if (hw->reset.stage == RESET_STAGE_RESTORE) {
1791 rte_spinlock_lock(&hw->lock);
1792 ret = hw->reset.ops->restore_conf(hns);
1793 rte_spinlock_unlock(&hw->lock);
1794 gettimeofday(&tv, NULL);
1797 "Reset step6 restore fail=%d retries=%d",
1798 ret, hw->reset.retries);
1801 hns3_warn(hw, "Reset step6 restore success time=%ld.%.6ld",
1802 tv.tv_sec, tv.tv_usec);
1803 hw->reset.retries = 0;
1804 hw->reset.stage = RESET_STAGE_DONE;
1806 if (hw->reset.stage == RESET_STAGE_DONE) {
1807 /* IMP will wait ready flag before reset */
1808 hns3_notify_reset_ready(hw, false);
1809 hns3_clear_reset_level(hw, &hw->reset.pending);
1810 rte_atomic16_clear(&hns->hw.reset.resetting);
1811 hw->reset.attempts = 0;
1812 hw->reset.stats.success_cnt++;
1813 hw->reset.stage = RESET_STAGE_NONE;
1814 rte_spinlock_lock(&hw->lock);
1815 hw->reset.ops->start_service(hns);
1816 rte_spinlock_unlock(&hw->lock);
1817 gettimeofday(&tv, NULL);
1818 timersub(&tv, &hw->reset.start_time, &tv_delta);
1819 hns3_warn(hw, "%s reset done fail_cnt:%" PRIx64
1820 " success_cnt:%" PRIx64 " global_cnt:%" PRIx64
1821 " imp_cnt:%" PRIx64 " request_cnt:%" PRIx64
1822 " exec_cnt:%" PRIx64 " merge_cnt:%" PRIx64,
1823 reset_string[hw->reset.level],
1824 hw->reset.stats.fail_cnt, hw->reset.stats.success_cnt,
1825 hw->reset.stats.global_cnt, hw->reset.stats.imp_cnt,
1826 hw->reset.stats.request_cnt, hw->reset.stats.exec_cnt,
1827 hw->reset.stats.merge_cnt);
1829 "%s reset done delta %ld ms time=%ld.%.6ld",
1830 reset_string[hw->reset.level],
1831 tv_delta.tv_sec * MSEC_PER_SEC +
1832 tv_delta.tv_usec / USEC_PER_MSEC,
1833 tv.tv_sec, tv.tv_usec);
1834 hw->reset.level = HNS3_NONE_RESET;
1839 if (ret == -ETIME) {
1840 hw->reset.retries++;
1841 if (hw->reset.retries < TIMEOUT_RETRIES_CNT) {
1842 rte_eal_alarm_set(HNS3_RESET_SYNC_US,
1843 hw->reset.ops->reset_service, hns);
1847 hw->reset.retries = 0;
1852 * There are three scenarios as follows:
1853 * When the reset is not in progress, the reset process starts.
1854 * During the reset process, if the reset level has not changed,
1855 * the reset process continues; otherwise, the reset process is aborted.
1856 * hw->reset.level new_level action
1857 * HNS3_NONE_RESET HNS3_XXXX_RESET start reset
1858 * HNS3_XXXX_RESET HNS3_XXXX_RESET continue reset
1859 * HNS3_LOW_RESET HNS3_HIGH_RESET abort
1862 hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level)
1864 struct hns3_hw *hw = &hns->hw;
1865 struct timeval tv_delta;
1869 if (hw->reset.level == HNS3_NONE_RESET) {
1870 hw->reset.level = new_level;
1871 hw->reset.stats.exec_cnt++;
1872 gettimeofday(&hw->reset.start_time, NULL);
1873 hns3_warn(hw, "Start %s reset time=%ld.%.6ld",
1874 reset_string[hw->reset.level],
1875 hw->reset.start_time.tv_sec,
1876 hw->reset.start_time.tv_usec);
1879 if (is_reset_pending(hns)) {
1880 gettimeofday(&tv, NULL);
1882 "%s reset is aborted by high level time=%ld.%.6ld",
1883 reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);
1884 if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)
1885 rte_eal_alarm_cancel(hns3_wait_callback,
1886 hw->reset.wait_data);
1890 ret = hns3_reset_pre(hns);
1894 if (hw->reset.stage == RESET_STAGE_REQ_HW_RESET) {
1895 ret = hns3_reset_req_hw_reset(hns);
1898 gettimeofday(&tv, NULL);
1900 "Reset step3 request IMP reset success time=%ld.%.6ld",
1901 tv.tv_sec, tv.tv_usec);
1902 hw->reset.stage = RESET_STAGE_WAIT;
1903 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;
1905 if (hw->reset.stage == RESET_STAGE_WAIT) {
1906 ret = hw->reset.ops->wait_hardware_ready(hns);
1909 gettimeofday(&tv, NULL);
1910 hns3_warn(hw, "Reset step4 reset wait success time=%ld.%.6ld",
1911 tv.tv_sec, tv.tv_usec);
1912 hw->reset.stage = RESET_STAGE_DEV_INIT;
1915 ret = hns3_reset_post(hns);
1924 hns3_clear_reset_level(hw, &hw->reset.pending);
1925 if (hns3_reset_err_handle(hns)) {
1926 hw->reset.stage = RESET_STAGE_PREWAIT;
1927 hns3_schedule_reset(hns);
1929 rte_spinlock_lock(&hw->lock);
1930 if (hw->reset.mbuf_deferred_free) {
1931 hns3_dev_release_mbufs(hns);
1932 hw->reset.mbuf_deferred_free = false;
1934 rte_spinlock_unlock(&hw->lock);
1935 rte_atomic16_clear(&hns->hw.reset.resetting);
1936 hw->reset.stage = RESET_STAGE_NONE;
1937 gettimeofday(&tv, NULL);
1938 timersub(&tv, &hw->reset.start_time, &tv_delta);
1939 hns3_warn(hw, "%s reset fail delta %ld ms time=%ld.%.6ld",
1940 reset_string[hw->reset.level],
1941 tv_delta.tv_sec * MSEC_PER_SEC +
1942 tv_delta.tv_usec / USEC_PER_MSEC,
1943 tv.tv_sec, tv.tv_usec);
1944 hw->reset.level = HNS3_NONE_RESET;
1951 * The reset process can only be terminated after handshake with IMP(step3),
1952 * so that IMP can complete the reset process normally.
1955 hns3_reset_abort(struct hns3_adapter *hns)
1957 struct hns3_hw *hw = &hns->hw;
1961 for (i = 0; i < HNS3_QUIT_RESET_CNT; i++) {
1962 if (hw->reset.level == HNS3_NONE_RESET)
1964 rte_delay_ms(HNS3_QUIT_RESET_DELAY_MS);
1967 /* IMP no longer waiting the ready flag */
1968 hns3_notify_reset_ready(hw, true);
1970 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);
1971 rte_eal_alarm_cancel(hns3_wait_callback, hw->reset.wait_data);
1973 if (hw->reset.level != HNS3_NONE_RESET) {
1974 gettimeofday(&tv, NULL);
1975 hns3_err(hw, "Failed to terminate reset: %s time=%ld.%.6ld",
1976 reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);