1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
6 #include <rte_cycles.h>
7 #include <rte_ethdev.h>
9 #include <rte_malloc.h>
11 #include "hns3_ethdev.h"
12 #include "hns3_logs.h"
13 #include "hns3_intr.h"
14 #include "hns3_regs.h"
15 #include "hns3_rxtx.h"
17 #define SWITCH_CONTEXT_US 10
19 #define HNS3_CHECK_MERGE_CNT(val) \
22 hw->reset.stats.merge_cnt++; \
25 static const char *reset_string[HNS3_MAX_RESET] = {
26 "none", "vf_func", "vf_pf_func", "vf_full", "flr",
27 "vf_global", "pf_func", "global", "IMP",
30 static const struct hns3_hw_error mac_afifo_tnl_int[] = {
33 .msg = "egu_cge_afifo_ecc_1bit_err",
34 .reset_level = HNS3_NONE_RESET
37 .msg = "egu_cge_afifo_ecc_mbit_err",
38 .reset_level = HNS3_GLOBAL_RESET
41 .msg = "egu_lge_afifo_ecc_1bit_err",
42 .reset_level = HNS3_NONE_RESET
45 .msg = "egu_lge_afifo_ecc_mbit_err",
46 .reset_level = HNS3_GLOBAL_RESET
49 .msg = "cge_igu_afifo_ecc_1bit_err",
50 .reset_level = HNS3_NONE_RESET
53 .msg = "cge_igu_afifo_ecc_mbit_err",
54 .reset_level = HNS3_GLOBAL_RESET
57 .msg = "lge_igu_afifo_ecc_1bit_err",
58 .reset_level = HNS3_NONE_RESET
61 .msg = "lge_igu_afifo_ecc_mbit_err",
62 .reset_level = HNS3_GLOBAL_RESET
65 .msg = "cge_igu_afifo_overflow_err",
66 .reset_level = HNS3_GLOBAL_RESET
69 .msg = "lge_igu_afifo_overflow_err",
70 .reset_level = HNS3_GLOBAL_RESET
73 .msg = "egu_cge_afifo_underrun_err",
74 .reset_level = HNS3_GLOBAL_RESET
77 .msg = "egu_lge_afifo_underrun_err",
78 .reset_level = HNS3_GLOBAL_RESET
81 .msg = "egu_ge_afifo_underrun_err",
82 .reset_level = HNS3_GLOBAL_RESET
85 .msg = "ge_igu_afifo_overflow_err",
86 .reset_level = HNS3_GLOBAL_RESET
90 .reset_level = HNS3_NONE_RESET
94 static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = {
96 .int_msk = 0xFFFFFFFF,
97 .msg = "rpu_rx_pkt_ecc_mbit_err",
98 .reset_level = HNS3_GLOBAL_RESET
102 .reset_level = HNS3_NONE_RESET
106 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = {
109 .msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
110 .reset_level = HNS3_GLOBAL_RESET
113 .msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
114 .reset_level = HNS3_GLOBAL_RESET
117 .msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
118 .reset_level = HNS3_GLOBAL_RESET
121 .msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
122 .reset_level = HNS3_GLOBAL_RESET
125 .msg = "rcb_tx_ring_ecc_mbit_err",
126 .reset_level = HNS3_GLOBAL_RESET
129 .msg = "rcb_rx_ring_ecc_mbit_err",
130 .reset_level = HNS3_GLOBAL_RESET
133 .msg = "rcb_tx_fbd_ecc_mbit_err",
134 .reset_level = HNS3_GLOBAL_RESET
137 .msg = "rcb_rx_ebd_ecc_mbit_err",
138 .reset_level = HNS3_GLOBAL_RESET
141 .msg = "rcb_tso_info_ecc_mbit_err",
142 .reset_level = HNS3_GLOBAL_RESET
145 .msg = "rcb_tx_int_info_ecc_mbit_err",
146 .reset_level = HNS3_GLOBAL_RESET
149 .msg = "rcb_rx_int_info_ecc_mbit_err",
150 .reset_level = HNS3_GLOBAL_RESET
153 .msg = "tpu_tx_pkt_0_ecc_mbit_err",
154 .reset_level = HNS3_GLOBAL_RESET
157 .msg = "tpu_tx_pkt_1_ecc_mbit_err",
158 .reset_level = HNS3_GLOBAL_RESET
162 .reset_level = HNS3_GLOBAL_RESET
166 .reset_level = HNS3_GLOBAL_RESET
169 .msg = "ooo_ecc_err_detect",
170 .reset_level = HNS3_NONE_RESET
173 .msg = "ooo_ecc_err_multpl",
174 .reset_level = HNS3_GLOBAL_RESET
178 .reset_level = HNS3_NONE_RESET
182 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = {
185 .msg = "rx_q_search_miss",
186 .reset_level = HNS3_NONE_RESET
190 .reset_level = HNS3_NONE_RESET
194 static const struct hns3_hw_error ssu_port_based_pf_int[] = {
197 .msg = "roc_pkt_without_key_port",
198 .reset_level = HNS3_GLOBAL_RESET
201 .msg = "low_water_line_err_port",
202 .reset_level = HNS3_NONE_RESET
206 .reset_level = HNS3_NONE_RESET
210 static const struct hns3_hw_error ppp_pf_abnormal_int[] = {
213 .msg = "tx_vlan_tag_err",
214 .reset_level = HNS3_NONE_RESET
217 .msg = "rss_list_tc_unassigned_queue_err",
218 .reset_level = HNS3_NONE_RESET
222 .reset_level = HNS3_NONE_RESET
226 static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = {
229 .msg = "tx_rd_fbd_poison",
230 .reset_level = HNS3_FUNC_RESET
233 .msg = "rx_rd_ebd_poison",
234 .reset_level = HNS3_FUNC_RESET
238 .reset_level = HNS3_NONE_RESET
242 static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = {
245 .msg = "over_8bd_no_fe",
246 .reset_level = HNS3_FUNC_RESET
249 .msg = "tso_mss_cmp_min_err",
250 .reset_level = HNS3_NONE_RESET
253 .msg = "tso_mss_cmp_max_err",
254 .reset_level = HNS3_NONE_RESET
257 .msg = "buf_wait_timeout",
258 .reset_level = HNS3_NONE_RESET
262 .reset_level = HNS3_NONE_RESET
266 static const struct hns3_hw_error imp_tcm_ecc_int[] = {
269 .msg = "imp_itcm0_ecc_mbit_err",
270 .reset_level = HNS3_NONE_RESET
273 .msg = "imp_itcm1_ecc_mbit_err",
274 .reset_level = HNS3_NONE_RESET
277 .msg = "imp_itcm2_ecc_mbit_err",
278 .reset_level = HNS3_NONE_RESET
281 .msg = "imp_itcm3_ecc_mbit_err",
282 .reset_level = HNS3_NONE_RESET
285 .msg = "imp_dtcm0_mem0_ecc_mbit_err",
286 .reset_level = HNS3_NONE_RESET
289 .msg = "imp_dtcm0_mem1_ecc_mbit_err",
290 .reset_level = HNS3_NONE_RESET
293 .msg = "imp_dtcm1_mem0_ecc_mbit_err",
294 .reset_level = HNS3_NONE_RESET
297 .msg = "imp_dtcm1_mem1_ecc_mbit_err",
298 .reset_level = HNS3_NONE_RESET
301 .msg = "imp_itcm4_ecc_mbit_err",
302 .reset_level = HNS3_NONE_RESET
306 .reset_level = HNS3_NONE_RESET
310 static const struct hns3_hw_error cmdq_mem_ecc_int[] = {
313 .msg = "cmdq_nic_rx_depth_ecc_mbit_err",
314 .reset_level = HNS3_NONE_RESET
317 .msg = "cmdq_nic_tx_depth_ecc_mbit_err",
318 .reset_level = HNS3_NONE_RESET
321 .msg = "cmdq_nic_rx_tail_ecc_mbit_err",
322 .reset_level = HNS3_NONE_RESET
325 .msg = "cmdq_nic_tx_tail_ecc_mbit_err",
326 .reset_level = HNS3_NONE_RESET
329 .msg = "cmdq_nic_rx_head_ecc_mbit_err",
330 .reset_level = HNS3_NONE_RESET
333 .msg = "cmdq_nic_tx_head_ecc_mbit_err",
334 .reset_level = HNS3_NONE_RESET
337 .msg = "cmdq_nic_rx_addr_ecc_mbit_err",
338 .reset_level = HNS3_NONE_RESET
341 .msg = "cmdq_nic_tx_addr_ecc_mbit_err",
342 .reset_level = HNS3_NONE_RESET
346 .reset_level = HNS3_NONE_RESET
350 static const struct hns3_hw_error tqp_int_ecc_int[] = {
353 .msg = "tqp_int_cfg_even_ecc_mbit_err",
354 .reset_level = HNS3_NONE_RESET
357 .msg = "tqp_int_cfg_odd_ecc_mbit_err",
358 .reset_level = HNS3_NONE_RESET
361 .msg = "tqp_int_ctrl_even_ecc_mbit_err",
362 .reset_level = HNS3_NONE_RESET
365 .msg = "tqp_int_ctrl_odd_ecc_mbit_err",
366 .reset_level = HNS3_NONE_RESET
369 .msg = "tx_queue_scan_int_ecc_mbit_err",
370 .reset_level = HNS3_NONE_RESET
373 .msg = "rx_queue_scan_int_ecc_mbit_err",
374 .reset_level = HNS3_NONE_RESET
378 .reset_level = HNS3_NONE_RESET
382 static const struct hns3_hw_error imp_rd_poison_int[] = {
385 .msg = "imp_rd_poison_int",
386 .reset_level = HNS3_NONE_RESET
390 .reset_level = HNS3_NONE_RESET
394 #define HNS3_SSU_MEM_ECC_ERR(x) \
397 .msg = "ssu_mem" #x "_ecc_mbit_err", \
398 .reset_level = HNS3_GLOBAL_RESET \
401 static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = {
402 HNS3_SSU_MEM_ECC_ERR(0),
403 HNS3_SSU_MEM_ECC_ERR(1),
404 HNS3_SSU_MEM_ECC_ERR(2),
405 HNS3_SSU_MEM_ECC_ERR(3),
406 HNS3_SSU_MEM_ECC_ERR(4),
407 HNS3_SSU_MEM_ECC_ERR(5),
408 HNS3_SSU_MEM_ECC_ERR(6),
409 HNS3_SSU_MEM_ECC_ERR(7),
410 HNS3_SSU_MEM_ECC_ERR(8),
411 HNS3_SSU_MEM_ECC_ERR(9),
412 HNS3_SSU_MEM_ECC_ERR(10),
413 HNS3_SSU_MEM_ECC_ERR(11),
414 HNS3_SSU_MEM_ECC_ERR(12),
415 HNS3_SSU_MEM_ECC_ERR(13),
416 HNS3_SSU_MEM_ECC_ERR(14),
417 HNS3_SSU_MEM_ECC_ERR(15),
418 HNS3_SSU_MEM_ECC_ERR(16),
419 HNS3_SSU_MEM_ECC_ERR(17),
420 HNS3_SSU_MEM_ECC_ERR(18),
421 HNS3_SSU_MEM_ECC_ERR(19),
422 HNS3_SSU_MEM_ECC_ERR(20),
423 HNS3_SSU_MEM_ECC_ERR(21),
424 HNS3_SSU_MEM_ECC_ERR(22),
425 HNS3_SSU_MEM_ECC_ERR(23),
426 HNS3_SSU_MEM_ECC_ERR(24),
427 HNS3_SSU_MEM_ECC_ERR(25),
428 HNS3_SSU_MEM_ECC_ERR(26),
429 HNS3_SSU_MEM_ECC_ERR(27),
430 HNS3_SSU_MEM_ECC_ERR(28),
431 HNS3_SSU_MEM_ECC_ERR(29),
432 HNS3_SSU_MEM_ECC_ERR(30),
433 HNS3_SSU_MEM_ECC_ERR(31),
436 .reset_level = HNS3_NONE_RESET}
439 static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = {
442 .msg = "ssu_mem32_ecc_mbit_err",
443 .reset_level = HNS3_GLOBAL_RESET
447 .reset_level = HNS3_NONE_RESET
451 static const struct hns3_hw_error ssu_common_ecc_int[] = {
454 .msg = "buf_sum_err",
455 .reset_level = HNS3_NONE_RESET
458 .msg = "ppp_mb_num_err",
459 .reset_level = HNS3_NONE_RESET
462 .msg = "ppp_mbid_err",
463 .reset_level = HNS3_GLOBAL_RESET
466 .msg = "ppp_rlt_mac_err",
467 .reset_level = HNS3_GLOBAL_RESET
470 .msg = "ppp_rlt_host_err",
471 .reset_level = HNS3_GLOBAL_RESET
474 .msg = "cks_edit_position_err",
475 .reset_level = HNS3_GLOBAL_RESET
478 .msg = "cks_edit_condition_err",
479 .reset_level = HNS3_GLOBAL_RESET
482 .msg = "vlan_edit_condition_err",
483 .reset_level = HNS3_GLOBAL_RESET
486 .msg = "vlan_num_ot_err",
487 .reset_level = HNS3_GLOBAL_RESET
490 .msg = "vlan_num_in_err",
491 .reset_level = HNS3_GLOBAL_RESET
495 .reset_level = HNS3_NONE_RESET
499 static const struct hns3_hw_error igu_int[] = {
502 .msg = "igu_rx_buf0_ecc_mbit_err",
503 .reset_level = HNS3_GLOBAL_RESET
506 .msg = "igu_rx_buf1_ecc_mbit_err",
507 .reset_level = HNS3_GLOBAL_RESET
511 .reset_level = HNS3_NONE_RESET
515 static const struct hns3_hw_error msix_ecc_int[] = {
518 .msg = "msix_nic_ecc_mbit_err",
519 .reset_level = HNS3_NONE_RESET
523 .reset_level = HNS3_NONE_RESET
527 static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = {
530 .msg = "vf_vlan_ad_mem_ecc_mbit_err",
531 .reset_level = HNS3_GLOBAL_RESET
534 .msg = "umv_mcast_group_mem_ecc_mbit_err",
535 .reset_level = HNS3_GLOBAL_RESET
538 .msg = "umv_key_mem0_ecc_mbit_err",
539 .reset_level = HNS3_GLOBAL_RESET
542 .msg = "umv_key_mem1_ecc_mbit_err",
543 .reset_level = HNS3_GLOBAL_RESET
546 .msg = "umv_key_mem2_ecc_mbit_err",
547 .reset_level = HNS3_GLOBAL_RESET
550 .msg = "umv_key_mem3_ecc_mbit_err",
551 .reset_level = HNS3_GLOBAL_RESET
554 .msg = "umv_ad_mem_ecc_mbit_err",
555 .reset_level = HNS3_GLOBAL_RESET
558 .msg = "rss_tc_mode_mem_ecc_mbit_err",
559 .reset_level = HNS3_GLOBAL_RESET
562 .msg = "rss_idt_mem0_ecc_mbit_err",
563 .reset_level = HNS3_GLOBAL_RESET
566 .msg = "rss_idt_mem1_ecc_mbit_err",
567 .reset_level = HNS3_GLOBAL_RESET
570 .msg = "rss_idt_mem2_ecc_mbit_err",
571 .reset_level = HNS3_GLOBAL_RESET
574 .msg = "rss_idt_mem3_ecc_mbit_err",
575 .reset_level = HNS3_GLOBAL_RESET
578 .msg = "rss_idt_mem4_ecc_mbit_err",
579 .reset_level = HNS3_GLOBAL_RESET
582 .msg = "rss_idt_mem5_ecc_mbit_err",
583 .reset_level = HNS3_GLOBAL_RESET
586 .msg = "rss_idt_mem6_ecc_mbit_err",
587 .reset_level = HNS3_GLOBAL_RESET
590 .msg = "rss_idt_mem7_ecc_mbit_err",
591 .reset_level = HNS3_GLOBAL_RESET
594 .msg = "rss_idt_mem8_ecc_mbit_err",
595 .reset_level = HNS3_GLOBAL_RESET
598 .msg = "rss_idt_mem9_ecc_mbit_err",
599 .reset_level = HNS3_GLOBAL_RESET
602 .msg = "rss_idt_mem10_ecc_m1bit_err",
603 .reset_level = HNS3_GLOBAL_RESET
606 .msg = "rss_idt_mem11_ecc_mbit_err",
607 .reset_level = HNS3_GLOBAL_RESET
610 .msg = "rss_idt_mem12_ecc_mbit_err",
611 .reset_level = HNS3_GLOBAL_RESET
614 .msg = "rss_idt_mem13_ecc_mbit_err",
615 .reset_level = HNS3_GLOBAL_RESET
618 .msg = "rss_idt_mem14_ecc_mbit_err",
619 .reset_level = HNS3_GLOBAL_RESET
622 .msg = "rss_idt_mem15_ecc_mbit_err",
623 .reset_level = HNS3_GLOBAL_RESET
626 .msg = "port_vlan_mem_ecc_mbit_err",
627 .reset_level = HNS3_GLOBAL_RESET
630 .msg = "mcast_linear_table_mem_ecc_mbit_err",
631 .reset_level = HNS3_GLOBAL_RESET
634 .msg = "mcast_result_mem_ecc_mbit_err",
635 .reset_level = HNS3_GLOBAL_RESET
638 .msg = "flow_director_ad_mem0_ecc_mbit_err",
639 .reset_level = HNS3_GLOBAL_RESET
642 .msg = "flow_director_ad_mem1_ecc_mbit_err",
643 .reset_level = HNS3_GLOBAL_RESET
646 .msg = "rx_vlan_tag_memory_ecc_mbit_err",
647 .reset_level = HNS3_GLOBAL_RESET
650 .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
651 .reset_level = HNS3_GLOBAL_RESET
655 .reset_level = HNS3_NONE_RESET
659 static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = {
662 .msg = "hfs_fifo_mem_ecc_mbit_err",
663 .reset_level = HNS3_GLOBAL_RESET
666 .msg = "rslt_descr_fifo_mem_ecc_mbit_err",
667 .reset_level = HNS3_GLOBAL_RESET
670 .msg = "tx_vlan_tag_mem_ecc_mbit_err",
671 .reset_level = HNS3_GLOBAL_RESET
674 .msg = "FD_CN0_memory_ecc_mbit_err",
675 .reset_level = HNS3_GLOBAL_RESET
678 .msg = "FD_CN1_memory_ecc_mbit_err",
679 .reset_level = HNS3_GLOBAL_RESET
682 .msg = "GRO_AD_memory_ecc_mbit_err",
683 .reset_level = HNS3_GLOBAL_RESET
687 .reset_level = HNS3_NONE_RESET
691 static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = {
694 .msg = "gro_bd_ecc_mbit_err",
695 .reset_level = HNS3_GLOBAL_RESET
698 .msg = "gro_context_ecc_mbit_err",
699 .reset_level = HNS3_GLOBAL_RESET
702 .msg = "rx_stash_cfg_ecc_mbit_err",
703 .reset_level = HNS3_GLOBAL_RESET
706 .msg = "axi_rd_fbd_ecc_mbit_err",
707 .reset_level = HNS3_GLOBAL_RESET
711 .reset_level = HNS3_NONE_RESET
715 static const struct hns3_hw_error tm_sch_int[] = {
718 .msg = "tm_sch_ecc_mbit_err",
719 .reset_level = HNS3_GLOBAL_RESET
722 .msg = "tm_sch_port_shap_sub_fifo_wr_err",
723 .reset_level = HNS3_GLOBAL_RESET
726 .msg = "tm_sch_port_shap_sub_fifo_rd_err",
727 .reset_level = HNS3_GLOBAL_RESET
730 .msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
731 .reset_level = HNS3_GLOBAL_RESET
734 .msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
735 .reset_level = HNS3_GLOBAL_RESET
738 .msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
739 .reset_level = HNS3_GLOBAL_RESET
742 .msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
743 .reset_level = HNS3_GLOBAL_RESET
746 .msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
747 .reset_level = HNS3_GLOBAL_RESET
750 .msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
751 .reset_level = HNS3_GLOBAL_RESET
754 .msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
755 .reset_level = HNS3_GLOBAL_RESET
758 .msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
759 .reset_level = HNS3_GLOBAL_RESET
762 .msg = "tm_sch_port_shap_offset_fifo_wr_err",
763 .reset_level = HNS3_GLOBAL_RESET
766 .msg = "tm_sch_port_shap_offset_fifo_rd_err",
767 .reset_level = HNS3_GLOBAL_RESET
770 .msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
771 .reset_level = HNS3_GLOBAL_RESET
774 .msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
775 .reset_level = HNS3_GLOBAL_RESET
778 .msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
779 .reset_level = HNS3_GLOBAL_RESET
782 .msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
783 .reset_level = HNS3_GLOBAL_RESET
786 .msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
787 .reset_level = HNS3_GLOBAL_RESET
790 .msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
791 .reset_level = HNS3_GLOBAL_RESET
794 .msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
795 .reset_level = HNS3_GLOBAL_RESET
798 .msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
799 .reset_level = HNS3_GLOBAL_RESET
802 .msg = "tm_sch_rq_fifo_wr_err",
803 .reset_level = HNS3_GLOBAL_RESET
806 .msg = "tm_sch_rq_fifo_rd_err",
807 .reset_level = HNS3_GLOBAL_RESET
810 .msg = "tm_sch_nq_fifo_wr_err",
811 .reset_level = HNS3_GLOBAL_RESET
814 .msg = "tm_sch_nq_fifo_rd_err",
815 .reset_level = HNS3_GLOBAL_RESET
818 .msg = "tm_sch_roce_up_fifo_wr_err",
819 .reset_level = HNS3_GLOBAL_RESET
822 .msg = "tm_sch_roce_up_fifo_rd_err",
823 .reset_level = HNS3_GLOBAL_RESET
826 .msg = "tm_sch_rcb_byte_fifo_wr_err",
827 .reset_level = HNS3_GLOBAL_RESET
830 .msg = "tm_sch_rcb_byte_fifo_rd_err",
831 .reset_level = HNS3_GLOBAL_RESET
834 .msg = "tm_sch_ssu_byte_fifo_wr_err",
835 .reset_level = HNS3_GLOBAL_RESET
838 .msg = "tm_sch_ssu_byte_fifo_rd_err",
839 .reset_level = HNS3_GLOBAL_RESET
843 .reset_level = HNS3_NONE_RESET
847 static const struct hns3_hw_error qcn_fifo_int[] = {
850 .msg = "qcn_shap_gp0_sch_fifo_rd_err",
851 .reset_level = HNS3_GLOBAL_RESET
854 .msg = "qcn_shap_gp0_sch_fifo_wr_err",
855 .reset_level = HNS3_GLOBAL_RESET
858 .msg = "qcn_shap_gp1_sch_fifo_rd_err",
859 .reset_level = HNS3_GLOBAL_RESET
862 .msg = "qcn_shap_gp1_sch_fifo_wr_err",
863 .reset_level = HNS3_GLOBAL_RESET
866 .msg = "qcn_shap_gp2_sch_fifo_rd_err",
867 .reset_level = HNS3_GLOBAL_RESET
870 .msg = "qcn_shap_gp2_sch_fifo_wr_err",
871 .reset_level = HNS3_GLOBAL_RESET
874 .msg = "qcn_shap_gp3_sch_fifo_rd_err",
875 .reset_level = HNS3_GLOBAL_RESET
878 .msg = "qcn_shap_gp3_sch_fifo_wr_err",
879 .reset_level = HNS3_GLOBAL_RESET
882 .msg = "qcn_shap_gp0_offset_fifo_rd_err",
883 .reset_level = HNS3_GLOBAL_RESET
886 .msg = "qcn_shap_gp0_offset_fifo_wr_err",
887 .reset_level = HNS3_GLOBAL_RESET
890 .msg = "qcn_shap_gp1_offset_fifo_rd_err",
891 .reset_level = HNS3_GLOBAL_RESET
894 .msg = "qcn_shap_gp1_offset_fifo_wr_err",
895 .reset_level = HNS3_GLOBAL_RESET
898 .msg = "qcn_shap_gp2_offset_fifo_rd_err",
899 .reset_level = HNS3_GLOBAL_RESET
902 .msg = "qcn_shap_gp2_offset_fifo_wr_err",
903 .reset_level = HNS3_GLOBAL_RESET
906 .msg = "qcn_shap_gp3_offset_fifo_rd_err",
907 .reset_level = HNS3_GLOBAL_RESET
910 .msg = "qcn_shap_gp3_offset_fifo_wr_err",
911 .reset_level = HNS3_GLOBAL_RESET
914 .msg = "qcn_byte_info_fifo_rd_err",
915 .reset_level = HNS3_GLOBAL_RESET
918 .msg = "qcn_byte_info_fifo_wr_err",
919 .reset_level = HNS3_GLOBAL_RESET
923 .reset_level = HNS3_NONE_RESET
927 static const struct hns3_hw_error qcn_ecc_int[] = {
930 .msg = "qcn_byte_mem_ecc_mbit_err",
931 .reset_level = HNS3_GLOBAL_RESET
934 .msg = "qcn_time_mem_ecc_mbit_err",
935 .reset_level = HNS3_GLOBAL_RESET
938 .msg = "qcn_fb_mem_ecc_mbit_err",
939 .reset_level = HNS3_GLOBAL_RESET
942 .msg = "qcn_link_mem_ecc_mbit_err",
943 .reset_level = HNS3_GLOBAL_RESET
946 .msg = "qcn_rate_mem_ecc_mbit_err",
947 .reset_level = HNS3_GLOBAL_RESET
950 .msg = "qcn_tmplt_mem_ecc_mbit_err",
951 .reset_level = HNS3_GLOBAL_RESET
954 .msg = "qcn_shap_cfg_mem_ecc_mbit_err",
955 .reset_level = HNS3_GLOBAL_RESET
958 .msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
959 .reset_level = HNS3_GLOBAL_RESET
962 .msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
963 .reset_level = HNS3_GLOBAL_RESET
966 .msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
967 .reset_level = HNS3_GLOBAL_RESET
970 .msg = "qcn_gp3_barral_mem_ecc_mbit_err",
971 .reset_level = HNS3_GLOBAL_RESET
975 .reset_level = HNS3_NONE_RESET
979 static const struct hns3_hw_error ncsi_ecc_int[] = {
982 .msg = "ncsi_tx_ecc_mbit_err",
983 .reset_level = HNS3_NONE_RESET
987 .reset_level = HNS3_NONE_RESET
991 static const struct hns3_hw_error ssu_fifo_overflow_int[] = {
994 .msg = "ig_mac_inf_int",
995 .reset_level = HNS3_GLOBAL_RESET
998 .msg = "ig_host_inf_int",
999 .reset_level = HNS3_GLOBAL_RESET
1002 .msg = "ig_roc_buf_int",
1003 .reset_level = HNS3_GLOBAL_RESET
1006 .msg = "ig_host_data_fifo_int",
1007 .reset_level = HNS3_GLOBAL_RESET
1010 .msg = "ig_host_key_fifo_int",
1011 .reset_level = HNS3_GLOBAL_RESET
1014 .msg = "tx_qcn_fifo_int",
1015 .reset_level = HNS3_GLOBAL_RESET
1018 .msg = "rx_qcn_fifo_int",
1019 .reset_level = HNS3_GLOBAL_RESET
1022 .msg = "tx_pf_rd_fifo_int",
1023 .reset_level = HNS3_GLOBAL_RESET
1026 .msg = "rx_pf_rd_fifo_int",
1027 .reset_level = HNS3_GLOBAL_RESET
1030 .msg = "qm_eof_fifo_int",
1031 .reset_level = HNS3_GLOBAL_RESET
1034 .msg = "mb_rlt_fifo_int",
1035 .reset_level = HNS3_GLOBAL_RESET
1038 .msg = "dup_uncopy_fifo_int",
1039 .reset_level = HNS3_GLOBAL_RESET
1042 .msg = "dup_cnt_rd_fifo_int",
1043 .reset_level = HNS3_GLOBAL_RESET
1046 .msg = "dup_cnt_drop_fifo_int",
1047 .reset_level = HNS3_GLOBAL_RESET
1050 .msg = "dup_cnt_wrb_fifo_int",
1051 .reset_level = HNS3_GLOBAL_RESET
1054 .msg = "host_cmd_fifo_int",
1055 .reset_level = HNS3_GLOBAL_RESET
1058 .msg = "mac_cmd_fifo_int",
1059 .reset_level = HNS3_GLOBAL_RESET
1062 .msg = "host_cmd_bitmap_empty_int",
1063 .reset_level = HNS3_GLOBAL_RESET
1066 .msg = "mac_cmd_bitmap_empty_int",
1067 .reset_level = HNS3_GLOBAL_RESET
1070 .msg = "dup_bitmap_empty_int",
1071 .reset_level = HNS3_GLOBAL_RESET
1074 .msg = "out_queue_bitmap_empty_int",
1075 .reset_level = HNS3_GLOBAL_RESET
1078 .msg = "bank2_bitmap_empty_int",
1079 .reset_level = HNS3_GLOBAL_RESET
1082 .msg = "bank1_bitmap_empty_int",
1083 .reset_level = HNS3_GLOBAL_RESET
1086 .msg = "bank0_bitmap_empty_int",
1087 .reset_level = HNS3_GLOBAL_RESET
1091 .reset_level = HNS3_NONE_RESET
1095 static const struct hns3_hw_error ssu_ets_tcg_int[] = {
1098 .msg = "ets_rd_int_rx_tcg",
1099 .reset_level = HNS3_GLOBAL_RESET
1102 .msg = "ets_wr_int_rx_tcg",
1103 .reset_level = HNS3_GLOBAL_RESET
1106 .msg = "ets_rd_int_tx_tcg",
1107 .reset_level = HNS3_GLOBAL_RESET
1110 .msg = "ets_wr_int_tx_tcg",
1111 .reset_level = HNS3_GLOBAL_RESET
1115 .reset_level = HNS3_NONE_RESET
1119 static const struct hns3_hw_error igu_egu_tnl_int[] = {
1122 .msg = "rx_buf_overflow",
1123 .reset_level = HNS3_GLOBAL_RESET
1126 .msg = "rx_stp_fifo_overflow",
1127 .reset_level = HNS3_GLOBAL_RESET
1130 .msg = "rx_stp_fifo_underflow",
1131 .reset_level = HNS3_GLOBAL_RESET
1134 .msg = "tx_buf_overflow",
1135 .reset_level = HNS3_GLOBAL_RESET
1138 .msg = "tx_buf_underrun",
1139 .reset_level = HNS3_GLOBAL_RESET
1142 .msg = "rx_stp_buf_overflow",
1143 .reset_level = HNS3_GLOBAL_RESET
1147 .reset_level = HNS3_NONE_RESET
1151 static const struct hns3_hw_error ssu_port_based_err_int[] = {
1154 .msg = "roc_pkt_without_key_port",
1155 .reset_level = HNS3_FUNC_RESET
1158 .msg = "tpu_pkt_without_key_port",
1159 .reset_level = HNS3_GLOBAL_RESET
1162 .msg = "igu_pkt_without_key_port",
1163 .reset_level = HNS3_GLOBAL_RESET
1166 .msg = "roc_eof_mis_match_port",
1167 .reset_level = HNS3_GLOBAL_RESET
1170 .msg = "tpu_eof_mis_match_port",
1171 .reset_level = HNS3_GLOBAL_RESET
1174 .msg = "igu_eof_mis_match_port",
1175 .reset_level = HNS3_GLOBAL_RESET
1178 .msg = "roc_sof_mis_match_port",
1179 .reset_level = HNS3_GLOBAL_RESET
1182 .msg = "tpu_sof_mis_match_port",
1183 .reset_level = HNS3_GLOBAL_RESET
1186 .msg = "igu_sof_mis_match_port",
1187 .reset_level = HNS3_GLOBAL_RESET
1190 .msg = "ets_rd_int_rx_port",
1191 .reset_level = HNS3_GLOBAL_RESET
1194 .msg = "ets_wr_int_rx_port",
1195 .reset_level = HNS3_GLOBAL_RESET
1198 .msg = "ets_rd_int_tx_port",
1199 .reset_level = HNS3_GLOBAL_RESET
1202 .msg = "ets_wr_int_tx_port",
1203 .reset_level = HNS3_GLOBAL_RESET
1207 .reset_level = HNS3_NONE_RESET
1211 static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = {
1215 .msg = "IMP_TCM_ECC_INT_STS",
1216 .hw_err = imp_tcm_ecc_int
1220 .msg = "CMDQ_MEM_ECC_INT_STS",
1221 .hw_err = cmdq_mem_ecc_int
1225 .msg = "IMP_RD_POISON_INT_STS",
1226 .hw_err = imp_rd_poison_int
1230 .msg = "TQP_INT_ECC_INT_STS",
1231 .hw_err = tqp_int_ecc_int
1235 .msg = "MSIX_ECC_INT_STS",
1236 .hw_err = msix_ecc_int
1240 .msg = "SSU_ECC_MULTI_BIT_INT_0",
1241 .hw_err = ssu_ecc_multi_bit_int_0
1245 .msg = "SSU_ECC_MULTI_BIT_INT_1",
1246 .hw_err = ssu_ecc_multi_bit_int_1
1250 .msg = "SSU_COMMON_ERR_INT",
1251 .hw_err = ssu_common_ecc_int
1255 .msg = "IGU_INT_STS",
1260 .msg = "PPP_MPF_ABNORMAL_INT_ST1",
1261 .hw_err = ppp_mpf_abnormal_int_st1
1265 .msg = "PPP_MPF_ABNORMAL_INT_ST3",
1266 .hw_err = ppp_mpf_abnormal_int_st3
1270 .msg = "PPU_MPF_ABNORMAL_INT_ST1",
1271 .hw_err = ppu_mpf_abnormal_int_st1
1275 .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS",
1276 .hw_err = ppu_mpf_abnormal_int_st2_ras
1280 .msg = "PPU_MPF_ABNORMAL_INT_ST3",
1281 .hw_err = ppu_mpf_abnormal_int_st3
1285 .msg = "TM_SCH_RINT",
1286 .hw_err = tm_sch_int
1290 .msg = "QCN_FIFO_RINT",
1291 .hw_err = qcn_fifo_int
1295 .msg = "QCN_ECC_RINT",
1296 .hw_err = qcn_ecc_int
1300 .msg = "NCSI_ECC_INT_RPT",
1301 .hw_err = ncsi_ecc_int
1310 static const struct hns3_hw_error_desc pf_ras_err_tbl[] = {
1314 .msg = "SSU_PORT_BASED_ERR_INT_RAS",
1315 .hw_err = ssu_port_based_err_int
1319 .msg = "SSU_FIFO_OVERFLOW_INT",
1320 .hw_err = ssu_fifo_overflow_int
1324 .msg = "SSU_ETS_TCG_INT",
1325 .hw_err = ssu_ets_tcg_int
1329 .msg = "IGU_EGU_TNL_INT_STS",
1330 .hw_err = igu_egu_tnl_int
1334 .msg = "PPU_PF_ABNORMAL_INT_ST_RAS",
1335 .hw_err = ppu_pf_abnormal_int_ras
1344 static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = {
1348 .msg = "MAC_AFIFO_TNL_INT_R",
1349 .hw_err = mac_afifo_tnl_int
1353 .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX",
1354 .hw_err = ppu_mpf_abnormal_int_st2_msix
1363 static const struct hns3_hw_error_desc pf_msix_err_tbl[] = {
1367 .msg = "SSU_PORT_BASED_ERR_INT_MSIX",
1368 .hw_err = ssu_port_based_pf_int
1372 .msg = "PPP_PF_ABNORMAL_INT_ST0",
1373 .hw_err = ppp_pf_abnormal_int
1377 .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX",
1378 .hw_err = ppu_pf_abnormal_int_msix
1387 enum hns3_hw_err_type {
1395 hns3_config_ncsi_hw_err_int(struct hns3_adapter *hns, bool en)
1397 struct hns3_hw *hw = &hns->hw;
1398 struct hns3_cmd_desc desc;
1401 /* configure NCSI error interrupts */
1402 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_NCSI_INT_EN, false);
1404 desc.data[0] = rte_cpu_to_le_32(HNS3_NCSI_ERR_INT_EN);
1406 ret = hns3_cmd_send(hw, &desc, 1);
1408 hns3_err(hw, "fail to %s NCSI error interrupts, ret = %d",
1409 en ? "enable" : "disable", ret);
1415 enable_igu_egu_err_intr(struct hns3_adapter *hns, bool en)
1417 struct hns3_hw *hw = &hns->hw;
1418 struct hns3_cmd_desc desc;
1421 /* configure IGU,EGU error interrupts */
1422 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_COMMON_INT_EN, false);
1424 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_ENABLE);
1426 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_DISABLE);
1428 desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_EN_MASK);
1430 ret = hns3_cmd_send(hw, &desc, 1);
1432 hns3_err(hw, "fail to %s IGU common interrupts, ret = %d",
1433 en ? "enable" : "disable", ret);
1437 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_EGU_TNL_INT_EN, false);
1439 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN);
1441 desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN_MASK);
1443 ret = hns3_cmd_send(hw, &desc, 1);
1445 hns3_err(hw, "fail to %s IGU-EGU TNL interrupts, ret = %d",
1446 en ? "enable" : "disable", ret);
1450 return hns3_config_ncsi_hw_err_int(hns, en);
1454 config_ppp_err_intr(struct hns3_adapter *hns, uint32_t cmd, bool en)
1456 struct hns3_hw *hw = &hns->hw;
1457 struct hns3_cmd_desc desc[2];
1460 /* configure PPP error interrupts */
1461 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1462 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1463 hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
1465 if (cmd == HNS3_OPC_PPP_CMD0_INT_CMD) {
1468 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN);
1470 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN);
1472 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN);
1476 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK);
1478 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK);
1480 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN_MASK);
1481 } else if (cmd == HNS3_OPC_PPP_CMD1_INT_CMD) {
1484 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN);
1486 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN);
1490 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK);
1492 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK);
1495 ret = hns3_cmd_send(hw, &desc[0], 2);
1497 hns3_err(hw, "fail to %s PPP error int, ret = %d",
1498 en ? "enable" : "disable", ret);
1504 enable_ppp_err_intr(struct hns3_adapter *hns, bool en)
1508 ret = config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD0_INT_CMD, en);
1512 return config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD1_INT_CMD, en);
1516 enable_ssu_err_intr(struct hns3_adapter *hns, bool en)
1518 struct hns3_hw *hw = &hns->hw;
1519 struct hns3_cmd_desc desc[2];
1522 /* configure SSU ecc error interrupts */
1523 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_ECC_INT_CMD, false);
1524 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1525 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_ECC_INT_CMD, false);
1528 rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN);
1530 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN);
1532 rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN);
1535 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK);
1537 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK);
1538 desc[1].data[2] = rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK);
1540 ret = hns3_cmd_send(hw, &desc[0], 2);
1542 hns3_err(hw, "fail to %s SSU ECC error interrupt, ret = %d",
1543 en ? "enable" : "disable", ret);
1547 /* configure SSU common error interrupts */
1548 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_COMMON_INT_CMD, false);
1549 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1550 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_COMMON_INT_CMD, false);
1553 desc[0].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN);
1555 rte_cpu_to_le_32(HNS3_SSU_PORT_BASED_ERR_INT_EN);
1557 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN);
1560 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN_MASK |
1561 HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK);
1563 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK);
1565 ret = hns3_cmd_send(hw, &desc[0], 2);
1567 hns3_err(hw, "fail to %s SSU COMMON error intr, ret = %d",
1568 en ? "enable" : "disable", ret);
1574 hns3_config_mac_tnl_int(struct hns3_hw *hw, bool en)
1576 struct hns3_cmd_desc desc;
1579 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_TNL_INT_EN, false);
1581 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_EN);
1585 desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_EN_MASK);
1587 ret = hns3_cmd_send(hw, &desc, 1);
1589 hns3_err(hw, "fail to %s mac tnl intr, ret = %d",
1590 en ? "enable" : "disable", ret);
1594 config_ppu_err_intrs(struct hns3_adapter *hns, uint32_t cmd, bool en)
1596 struct hns3_hw *hw = &hns->hw;
1597 struct hns3_cmd_desc desc[2];
1600 /* configure PPU error interrupts */
1602 case HNS3_OPC_PPU_MPF_ECC_INT_CMD:
1603 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1604 desc[0].flag |= HNS3_CMD_FLAG_NEXT;
1605 hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
1607 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN;
1608 desc[0].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN;
1609 desc[1].data[3] = HNS3_PPU_MPF_ABNORMAL_INT3_EN;
1610 desc[1].data[4] = HNS3_PPU_MPF_ABNORMAL_INT2_EN;
1613 desc[1].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK;
1614 desc[1].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK;
1615 desc[1].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK;
1616 desc[1].data[3] |= HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK;
1619 case HNS3_OPC_PPU_MPF_OTHER_INT_CMD:
1620 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1622 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2;
1624 desc[0].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK;
1626 case HNS3_OPC_PPU_PF_OTHER_INT_CMD:
1627 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1629 desc[0].data[0] = HNS3_PPU_PF_ABNORMAL_INT_EN;
1631 desc[0].data[2] = HNS3_PPU_PF_ABNORMAL_INT_EN_MASK;
1635 "Invalid cmd(%u) to configure PPU error interrupts.",
1640 return hns3_cmd_send(hw, &desc[0], num);
1644 enable_ppu_err_intr(struct hns3_adapter *hns, bool en)
1646 struct hns3_hw *hw = &hns->hw;
1649 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_MPF_ECC_INT_CMD, en);
1651 hns3_err(hw, "fail to %s PPU MPF ECC error intr, ret = %d",
1652 en ? "enable" : "disable", ret);
1656 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_MPF_OTHER_INT_CMD, en);
1658 hns3_err(hw, "fail to %s PPU MPF other intr, ret = %d",
1659 en ? "enable" : "disable", ret);
1663 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_PF_OTHER_INT_CMD, en);
1665 hns3_err(hw, "fail to %s PPU PF error interrupts, ret = %d",
1666 en ? "enable" : "disable", ret);
1671 enable_tm_err_intr(struct hns3_adapter *hns, bool en)
1673 struct hns3_hw *hw = &hns->hw;
1674 struct hns3_cmd_desc desc;
1677 /* configure TM SCH error interrupts */
1678 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_SCH_ECC_INT_EN, false);
1680 desc.data[0] = rte_cpu_to_le_32(HNS3_TM_SCH_ECC_ERR_INT_EN);
1682 ret = hns3_cmd_send(hw, &desc, 1);
1684 hns3_err(hw, "fail to %s TM SCH interrupts, ret = %d",
1685 en ? "enable" : "disable", ret);
1689 /* configure TM QCN hw errors */
1690 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QCN_MEM_INT_CFG, true);
1691 ret = hns3_cmd_send(hw, &desc, 1);
1693 hns3_err(hw, "fail to read TM QCN CFG status, ret = %d\n", ret);
1697 hns3_cmd_reuse_desc(&desc, false);
1699 desc.data[1] = rte_cpu_to_le_32(HNS3_TM_QCN_MEM_ERR_INT_EN);
1701 ret = hns3_cmd_send(hw, &desc, 1);
1703 hns3_err(hw, "fail to %s TM QCN mem errors, ret = %d\n",
1704 en ? "enable" : "disable", ret);
1710 enable_common_err_intr(struct hns3_adapter *hns, bool en)
1712 struct hns3_hw *hw = &hns->hw;
1713 struct hns3_cmd_desc desc[2];
1716 /* configure common error interrupts */
1717 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_COMMON_ECC_INT_CFG, false);
1718 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1719 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_COMMON_ECC_INT_CFG, false);
1723 rte_cpu_to_le_32(HNS3_IMP_TCM_ECC_ERR_INT_EN);
1725 rte_cpu_to_le_32(HNS3_CMDQ_NIC_ECC_ERR_INT_EN);
1727 rte_cpu_to_le_32(HNS3_IMP_RD_POISON_ERR_INT_EN);
1729 rte_cpu_to_le_32(HNS3_TQP_ECC_ERR_INT_EN |
1730 HNS3_MSIX_SRAM_ECC_ERR_INT_EN);
1732 rte_cpu_to_le_32(HNS3_IMP_ITCM4_ECC_ERR_INT_EN);
1735 desc[1].data[0] = rte_cpu_to_le_32(HNS3_IMP_TCM_ECC_ERR_INT_EN_MASK);
1736 desc[1].data[2] = rte_cpu_to_le_32(HNS3_CMDQ_NIC_ECC_ERR_INT_EN_MASK);
1737 desc[1].data[3] = rte_cpu_to_le_32(HNS3_IMP_RD_POISON_ERR_INT_EN_MASK);
1738 desc[1].data[4] = rte_cpu_to_le_32(HNS3_TQP_ECC_ERR_INT_EN_MASK |
1739 HNS3_MSIX_SRAM_ECC_ERR_INT_EN_MASK);
1740 desc[1].data[5] = rte_cpu_to_le_32(HNS3_IMP_ITCM4_ECC_ERR_INT_EN_MASK);
1742 ret = hns3_cmd_send(hw, &desc[0], RTE_DIM(desc));
1744 hns3_err(hw, "fail to %s common err interrupts, ret = %d\n",
1745 en ? "enable" : "disable", ret);
1751 enable_mac_err_intr(struct hns3_adapter *hns, bool en)
1753 struct hns3_hw *hw = &hns->hw;
1754 struct hns3_cmd_desc desc;
1757 /* configure MAC common error interrupts */
1758 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_COMMON_INT_EN, false);
1760 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN);
1762 desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN_MASK);
1764 ret = hns3_cmd_send(hw, &desc, 1);
1766 hns3_err(hw, "fail to %s MAC COMMON error intr: %d",
1767 en ? "enable" : "disable", ret);
1772 static const struct hns3_hw_blk hw_blk[] = {
1775 .enable_err_intr = enable_igu_egu_err_intr,
1779 .enable_err_intr = enable_ppp_err_intr,
1783 .enable_err_intr = enable_ssu_err_intr,
1787 .enable_err_intr = enable_ppu_err_intr,
1791 .enable_err_intr = enable_tm_err_intr,
1795 .enable_err_intr = enable_common_err_intr,
1799 .enable_err_intr = enable_mac_err_intr,
1803 .enable_err_intr = NULL,
1808 hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool en)
1810 const struct hns3_hw_blk *module = hw_blk;
1813 while (module->enable_err_intr) {
1814 ret = module->enable_err_intr(hns, en);
1824 static enum hns3_reset_level
1825 hns3_find_highest_level(struct hns3_adapter *hns, const char *reg,
1826 const struct hns3_hw_error *err, uint32_t err_sts)
1828 enum hns3_reset_level reset_level = HNS3_FUNC_RESET;
1829 struct hns3_hw *hw = &hns->hw;
1830 bool need_reset = false;
1833 if (err->int_msk & err_sts) {
1834 hns3_warn(hw, "%s %s found [error status=0x%x]",
1835 reg, err->msg, err_sts);
1836 if (err->reset_level != HNS3_NONE_RESET &&
1837 err->reset_level >= reset_level) {
1838 reset_level = err->reset_level;
1847 return HNS3_NONE_RESET;
1851 query_num_bds(struct hns3_hw *hw, bool is_ras, uint32_t *mpf_bd_num,
1852 uint32_t *pf_bd_num)
1854 uint32_t mpf_min_bd_num, pf_min_bd_num;
1855 uint32_t mpf_bd_num_val, pf_bd_num_val;
1856 enum hns3_opcode_type opcode;
1857 struct hns3_cmd_desc desc;
1861 opcode = HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM;
1862 mpf_min_bd_num = HNS3_MPF_RAS_INT_MIN_BD_NUM;
1863 pf_min_bd_num = HNS3_PF_RAS_INT_MIN_BD_NUM;
1865 opcode = HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM;
1866 mpf_min_bd_num = HNS3_MPF_MSIX_INT_MIN_BD_NUM;
1867 pf_min_bd_num = HNS3_PF_MSIX_INT_MIN_BD_NUM;
1870 hns3_cmd_setup_basic_desc(&desc, opcode, true);
1871 ret = hns3_cmd_send(hw, &desc, 1);
1873 hns3_err(hw, "query num bds in msix failed, ret = %d", ret);
1877 mpf_bd_num_val = rte_le_to_cpu_32(desc.data[0]);
1878 pf_bd_num_val = rte_le_to_cpu_32(desc.data[1]);
1879 if (mpf_bd_num_val < mpf_min_bd_num || pf_bd_num_val < pf_min_bd_num) {
1880 hns3_err(hw, "error bd num: mpf(%u), min_mpf(%u), "
1881 "pf(%u), min_pf(%u)\n", mpf_bd_num_val, mpf_min_bd_num,
1882 pf_bd_num_val, pf_min_bd_num);
1886 *mpf_bd_num = mpf_bd_num_val;
1887 *pf_bd_num = pf_bd_num_val;
1893 hns3_intr_unregister(const struct rte_intr_handle *hdl,
1894 rte_intr_callback_fn cb_fn, void *cb_arg)
1900 ret = rte_intr_callback_unregister(hdl, cb_fn, cb_arg);
1903 } else if (ret != -EAGAIN) {
1904 PMD_INIT_LOG(ERR, "Failed to unregister intr: %d", ret);
1907 rte_delay_ms(HNS3_INTR_UNREG_FAIL_DELAY_MS);
1908 } while (retry_cnt++ < HNS3_INTR_UNREG_FAIL_RETRY_CNT);
1912 hns3_get_hw_error_status(struct hns3_cmd_desc *desc, uint8_t desc_offset,
1913 uint8_t data_offset)
1916 uint32_t *desc_data;
1918 if (desc_offset == 0)
1919 status = rte_le_to_cpu_32(desc[desc_offset].data[data_offset]);
1921 desc_data = (uint32_t *)&desc[desc_offset];
1922 status = rte_le_to_cpu_32(*(desc_data + data_offset));
1929 hns3_handle_hw_error(struct hns3_adapter *hns, struct hns3_cmd_desc *desc,
1930 int num, uint64_t *levels, enum hns3_hw_err_type err_type)
1932 const struct hns3_hw_error_desc *err = pf_ras_err_tbl;
1933 enum hns3_opcode_type opcode;
1934 enum hns3_reset_level req_level;
1935 struct hns3_hw *hw = &hns->hw;
1941 err = mpf_msix_err_tbl;
1942 opcode = HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT;
1945 err = pf_msix_err_tbl;
1946 opcode = HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT;
1949 err = mpf_ras_err_tbl;
1950 opcode = HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT;
1953 err = pf_ras_err_tbl;
1954 opcode = HNS3_OPC_QUERY_CLEAR_PF_RAS_INT;
1957 hns3_err(hw, "error hardware err_type = %d\n", err_type);
1961 /* query all hardware errors */
1962 hns3_cmd_setup_basic_desc(&desc[0], opcode, true);
1963 ret = hns3_cmd_send(hw, &desc[0], num);
1965 hns3_err(hw, "query hw err int 0x%x cmd failed, ret = %d\n",
1970 /* traverses the error table and process based on the error type */
1972 status = hns3_get_hw_error_status(desc, err->desc_offset,
1976 * set the reset_level or non_reset flag based on
1977 * the error type and add error statistics. here just
1978 * set the flag, the actual reset action is in
1979 * hns3_msix_process.
1981 req_level = hns3_find_highest_level(hns, err->msg,
1984 hns3_atomic_set_bit(req_level, levels);
1989 /* clear all hardware errors */
1990 hns3_cmd_reuse_desc(&desc[0], false);
1991 ret = hns3_cmd_send(hw, &desc[0], num);
1993 hns3_err(hw, "clear all hw err int cmd failed, ret = %d\n",
2000 hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels)
2002 uint32_t mpf_bd_num, pf_bd_num, bd_num;
2003 struct hns3_hw *hw = &hns->hw;
2004 struct hns3_cmd_desc *desc;
2007 /* query the number of bds for the MSIx int status */
2008 ret = query_num_bds(hw, false, &mpf_bd_num, &pf_bd_num);
2010 hns3_err(hw, "fail to query msix int status bd num: ret = %d",
2015 bd_num = RTE_MAX(mpf_bd_num, pf_bd_num);
2016 desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0);
2019 "fail to zmalloc desc for handling msix error, size = %zu",
2020 bd_num * sizeof(struct hns3_cmd_desc));
2024 /* handle all main PF MSIx errors */
2025 ret = hns3_handle_hw_error(hns, desc, mpf_bd_num, levels, MPF_MSIX_ERR);
2027 hns3_err(hw, "fail to handle all main pf msix errors, ret = %d",
2032 memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc));
2034 /* handle all PF MSIx errors */
2035 ret = hns3_handle_hw_error(hns, desc, pf_bd_num, levels, PF_MSIX_ERR);
2037 hns3_err(hw, "fail to handle all pf msix errors, ret = %d",
2047 hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels)
2049 uint32_t mpf_bd_num, pf_bd_num, bd_num;
2050 struct hns3_hw *hw = &hns->hw;
2051 struct hns3_cmd_desc *desc;
2055 status = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
2056 if ((status & HNS3_RAS_REG_NFE_MASK) == 0)
2059 /* query the number of bds for the RAS int status */
2060 ret = query_num_bds(hw, true, &mpf_bd_num, &pf_bd_num);
2062 hns3_err(hw, "fail to query ras int status bd num: ret = %d",
2067 bd_num = RTE_MAX(mpf_bd_num, pf_bd_num);
2068 desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0);
2071 "fail to zmalloc desc for handing ras error, size = %zu",
2072 bd_num * sizeof(struct hns3_cmd_desc));
2076 /* handle all main PF RAS errors */
2077 ret = hns3_handle_hw_error(hns, desc, mpf_bd_num, levels, MPF_RAS_ERR);
2079 hns3_err(hw, "fail to handle all main pf ras errors, ret = %d",
2084 memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc));
2086 /* handle all PF RAS errors */
2087 ret = hns3_handle_hw_error(hns, desc, pf_bd_num, levels, PF_RAS_ERR);
2089 hns3_err(hw, "fail to handle all pf ras errors, ret = %d", ret);
2098 hns3_reset_init(struct hns3_hw *hw)
2100 rte_spinlock_init(&hw->lock);
2101 hw->reset.level = HNS3_NONE_RESET;
2102 hw->reset.stage = RESET_STAGE_NONE;
2103 hw->reset.request = 0;
2104 hw->reset.pending = 0;
2105 hw->reset.resetting = 0;
2106 __atomic_store_n(&hw->reset.disable_cmd, 0, __ATOMIC_RELAXED);
2107 hw->reset.wait_data = rte_zmalloc("wait_data",
2108 sizeof(struct hns3_wait_data), 0);
2109 if (!hw->reset.wait_data) {
2110 PMD_INIT_LOG(ERR, "Failed to allocate memory for wait_data");
2117 hns3_schedule_reset(struct hns3_adapter *hns)
2119 struct hns3_hw *hw = &hns->hw;
2121 /* Reschedule the reset process after successful initialization */
2122 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {
2123 __atomic_store_n(&hw->reset.schedule, SCHEDULE_PENDING,
2128 if (hw->adapter_state >= HNS3_NIC_CLOSED)
2131 /* Schedule restart alarm if it is not scheduled yet */
2132 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2135 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2137 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);
2138 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2141 rte_eal_alarm_set(SWITCH_CONTEXT_US, hw->reset.ops->reset_service, hns);
2145 hns3_schedule_delayed_reset(struct hns3_adapter *hns)
2147 #define DEFERRED_SCHED_US (3 * MSEC_PER_SEC * USEC_PER_MSEC)
2148 struct hns3_hw *hw = &hns->hw;
2150 /* Do nothing if it is uninited or closed */
2151 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED ||
2152 hw->adapter_state >= HNS3_NIC_CLOSED) {
2156 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) !=
2159 __atomic_store_n(&hw->reset.schedule, SCHEDULE_DEFERRED,
2161 rte_eal_alarm_set(DEFERRED_SCHED_US, hw->reset.ops->reset_service, hns);
2165 hns3_wait_callback(void *param)
2167 struct hns3_wait_data *data = (struct hns3_wait_data *)param;
2168 struct hns3_adapter *hns = data->hns;
2169 struct hns3_hw *hw = &hns->hw;
2174 if (data->check_completion) {
2176 * Check if the current time exceeds the deadline
2177 * or a pending reset coming, or reset during close.
2179 msec = get_timeofday_ms();
2180 if (msec > data->end_ms || is_reset_pending(hns) ||
2181 hw->adapter_state == HNS3_NIC_CLOSING) {
2185 done = data->check_completion(hw);
2189 if (!done && data->count > 0) {
2190 rte_eal_alarm_set(data->interval, hns3_wait_callback, data);
2194 data->result = HNS3_WAIT_SUCCESS;
2196 hns3_err(hw, "%s wait timeout at stage %d",
2197 reset_string[hw->reset.level], hw->reset.stage);
2198 data->result = HNS3_WAIT_TIMEOUT;
2200 hns3_schedule_reset(hns);
2204 hns3_notify_reset_ready(struct hns3_hw *hw, bool enable)
2208 reg_val = hns3_read_dev(hw, HNS3_CMDQ_TX_DEPTH_REG);
2210 reg_val |= HNS3_NIC_SW_RST_RDY;
2212 reg_val &= ~HNS3_NIC_SW_RST_RDY;
2214 hns3_write_dev(hw, HNS3_CMDQ_TX_DEPTH_REG, reg_val);
2218 hns3_reset_req_hw_reset(struct hns3_adapter *hns)
2220 struct hns3_hw *hw = &hns->hw;
2222 if (hw->reset.wait_data->result == HNS3_WAIT_UNKNOWN) {
2223 hw->reset.wait_data->hns = hns;
2224 hw->reset.wait_data->check_completion = NULL;
2225 hw->reset.wait_data->interval = HNS3_RESET_SYNC_US;
2226 hw->reset.wait_data->count = 1;
2227 hw->reset.wait_data->result = HNS3_WAIT_REQUEST;
2228 rte_eal_alarm_set(hw->reset.wait_data->interval,
2229 hns3_wait_callback, hw->reset.wait_data);
2231 } else if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)
2234 /* inform hardware that preparatory work is done */
2235 hns3_notify_reset_ready(hw, true);
2240 hns3_clear_reset_level(struct hns3_hw *hw, uint64_t *levels)
2242 uint64_t merge_cnt = hw->reset.stats.merge_cnt;
2245 switch (hw->reset.level) {
2246 case HNS3_IMP_RESET:
2247 hns3_atomic_clear_bit(HNS3_IMP_RESET, levels);
2248 tmp = hns3_test_and_clear_bit(HNS3_GLOBAL_RESET, levels);
2249 HNS3_CHECK_MERGE_CNT(tmp);
2250 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);
2251 HNS3_CHECK_MERGE_CNT(tmp);
2253 case HNS3_GLOBAL_RESET:
2254 hns3_atomic_clear_bit(HNS3_GLOBAL_RESET, levels);
2255 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);
2256 HNS3_CHECK_MERGE_CNT(tmp);
2258 case HNS3_FUNC_RESET:
2259 hns3_atomic_clear_bit(HNS3_FUNC_RESET, levels);
2262 hns3_atomic_clear_bit(HNS3_VF_RESET, levels);
2263 tmp = hns3_test_and_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);
2264 HNS3_CHECK_MERGE_CNT(tmp);
2265 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
2266 HNS3_CHECK_MERGE_CNT(tmp);
2268 case HNS3_VF_FULL_RESET:
2269 hns3_atomic_clear_bit(HNS3_VF_FULL_RESET, levels);
2270 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
2271 HNS3_CHECK_MERGE_CNT(tmp);
2273 case HNS3_VF_PF_FUNC_RESET:
2274 hns3_atomic_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);
2275 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
2276 HNS3_CHECK_MERGE_CNT(tmp);
2278 case HNS3_VF_FUNC_RESET:
2279 hns3_atomic_clear_bit(HNS3_VF_FUNC_RESET, levels);
2281 case HNS3_FLR_RESET:
2282 hns3_atomic_clear_bit(HNS3_FLR_RESET, levels);
2284 case HNS3_NONE_RESET:
2288 if (merge_cnt != hw->reset.stats.merge_cnt)
2290 "No need to do low-level reset after %s reset. "
2291 "merge cnt: %" PRIx64 " total merge cnt: %" PRIx64,
2292 reset_string[hw->reset.level],
2293 hw->reset.stats.merge_cnt - merge_cnt,
2294 hw->reset.stats.merge_cnt);
2298 hns3_reset_err_handle(struct hns3_adapter *hns)
2300 #define MAX_RESET_FAIL_CNT 5
2302 struct hns3_hw *hw = &hns->hw;
2304 if (hw->adapter_state == HNS3_NIC_CLOSING)
2307 if (is_reset_pending(hns)) {
2308 hw->reset.attempts = 0;
2309 hw->reset.stats.fail_cnt++;
2310 hns3_warn(hw, "%s reset fail because new Reset is pending "
2311 "attempts:%" PRIx64,
2312 reset_string[hw->reset.level],
2313 hw->reset.stats.fail_cnt);
2314 hw->reset.level = HNS3_NONE_RESET;
2318 hw->reset.attempts++;
2319 if (hw->reset.attempts < MAX_RESET_FAIL_CNT) {
2320 hns3_atomic_set_bit(hw->reset.level, &hw->reset.pending);
2321 hns3_warn(hw, "%s retry to reset attempts: %d",
2322 reset_string[hw->reset.level],
2323 hw->reset.attempts);
2328 * Failure to reset does not mean that the network port is
2329 * completely unavailable, so cmd still needs to be initialized.
2330 * Regardless of whether the execution is successful or not, the
2331 * flow after execution must be continued.
2333 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED))
2334 (void)hns3_cmd_init(hw);
2336 hw->reset.attempts = 0;
2337 hw->reset.stats.fail_cnt++;
2338 hns3_warn(hw, "%s reset fail fail_cnt:%" PRIx64 " success_cnt:%" PRIx64
2339 " global_cnt:%" PRIx64 " imp_cnt:%" PRIx64
2340 " request_cnt:%" PRIx64 " exec_cnt:%" PRIx64
2341 " merge_cnt:%" PRIx64 "adapter_state:%d",
2342 reset_string[hw->reset.level], hw->reset.stats.fail_cnt,
2343 hw->reset.stats.success_cnt, hw->reset.stats.global_cnt,
2344 hw->reset.stats.imp_cnt, hw->reset.stats.request_cnt,
2345 hw->reset.stats.exec_cnt, hw->reset.stats.merge_cnt,
2348 /* IMP no longer waiting the ready flag */
2349 hns3_notify_reset_ready(hw, true);
2354 hns3_reset_pre(struct hns3_adapter *hns)
2356 struct hns3_hw *hw = &hns->hw;
2360 if (hw->reset.stage == RESET_STAGE_NONE) {
2361 __atomic_store_n(&hns->hw.reset.resetting, 1, __ATOMIC_RELAXED);
2362 hw->reset.stage = RESET_STAGE_DOWN;
2363 ret = hw->reset.ops->stop_service(hns);
2364 gettimeofday(&tv, NULL);
2366 hns3_warn(hw, "Reset step1 down fail=%d time=%ld.%.6ld",
2367 ret, tv.tv_sec, tv.tv_usec);
2370 hns3_warn(hw, "Reset step1 down success time=%ld.%.6ld",
2371 tv.tv_sec, tv.tv_usec);
2372 hw->reset.stage = RESET_STAGE_PREWAIT;
2374 if (hw->reset.stage == RESET_STAGE_PREWAIT) {
2375 ret = hw->reset.ops->prepare_reset(hns);
2376 gettimeofday(&tv, NULL);
2379 "Reset step2 prepare wait fail=%d time=%ld.%.6ld",
2380 ret, tv.tv_sec, tv.tv_usec);
2383 hns3_warn(hw, "Reset step2 prepare wait success time=%ld.%.6ld",
2384 tv.tv_sec, tv.tv_usec);
2385 hw->reset.stage = RESET_STAGE_REQ_HW_RESET;
2386 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;
2392 hns3_reset_post(struct hns3_adapter *hns)
2394 #define TIMEOUT_RETRIES_CNT 5
2395 struct hns3_hw *hw = &hns->hw;
2396 struct timeval tv_delta;
2400 if (hw->adapter_state == HNS3_NIC_CLOSING) {
2401 hns3_warn(hw, "Don't do reset_post during closing, just uninit cmd");
2402 hns3_cmd_uninit(hw);
2406 if (hw->reset.stage == RESET_STAGE_DEV_INIT) {
2407 rte_spinlock_lock(&hw->lock);
2408 if (hw->reset.mbuf_deferred_free) {
2409 hns3_dev_release_mbufs(hns);
2410 hw->reset.mbuf_deferred_free = false;
2412 ret = hw->reset.ops->reinit_dev(hns);
2413 rte_spinlock_unlock(&hw->lock);
2414 gettimeofday(&tv, NULL);
2416 hns3_warn(hw, "Reset step5 devinit fail=%d retries=%d",
2417 ret, hw->reset.retries);
2420 hns3_warn(hw, "Reset step5 devinit success time=%ld.%.6ld",
2421 tv.tv_sec, tv.tv_usec);
2422 hw->reset.retries = 0;
2423 hw->reset.stage = RESET_STAGE_RESTORE;
2424 rte_eal_alarm_set(SWITCH_CONTEXT_US,
2425 hw->reset.ops->reset_service, hns);
2428 if (hw->reset.stage == RESET_STAGE_RESTORE) {
2429 rte_spinlock_lock(&hw->lock);
2430 ret = hw->reset.ops->restore_conf(hns);
2431 rte_spinlock_unlock(&hw->lock);
2432 gettimeofday(&tv, NULL);
2435 "Reset step6 restore fail=%d retries=%d",
2436 ret, hw->reset.retries);
2439 hns3_warn(hw, "Reset step6 restore success time=%ld.%.6ld",
2440 tv.tv_sec, tv.tv_usec);
2441 hw->reset.retries = 0;
2442 hw->reset.stage = RESET_STAGE_DONE;
2444 if (hw->reset.stage == RESET_STAGE_DONE) {
2445 /* IMP will wait ready flag before reset */
2446 hns3_notify_reset_ready(hw, false);
2447 hns3_clear_reset_level(hw, &hw->reset.pending);
2448 __atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED);
2449 hw->reset.attempts = 0;
2450 hw->reset.stats.success_cnt++;
2451 hw->reset.stage = RESET_STAGE_NONE;
2452 rte_spinlock_lock(&hw->lock);
2453 hw->reset.ops->start_service(hns);
2454 rte_spinlock_unlock(&hw->lock);
2455 gettimeofday(&tv, NULL);
2456 timersub(&tv, &hw->reset.start_time, &tv_delta);
2457 hns3_warn(hw, "%s reset done fail_cnt:%" PRIx64
2458 " success_cnt:%" PRIx64 " global_cnt:%" PRIx64
2459 " imp_cnt:%" PRIx64 " request_cnt:%" PRIx64
2460 " exec_cnt:%" PRIx64 " merge_cnt:%" PRIx64,
2461 reset_string[hw->reset.level],
2462 hw->reset.stats.fail_cnt, hw->reset.stats.success_cnt,
2463 hw->reset.stats.global_cnt, hw->reset.stats.imp_cnt,
2464 hw->reset.stats.request_cnt, hw->reset.stats.exec_cnt,
2465 hw->reset.stats.merge_cnt);
2467 "%s reset done delta %ld ms time=%ld.%.6ld",
2468 reset_string[hw->reset.level],
2469 tv_delta.tv_sec * MSEC_PER_SEC +
2470 tv_delta.tv_usec / USEC_PER_MSEC,
2471 tv.tv_sec, tv.tv_usec);
2472 hw->reset.level = HNS3_NONE_RESET;
2477 if (ret == -ETIME) {
2478 hw->reset.retries++;
2479 if (hw->reset.retries < TIMEOUT_RETRIES_CNT) {
2480 rte_eal_alarm_set(HNS3_RESET_SYNC_US,
2481 hw->reset.ops->reset_service, hns);
2485 hw->reset.retries = 0;
2490 * There are three scenarios as follows:
2491 * When the reset is not in progress, the reset process starts.
2492 * During the reset process, if the reset level has not changed,
2493 * the reset process continues; otherwise, the reset process is aborted.
2494 * hw->reset.level new_level action
2495 * HNS3_NONE_RESET HNS3_XXXX_RESET start reset
2496 * HNS3_XXXX_RESET HNS3_XXXX_RESET continue reset
2497 * HNS3_LOW_RESET HNS3_HIGH_RESET abort
2500 hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level)
2502 struct hns3_hw *hw = &hns->hw;
2503 struct timeval tv_delta;
2507 if (hw->reset.level == HNS3_NONE_RESET) {
2508 hw->reset.level = new_level;
2509 hw->reset.stats.exec_cnt++;
2510 gettimeofday(&hw->reset.start_time, NULL);
2511 hns3_warn(hw, "Start %s reset time=%ld.%.6ld",
2512 reset_string[hw->reset.level],
2513 hw->reset.start_time.tv_sec,
2514 hw->reset.start_time.tv_usec);
2517 if (is_reset_pending(hns)) {
2518 gettimeofday(&tv, NULL);
2520 "%s reset is aborted by high level time=%ld.%.6ld",
2521 reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);
2522 if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)
2523 rte_eal_alarm_cancel(hns3_wait_callback,
2524 hw->reset.wait_data);
2528 ret = hns3_reset_pre(hns);
2532 if (hw->reset.stage == RESET_STAGE_REQ_HW_RESET) {
2533 ret = hns3_reset_req_hw_reset(hns);
2536 gettimeofday(&tv, NULL);
2538 "Reset step3 request IMP reset success time=%ld.%.6ld",
2539 tv.tv_sec, tv.tv_usec);
2540 hw->reset.stage = RESET_STAGE_WAIT;
2541 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;
2543 if (hw->reset.stage == RESET_STAGE_WAIT) {
2544 ret = hw->reset.ops->wait_hardware_ready(hns);
2547 gettimeofday(&tv, NULL);
2548 hns3_warn(hw, "Reset step4 reset wait success time=%ld.%.6ld",
2549 tv.tv_sec, tv.tv_usec);
2550 hw->reset.stage = RESET_STAGE_DEV_INIT;
2553 ret = hns3_reset_post(hns);
2562 hns3_clear_reset_level(hw, &hw->reset.pending);
2563 if (hns3_reset_err_handle(hns)) {
2564 hw->reset.stage = RESET_STAGE_PREWAIT;
2565 hns3_schedule_reset(hns);
2567 rte_spinlock_lock(&hw->lock);
2568 if (hw->reset.mbuf_deferred_free) {
2569 hns3_dev_release_mbufs(hns);
2570 hw->reset.mbuf_deferred_free = false;
2572 rte_spinlock_unlock(&hw->lock);
2573 __atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED);
2574 hw->reset.stage = RESET_STAGE_NONE;
2575 gettimeofday(&tv, NULL);
2576 timersub(&tv, &hw->reset.start_time, &tv_delta);
2577 hns3_warn(hw, "%s reset fail delta %ld ms time=%ld.%.6ld",
2578 reset_string[hw->reset.level],
2579 tv_delta.tv_sec * MSEC_PER_SEC +
2580 tv_delta.tv_usec / USEC_PER_MSEC,
2581 tv.tv_sec, tv.tv_usec);
2582 hw->reset.level = HNS3_NONE_RESET;
2589 * The reset process can only be terminated after handshake with IMP(step3),
2590 * so that IMP can complete the reset process normally.
2593 hns3_reset_abort(struct hns3_adapter *hns)
2595 struct hns3_hw *hw = &hns->hw;
2599 for (i = 0; i < HNS3_QUIT_RESET_CNT; i++) {
2600 if (hw->reset.level == HNS3_NONE_RESET)
2602 rte_delay_ms(HNS3_QUIT_RESET_DELAY_MS);
2605 /* IMP no longer waiting the ready flag */
2606 hns3_notify_reset_ready(hw, true);
2608 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);
2609 rte_eal_alarm_cancel(hns3_wait_callback, hw->reset.wait_data);
2611 if (hw->reset.level != HNS3_NONE_RESET) {
2612 gettimeofday(&tv, NULL);
2613 hns3_err(hw, "Failed to terminate reset: %s time=%ld.%.6ld",
2614 reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);