drivers/net/hns3/hns3_intr.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_cycles.h>
   7 #include <rte_ethdev.h>
   8 #include <rte_io.h>
   9 #include <rte_malloc.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_intr.h"
  14 #include "hns3_regs.h"
  15 #include "hns3_rxtx.h"
  16
  17 #define SWITCH_CONTEXT_US       10
  18
  19 #define HNS3_CHECK_MERGE_CNT(val)                       \
  20         do {                                            \
  21                 if (val)                                \
  22                         hw->reset.stats.merge_cnt++;    \
  23         } while (0)
  24
  25 static const char *reset_string[HNS3_MAX_RESET] = {
  26         "none", "vf_func", "vf_pf_func", "vf_full", "flr",
  27         "vf_global", "pf_func", "global", "IMP",
  28 };
  29
  30 static const struct hns3_hw_error mac_afifo_tnl_int[] = {
  31         { .int_msk = BIT(0),
  32           .msg = "egu_cge_afifo_ecc_1bit_err",
  33           .reset_level = HNS3_NONE_RESET },
  34         { .int_msk = BIT(1),
  35           .msg = "egu_cge_afifo_ecc_mbit_err",
  36           .reset_level = HNS3_GLOBAL_RESET },
  37         { .int_msk = BIT(2),
  38           .msg = "egu_lge_afifo_ecc_1bit_err",
  39           .reset_level = HNS3_NONE_RESET },
  40         { .int_msk = BIT(3),
  41           .msg = "egu_lge_afifo_ecc_mbit_err",
  42           .reset_level = HNS3_GLOBAL_RESET },
  43         { .int_msk = BIT(4),
  44           .msg = "cge_igu_afifo_ecc_1bit_err",
  45           .reset_level = HNS3_NONE_RESET },
  46         { .int_msk = BIT(5),
  47           .msg = "cge_igu_afifo_ecc_mbit_err",
  48           .reset_level = HNS3_GLOBAL_RESET },
  49         { .int_msk = BIT(6),
  50           .msg = "lge_igu_afifo_ecc_1bit_err",
  51           .reset_level = HNS3_NONE_RESET },
  52         { .int_msk = BIT(7),
  53           .msg = "lge_igu_afifo_ecc_mbit_err",
  54           .reset_level = HNS3_GLOBAL_RESET },
  55         { .int_msk = BIT(8),
  56           .msg = "cge_igu_afifo_overflow_err",
  57           .reset_level = HNS3_GLOBAL_RESET },
  58         { .int_msk = BIT(9),
  59           .msg = "lge_igu_afifo_overflow_err",
  60           .reset_level = HNS3_GLOBAL_RESET },
  61         { .int_msk = BIT(10),
  62           .msg = "egu_cge_afifo_underrun_err",
  63           .reset_level = HNS3_GLOBAL_RESET },
  64         { .int_msk = BIT(11),
  65           .msg = "egu_lge_afifo_underrun_err",
  66           .reset_level = HNS3_GLOBAL_RESET },
  67         { .int_msk = BIT(12),
  68           .msg = "egu_ge_afifo_underrun_err",
  69           .reset_level = HNS3_GLOBAL_RESET },
  70         { .int_msk = BIT(13),
  71           .msg = "ge_igu_afifo_overflow_err",
  72           .reset_level = HNS3_GLOBAL_RESET },
  73         { .int_msk = 0,
  74           .msg = NULL,
  75           .reset_level = HNS3_NONE_RESET}
  76 };
  77
  78 static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = {
  79         { .int_msk = 0xFFFFFFFF,
  80           .msg = "rpu_rx_pkt_ecc_mbit_err",
  81           .reset_level = HNS3_GLOBAL_RESET },
  82         { .int_msk = 0,
  83           .msg = NULL,
  84           .reset_level = HNS3_NONE_RESET}
  85 };
  86
  87 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = {
  88         { .int_msk = BIT(13),
  89           .msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
  90           .reset_level = HNS3_GLOBAL_RESET },
  91         { .int_msk = BIT(14),
  92           .msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
  93           .reset_level = HNS3_GLOBAL_RESET },
  94         { .int_msk = BIT(15),
  95           .msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
  96           .reset_level = HNS3_GLOBAL_RESET },
  97         { .int_msk = BIT(16),
  98           .msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
  99           .reset_level = HNS3_GLOBAL_RESET },
 100         { .int_msk = BIT(17),
 101           .msg = "rcb_tx_ring_ecc_mbit_err",
 102           .reset_level = HNS3_GLOBAL_RESET },
 103         { .int_msk = BIT(18),
 104           .msg = "rcb_rx_ring_ecc_mbit_err",
 105           .reset_level = HNS3_GLOBAL_RESET },
 106         { .int_msk = BIT(19),
 107           .msg = "rcb_tx_fbd_ecc_mbit_err",
 108           .reset_level = HNS3_GLOBAL_RESET },
 109         { .int_msk = BIT(20),
 110           .msg = "rcb_rx_ebd_ecc_mbit_err",
 111           .reset_level = HNS3_GLOBAL_RESET },
 112         { .int_msk = BIT(21),
 113           .msg = "rcb_tso_info_ecc_mbit_err",
 114           .reset_level = HNS3_GLOBAL_RESET },
 115         { .int_msk = BIT(22),
 116           .msg = "rcb_tx_int_info_ecc_mbit_err",
 117           .reset_level = HNS3_GLOBAL_RESET },
 118         { .int_msk = BIT(23),
 119           .msg = "rcb_rx_int_info_ecc_mbit_err",
 120           .reset_level = HNS3_GLOBAL_RESET },
 121         { .int_msk = BIT(24),
 122           .msg = "tpu_tx_pkt_0_ecc_mbit_err",
 123           .reset_level = HNS3_GLOBAL_RESET },
 124         { .int_msk = BIT(25),
 125           .msg = "tpu_tx_pkt_1_ecc_mbit_err",
 126           .reset_level = HNS3_GLOBAL_RESET },
 127         { .int_msk = BIT(26),
 128           .msg = "rd_bus_err",
 129           .reset_level = HNS3_GLOBAL_RESET },
 130         { .int_msk = BIT(27),
 131           .msg = "wr_bus_err",
 132           .reset_level = HNS3_GLOBAL_RESET },
 133         { .int_msk = BIT(30),
 134           .msg = "ooo_ecc_err_detect",
 135           .reset_level = HNS3_NONE_RESET },
 136         { .int_msk = BIT(31),
 137           .msg = "ooo_ecc_err_multpl",
 138           .reset_level = HNS3_GLOBAL_RESET },
 139         { .int_msk = 0,
 140           .msg = NULL,
 141           .reset_level = HNS3_NONE_RESET}
 142 };
 143
 144 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = {
 145         { .int_msk = BIT(29),
 146           .msg = "rx_q_search_miss",
 147           .reset_level = HNS3_NONE_RESET },
 148         { .int_msk = 0,
 149           .msg = NULL,
 150           .reset_level = HNS3_NONE_RESET}
 151 };
 152
 153 static const struct hns3_hw_error ssu_port_based_pf_int[] = {
 154         { .int_msk = BIT(0),
 155           .msg = "roc_pkt_without_key_port",
 156           .reset_level = HNS3_GLOBAL_RESET },
 157         { .int_msk = BIT(9),
 158           .msg = "low_water_line_err_port",
 159           .reset_level = HNS3_NONE_RESET },
 160         { .int_msk = 0,
 161           .msg = NULL,
 162           .reset_level = HNS3_NONE_RESET}
 163 };
 164
 165 static const struct hns3_hw_error ppp_pf_abnormal_int[] = {
 166         { .int_msk = BIT(0),
 167           .msg = "tx_vlan_tag_err",
 168           .reset_level = HNS3_NONE_RESET },
 169         { .int_msk = BIT(1),
 170           .msg = "rss_list_tc_unassigned_queue_err",
 171           .reset_level = HNS3_NONE_RESET },
 172         { .int_msk = 0,
 173           .msg = NULL,
 174           .reset_level = HNS3_NONE_RESET}
 175 };
 176
 177 static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = {
 178         { .int_msk = BIT(3),
 179           .msg = "tx_rd_fbd_poison",
 180           .reset_level = HNS3_FUNC_RESET },
 181         { .int_msk = BIT(4),
 182           .msg = "rx_rd_ebd_poison",
 183           .reset_level = HNS3_FUNC_RESET },
 184         { .int_msk = 0,
 185           .msg = NULL,
 186           .reset_level = HNS3_NONE_RESET}
 187 };
 188
 189 static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = {
 190         { .int_msk = BIT(0),
 191           .msg = "over_8bd_no_fe",
 192           .reset_level = HNS3_FUNC_RESET },
 193         { .int_msk = BIT(1),
 194           .msg = "tso_mss_cmp_min_err",
 195           .reset_level = HNS3_NONE_RESET },
 196         { .int_msk = BIT(2),
 197           .msg = "tso_mss_cmp_max_err",
 198           .reset_level = HNS3_NONE_RESET },
 199         { .int_msk = BIT(5),
 200           .msg = "buf_wait_timeout",
 201           .reset_level = HNS3_NONE_RESET },
 202         { .int_msk = 0,
 203           .msg = NULL,
 204           .reset_level = HNS3_NONE_RESET}
 205 };
 206
 207 static const struct hns3_hw_error imp_tcm_ecc_int[] = {
 208         { .int_msk = BIT(1),
 209           .msg = "imp_itcm0_ecc_mbit_err",
 210           .reset_level = HNS3_NONE_RESET },
 211         { .int_msk = BIT(3),
 212           .msg = "imp_itcm1_ecc_mbit_err",
 213           .reset_level = HNS3_NONE_RESET },
 214         { .int_msk = BIT(5),
 215           .msg = "imp_itcm2_ecc_mbit_err",
 216           .reset_level = HNS3_NONE_RESET },
 217         { .int_msk = BIT(7),
 218           .msg = "imp_itcm3_ecc_mbit_err",
 219           .reset_level = HNS3_NONE_RESET },
 220         { .int_msk = BIT(9),
 221           .msg = "imp_dtcm0_mem0_ecc_mbit_err",
 222           .reset_level = HNS3_NONE_RESET },
 223         { .int_msk = BIT(11),
 224           .msg = "imp_dtcm0_mem1_ecc_mbit_err",
 225           .reset_level = HNS3_NONE_RESET },
 226         { .int_msk = BIT(13),
 227           .msg = "imp_dtcm1_mem0_ecc_mbit_err",
 228           .reset_level = HNS3_NONE_RESET },
 229         { .int_msk = BIT(15),
 230           .msg = "imp_dtcm1_mem1_ecc_mbit_err",
 231           .reset_level = HNS3_NONE_RESET },
 232         { .int_msk = BIT(17),
 233           .msg = "imp_itcm4_ecc_mbit_err",
 234           .reset_level = HNS3_NONE_RESET },
 235         { .int_msk = 0,
 236           .msg = NULL,
 237           .reset_level = HNS3_NONE_RESET}
 238 };
 239
 240 static const struct hns3_hw_error cmdq_mem_ecc_int[] = {
 241         { .int_msk = BIT(1),
 242           .msg = "cmdq_nic_rx_depth_ecc_mbit_err",
 243           .reset_level = HNS3_NONE_RESET },
 244         { .int_msk = BIT(3),
 245           .msg = "cmdq_nic_tx_depth_ecc_mbit_err",
 246           .reset_level = HNS3_NONE_RESET },
 247         { .int_msk = BIT(5),
 248           .msg = "cmdq_nic_rx_tail_ecc_mbit_err",
 249           .reset_level = HNS3_NONE_RESET },
 250         { .int_msk = BIT(7),
 251           .msg = "cmdq_nic_tx_tail_ecc_mbit_err",
 252           .reset_level = HNS3_NONE_RESET },
 253         { .int_msk = BIT(9),
 254           .msg = "cmdq_nic_rx_head_ecc_mbit_err",
 255           .reset_level = HNS3_NONE_RESET },
 256         { .int_msk = BIT(11),
 257           .msg = "cmdq_nic_tx_head_ecc_mbit_err",
 258           .reset_level = HNS3_NONE_RESET },
 259         { .int_msk = BIT(13),
 260           .msg = "cmdq_nic_rx_addr_ecc_mbit_err",
 261           .reset_level = HNS3_NONE_RESET },
 262         { .int_msk = BIT(15),
 263           .msg = "cmdq_nic_tx_addr_ecc_mbit_err",
 264           .reset_level = HNS3_NONE_RESET },
 265         { .int_msk = 0,
 266           .msg = NULL,
 267           .reset_level = HNS3_NONE_RESET}
 268 };
 269
 270 static const struct hns3_hw_error tqp_int_ecc_int[] = {
 271         { .int_msk = BIT(6),
 272           .msg = "tqp_int_cfg_even_ecc_mbit_err",
 273           .reset_level = HNS3_NONE_RESET },
 274         { .int_msk = BIT(7),
 275           .msg = "tqp_int_cfg_odd_ecc_mbit_err",
 276           .reset_level = HNS3_NONE_RESET },
 277         { .int_msk = BIT(8),
 278           .msg = "tqp_int_ctrl_even_ecc_mbit_err",
 279           .reset_level = HNS3_NONE_RESET },
 280         { .int_msk = BIT(9),
 281           .msg = "tqp_int_ctrl_odd_ecc_mbit_err",
 282           .reset_level = HNS3_NONE_RESET },
 283         { .int_msk = BIT(10),
 284           .msg = "tx_queue_scan_int_ecc_mbit_err",
 285           .reset_level = HNS3_NONE_RESET },
 286         { .int_msk = BIT(11),
 287           .msg = "rx_queue_scan_int_ecc_mbit_err",
 288           .reset_level = HNS3_NONE_RESET },
 289         { .int_msk = 0,
 290           .msg = NULL,
 291           .reset_level = HNS3_NONE_RESET}
 292 };
 293
 294 static const struct hns3_hw_error imp_rd_poison_int[] = {
 295         { .int_msk = BIT(0),
 296           .msg = "imp_rd_poison_int",
 297           .reset_level = HNS3_NONE_RESET },
 298         { .int_msk = 0,
 299           .msg = NULL,
 300           .reset_level = HNS3_NONE_RESET}
 301 };
 302
 303 #define HNS3_SSU_MEM_ECC_ERR(x) \
 304         { .int_msk = BIT(x), \
 305           .msg = "ssu_mem" #x "_ecc_mbit_err", \
 306           .reset_level = HNS3_GLOBAL_RESET }
 307
 308 static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = {
 309         HNS3_SSU_MEM_ECC_ERR(0),
 310         HNS3_SSU_MEM_ECC_ERR(1),
 311         HNS3_SSU_MEM_ECC_ERR(2),
 312         HNS3_SSU_MEM_ECC_ERR(3),
 313         HNS3_SSU_MEM_ECC_ERR(4),
 314         HNS3_SSU_MEM_ECC_ERR(5),
 315         HNS3_SSU_MEM_ECC_ERR(6),
 316         HNS3_SSU_MEM_ECC_ERR(7),
 317         HNS3_SSU_MEM_ECC_ERR(8),
 318         HNS3_SSU_MEM_ECC_ERR(9),
 319         HNS3_SSU_MEM_ECC_ERR(10),
 320         HNS3_SSU_MEM_ECC_ERR(11),
 321         HNS3_SSU_MEM_ECC_ERR(12),
 322         HNS3_SSU_MEM_ECC_ERR(13),
 323         HNS3_SSU_MEM_ECC_ERR(14),
 324         HNS3_SSU_MEM_ECC_ERR(15),
 325         HNS3_SSU_MEM_ECC_ERR(16),
 326         HNS3_SSU_MEM_ECC_ERR(17),
 327         HNS3_SSU_MEM_ECC_ERR(18),
 328         HNS3_SSU_MEM_ECC_ERR(19),
 329         HNS3_SSU_MEM_ECC_ERR(20),
 330         HNS3_SSU_MEM_ECC_ERR(21),
 331         HNS3_SSU_MEM_ECC_ERR(22),
 332         HNS3_SSU_MEM_ECC_ERR(23),
 333         HNS3_SSU_MEM_ECC_ERR(24),
 334         HNS3_SSU_MEM_ECC_ERR(25),
 335         HNS3_SSU_MEM_ECC_ERR(26),
 336         HNS3_SSU_MEM_ECC_ERR(27),
 337         HNS3_SSU_MEM_ECC_ERR(28),
 338         HNS3_SSU_MEM_ECC_ERR(29),
 339         HNS3_SSU_MEM_ECC_ERR(30),
 340         HNS3_SSU_MEM_ECC_ERR(31),
 341         { .int_msk = 0,
 342           .msg = NULL,
 343           .reset_level = HNS3_NONE_RESET}
 344 };
 345
 346 static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = {
 347         { .int_msk = BIT(0),
 348           .msg = "ssu_mem32_ecc_mbit_err",
 349           .reset_level = HNS3_GLOBAL_RESET },
 350         { .int_msk = 0,
 351           .msg = NULL,
 352           .reset_level = HNS3_NONE_RESET}
 353 };
 354
 355 static const struct hns3_hw_error ssu_common_ecc_int[] = {
 356         { .int_msk = BIT(0),
 357           .msg = "buf_sum_err",
 358           .reset_level = HNS3_NONE_RESET },
 359         { .int_msk = BIT(1),
 360           .msg = "ppp_mb_num_err",
 361           .reset_level = HNS3_NONE_RESET },
 362         { .int_msk = BIT(2),
 363           .msg = "ppp_mbid_err",
 364           .reset_level = HNS3_GLOBAL_RESET },
 365         { .int_msk = BIT(3),
 366           .msg = "ppp_rlt_mac_err",
 367           .reset_level = HNS3_GLOBAL_RESET },
 368         { .int_msk = BIT(4),
 369           .msg = "ppp_rlt_host_err",
 370           .reset_level = HNS3_GLOBAL_RESET },
 371         { .int_msk = BIT(5),
 372           .msg = "cks_edit_position_err",
 373           .reset_level = HNS3_GLOBAL_RESET },
 374         { .int_msk = BIT(6),
 375           .msg = "cks_edit_condition_err",
 376           .reset_level = HNS3_GLOBAL_RESET },
 377         { .int_msk = BIT(7),
 378           .msg = "vlan_edit_condition_err",
 379           .reset_level = HNS3_GLOBAL_RESET },
 380         { .int_msk = BIT(8),
 381           .msg = "vlan_num_ot_err",
 382           .reset_level = HNS3_GLOBAL_RESET },
 383         { .int_msk = BIT(9),
 384           .msg = "vlan_num_in_err",
 385           .reset_level = HNS3_GLOBAL_RESET },
 386         { .int_msk = 0,
 387           .msg = NULL,
 388           .reset_level = HNS3_NONE_RESET}
 389 };
 390
 391 static const struct hns3_hw_error igu_int[] = {
 392         { .int_msk = BIT(0),
 393           .msg = "igu_rx_buf0_ecc_mbit_err",
 394           .reset_level = HNS3_GLOBAL_RESET },
 395         { .int_msk = BIT(2),
 396           .msg = "igu_rx_buf1_ecc_mbit_err",
 397           .reset_level = HNS3_GLOBAL_RESET },
 398         { .int_msk = 0,
 399           .msg = NULL,
 400           .reset_level = HNS3_NONE_RESET}
 401 };
 402
 403 static const struct hns3_hw_error msix_ecc_int[] = {
 404         { .int_msk = BIT(1),
 405           .msg = "msix_nic_ecc_mbit_err",
 406           .reset_level = HNS3_NONE_RESET },
 407         { .int_msk = 0,
 408           .msg = NULL,
 409           .reset_level = HNS3_NONE_RESET}
 410 };
 411
 412 static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = {
 413         { .int_msk = BIT(0),
 414           .msg = "vf_vlan_ad_mem_ecc_mbit_err",
 415           .reset_level = HNS3_GLOBAL_RESET },
 416         { .int_msk = BIT(1),
 417           .msg = "umv_mcast_group_mem_ecc_mbit_err",
 418           .reset_level = HNS3_GLOBAL_RESET },
 419         { .int_msk = BIT(2),
 420           .msg = "umv_key_mem0_ecc_mbit_err",
 421           .reset_level = HNS3_GLOBAL_RESET },
 422         { .int_msk = BIT(3),
 423           .msg = "umv_key_mem1_ecc_mbit_err",
 424           .reset_level = HNS3_GLOBAL_RESET },
 425         { .int_msk = BIT(4),
 426           .msg = "umv_key_mem2_ecc_mbit_err",
 427           .reset_level = HNS3_GLOBAL_RESET },
 428         { .int_msk = BIT(5),
 429           .msg = "umv_key_mem3_ecc_mbit_err",
 430           .reset_level = HNS3_GLOBAL_RESET },
 431         { .int_msk = BIT(6),
 432           .msg = "umv_ad_mem_ecc_mbit_err",
 433           .reset_level = HNS3_GLOBAL_RESET },
 434         { .int_msk = BIT(7),
 435           .msg = "rss_tc_mode_mem_ecc_mbit_err",
 436           .reset_level = HNS3_GLOBAL_RESET },
 437         { .int_msk = BIT(8),
 438           .msg = "rss_idt_mem0_ecc_mbit_err",
 439           .reset_level = HNS3_GLOBAL_RESET },
 440         { .int_msk = BIT(9),
 441           .msg = "rss_idt_mem1_ecc_mbit_err",
 442           .reset_level = HNS3_GLOBAL_RESET },
 443         { .int_msk = BIT(10),
 444           .msg = "rss_idt_mem2_ecc_mbit_err",
 445           .reset_level = HNS3_GLOBAL_RESET },
 446         { .int_msk = BIT(11),
 447           .msg = "rss_idt_mem3_ecc_mbit_err",
 448           .reset_level = HNS3_GLOBAL_RESET },
 449         { .int_msk = BIT(12),
 450           .msg = "rss_idt_mem4_ecc_mbit_err",
 451           .reset_level = HNS3_GLOBAL_RESET },
 452         { .int_msk = BIT(13),
 453           .msg = "rss_idt_mem5_ecc_mbit_err",
 454           .reset_level = HNS3_GLOBAL_RESET },
 455         { .int_msk = BIT(14),
 456           .msg = "rss_idt_mem6_ecc_mbit_err",
 457           .reset_level = HNS3_GLOBAL_RESET },
 458         { .int_msk = BIT(15),
 459           .msg = "rss_idt_mem7_ecc_mbit_err",
 460           .reset_level = HNS3_GLOBAL_RESET },
 461         { .int_msk = BIT(16),
 462           .msg = "rss_idt_mem8_ecc_mbit_err",
 463           .reset_level = HNS3_GLOBAL_RESET },
 464         { .int_msk = BIT(17),
 465           .msg = "rss_idt_mem9_ecc_mbit_err",
 466           .reset_level = HNS3_GLOBAL_RESET },
 467         { .int_msk = BIT(18),
 468           .msg = "rss_idt_mem10_ecc_m1bit_err",
 469           .reset_level = HNS3_GLOBAL_RESET },
 470         { .int_msk = BIT(19),
 471           .msg = "rss_idt_mem11_ecc_mbit_err",
 472           .reset_level = HNS3_GLOBAL_RESET },
 473         { .int_msk = BIT(20),
 474           .msg = "rss_idt_mem12_ecc_mbit_err",
 475           .reset_level = HNS3_GLOBAL_RESET },
 476         { .int_msk = BIT(21),
 477           .msg = "rss_idt_mem13_ecc_mbit_err",
 478           .reset_level = HNS3_GLOBAL_RESET },
 479         { .int_msk = BIT(22),
 480           .msg = "rss_idt_mem14_ecc_mbit_err",
 481           .reset_level = HNS3_GLOBAL_RESET },
 482         { .int_msk = BIT(23),
 483           .msg = "rss_idt_mem15_ecc_mbit_err",
 484           .reset_level = HNS3_GLOBAL_RESET },
 485         { .int_msk = BIT(24),
 486           .msg = "port_vlan_mem_ecc_mbit_err",
 487           .reset_level = HNS3_GLOBAL_RESET },
 488         { .int_msk = BIT(25),
 489           .msg = "mcast_linear_table_mem_ecc_mbit_err",
 490           .reset_level = HNS3_GLOBAL_RESET },
 491         { .int_msk = BIT(26),
 492           .msg = "mcast_result_mem_ecc_mbit_err",
 493           .reset_level = HNS3_GLOBAL_RESET },
 494         { .int_msk = BIT(27),
 495           .msg = "flow_director_ad_mem0_ecc_mbit_err",
 496           .reset_level = HNS3_GLOBAL_RESET },
 497         { .int_msk = BIT(28),
 498           .msg = "flow_director_ad_mem1_ecc_mbit_err",
 499           .reset_level = HNS3_GLOBAL_RESET },
 500         { .int_msk = BIT(29),
 501           .msg = "rx_vlan_tag_memory_ecc_mbit_err",
 502           .reset_level = HNS3_GLOBAL_RESET },
 503         { .int_msk = BIT(30),
 504           .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
 505           .reset_level = HNS3_GLOBAL_RESET },
 506         { .int_msk = 0,
 507           .msg = NULL,
 508           .reset_level = HNS3_NONE_RESET}
 509 };
 510
 511 static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = {
 512         { .int_msk = BIT(0),
 513           .msg = "hfs_fifo_mem_ecc_mbit_err",
 514           .reset_level = HNS3_GLOBAL_RESET },
 515         { .int_msk = BIT(1),
 516           .msg = "rslt_descr_fifo_mem_ecc_mbit_err",
 517           .reset_level = HNS3_GLOBAL_RESET },
 518         { .int_msk = BIT(2),
 519           .msg = "tx_vlan_tag_mem_ecc_mbit_err",
 520           .reset_level = HNS3_GLOBAL_RESET },
 521         { .int_msk = BIT(3),
 522           .msg = "FD_CN0_memory_ecc_mbit_err",
 523           .reset_level = HNS3_GLOBAL_RESET },
 524         { .int_msk = BIT(4),
 525           .msg = "FD_CN1_memory_ecc_mbit_err",
 526           .reset_level = HNS3_GLOBAL_RESET },
 527         { .int_msk = BIT(5),
 528           .msg = "GRO_AD_memory_ecc_mbit_err",
 529           .reset_level = HNS3_GLOBAL_RESET },
 530         { .int_msk = 0,
 531           .msg = NULL,
 532           .reset_level = HNS3_NONE_RESET}
 533 };
 534
 535 static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = {
 536         { .int_msk = BIT(4),
 537           .msg = "gro_bd_ecc_mbit_err",
 538           .reset_level = HNS3_GLOBAL_RESET },
 539         { .int_msk = BIT(5),
 540           .msg = "gro_context_ecc_mbit_err",
 541           .reset_level = HNS3_GLOBAL_RESET },
 542         { .int_msk = BIT(6),
 543           .msg = "rx_stash_cfg_ecc_mbit_err",
 544           .reset_level = HNS3_GLOBAL_RESET },
 545         { .int_msk = BIT(7),
 546           .msg = "axi_rd_fbd_ecc_mbit_err",
 547           .reset_level = HNS3_GLOBAL_RESET },
 548         { .int_msk = 0,
 549           .msg = NULL,
 550           .reset_level = HNS3_NONE_RESET}
 551 };
 552
 553 static const struct hns3_hw_error tm_sch_int[] = {
 554         { .int_msk = BIT(1),
 555           .msg = "tm_sch_ecc_mbit_err",
 556           .reset_level = HNS3_GLOBAL_RESET },
 557         { .int_msk = BIT(2),
 558           .msg = "tm_sch_port_shap_sub_fifo_wr_err",
 559           .reset_level = HNS3_GLOBAL_RESET },
 560         { .int_msk = BIT(3),
 561           .msg = "tm_sch_port_shap_sub_fifo_rd_err",
 562           .reset_level = HNS3_GLOBAL_RESET },
 563         { .int_msk = BIT(4),
 564           .msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
 565           .reset_level = HNS3_GLOBAL_RESET },
 566         { .int_msk = BIT(5),
 567           .msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
 568           .reset_level = HNS3_GLOBAL_RESET },
 569         { .int_msk = BIT(6),
 570           .msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
 571           .reset_level = HNS3_GLOBAL_RESET },
 572         { .int_msk = BIT(7),
 573           .msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
 574           .reset_level = HNS3_GLOBAL_RESET },
 575         { .int_msk = BIT(8),
 576           .msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
 577           .reset_level = HNS3_GLOBAL_RESET },
 578         { .int_msk = BIT(9),
 579           .msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
 580           .reset_level = HNS3_GLOBAL_RESET },
 581         { .int_msk = BIT(10),
 582           .msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
 583           .reset_level = HNS3_GLOBAL_RESET },
 584         { .int_msk = BIT(11),
 585           .msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
 586           .reset_level = HNS3_GLOBAL_RESET },
 587         { .int_msk = BIT(12),
 588           .msg = "tm_sch_port_shap_offset_fifo_wr_err",
 589           .reset_level = HNS3_GLOBAL_RESET },
 590         { .int_msk = BIT(13),
 591           .msg = "tm_sch_port_shap_offset_fifo_rd_err",
 592           .reset_level = HNS3_GLOBAL_RESET },
 593         { .int_msk = BIT(14),
 594           .msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
 595           .reset_level = HNS3_GLOBAL_RESET },
 596         { .int_msk = BIT(15),
 597           .msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
 598           .reset_level = HNS3_GLOBAL_RESET },
 599         { .int_msk = BIT(16),
 600           .msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
 601           .reset_level = HNS3_GLOBAL_RESET },
 602         { .int_msk = BIT(17),
 603           .msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
 604           .reset_level = HNS3_GLOBAL_RESET },
 605         { .int_msk = BIT(18),
 606           .msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
 607           .reset_level = HNS3_GLOBAL_RESET },
 608         { .int_msk = BIT(19),
 609           .msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
 610           .reset_level = HNS3_GLOBAL_RESET },
 611         { .int_msk = BIT(20),
 612           .msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
 613           .reset_level = HNS3_GLOBAL_RESET },
 614         { .int_msk = BIT(21),
 615           .msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
 616           .reset_level = HNS3_GLOBAL_RESET },
 617         { .int_msk = BIT(22),
 618           .msg = "tm_sch_rq_fifo_wr_err",
 619           .reset_level = HNS3_GLOBAL_RESET },
 620         { .int_msk = BIT(23),
 621           .msg = "tm_sch_rq_fifo_rd_err",
 622           .reset_level = HNS3_GLOBAL_RESET },
 623         { .int_msk = BIT(24),
 624           .msg = "tm_sch_nq_fifo_wr_err",
 625           .reset_level = HNS3_GLOBAL_RESET },
 626         { .int_msk = BIT(25),
 627           .msg = "tm_sch_nq_fifo_rd_err",
 628           .reset_level = HNS3_GLOBAL_RESET },
 629         { .int_msk = BIT(26),
 630           .msg = "tm_sch_roce_up_fifo_wr_err",
 631           .reset_level = HNS3_GLOBAL_RESET },
 632         { .int_msk = BIT(27),
 633           .msg = "tm_sch_roce_up_fifo_rd_err",
 634           .reset_level = HNS3_GLOBAL_RESET },
 635         { .int_msk = BIT(28),
 636           .msg = "tm_sch_rcb_byte_fifo_wr_err",
 637           .reset_level = HNS3_GLOBAL_RESET },
 638         { .int_msk = BIT(29),
 639           .msg = "tm_sch_rcb_byte_fifo_rd_err",
 640           .reset_level = HNS3_GLOBAL_RESET },
 641         { .int_msk = BIT(30),
 642           .msg = "tm_sch_ssu_byte_fifo_wr_err",
 643           .reset_level = HNS3_GLOBAL_RESET },
 644         { .int_msk = BIT(31),
 645           .msg = "tm_sch_ssu_byte_fifo_rd_err",
 646           .reset_level = HNS3_GLOBAL_RESET },
 647         { .int_msk = 0,
 648           .msg = NULL,
 649           .reset_level = HNS3_NONE_RESET}
 650 };
 651
 652 static const struct hns3_hw_error qcn_fifo_int[] = {
 653         { .int_msk = BIT(0),
 654           .msg = "qcn_shap_gp0_sch_fifo_rd_err",
 655           .reset_level = HNS3_GLOBAL_RESET },
 656         { .int_msk = BIT(1),
 657           .msg = "qcn_shap_gp0_sch_fifo_wr_err",
 658           .reset_level = HNS3_GLOBAL_RESET },
 659         { .int_msk = BIT(2),
 660           .msg = "qcn_shap_gp1_sch_fifo_rd_err",
 661           .reset_level = HNS3_GLOBAL_RESET },
 662         { .int_msk = BIT(3),
 663           .msg = "qcn_shap_gp1_sch_fifo_wr_err",
 664           .reset_level = HNS3_GLOBAL_RESET },
 665         { .int_msk = BIT(4),
 666           .msg = "qcn_shap_gp2_sch_fifo_rd_err",
 667           .reset_level = HNS3_GLOBAL_RESET },
 668         { .int_msk = BIT(5),
 669           .msg = "qcn_shap_gp2_sch_fifo_wr_err",
 670           .reset_level = HNS3_GLOBAL_RESET },
 671         { .int_msk = BIT(6),
 672           .msg = "qcn_shap_gp3_sch_fifo_rd_err",
 673           .reset_level = HNS3_GLOBAL_RESET },
 674         { .int_msk = BIT(7),
 675           .msg = "qcn_shap_gp3_sch_fifo_wr_err",
 676           .reset_level = HNS3_GLOBAL_RESET },
 677         { .int_msk = BIT(8),
 678           .msg = "qcn_shap_gp0_offset_fifo_rd_err",
 679           .reset_level = HNS3_GLOBAL_RESET },
 680         { .int_msk = BIT(9),
 681           .msg = "qcn_shap_gp0_offset_fifo_wr_err",
 682           .reset_level = HNS3_GLOBAL_RESET },
 683         { .int_msk = BIT(10),
 684           .msg = "qcn_shap_gp1_offset_fifo_rd_err",
 685           .reset_level = HNS3_GLOBAL_RESET },
 686         { .int_msk = BIT(11),
 687           .msg = "qcn_shap_gp1_offset_fifo_wr_err",
 688           .reset_level = HNS3_GLOBAL_RESET },
 689         { .int_msk = BIT(12),
 690           .msg = "qcn_shap_gp2_offset_fifo_rd_err",
 691           .reset_level = HNS3_GLOBAL_RESET },
 692         { .int_msk = BIT(13),
 693           .msg = "qcn_shap_gp2_offset_fifo_wr_err",
 694           .reset_level = HNS3_GLOBAL_RESET },
 695         { .int_msk = BIT(14),
 696           .msg = "qcn_shap_gp3_offset_fifo_rd_err",
 697           .reset_level = HNS3_GLOBAL_RESET },
 698         { .int_msk = BIT(15),
 699           .msg = "qcn_shap_gp3_offset_fifo_wr_err",
 700           .reset_level = HNS3_GLOBAL_RESET },
 701         { .int_msk = BIT(16),
 702           .msg = "qcn_byte_info_fifo_rd_err",
 703           .reset_level = HNS3_GLOBAL_RESET },
 704         { .int_msk = BIT(17),
 705           .msg = "qcn_byte_info_fifo_wr_err",
 706           .reset_level = HNS3_GLOBAL_RESET },
 707         { .int_msk = 0,
 708           .msg = NULL,
 709           .reset_level = HNS3_NONE_RESET}
 710 };
 711
 712 static const struct hns3_hw_error qcn_ecc_int[] = {
 713         { .int_msk = BIT(1),
 714           .msg = "qcn_byte_mem_ecc_mbit_err",
 715           .reset_level = HNS3_GLOBAL_RESET },
 716         { .int_msk = BIT(3),
 717           .msg = "qcn_time_mem_ecc_mbit_err",
 718           .reset_level = HNS3_GLOBAL_RESET },
 719         { .int_msk = BIT(5),
 720           .msg = "qcn_fb_mem_ecc_mbit_err",
 721           .reset_level = HNS3_GLOBAL_RESET },
 722         { .int_msk = BIT(7),
 723           .msg = "qcn_link_mem_ecc_mbit_err",
 724           .reset_level = HNS3_GLOBAL_RESET },
 725         { .int_msk = BIT(9),
 726           .msg = "qcn_rate_mem_ecc_mbit_err",
 727           .reset_level = HNS3_GLOBAL_RESET },
 728         { .int_msk = BIT(11),
 729           .msg = "qcn_tmplt_mem_ecc_mbit_err",
 730           .reset_level = HNS3_GLOBAL_RESET },
 731         { .int_msk = BIT(13),
 732           .msg = "qcn_shap_cfg_mem_ecc_mbit_err",
 733           .reset_level = HNS3_GLOBAL_RESET },
 734         { .int_msk = BIT(15),
 735           .msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
 736           .reset_level = HNS3_GLOBAL_RESET },
 737         { .int_msk = BIT(17),
 738           .msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
 739           .reset_level = HNS3_GLOBAL_RESET },
 740         { .int_msk = BIT(19),
 741           .msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
 742           .reset_level = HNS3_GLOBAL_RESET },
 743         { .int_msk = BIT(21),
 744           .msg = "qcn_gp3_barral_mem_ecc_mbit_err",
 745           .reset_level = HNS3_GLOBAL_RESET },
 746         { .int_msk = 0,
 747           .msg = NULL,
 748           .reset_level = HNS3_NONE_RESET}
 749 };
 750
 751 static const struct hns3_hw_error ncsi_ecc_int[] = {
 752         { .int_msk = BIT(1),
 753           .msg = "ncsi_tx_ecc_mbit_err",
 754           .reset_level = HNS3_NONE_RESET },
 755         { .int_msk = 0,
 756           .msg = NULL,
 757           .reset_level = HNS3_NONE_RESET}
 758 };
 759
 760 static const struct hns3_hw_error ssu_fifo_overflow_int[] = {
 761         { .int_msk = BIT(0),
 762           .msg = "ig_mac_inf_int",
 763           .reset_level = HNS3_GLOBAL_RESET },
 764         { .int_msk = BIT(1),
 765           .msg = "ig_host_inf_int",
 766           .reset_level = HNS3_GLOBAL_RESET },
 767         { .int_msk = BIT(2),
 768           .msg = "ig_roc_buf_int",
 769           .reset_level = HNS3_GLOBAL_RESET },
 770         { .int_msk = BIT(3),
 771           .msg = "ig_host_data_fifo_int",
 772           .reset_level = HNS3_GLOBAL_RESET },
 773         { .int_msk = BIT(4),
 774           .msg = "ig_host_key_fifo_int",
 775           .reset_level = HNS3_GLOBAL_RESET },
 776         { .int_msk = BIT(5),
 777           .msg = "tx_qcn_fifo_int",
 778           .reset_level = HNS3_GLOBAL_RESET },
 779         { .int_msk = BIT(6),
 780           .msg = "rx_qcn_fifo_int",
 781           .reset_level = HNS3_GLOBAL_RESET },
 782         { .int_msk = BIT(7),
 783           .msg = "tx_pf_rd_fifo_int",
 784           .reset_level = HNS3_GLOBAL_RESET },
 785         { .int_msk = BIT(8),
 786           .msg = "rx_pf_rd_fifo_int",
 787           .reset_level = HNS3_GLOBAL_RESET },
 788         { .int_msk = BIT(9),
 789           .msg = "qm_eof_fifo_int",
 790           .reset_level = HNS3_GLOBAL_RESET },
 791         { .int_msk = BIT(10),
 792           .msg = "mb_rlt_fifo_int",
 793           .reset_level = HNS3_GLOBAL_RESET },
 794         { .int_msk = BIT(11),
 795           .msg = "dup_uncopy_fifo_int",
 796           .reset_level = HNS3_GLOBAL_RESET },
 797         { .int_msk = BIT(12),
 798           .msg = "dup_cnt_rd_fifo_int",
 799           .reset_level = HNS3_GLOBAL_RESET },
 800         { .int_msk = BIT(13),
 801           .msg = "dup_cnt_drop_fifo_int",
 802           .reset_level = HNS3_GLOBAL_RESET },
 803         { .int_msk = BIT(14),
 804           .msg = "dup_cnt_wrb_fifo_int",
 805           .reset_level = HNS3_GLOBAL_RESET },
 806         { .int_msk = BIT(15),
 807           .msg = "host_cmd_fifo_int",
 808           .reset_level = HNS3_GLOBAL_RESET },
 809         { .int_msk = BIT(16),
 810           .msg = "mac_cmd_fifo_int",
 811           .reset_level = HNS3_GLOBAL_RESET },
 812         { .int_msk = BIT(17),
 813           .msg = "host_cmd_bitmap_empty_int",
 814           .reset_level = HNS3_GLOBAL_RESET },
 815         { .int_msk = BIT(18),
 816           .msg = "mac_cmd_bitmap_empty_int",
 817           .reset_level = HNS3_GLOBAL_RESET },
 818         { .int_msk = BIT(19),
 819           .msg = "dup_bitmap_empty_int",
 820           .reset_level = HNS3_GLOBAL_RESET },
 821         { .int_msk = BIT(20),
 822           .msg = "out_queue_bitmap_empty_int",
 823           .reset_level = HNS3_GLOBAL_RESET },
 824         { .int_msk = BIT(21),
 825           .msg = "bank2_bitmap_empty_int",
 826           .reset_level = HNS3_GLOBAL_RESET },
 827         { .int_msk = BIT(22),
 828           .msg = "bank1_bitmap_empty_int",
 829           .reset_level = HNS3_GLOBAL_RESET },
 830         { .int_msk = BIT(23),
 831           .msg = "bank0_bitmap_empty_int",
 832           .reset_level = HNS3_GLOBAL_RESET },
 833         { .int_msk = 0,
 834           .msg = NULL,
 835           .reset_level = HNS3_NONE_RESET}
 836 };
 837
 838 static const struct hns3_hw_error ssu_ets_tcg_int[] = {
 839         { .int_msk = BIT(0),
 840           .msg = "ets_rd_int_rx_tcg",
 841           .reset_level = HNS3_GLOBAL_RESET },
 842         { .int_msk = BIT(1),
 843           .msg = "ets_wr_int_rx_tcg",
 844           .reset_level = HNS3_GLOBAL_RESET },
 845         { .int_msk = BIT(2),
 846           .msg = "ets_rd_int_tx_tcg",
 847           .reset_level = HNS3_GLOBAL_RESET },
 848         { .int_msk = BIT(3),
 849           .msg = "ets_wr_int_tx_tcg",
 850           .reset_level = HNS3_GLOBAL_RESET },
 851         { .int_msk = 0,
 852           .msg = NULL,
 853           .reset_level = HNS3_NONE_RESET}
 854 };
 855
 856 static const struct hns3_hw_error igu_egu_tnl_int[] = {
 857         { .int_msk = BIT(0),
 858           .msg = "rx_buf_overflow",
 859           .reset_level = HNS3_GLOBAL_RESET },
 860         { .int_msk = BIT(1),
 861           .msg = "rx_stp_fifo_overflow",
 862           .reset_level = HNS3_GLOBAL_RESET },
 863         { .int_msk = BIT(2),
 864           .msg = "rx_stp_fifo_underflow",
 865           .reset_level = HNS3_GLOBAL_RESET },
 866         { .int_msk = BIT(3),
 867           .msg = "tx_buf_overflow",
 868           .reset_level = HNS3_GLOBAL_RESET },
 869         { .int_msk = BIT(4),
 870           .msg = "tx_buf_underrun",
 871           .reset_level = HNS3_GLOBAL_RESET },
 872         { .int_msk = BIT(5),
 873           .msg = "rx_stp_buf_overflow",
 874           .reset_level = HNS3_GLOBAL_RESET },
 875         { .int_msk = 0,
 876           .msg = NULL,
 877           .reset_level = HNS3_NONE_RESET}
 878 };
 879
 880 static const struct hns3_hw_error ssu_port_based_err_int[] = {
 881         { .int_msk = BIT(0),
 882           .msg = "roc_pkt_without_key_port",
 883           .reset_level = HNS3_FUNC_RESET },
 884         { .int_msk = BIT(1),
 885           .msg = "tpu_pkt_without_key_port",
 886           .reset_level = HNS3_GLOBAL_RESET },
 887         { .int_msk = BIT(2),
 888           .msg = "igu_pkt_without_key_port",
 889           .reset_level = HNS3_GLOBAL_RESET },
 890         { .int_msk = BIT(3),
 891           .msg = "roc_eof_mis_match_port",
 892           .reset_level = HNS3_GLOBAL_RESET },
 893         { .int_msk = BIT(4),
 894           .msg = "tpu_eof_mis_match_port",
 895           .reset_level = HNS3_GLOBAL_RESET },
 896         { .int_msk = BIT(5),
 897           .msg = "igu_eof_mis_match_port",
 898           .reset_level = HNS3_GLOBAL_RESET },
 899         { .int_msk = BIT(6),
 900           .msg = "roc_sof_mis_match_port",
 901           .reset_level = HNS3_GLOBAL_RESET },
 902         { .int_msk = BIT(7),
 903           .msg = "tpu_sof_mis_match_port",
 904           .reset_level = HNS3_GLOBAL_RESET },
 905         { .int_msk = BIT(8),
 906           .msg = "igu_sof_mis_match_port",
 907           .reset_level = HNS3_GLOBAL_RESET },
 908         { .int_msk = BIT(11),
 909           .msg = "ets_rd_int_rx_port",
 910           .reset_level = HNS3_GLOBAL_RESET },
 911         { .int_msk = BIT(12),
 912           .msg = "ets_wr_int_rx_port",
 913           .reset_level = HNS3_GLOBAL_RESET },
 914         { .int_msk = BIT(13),
 915           .msg = "ets_rd_int_tx_port",
 916           .reset_level = HNS3_GLOBAL_RESET },
 917         { .int_msk = BIT(14),
 918           .msg = "ets_wr_int_tx_port",
 919           .reset_level = HNS3_GLOBAL_RESET },
 920         { .int_msk = 0,
 921           .msg = NULL,
 922           .reset_level = HNS3_NONE_RESET}
 923 };
 924
 925 static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = {
 926         { .desc_offset = 0,
 927           .data_offset = 0,
 928           .msg = "IMP_TCM_ECC_INT_STS",
 929           .hw_err = imp_tcm_ecc_int },
 930         { .desc_offset = 0,
 931           .data_offset = 1,
 932           .msg = "CMDQ_MEM_ECC_INT_STS",
 933           .hw_err = cmdq_mem_ecc_int },
 934         { .desc_offset = 0,
 935           .data_offset = 2,
 936           .msg = "IMP_RD_POISON_INT_STS",
 937           .hw_err = imp_rd_poison_int },
 938         { .desc_offset = 0,
 939           .data_offset = 3,
 940           .msg = "TQP_INT_ECC_INT_STS",
 941           .hw_err = tqp_int_ecc_int },
 942         { .desc_offset = 0,
 943           .data_offset = 4,
 944           .msg = "MSIX_ECC_INT_STS",
 945           .hw_err = msix_ecc_int },
 946         { .desc_offset = 2,
 947           .data_offset = 2,
 948           .msg = "SSU_ECC_MULTI_BIT_INT_0",
 949           .hw_err = ssu_ecc_multi_bit_int_0 },
 950         { .desc_offset = 2,
 951           .data_offset = 3,
 952           .msg = "SSU_ECC_MULTI_BIT_INT_1",
 953           .hw_err = ssu_ecc_multi_bit_int_1 },
 954         { .desc_offset = 2,
 955           .data_offset = 4,
 956           .msg = "SSU_COMMON_ERR_INT",
 957           .hw_err = ssu_common_ecc_int },
 958         { .desc_offset = 3,
 959           .data_offset = 0,
 960           .msg = "IGU_INT_STS",
 961           .hw_err = igu_int },
 962         { .desc_offset = 4,
 963           .data_offset = 1,
 964           .msg = "PPP_MPF_ABNORMAL_INT_ST1",
 965           .hw_err = ppp_mpf_abnormal_int_st1 },
 966         { .desc_offset = 4,
 967           .data_offset = 3,
 968           .msg = "PPP_MPF_ABNORMAL_INT_ST3",
 969           .hw_err = ppp_mpf_abnormal_int_st3 },
 970         { .desc_offset = 5,
 971           .data_offset = 1,
 972           .msg = "PPU_MPF_ABNORMAL_INT_ST1",
 973           .hw_err = ppu_mpf_abnormal_int_st1 },
 974         { .desc_offset = 5,
 975           .data_offset = 2,
 976           .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS",
 977           .hw_err = ppu_mpf_abnormal_int_st2_ras },
 978         { .desc_offset = 5,
 979           .data_offset = 3,
 980           .msg = "PPU_MPF_ABNORMAL_INT_ST3",
 981           .hw_err = ppu_mpf_abnormal_int_st3 },
 982         { .desc_offset = 6,
 983           .data_offset = 0,
 984           .msg = "TM_SCH_RINT",
 985           .hw_err = tm_sch_int },
 986         { .desc_offset = 7,
 987           .data_offset = 0,
 988           .msg = "QCN_FIFO_RINT",
 989           .hw_err = qcn_fifo_int },
 990         { .desc_offset = 7,
 991           .data_offset = 1,
 992           .msg = "QCN_ECC_RINT",
 993           .hw_err = qcn_ecc_int },
 994         { .desc_offset = 9,
 995           .data_offset = 0,
 996           .msg = "NCSI_ECC_INT_RPT",
 997           .hw_err = ncsi_ecc_int },
 998         { .desc_offset = 0,
 999           .data_offset = 0,
1000           .msg = NULL,
1001           .hw_err = NULL }
1002 };
1003
1004 static const struct hns3_hw_error_desc pf_ras_err_tbl[] = {
1005         { .desc_offset = 0,
1006           .data_offset = 0,
1007           .msg = "SSU_PORT_BASED_ERR_INT_RAS",
1008           .hw_err = ssu_port_based_err_int },
1009         { .desc_offset = 0,
1010           .data_offset = 1,
1011           .msg = "SSU_FIFO_OVERFLOW_INT",
1012           .hw_err = ssu_fifo_overflow_int },
1013         { .desc_offset = 0,
1014           .data_offset = 2,
1015           .msg = "SSU_ETS_TCG_INT",
1016           .hw_err = ssu_ets_tcg_int },
1017         { .desc_offset = 1,
1018           .data_offset = 0,
1019           .msg = "IGU_EGU_TNL_INT_STS",
1020           .hw_err = igu_egu_tnl_int },
1021         { .desc_offset = 3,
1022           .data_offset = 0,
1023           .msg = "PPU_PF_ABNORMAL_INT_ST_RAS",
1024           .hw_err = ppu_pf_abnormal_int_ras },
1025         { .desc_offset = 0,
1026           .data_offset = 0,
1027           .msg = NULL,
1028           .hw_err = NULL }
1029 };
1030
1031 static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = {
1032         { .desc_offset = 1,
1033           .data_offset = 0,
1034           .msg = "MAC_AFIFO_TNL_INT_R",
1035           .hw_err = mac_afifo_tnl_int },
1036         { .desc_offset = 5,
1037           .data_offset = 2,
1038           .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX",
1039           .hw_err = ppu_mpf_abnormal_int_st2_msix },
1040         { .desc_offset = 0,
1041           .data_offset = 0,
1042           .msg = NULL,
1043           .hw_err = NULL }
1044 };
1045
1046 static const struct hns3_hw_error_desc pf_msix_err_tbl[] = {
1047         { .desc_offset = 0,
1048           .data_offset = 0,
1049           .msg = "SSU_PORT_BASED_ERR_INT_MSIX",
1050           .hw_err = ssu_port_based_pf_int },
1051         { .desc_offset = 2,
1052           .data_offset = 0,
1053           .msg = "PPP_PF_ABNORMAL_INT_ST0",
1054           .hw_err = ppp_pf_abnormal_int },
1055         { .desc_offset = 3,
1056           .data_offset = 0,
1057           .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX",
1058           .hw_err = ppu_pf_abnormal_int_msix },
1059         { .desc_offset = 0,
1060           .data_offset = 0,
1061           .msg = NULL,
1062           .hw_err = NULL }
1063 };
1064
1065 enum hns3_hw_err_type {
1066         MPF_MSIX_ERR,
1067         PF_MSIX_ERR,
1068         MPF_RAS_ERR,
1069         PF_RAS_ERR,
1070 };
1071
1072 static int
1073 hns3_config_ncsi_hw_err_int(struct hns3_adapter *hns, bool en)
1074 {
1075         struct hns3_hw *hw = &hns->hw;
1076         struct hns3_cmd_desc desc;
1077         int ret;
1078
1079         /* configure NCSI error interrupts */
1080         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_NCSI_INT_EN, false);
1081         if (en)
1082                 desc.data[0] = rte_cpu_to_le_32(HNS3_NCSI_ERR_INT_EN);
1083
1084         ret = hns3_cmd_send(hw, &desc, 1);
1085         if (ret)
1086                 hns3_err(hw, "fail to %s NCSI error interrupts, ret = %d",
1087                          en ? "enable" : "disable", ret);
1088
1089         return ret;
1090 }
1091
1092 static int
1093 enable_igu_egu_err_intr(struct hns3_adapter *hns, bool en)
1094 {
1095         struct hns3_hw *hw = &hns->hw;
1096         struct hns3_cmd_desc desc;
1097         int ret;
1098
1099         /* configure IGU,EGU error interrupts */
1100         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_COMMON_INT_EN, false);
1101         if (en)
1102                 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_ENABLE);
1103         else
1104                 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_DISABLE);
1105
1106         desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_EN_MASK);
1107
1108         ret = hns3_cmd_send(hw, &desc, 1);
1109         if (ret) {
1110                 hns3_err(hw, "fail to %s IGU common interrupts, ret = %d",
1111                          en ? "enable" : "disable", ret);
1112                 return ret;
1113         }
1114
1115         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_EGU_TNL_INT_EN, false);
1116         if (en)
1117                 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN);
1118
1119         desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN_MASK);
1120
1121         ret = hns3_cmd_send(hw, &desc, 1);
1122         if (ret) {
1123                 hns3_err(hw, "fail to %s IGU-EGU TNL interrupts, ret = %d",
1124                          en ? "enable" : "disable", ret);
1125                 return ret;
1126         }
1127
1128         return hns3_config_ncsi_hw_err_int(hns, en);
1129 }
1130
1131 static int
1132 config_ppp_err_intr(struct hns3_adapter *hns, uint32_t cmd, bool en)
1133 {
1134         struct hns3_hw *hw = &hns->hw;
1135         struct hns3_cmd_desc desc[2];
1136         int ret;
1137
1138         /* configure PPP error interrupts */
1139         hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1140         desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1141         hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
1142
1143         if (cmd == HNS3_OPC_PPP_CMD0_INT_CMD) {
1144                 if (en) {
1145                         desc[0].data[0] =
1146                                 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN);
1147                         desc[0].data[1] =
1148                                 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN);
1149                         desc[0].data[4] =
1150                                 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN);
1151                 }
1152
1153                 desc[1].data[0] =
1154                         rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK);
1155                 desc[1].data[1] =
1156                         rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK);
1157                 desc[1].data[2] =
1158                         rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN_MASK);
1159         } else if (cmd == HNS3_OPC_PPP_CMD1_INT_CMD) {
1160                 if (en) {
1161                         desc[0].data[0] =
1162                                 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN);
1163                         desc[0].data[1] =
1164                                 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN);
1165                 }
1166
1167                 desc[1].data[0] =
1168                         rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK);
1169                 desc[1].data[1] =
1170                         rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK);
1171         }
1172
1173         ret = hns3_cmd_send(hw, &desc[0], 2);
1174         if (ret)
1175                 hns3_err(hw, "fail to %s PPP error int, ret = %d",
1176                 en ? "enable" : "disable", ret);
1177
1178         return ret;
1179 }
1180
1181 static int
1182 enable_ppp_err_intr(struct hns3_adapter *hns, bool en)
1183 {
1184         int ret;
1185
1186         ret = config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD0_INT_CMD, en);
1187         if (ret)
1188                 return ret;
1189
1190         return config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD1_INT_CMD, en);
1191 }
1192
1193 static int
1194 enable_ssu_err_intr(struct hns3_adapter *hns, bool en)
1195 {
1196         struct hns3_hw *hw = &hns->hw;
1197         struct hns3_cmd_desc desc[2];
1198         int ret;
1199
1200         /* configure SSU ecc error interrupts */
1201         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_ECC_INT_CMD, false);
1202         desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1203         hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_ECC_INT_CMD, false);
1204         if (en) {
1205                 desc[0].data[0] =
1206                         rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN);
1207                 desc[0].data[1] =
1208                         rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN);
1209                 desc[0].data[4] =
1210                         rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN);
1211         }
1212
1213         desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK);
1214         desc[1].data[1] =
1215                 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK);
1216         desc[1].data[2] = rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK);
1217
1218         ret = hns3_cmd_send(hw, &desc[0], 2);
1219         if (ret) {
1220                 hns3_err(hw, "fail to %s SSU ECC error interrupt, ret = %d",
1221                          en ? "enable" : "disable", ret);
1222                 return ret;
1223         }
1224
1225         /* configure SSU common error interrupts */
1226         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_COMMON_INT_CMD, false);
1227         desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1228         hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_COMMON_INT_CMD, false);
1229
1230         if (en) {
1231                 desc[0].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN);
1232                 desc[0].data[1] =
1233                         rte_cpu_to_le_32(HNS3_SSU_PORT_BASED_ERR_INT_EN);
1234                 desc[0].data[2] =
1235                         rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN);
1236         }
1237
1238         desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN_MASK |
1239                                            HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK);
1240         desc[1].data[1] =
1241                 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK);
1242
1243         ret = hns3_cmd_send(hw, &desc[0], 2);
1244         if (ret)
1245                 hns3_err(hw, "fail to %s SSU COMMON error intr, ret = %d",
1246                          en ? "enable" : "disable", ret);
1247
1248         return ret;
1249 }
1250
1251 static int
1252 config_ppu_err_intrs(struct hns3_adapter *hns, uint32_t cmd, bool en)
1253 {
1254         struct hns3_hw *hw = &hns->hw;
1255         struct hns3_cmd_desc desc[2];
1256         int num = 1;
1257
1258         /* configure PPU error interrupts */
1259         switch (cmd) {
1260         case HNS3_OPC_PPU_MPF_ECC_INT_CMD:
1261                 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1262                 desc[0].flag |= HNS3_CMD_FLAG_NEXT;
1263                 hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
1264                 if (en) {
1265                         desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN;
1266                         desc[0].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN;
1267                         desc[1].data[3] = HNS3_PPU_MPF_ABNORMAL_INT3_EN;
1268                         desc[1].data[4] = HNS3_PPU_MPF_ABNORMAL_INT2_EN;
1269                 }
1270
1271                 desc[1].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK;
1272                 desc[1].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK;
1273                 desc[1].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK;
1274                 desc[1].data[3] |= HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK;
1275                 num = 2;
1276                 break;
1277         case HNS3_OPC_PPU_MPF_OTHER_INT_CMD:
1278                 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1279                 if (en)
1280                         desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2;
1281
1282                 desc[0].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK;
1283                 break;
1284         case HNS3_OPC_PPU_PF_OTHER_INT_CMD:
1285                 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1286                 if (en)
1287                         desc[0].data[0] = HNS3_PPU_PF_ABNORMAL_INT_EN;
1288
1289                 desc[0].data[2] = HNS3_PPU_PF_ABNORMAL_INT_EN_MASK;
1290                 break;
1291         default:
1292                 hns3_err(hw,
1293                          "Invalid cmd(%u) to configure PPU error interrupts.",
1294                          cmd);
1295                 return -EINVAL;
1296         }
1297
1298         return hns3_cmd_send(hw, &desc[0], num);
1299 }
1300
1301 static int
1302 enable_ppu_err_intr(struct hns3_adapter *hns, bool en)
1303 {
1304         struct hns3_hw *hw = &hns->hw;
1305         int ret;
1306
1307         ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_MPF_ECC_INT_CMD, en);
1308         if (ret) {
1309                 hns3_err(hw, "fail to %s PPU MPF ECC error intr, ret = %d",
1310                          en ? "enable" : "disable", ret);
1311                 return ret;
1312         }
1313
1314         ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_MPF_OTHER_INT_CMD, en);
1315         if (ret) {
1316                 hns3_err(hw, "fail to %s PPU MPF other intr, ret = %d",
1317                          en ? "enable" : "disable", ret);
1318                 return ret;
1319         }
1320
1321         ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_PF_OTHER_INT_CMD, en);
1322         if (ret)
1323                 hns3_err(hw, "fail to %s PPU PF error interrupts, ret = %d",
1324                          en ? "enable" : "disable", ret);
1325         return ret;
1326 }
1327
1328 static int
1329 enable_tm_err_intr(struct hns3_adapter *hns, bool en)
1330 {
1331         struct hns3_hw *hw = &hns->hw;
1332         struct hns3_cmd_desc desc;
1333         int ret;
1334
1335         /* configure TM SCH error interrupts */
1336         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_SCH_ECC_INT_EN, false);
1337         if (en)
1338                 desc.data[0] = rte_cpu_to_le_32(HNS3_TM_SCH_ECC_ERR_INT_EN);
1339
1340         ret = hns3_cmd_send(hw, &desc, 1);
1341         if (ret) {
1342                 hns3_err(hw, "fail to %s TM SCH interrupts, ret = %d",
1343                          en ? "enable" : "disable", ret);
1344                 return ret;
1345         }
1346
1347         /* configure TM QCN hw errors */
1348         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QCN_MEM_INT_CFG, true);
1349         ret = hns3_cmd_send(hw, &desc, 1);
1350         if (ret) {
1351                 hns3_err(hw, "fail to read TM QCN CFG status, ret = %d\n", ret);
1352                 return ret;
1353         }
1354
1355         hns3_cmd_reuse_desc(&desc, false);
1356         if (en)
1357                 desc.data[1] = rte_cpu_to_le_32(HNS3_TM_QCN_MEM_ERR_INT_EN);
1358
1359         ret = hns3_cmd_send(hw, &desc, 1);
1360         if (ret)
1361                 hns3_err(hw, "fail to %s TM QCN mem errors, ret = %d\n",
1362                          en ? "enable" : "disable", ret);
1363
1364         return ret;
1365 }
1366
1367 static int
1368 enable_common_err_intr(struct hns3_adapter *hns, bool en)
1369 {
1370         struct hns3_hw *hw = &hns->hw;
1371         struct hns3_cmd_desc desc[2];
1372         int ret;
1373
1374         /* configure common error interrupts */
1375         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_COMMON_ECC_INT_CFG, false);
1376         desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1377         hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_COMMON_ECC_INT_CFG, false);
1378
1379         if (en) {
1380                 desc[0].data[0] =
1381                         rte_cpu_to_le_32(HNS3_IMP_TCM_ECC_ERR_INT_EN);
1382                 desc[0].data[2] =
1383                         rte_cpu_to_le_32(HNS3_CMDQ_NIC_ECC_ERR_INT_EN);
1384                 desc[0].data[3] =
1385                         rte_cpu_to_le_32(HNS3_IMP_RD_POISON_ERR_INT_EN);
1386                 desc[0].data[4] =
1387                         rte_cpu_to_le_32(HNS3_TQP_ECC_ERR_INT_EN |
1388                                          HNS3_MSIX_SRAM_ECC_ERR_INT_EN);
1389                 desc[0].data[5] =
1390                         rte_cpu_to_le_32(HNS3_IMP_ITCM4_ECC_ERR_INT_EN);
1391         }
1392
1393         desc[1].data[0] = rte_cpu_to_le_32(HNS3_IMP_TCM_ECC_ERR_INT_EN_MASK);
1394         desc[1].data[2] = rte_cpu_to_le_32(HNS3_CMDQ_NIC_ECC_ERR_INT_EN_MASK);
1395         desc[1].data[3] = rte_cpu_to_le_32(HNS3_IMP_RD_POISON_ERR_INT_EN_MASK);
1396         desc[1].data[4] = rte_cpu_to_le_32(HNS3_TQP_ECC_ERR_INT_EN_MASK |
1397                                       HNS3_MSIX_SRAM_ECC_ERR_INT_EN_MASK);
1398         desc[1].data[5] = rte_cpu_to_le_32(HNS3_IMP_ITCM4_ECC_ERR_INT_EN_MASK);
1399
1400         ret = hns3_cmd_send(hw, &desc[0], RTE_DIM(desc));
1401         if (ret)
1402                 hns3_err(hw, "fail to %s common err interrupts, ret = %d\n",
1403                          en ? "enable" : "disable", ret);
1404
1405         return ret;
1406 }
1407
1408 static int
1409 enable_mac_err_intr(struct hns3_adapter *hns, bool en)
1410 {
1411         struct hns3_hw *hw = &hns->hw;
1412         struct hns3_cmd_desc desc;
1413         int ret;
1414
1415         /* configure MAC common error interrupts */
1416         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_COMMON_INT_EN, false);
1417         if (en)
1418                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN);
1419
1420         desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN_MASK);
1421
1422         ret = hns3_cmd_send(hw, &desc, 1);
1423         if (ret)
1424                 hns3_err(hw, "fail to %s MAC COMMON error intr: %d",
1425                          en ? "enable" : "disable", ret);
1426
1427         return ret;
1428 }
1429
1430 static const struct hns3_hw_blk hw_blk[] = {
1431         {
1432                 .name = "IGU_EGU",
1433                 .enable_err_intr = enable_igu_egu_err_intr,
1434         },
1435         {
1436                 .name = "PPP",
1437                 .enable_err_intr = enable_ppp_err_intr,
1438         },
1439         {
1440                 .name = "SSU",
1441                 .enable_err_intr = enable_ssu_err_intr,
1442         },
1443         {
1444                 .name = "PPU",
1445                 .enable_err_intr = enable_ppu_err_intr,
1446         },
1447         {
1448                 .name = "TM",
1449                 .enable_err_intr = enable_tm_err_intr,
1450         },
1451         {
1452                 .name = "COMMON",
1453                 .enable_err_intr = enable_common_err_intr,
1454         },
1455         {
1456                 .name = "MAC",
1457                 .enable_err_intr = enable_mac_err_intr,
1458         },
1459         {
1460                 .name = NULL,
1461                 .enable_err_intr = NULL,
1462         }
1463 };
1464
1465 int
1466 hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool en)
1467 {
1468         const struct hns3_hw_blk *module = hw_blk;
1469         int ret = 0;
1470
1471         while (module->enable_err_intr) {
1472                 ret = module->enable_err_intr(hns, en);
1473                 if (ret)
1474                         return ret;
1475
1476                 module++;
1477         }
1478
1479         return ret;
1480 }
1481
1482 static enum hns3_reset_level
1483 hns3_find_highest_level(struct hns3_adapter *hns, const char *reg,
1484                         const struct hns3_hw_error *err, uint32_t err_sts)
1485 {
1486         enum hns3_reset_level reset_level = HNS3_FUNC_RESET;
1487         struct hns3_hw *hw = &hns->hw;
1488         bool need_reset = false;
1489
1490         while (err->msg) {
1491                 if (err->int_msk & err_sts) {
1492                         hns3_warn(hw, "%s %s found [error status=0x%x]",
1493                                   reg, err->msg, err_sts);
1494                         if (err->reset_level != HNS3_NONE_RESET &&
1495                             err->reset_level >= reset_level) {
1496                                 reset_level = err->reset_level;
1497                                 need_reset = true;
1498                         }
1499                         hns3_error_int_stats_add(hns, reg);
1500                 }
1501                 err++;
1502         }
1503         if (need_reset)
1504                 return reset_level;
1505         else
1506                 return HNS3_NONE_RESET;
1507 }
1508
1509 static int
1510 query_num_bds(struct hns3_hw *hw, bool is_ras, uint32_t *mpf_bd_num,
1511               uint32_t *pf_bd_num)
1512 {
1513         uint32_t mpf_min_bd_num, pf_min_bd_num;
1514         uint32_t mpf_bd_num_val, pf_bd_num_val;
1515         enum hns3_opcode_type opcode;
1516         struct hns3_cmd_desc desc;
1517         int ret;
1518
1519         if (is_ras) {
1520                 opcode = HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM;
1521                 mpf_min_bd_num = HNS3_MPF_RAS_INT_MIN_BD_NUM;
1522                 pf_min_bd_num = HNS3_PF_RAS_INT_MIN_BD_NUM;
1523         } else {
1524                 opcode = HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM;
1525                 mpf_min_bd_num = HNS3_MPF_MSIX_INT_MIN_BD_NUM;
1526                 pf_min_bd_num = HNS3_PF_MSIX_INT_MIN_BD_NUM;
1527         }
1528
1529         hns3_cmd_setup_basic_desc(&desc, opcode, true);
1530         ret = hns3_cmd_send(hw, &desc, 1);
1531         if (ret) {
1532                 hns3_err(hw, "query num bds in msix failed, ret = %d", ret);
1533                 return ret;
1534         }
1535
1536         mpf_bd_num_val = rte_le_to_cpu_32(desc.data[0]);
1537         pf_bd_num_val = rte_le_to_cpu_32(desc.data[1]);
1538         if (mpf_bd_num_val < mpf_min_bd_num || pf_bd_num_val < pf_min_bd_num) {
1539                 hns3_err(hw, "error bd num: mpf(%u), min_mpf(%u), "
1540                          "pf(%u), min_pf(%u)\n", mpf_bd_num_val, mpf_min_bd_num,
1541                          pf_bd_num_val, pf_min_bd_num);
1542                 return -EINVAL;
1543         }
1544
1545         *mpf_bd_num = mpf_bd_num_val;
1546         *pf_bd_num = pf_bd_num_val;
1547
1548         return 0;
1549 }
1550
1551 void
1552 hns3_intr_unregister(const struct rte_intr_handle *hdl,
1553                      rte_intr_callback_fn cb_fn, void *cb_arg)
1554 {
1555         int retry_cnt = 0;
1556         int ret;
1557
1558         do {
1559                 ret = rte_intr_callback_unregister(hdl, cb_fn, cb_arg);
1560                 if (ret >= 0) {
1561                         break;
1562                 } else if (ret != -EAGAIN) {
1563                         PMD_INIT_LOG(ERR, "Failed to unregister intr: %d", ret);
1564                         break;
1565                 }
1566                 rte_delay_ms(HNS3_INTR_UNREG_FAIL_DELAY_MS);
1567         } while (retry_cnt++ < HNS3_INTR_UNREG_FAIL_RETRY_CNT);
1568 }
1569
1570 static uint32_t
1571 hns3_get_hw_error_status(struct hns3_cmd_desc *desc, uint8_t desc_offset,
1572                          uint8_t data_offset)
1573 {
1574         uint32_t status;
1575         uint32_t *desc_data;
1576
1577         if (desc_offset == 0)
1578                 status = rte_le_to_cpu_32(desc[desc_offset].data[data_offset]);
1579         else {
1580                 desc_data = (uint32_t *)&desc[desc_offset];
1581                 status = rte_le_to_cpu_32(*(desc_data + data_offset));
1582         }
1583
1584         return status;
1585 }
1586
1587 static int
1588 hns3_handle_hw_error(struct hns3_adapter *hns, struct hns3_cmd_desc *desc,
1589                      int num, uint64_t *levels, enum hns3_hw_err_type err_type)
1590 {
1591         const struct hns3_hw_error_desc *err = pf_ras_err_tbl;
1592         enum hns3_opcode_type opcode;
1593         enum hns3_reset_level req_level;
1594         struct hns3_hw *hw = &hns->hw;
1595         uint32_t status;
1596         int ret;
1597
1598         switch (err_type) {
1599         case MPF_MSIX_ERR:
1600                 err = mpf_msix_err_tbl;
1601                 opcode = HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT;
1602                 break;
1603         case PF_MSIX_ERR:
1604                 err = pf_msix_err_tbl;
1605                 opcode = HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT;
1606                 break;
1607         case MPF_RAS_ERR:
1608                 err = mpf_ras_err_tbl;
1609                 opcode = HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT;
1610                 break;
1611         case PF_RAS_ERR:
1612                 err = pf_ras_err_tbl;
1613                 opcode = HNS3_OPC_QUERY_CLEAR_PF_RAS_INT;
1614                 break;
1615         default:
1616                 hns3_err(hw, "error hardware err_type = %d\n", err_type);
1617                 return -EINVAL;
1618         }
1619
1620         /* query all hardware errors */
1621         hns3_cmd_setup_basic_desc(&desc[0], opcode, true);
1622         ret = hns3_cmd_send(hw, &desc[0], num);
1623         if (ret) {
1624                 hns3_err(hw, "query hw err int 0x%x cmd failed, ret = %d\n",
1625                          opcode, ret);
1626                 return ret;
1627         }
1628
1629         /* traverses the error table and process based on the error type */
1630         while (err->msg) {
1631                 status = hns3_get_hw_error_status(desc, err->desc_offset,
1632                                                   err->data_offset);
1633                 if (status) {
1634                         /*
1635                          * set the reset_level or non_reset flag based on
1636                          * the error type and add error statistics. here just
1637                          * set the flag, the actual reset action is in
1638                          * hns3_msix_process.
1639                          */
1640                         req_level = hns3_find_highest_level(hns, err->msg,
1641                                                             err->hw_err,
1642                                                             status);
1643                         hns3_atomic_set_bit(req_level, levels);
1644                 }
1645                 err++;
1646         }
1647
1648         /* clear all hardware errors */
1649         hns3_cmd_reuse_desc(&desc[0], false);
1650         ret = hns3_cmd_send(hw, &desc[0], num);
1651         if (ret)
1652                 hns3_err(hw, "clear all hw err int cmd failed, ret = %d\n",
1653                          ret);
1654
1655         return ret;
1656 }
1657
1658 void
1659 hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels)
1660 {
1661         uint32_t mpf_bd_num, pf_bd_num, bd_num;
1662         struct hns3_hw *hw = &hns->hw;
1663         struct hns3_cmd_desc *desc;
1664         int ret;
1665
1666         /* query the number of bds for the MSIx int status */
1667         ret = query_num_bds(hw, false, &mpf_bd_num, &pf_bd_num);
1668         if (ret) {
1669                 hns3_err(hw, "fail to query msix int status bd num: ret = %d",
1670                          ret);
1671                 return;
1672         }
1673
1674         bd_num = RTE_MAX(mpf_bd_num, pf_bd_num);
1675         desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0);
1676         if (desc == NULL) {
1677                 hns3_err(hw,
1678                          "fail to zmalloc desc for handling msix error, size = %zu",
1679                          bd_num * sizeof(struct hns3_cmd_desc));
1680                 return;
1681         }
1682
1683         /* handle all main PF MSIx errors */
1684         ret = hns3_handle_hw_error(hns, desc, mpf_bd_num, levels, MPF_MSIX_ERR);
1685         if (ret) {
1686                 hns3_err(hw, "fail to handle all main pf msix errors, ret = %d",
1687                          ret);
1688                 goto out;
1689         }
1690
1691         memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc));
1692
1693         /* handle all PF MSIx errors */
1694         ret = hns3_handle_hw_error(hns, desc, pf_bd_num, levels, PF_MSIX_ERR);
1695         if (ret) {
1696                 hns3_err(hw, "fail to handle all pf msix errors, ret = %d",
1697                          ret);
1698                 goto out;
1699         }
1700
1701 out:
1702         rte_free(desc);
1703 }
1704
1705 void
1706 hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels)
1707 {
1708         uint32_t mpf_bd_num, pf_bd_num, bd_num;
1709         struct hns3_hw *hw = &hns->hw;
1710         struct hns3_cmd_desc *desc;
1711         uint32_t status;
1712         int ret;
1713
1714         status = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
1715         if ((status & HNS3_RAS_REG_NFE_MASK) == 0)
1716                 return;
1717
1718         /* query the number of bds for the RAS int status */
1719         ret = query_num_bds(hw, true, &mpf_bd_num, &pf_bd_num);
1720         if (ret) {
1721                 hns3_err(hw, "fail to query ras int status bd num: ret = %d",
1722                          ret);
1723                 return;
1724         }
1725
1726         bd_num = RTE_MAX(mpf_bd_num, pf_bd_num);
1727         desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0);
1728         if (desc == NULL) {
1729                 hns3_err(hw,
1730                          "fail to zmalloc desc for handing ras error, size = %zu",
1731                          bd_num * sizeof(struct hns3_cmd_desc));
1732                 return;
1733         }
1734
1735         /* handle all main PF RAS errors */
1736         ret = hns3_handle_hw_error(hns, desc, mpf_bd_num, levels, MPF_RAS_ERR);
1737         if (ret) {
1738                 hns3_err(hw, "fail to handle all main pf ras errors, ret = %d",
1739                          ret);
1740                 goto out;
1741         }
1742
1743         memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc));
1744
1745         /* handle all PF RAS errors */
1746         ret = hns3_handle_hw_error(hns, desc, pf_bd_num, levels, PF_RAS_ERR);
1747         if (ret) {
1748                 hns3_err(hw, "fail to handle all pf ras errors, ret = %d", ret);
1749                 goto out;
1750         }
1751
1752 out:
1753         rte_free(desc);
1754 }
1755
1756 int
1757 hns3_reset_init(struct hns3_hw *hw)
1758 {
1759         rte_spinlock_init(&hw->lock);
1760         hw->reset.level = HNS3_NONE_RESET;
1761         hw->reset.stage = RESET_STAGE_NONE;
1762         hw->reset.request = 0;
1763         hw->reset.pending = 0;
1764         rte_atomic16_init(&hw->reset.resetting);
1765         rte_atomic16_init(&hw->reset.disable_cmd);
1766         hw->reset.wait_data = rte_zmalloc("wait_data",
1767                                           sizeof(struct hns3_wait_data), 0);
1768         if (!hw->reset.wait_data) {
1769                 PMD_INIT_LOG(ERR, "Failed to allocate memory for wait_data");
1770                 return -ENOMEM;
1771         }
1772         return 0;
1773 }
1774
1775 void
1776 hns3_schedule_reset(struct hns3_adapter *hns)
1777 {
1778         struct hns3_hw *hw = &hns->hw;
1779
1780         /* Reschedule the reset process after successful initialization */
1781         if (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {
1782                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_PENDING);
1783                 return;
1784         }
1785
1786         if (hw->adapter_state >= HNS3_NIC_CLOSED)
1787                 return;
1788
1789         /* Schedule restart alarm if it is not scheduled yet */
1790         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_REQUESTED)
1791                 return;
1792         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED)
1793                 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);
1794         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
1795
1796         rte_eal_alarm_set(SWITCH_CONTEXT_US, hw->reset.ops->reset_service, hns);
1797 }
1798
1799 void
1800 hns3_schedule_delayed_reset(struct hns3_adapter *hns)
1801 {
1802 #define DEFERRED_SCHED_US (3 * MSEC_PER_SEC * USEC_PER_MSEC)
1803         struct hns3_hw *hw = &hns->hw;
1804
1805         /* Do nothing if it is uninited or closed */
1806         if (hw->adapter_state == HNS3_NIC_UNINITIALIZED ||
1807             hw->adapter_state >= HNS3_NIC_CLOSED) {
1808                 return;
1809         }
1810
1811         if (rte_atomic16_read(&hns->hw.reset.schedule) != SCHEDULE_NONE)
1812                 return;
1813         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_DEFERRED);
1814         rte_eal_alarm_set(DEFERRED_SCHED_US, hw->reset.ops->reset_service, hns);
1815 }
1816
1817 void
1818 hns3_wait_callback(void *param)
1819 {
1820         struct hns3_wait_data *data = (struct hns3_wait_data *)param;
1821         struct hns3_adapter *hns = data->hns;
1822         struct hns3_hw *hw = &hns->hw;
1823         uint64_t msec;
1824         bool done;
1825
1826         data->count--;
1827         if (data->check_completion) {
1828                 /*
1829                  * Check if the current time exceeds the deadline
1830                  * or a pending reset coming, or reset during close.
1831                  */
1832                 msec = get_timeofday_ms();
1833                 if (msec > data->end_ms || is_reset_pending(hns) ||
1834                     hw->adapter_state == HNS3_NIC_CLOSING) {
1835                         done = false;
1836                         data->count = 0;
1837                 } else
1838                         done = data->check_completion(hw);
1839         } else
1840                 done = true;
1841
1842         if (!done && data->count > 0) {
1843                 rte_eal_alarm_set(data->interval, hns3_wait_callback, data);
1844                 return;
1845         }
1846         if (done)
1847                 data->result = HNS3_WAIT_SUCCESS;
1848         else {
1849                 hns3_err(hw, "%s wait timeout at stage %d",
1850                          reset_string[hw->reset.level], hw->reset.stage);
1851                 data->result = HNS3_WAIT_TIMEOUT;
1852         }
1853         hns3_schedule_reset(hns);
1854 }
1855
1856 void
1857 hns3_notify_reset_ready(struct hns3_hw *hw, bool enable)
1858 {
1859         uint32_t reg_val;
1860
1861         reg_val = hns3_read_dev(hw, HNS3_CMDQ_TX_DEPTH_REG);
1862         if (enable)
1863                 reg_val |= HNS3_NIC_SW_RST_RDY;
1864         else
1865                 reg_val &= ~HNS3_NIC_SW_RST_RDY;
1866
1867         hns3_write_dev(hw, HNS3_CMDQ_TX_DEPTH_REG, reg_val);
1868 }
1869
1870 int
1871 hns3_reset_req_hw_reset(struct hns3_adapter *hns)
1872 {
1873         struct hns3_hw *hw = &hns->hw;
1874
1875         if (hw->reset.wait_data->result == HNS3_WAIT_UNKNOWN) {
1876                 hw->reset.wait_data->hns = hns;
1877                 hw->reset.wait_data->check_completion = NULL;
1878                 hw->reset.wait_data->interval = HNS3_RESET_SYNC_US;
1879                 hw->reset.wait_data->count = 1;
1880                 hw->reset.wait_data->result = HNS3_WAIT_REQUEST;
1881                 rte_eal_alarm_set(hw->reset.wait_data->interval,
1882                                   hns3_wait_callback, hw->reset.wait_data);
1883                 return -EAGAIN;
1884         } else if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)
1885                 return -EAGAIN;
1886
1887         /* inform hardware that preparatory work is done */
1888         hns3_notify_reset_ready(hw, true);
1889         return 0;
1890 }
1891
1892 static void
1893 hns3_clear_reset_level(struct hns3_hw *hw, uint64_t *levels)
1894 {
1895         uint64_t merge_cnt = hw->reset.stats.merge_cnt;
1896         int64_t tmp;
1897
1898         switch (hw->reset.level) {
1899         case HNS3_IMP_RESET:
1900                 hns3_atomic_clear_bit(HNS3_IMP_RESET, levels);
1901                 tmp = hns3_test_and_clear_bit(HNS3_GLOBAL_RESET, levels);
1902                 HNS3_CHECK_MERGE_CNT(tmp);
1903                 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);
1904                 HNS3_CHECK_MERGE_CNT(tmp);
1905                 break;
1906         case HNS3_GLOBAL_RESET:
1907                 hns3_atomic_clear_bit(HNS3_GLOBAL_RESET, levels);
1908                 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);
1909                 HNS3_CHECK_MERGE_CNT(tmp);
1910                 break;
1911         case HNS3_FUNC_RESET:
1912                 hns3_atomic_clear_bit(HNS3_FUNC_RESET, levels);
1913                 break;
1914         case HNS3_VF_RESET:
1915                 hns3_atomic_clear_bit(HNS3_VF_RESET, levels);
1916                 tmp = hns3_test_and_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);
1917                 HNS3_CHECK_MERGE_CNT(tmp);
1918                 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
1919                 HNS3_CHECK_MERGE_CNT(tmp);
1920                 break;
1921         case HNS3_VF_FULL_RESET:
1922                 hns3_atomic_clear_bit(HNS3_VF_FULL_RESET, levels);
1923                 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
1924                 HNS3_CHECK_MERGE_CNT(tmp);
1925                 break;
1926         case HNS3_VF_PF_FUNC_RESET:
1927                 hns3_atomic_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);
1928                 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
1929                 HNS3_CHECK_MERGE_CNT(tmp);
1930                 break;
1931         case HNS3_VF_FUNC_RESET:
1932                 hns3_atomic_clear_bit(HNS3_VF_FUNC_RESET, levels);
1933                 break;
1934         case HNS3_FLR_RESET:
1935                 hns3_atomic_clear_bit(HNS3_FLR_RESET, levels);
1936                 break;
1937         case HNS3_NONE_RESET:
1938         default:
1939                 return;
1940         };
1941         if (merge_cnt != hw->reset.stats.merge_cnt)
1942                 hns3_warn(hw,
1943                           "No need to do low-level reset after %s reset. "
1944                           "merge cnt: %" PRIx64 " total merge cnt: %" PRIx64,
1945                           reset_string[hw->reset.level],
1946                           hw->reset.stats.merge_cnt - merge_cnt,
1947                           hw->reset.stats.merge_cnt);
1948 }
1949
1950 static bool
1951 hns3_reset_err_handle(struct hns3_adapter *hns)
1952 {
1953 #define MAX_RESET_FAIL_CNT 5
1954
1955         struct hns3_hw *hw = &hns->hw;
1956
1957         if (hw->adapter_state == HNS3_NIC_CLOSING)
1958                 goto reset_fail;
1959
1960         if (is_reset_pending(hns)) {
1961                 hw->reset.attempts = 0;
1962                 hw->reset.stats.fail_cnt++;
1963                 hns3_warn(hw, "%s reset fail because new Reset is pending "
1964                               "attempts:%" PRIx64,
1965                           reset_string[hw->reset.level],
1966                           hw->reset.stats.fail_cnt);
1967                 hw->reset.level = HNS3_NONE_RESET;
1968                 return true;
1969         }
1970
1971         hw->reset.attempts++;
1972         if (hw->reset.attempts < MAX_RESET_FAIL_CNT) {
1973                 hns3_atomic_set_bit(hw->reset.level, &hw->reset.pending);
1974                 hns3_warn(hw, "%s retry to reset attempts: %d",
1975                           reset_string[hw->reset.level],
1976                           hw->reset.attempts);
1977                 return true;
1978         }
1979
1980         /*
1981          * Failure to reset does not mean that the network port is
1982          * completely unavailable, so cmd still needs to be initialized.
1983          * Regardless of whether the execution is successful or not, the
1984          * flow after execution must be continued.
1985          */
1986         if (rte_atomic16_read(&hw->reset.disable_cmd))
1987                 (void)hns3_cmd_init(hw);
1988 reset_fail:
1989         hw->reset.attempts = 0;
1990         hw->reset.stats.fail_cnt++;
1991         hns3_warn(hw, "%s reset fail fail_cnt:%" PRIx64 " success_cnt:%" PRIx64
1992                   " global_cnt:%" PRIx64 " imp_cnt:%" PRIx64
1993                   " request_cnt:%" PRIx64 " exec_cnt:%" PRIx64
1994                   " merge_cnt:%" PRIx64 "adapter_state:%d",
1995                   reset_string[hw->reset.level], hw->reset.stats.fail_cnt,
1996                   hw->reset.stats.success_cnt, hw->reset.stats.global_cnt,
1997                   hw->reset.stats.imp_cnt, hw->reset.stats.request_cnt,
1998                   hw->reset.stats.exec_cnt, hw->reset.stats.merge_cnt,
1999                   hw->adapter_state);
2000
2001         /* IMP no longer waiting the ready flag */
2002         hns3_notify_reset_ready(hw, true);
2003         return false;
2004 }
2005
2006 static int
2007 hns3_reset_pre(struct hns3_adapter *hns)
2008 {
2009         struct hns3_hw *hw = &hns->hw;
2010         struct timeval tv;
2011         int ret;
2012
2013         if (hw->reset.stage == RESET_STAGE_NONE) {
2014                 rte_atomic16_set(&hns->hw.reset.resetting, 1);
2015                 hw->reset.stage = RESET_STAGE_DOWN;
2016                 ret = hw->reset.ops->stop_service(hns);
2017                 gettimeofday(&tv, NULL);
2018                 if (ret) {
2019                         hns3_warn(hw, "Reset step1 down fail=%d time=%ld.%.6ld",
2020                                   ret, tv.tv_sec, tv.tv_usec);
2021                         return ret;
2022                 }
2023                 hns3_warn(hw, "Reset step1 down success time=%ld.%.6ld",
2024                           tv.tv_sec, tv.tv_usec);
2025                 hw->reset.stage = RESET_STAGE_PREWAIT;
2026         }
2027         if (hw->reset.stage == RESET_STAGE_PREWAIT) {
2028                 ret = hw->reset.ops->prepare_reset(hns);
2029                 gettimeofday(&tv, NULL);
2030                 if (ret) {
2031                         hns3_warn(hw,
2032                                   "Reset step2 prepare wait fail=%d time=%ld.%.6ld",
2033                                   ret, tv.tv_sec, tv.tv_usec);
2034                         return ret;
2035                 }
2036                 hns3_warn(hw, "Reset step2 prepare wait success time=%ld.%.6ld",
2037                           tv.tv_sec, tv.tv_usec);
2038                 hw->reset.stage = RESET_STAGE_REQ_HW_RESET;
2039                 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;
2040         }
2041         return 0;
2042 }
2043
2044 static int
2045 hns3_reset_post(struct hns3_adapter *hns)
2046 {
2047 #define TIMEOUT_RETRIES_CNT     5
2048         struct hns3_hw *hw = &hns->hw;
2049         struct timeval tv_delta;
2050         struct timeval tv;
2051         int ret = 0;
2052
2053         if (hw->adapter_state == HNS3_NIC_CLOSING) {
2054                 hns3_warn(hw, "Don't do reset_post during closing, just uninit cmd");
2055                 hns3_cmd_uninit(hw);
2056                 return -EPERM;
2057         }
2058
2059         if (hw->reset.stage == RESET_STAGE_DEV_INIT) {
2060                 rte_spinlock_lock(&hw->lock);
2061                 if (hw->reset.mbuf_deferred_free) {
2062                         hns3_dev_release_mbufs(hns);
2063                         hw->reset.mbuf_deferred_free = false;
2064                 }
2065                 ret = hw->reset.ops->reinit_dev(hns);
2066                 rte_spinlock_unlock(&hw->lock);
2067                 gettimeofday(&tv, NULL);
2068                 if (ret) {
2069                         hns3_warn(hw, "Reset step5 devinit fail=%d retries=%d",
2070                                   ret, hw->reset.retries);
2071                         goto err;
2072                 }
2073                 hns3_warn(hw, "Reset step5 devinit success time=%ld.%.6ld",
2074                           tv.tv_sec, tv.tv_usec);
2075                 hw->reset.retries = 0;
2076                 hw->reset.stage = RESET_STAGE_RESTORE;
2077                 rte_eal_alarm_set(SWITCH_CONTEXT_US,
2078                                   hw->reset.ops->reset_service, hns);
2079                 return -EAGAIN;
2080         }
2081         if (hw->reset.stage == RESET_STAGE_RESTORE) {
2082                 rte_spinlock_lock(&hw->lock);
2083                 ret = hw->reset.ops->restore_conf(hns);
2084                 rte_spinlock_unlock(&hw->lock);
2085                 gettimeofday(&tv, NULL);
2086                 if (ret) {
2087                         hns3_warn(hw,
2088                                   "Reset step6 restore fail=%d retries=%d",
2089                                   ret, hw->reset.retries);
2090                         goto err;
2091                 }
2092                 hns3_warn(hw, "Reset step6 restore success time=%ld.%.6ld",
2093                           tv.tv_sec, tv.tv_usec);
2094                 hw->reset.retries = 0;
2095                 hw->reset.stage = RESET_STAGE_DONE;
2096         }
2097         if (hw->reset.stage == RESET_STAGE_DONE) {
2098                 /* IMP will wait ready flag before reset */
2099                 hns3_notify_reset_ready(hw, false);
2100                 hns3_clear_reset_level(hw, &hw->reset.pending);
2101                 rte_atomic16_clear(&hns->hw.reset.resetting);
2102                 hw->reset.attempts = 0;
2103                 hw->reset.stats.success_cnt++;
2104                 hw->reset.stage = RESET_STAGE_NONE;
2105                 rte_spinlock_lock(&hw->lock);
2106                 hw->reset.ops->start_service(hns);
2107                 rte_spinlock_unlock(&hw->lock);
2108                 gettimeofday(&tv, NULL);
2109                 timersub(&tv, &hw->reset.start_time, &tv_delta);
2110                 hns3_warn(hw, "%s reset done fail_cnt:%" PRIx64
2111                           " success_cnt:%" PRIx64 " global_cnt:%" PRIx64
2112                           " imp_cnt:%" PRIx64 " request_cnt:%" PRIx64
2113                           " exec_cnt:%" PRIx64 " merge_cnt:%" PRIx64,
2114                           reset_string[hw->reset.level],
2115                           hw->reset.stats.fail_cnt, hw->reset.stats.success_cnt,
2116                           hw->reset.stats.global_cnt, hw->reset.stats.imp_cnt,
2117                           hw->reset.stats.request_cnt, hw->reset.stats.exec_cnt,
2118                           hw->reset.stats.merge_cnt);
2119                 hns3_warn(hw,
2120                           "%s reset done delta %ld ms time=%ld.%.6ld",
2121                           reset_string[hw->reset.level],
2122                           tv_delta.tv_sec * MSEC_PER_SEC +
2123                           tv_delta.tv_usec / USEC_PER_MSEC,
2124                           tv.tv_sec, tv.tv_usec);
2125                 hw->reset.level = HNS3_NONE_RESET;
2126         }
2127         return 0;
2128
2129 err:
2130         if (ret == -ETIME) {
2131                 hw->reset.retries++;
2132                 if (hw->reset.retries < TIMEOUT_RETRIES_CNT) {
2133                         rte_eal_alarm_set(HNS3_RESET_SYNC_US,
2134                                           hw->reset.ops->reset_service, hns);
2135                         return -EAGAIN;
2136                 }
2137         }
2138         hw->reset.retries = 0;
2139         return -EIO;
2140 }
2141
2142 /*
2143  * There are three scenarios as follows:
2144  * When the reset is not in progress, the reset process starts.
2145  * During the reset process, if the reset level has not changed,
2146  * the reset process continues; otherwise, the reset process is aborted.
2147  *      hw->reset.level   new_level          action
2148  *      HNS3_NONE_RESET  HNS3_XXXX_RESET    start reset
2149  *      HNS3_XXXX_RESET  HNS3_XXXX_RESET    continue reset
2150  *      HNS3_LOW_RESET   HNS3_HIGH_RESET    abort
2151  */
2152 int
2153 hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level)
2154 {
2155         struct hns3_hw *hw = &hns->hw;
2156         struct timeval tv_delta;
2157         struct timeval tv;
2158         int ret;
2159
2160         if (hw->reset.level == HNS3_NONE_RESET) {
2161                 hw->reset.level = new_level;
2162                 hw->reset.stats.exec_cnt++;
2163                 gettimeofday(&hw->reset.start_time, NULL);
2164                 hns3_warn(hw, "Start %s reset time=%ld.%.6ld",
2165                           reset_string[hw->reset.level],
2166                           hw->reset.start_time.tv_sec,
2167                           hw->reset.start_time.tv_usec);
2168         }
2169
2170         if (is_reset_pending(hns)) {
2171                 gettimeofday(&tv, NULL);
2172                 hns3_warn(hw,
2173                           "%s reset is aborted by high level time=%ld.%.6ld",
2174                           reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);
2175                 if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)
2176                         rte_eal_alarm_cancel(hns3_wait_callback,
2177                                              hw->reset.wait_data);
2178                 goto err;
2179         }
2180
2181         ret = hns3_reset_pre(hns);
2182         if (ret)
2183                 goto err;
2184
2185         if (hw->reset.stage == RESET_STAGE_REQ_HW_RESET) {
2186                 ret = hns3_reset_req_hw_reset(hns);
2187                 if (ret == -EAGAIN)
2188                         return ret;
2189                 gettimeofday(&tv, NULL);
2190                 hns3_warn(hw,
2191                           "Reset step3 request IMP reset success time=%ld.%.6ld",
2192                           tv.tv_sec, tv.tv_usec);
2193                 hw->reset.stage = RESET_STAGE_WAIT;
2194                 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;
2195         }
2196         if (hw->reset.stage == RESET_STAGE_WAIT) {
2197                 ret = hw->reset.ops->wait_hardware_ready(hns);
2198                 if (ret)
2199                         goto retry;
2200                 gettimeofday(&tv, NULL);
2201                 hns3_warn(hw, "Reset step4 reset wait success time=%ld.%.6ld",
2202                           tv.tv_sec, tv.tv_usec);
2203                 hw->reset.stage = RESET_STAGE_DEV_INIT;
2204         }
2205
2206         ret = hns3_reset_post(hns);
2207         if (ret)
2208                 goto retry;
2209
2210         return 0;
2211 retry:
2212         if (ret == -EAGAIN)
2213                 return ret;
2214 err:
2215         hns3_clear_reset_level(hw, &hw->reset.pending);
2216         if (hns3_reset_err_handle(hns)) {
2217                 hw->reset.stage = RESET_STAGE_PREWAIT;
2218                 hns3_schedule_reset(hns);
2219         } else {
2220                 rte_spinlock_lock(&hw->lock);
2221                 if (hw->reset.mbuf_deferred_free) {
2222                         hns3_dev_release_mbufs(hns);
2223                         hw->reset.mbuf_deferred_free = false;
2224                 }
2225                 rte_spinlock_unlock(&hw->lock);
2226                 rte_atomic16_clear(&hns->hw.reset.resetting);
2227                 hw->reset.stage = RESET_STAGE_NONE;
2228                 gettimeofday(&tv, NULL);
2229                 timersub(&tv, &hw->reset.start_time, &tv_delta);
2230                 hns3_warn(hw, "%s reset fail delta %ld ms time=%ld.%.6ld",
2231                           reset_string[hw->reset.level],
2232                           tv_delta.tv_sec * MSEC_PER_SEC +
2233                           tv_delta.tv_usec / USEC_PER_MSEC,
2234                           tv.tv_sec, tv.tv_usec);
2235                 hw->reset.level = HNS3_NONE_RESET;
2236         }
2237
2238         return -EIO;
2239 }
2240
2241 /*
2242  * The reset process can only be terminated after handshake with IMP(step3),
2243  * so that IMP can complete the reset process normally.
2244  */
2245 void
2246 hns3_reset_abort(struct hns3_adapter *hns)
2247 {
2248         struct hns3_hw *hw = &hns->hw;
2249         struct timeval tv;
2250         int i;
2251
2252         for (i = 0; i < HNS3_QUIT_RESET_CNT; i++) {
2253                 if (hw->reset.level == HNS3_NONE_RESET)
2254                         break;
2255                 rte_delay_ms(HNS3_QUIT_RESET_DELAY_MS);
2256         }
2257
2258         /* IMP no longer waiting the ready flag */
2259         hns3_notify_reset_ready(hw, true);
2260
2261         rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);
2262         rte_eal_alarm_cancel(hns3_wait_callback, hw->reset.wait_data);
2263
2264         if (hw->reset.level != HNS3_NONE_RESET) {
2265                 gettimeofday(&tv, NULL);
2266                 hns3_err(hw, "Failed to terminate reset: %s time=%ld.%.6ld",
2267                          reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);
2268         }
2269 }