1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
8 #define HNS3_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF
9 #define HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF
10 #define HNS3_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF
11 #define HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF
12 #define HNS3_PPP_PF_ERR_INT_EN 0x0003
13 #define HNS3_PPP_PF_ERR_INT_EN_MASK 0x0003
14 #define HNS3_PPP_MPF_ECC_ERR_INT2_EN 0x003F
15 #define HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F
16 #define HNS3_PPP_MPF_ECC_ERR_INT3_EN 0x003F
17 #define HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F
19 #define HNS3_MAC_COMMON_ERR_INT_EN 0x107FF
20 #define HNS3_MAC_COMMON_ERR_INT_EN_MASK 0x107FF
22 #define HNS3_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
23 #define HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
24 #define HNS3_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
25 #define HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0)
26 #define HNS3_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF
27 #define HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF
28 #define HNS3_PPU_MPF_ABNORMAL_INT2_EN2 0xB
29 #define HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB
30 #define HNS3_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)
31 #define HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)
32 #define HNS3_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
33 #define HNS3_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
34 #define HNS3_PPU_PF_INT_MSIX_MASK 0x27
35 #define HNS3_PPU_MPF_INT_ST2_MSIX_MASK GENMASK(29, 28)
37 #define HNS3_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)
38 #define HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
39 #define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0)
40 #define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
41 #define HNS3_SSU_BIT32_ECC_ERR_INT_EN 0x0101
42 #define HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101
43 #define HNS3_SSU_COMMON_INT_EN GENMASK(9, 0)
44 #define HNS3_SSU_COMMON_INT_EN_MASK GENMASK(9, 0)
45 #define HNS3_SSU_PORT_BASED_ERR_INT_EN 0x0BFF
46 #define HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000
47 #define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0)
48 #define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)
49 #define HNS3_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0)
50 #define HNS3_SSU_PORT_INT_MSIX_MASK 0x7BFF
52 #define HNS3_RESET_PROCESS_MS 200
56 int (*enable_err_intr)(struct hns3_adapter *hns, bool en);
59 struct hns3_hw_error {
62 enum hns3_reset_level reset_level;
65 int hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool state);
66 void hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels);
67 void hns3_intr_unregister(const struct rte_intr_handle *hdl,
68 rte_intr_callback_fn cb_fn, void *cb_arg);
69 void hns3_notify_reset_ready(struct hns3_hw *hw, bool enable);
70 int hns3_reset_init(struct hns3_hw *hw);
71 void hns3_wait_callback(void *param);
72 void hns3_schedule_reset(struct hns3_adapter *hns);
73 void hns3_schedule_delayed_reset(struct hns3_adapter *hns);
74 int hns3_reset_req_hw_reset(struct hns3_adapter *hns);
75 int hns3_reset_process(struct hns3_adapter *hns,
76 enum hns3_reset_level reset_level);
77 void hns3_reset_abort(struct hns3_adapter *hns);
79 #endif /* _HNS3_INTR_H_ */