1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #include <ethdev_driver.h>
8 #include "hns3_ethdev.h"
10 #include "hns3_logs.h"
11 #include "hns3_intr.h"
12 #include "hns3_rxtx.h"
14 #define HNS3_CMD_CODE_OFFSET 2
16 static const struct errno_respcode_map err_code_map[] = {
30 hns3_resp_to_errno(uint16_t resp_code)
34 num = sizeof(err_code_map) / sizeof(struct errno_respcode_map);
35 for (i = 0; i < num; i++) {
36 if (err_code_map[i].resp_code == resp_code)
37 return err_code_map[i].err_no;
44 hns3_get_mbx_resp(struct hns3_hw *hw, uint16_t code0, uint16_t code1,
45 uint8_t *resp_data, uint16_t resp_len)
47 #define HNS3_MAX_RETRY_MS 500
48 #define HNS3_WAIT_RESP_US 100
49 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
50 struct hns3_mbx_resp_status *mbx_resp;
54 if (resp_len > HNS3_MBX_MAX_RESP_DATA_SIZE) {
55 hns3_err(hw, "VF mbx response len(=%u) exceeds maximum(=%d)",
56 resp_len, HNS3_MBX_MAX_RESP_DATA_SIZE);
60 now = get_timeofday_ms();
61 end = now + HNS3_MAX_RETRY_MS;
62 while ((hw->mbx_resp.head != hw->mbx_resp.tail + hw->mbx_resp.lost) &&
64 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) {
65 hns3_err(hw, "Don't wait for mbx respone because of "
70 if (is_reset_pending(hns)) {
71 hw->mbx_resp.req_msg_data = 0;
72 hns3_err(hw, "Don't wait for mbx respone because of "
77 hns3_dev_handle_mbx_msg(hw);
78 rte_delay_us(HNS3_WAIT_RESP_US);
80 now = get_timeofday_ms();
82 hw->mbx_resp.req_msg_data = 0;
86 "VF could not get mbx(%u,%u) head(%u) tail(%u) "
88 code0, code1, hw->mbx_resp.head, hw->mbx_resp.tail,
93 mbx_resp = &hw->mbx_resp;
95 if (mbx_resp->resp_status)
96 return mbx_resp->resp_status;
99 memcpy(resp_data, &mbx_resp->additional_info[0], resp_len);
105 hns3_send_mbx_msg(struct hns3_hw *hw, uint16_t code, uint16_t subcode,
106 const uint8_t *msg_data, uint8_t msg_len, bool need_resp,
107 uint8_t *resp_data, uint16_t resp_len)
109 struct hns3_mbx_vf_to_pf_cmd *req;
110 struct hns3_cmd_desc desc;
111 bool is_ring_vector_msg;
115 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
117 /* first two bytes are reserved for code & subcode */
118 if (msg_len > (HNS3_MBX_MAX_MSG_SIZE - HNS3_CMD_CODE_OFFSET)) {
120 "VF send mbx msg fail, msg len %u exceeds max payload len %d",
121 msg_len, HNS3_MBX_MAX_MSG_SIZE - HNS3_CMD_CODE_OFFSET);
125 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
127 is_ring_vector_msg = (code == HNS3_MBX_MAP_RING_TO_VECTOR) ||
128 (code == HNS3_MBX_UNMAP_RING_TO_VECTOR) ||
129 (code == HNS3_MBX_GET_RING_VECTOR_MAP);
130 if (!is_ring_vector_msg)
131 req->msg[1] = subcode;
133 offset = is_ring_vector_msg ? 1 : HNS3_CMD_CODE_OFFSET;
134 memcpy(&req->msg[offset], msg_data, msg_len);
137 /* synchronous send */
139 req->mbx_need_resp |= HNS3_MBX_NEED_RESP_BIT;
140 rte_spinlock_lock(&hw->mbx_resp.lock);
141 hw->mbx_resp.req_msg_data = (uint32_t)code << 16 | subcode;
143 ret = hns3_cmd_send(hw, &desc, 1);
145 rte_spinlock_unlock(&hw->mbx_resp.lock);
146 hns3_err(hw, "VF failed(=%d) to send mbx message to PF",
151 ret = hns3_get_mbx_resp(hw, code, subcode, resp_data, resp_len);
152 rte_spinlock_unlock(&hw->mbx_resp.lock);
154 /* asynchronous send */
155 ret = hns3_cmd_send(hw, &desc, 1);
157 hns3_err(hw, "VF failed(=%d) to send mbx message to PF",
167 hns3_cmd_crq_empty(struct hns3_hw *hw)
169 uint32_t tail = hns3_read_dev(hw, HNS3_CMDQ_RX_TAIL_REG);
171 return tail == hw->cmq.crq.next_to_use;
175 hns3_mbx_handler(struct hns3_hw *hw)
177 enum hns3_reset_level reset_level;
178 uint8_t link_status, link_duplex;
186 /* process all the async queue messages */
187 while (tail != hw->arq.head) {
188 msg_q = hw->arq.msg_q[hw->arq.head];
190 opcode = msg_q[0] & 0xff;
192 case HNS3_MBX_LINK_STAT_CHANGE:
193 memcpy(&link_speed, &msg_q[2], sizeof(link_speed));
194 link_status = rte_le_to_cpu_16(msg_q[1]);
195 link_duplex = (uint8_t)rte_le_to_cpu_16(msg_q[4]);
196 hns3vf_update_link_status(hw, link_status, link_speed,
199 case HNS3_MBX_ASSERTING_RESET:
200 /* PF has asserted reset hence VF should go in pending
201 * state and poll for the hardware reset status till it
202 * has been completely reset. After this stack should
203 * eventually be re-initialized.
205 reset_level = rte_le_to_cpu_16(msg_q[1]);
206 hns3_atomic_set_bit(reset_level, &hw->reset.pending);
208 hns3_warn(hw, "PF inform reset level %d", reset_level);
209 hw->reset.stats.request_cnt++;
210 hns3_schedule_reset(HNS3_DEV_HW_TO_ADAPTER(hw));
213 hns3_err(hw, "Fetched unsupported(%u) message from arq",
218 hns3_mbx_head_ptr_move_arq(hw->arq);
219 msg_q = hw->arq.msg_q[hw->arq.head];
224 * Case1: receive response after timeout, req_msg_data
225 * is 0, not equal resp_msg, do lost--
226 * Case2: receive last response during new send_mbx_msg,
227 * req_msg_data is different with resp_msg, let
228 * lost--, continue to wait for response.
231 hns3_update_resp_position(struct hns3_hw *hw, uint32_t resp_msg)
233 struct hns3_mbx_resp_status *resp = &hw->mbx_resp;
234 uint32_t tail = resp->tail + 1;
236 if (tail > resp->head)
238 if (resp->req_msg_data != resp_msg) {
241 hns3_warn(hw, "Received a mismatched response req_msg(%x) "
242 "resp_msg(%x) head(%u) tail(%u) lost(%u)",
243 resp->req_msg_data, resp_msg, resp->head, tail,
245 } else if (tail + resp->lost > resp->head) {
247 hns3_warn(hw, "Received a new response again resp_msg(%x) "
248 "head(%u) tail(%u) lost(%u)", resp_msg,
249 resp->head, tail, resp->lost);
256 hns3_link_fail_parse(struct hns3_hw *hw, uint8_t link_fail_code)
258 switch (link_fail_code) {
259 case HNS3_MBX_LF_NORMAL:
261 case HNS3_MBX_LF_REF_CLOCK_LOST:
262 hns3_warn(hw, "Reference clock lost!");
264 case HNS3_MBX_LF_XSFP_TX_DISABLE:
265 hns3_warn(hw, "SFP tx is disabled!");
267 case HNS3_MBX_LF_XSFP_ABSENT:
268 hns3_warn(hw, "SFP is absent!");
271 hns3_warn(hw, "Unknown fail code:%u!", link_fail_code);
277 hns3_handle_link_change_event(struct hns3_hw *hw,
278 struct hns3_mbx_pf_to_vf_cmd *req)
280 #define LINK_STATUS_OFFSET 1
281 #define LINK_FAIL_CODE_OFFSET 2
283 if (!req->msg[LINK_STATUS_OFFSET])
284 hns3_link_fail_parse(hw, req->msg[LINK_FAIL_CODE_OFFSET]);
286 hns3_update_link_status_and_event(hw);
290 hns3_update_port_base_vlan_info(struct hns3_hw *hw,
291 struct hns3_mbx_pf_to_vf_cmd *req)
293 #define PVID_STATE_OFFSET 1
294 uint16_t new_pvid_state = req->msg[PVID_STATE_OFFSET] ?
295 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
297 * Currently, hardware doesn't support more than two layers VLAN offload
298 * based on hns3 network engine, which would cause packets loss or wrong
299 * packets for these types of packets. If the hns3 PF kernel ethdev
300 * driver sets the PVID for VF device after initialization of the
301 * related VF device, the PF driver will notify VF driver to update the
302 * PVID configuration state. The VF driver will update the PVID
303 * configuration state immediately to ensure that the VLAN process in Tx
304 * and Rx is correct. But in the window period of this state transition,
305 * packets loss or packets with wrong VLAN may occur.
307 if (hw->port_base_vlan_cfg.state != new_pvid_state) {
308 hw->port_base_vlan_cfg.state = new_pvid_state;
309 hns3_update_all_queues_pvid_proc_en(hw);
314 hns3_handle_promisc_info(struct hns3_hw *hw, uint16_t promisc_en)
318 * When promisc/allmulti mode is closed by the hns3 PF kernel
319 * ethdev driver for untrusted, modify VF's related status.
321 hns3_warn(hw, "Promisc mode will be closed by host for being "
323 hw->data->promiscuous = 0;
324 hw->data->all_multicast = 0;
329 hns3_dev_handle_mbx_msg(struct hns3_hw *hw)
331 struct hns3_mbx_resp_status *resp = &hw->mbx_resp;
332 struct hns3_cmq_ring *crq = &hw->cmq.crq;
333 struct hns3_mbx_pf_to_vf_cmd *req;
334 struct hns3_cmd_desc *desc;
342 rte_spinlock_lock(&hw->cmq.crq.lock);
344 while (!hns3_cmd_crq_empty(hw)) {
345 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) {
346 rte_spinlock_unlock(&hw->cmq.crq.lock);
350 desc = &crq->desc[crq->next_to_use];
351 req = (struct hns3_mbx_pf_to_vf_cmd *)desc->data;
352 opcode = req->msg[0] & 0xff;
354 flag = rte_le_to_cpu_16(crq->desc[crq->next_to_use].flag);
355 if (unlikely(!hns3_get_bit(flag, HNS3_CMDQ_RX_OUTVLD_B))) {
357 "dropped invalid mailbox message, code = %u",
360 /* dropping/not processing this invalid message */
361 crq->desc[crq->next_to_use].flag = 0;
362 hns3_mbx_ring_ptr_move_crq(crq);
367 case HNS3_MBX_PF_VF_RESP:
368 resp->resp_status = hns3_resp_to_errno(req->msg[3]);
370 temp = (uint8_t *)&req->msg[4];
371 for (i = 0; i < HNS3_MBX_MAX_RESP_DATA_SIZE; i++) {
372 resp->additional_info[i] = *temp;
375 msg_data = (uint32_t)req->msg[1] << 16 | req->msg[2];
376 hns3_update_resp_position(hw, msg_data);
378 case HNS3_MBX_LINK_STAT_CHANGE:
379 case HNS3_MBX_ASSERTING_RESET:
380 msg_q = hw->arq.msg_q[hw->arq.tail];
381 memcpy(&msg_q[0], req->msg,
382 HNS3_MBX_MAX_ARQ_MSG_SIZE * sizeof(uint16_t));
383 hns3_mbx_tail_ptr_move_arq(hw->arq);
385 hns3_mbx_handler(hw);
387 case HNS3_MBX_PUSH_LINK_STATUS:
388 hns3_handle_link_change_event(hw, req);
390 case HNS3_MBX_PUSH_VLAN_INFO:
392 * When the PVID configuration status of VF device is
393 * changed by the hns3 PF kernel driver, VF driver will
394 * receive this mailbox message from PF driver.
396 hns3_update_port_base_vlan_info(hw, req);
398 case HNS3_MBX_PUSH_PROMISC_INFO:
400 * When the trust status of VF device changed by the
401 * hns3 PF kernel driver, VF driver will receive this
402 * mailbox message from PF driver.
404 hns3_handle_promisc_info(hw, req->msg[1]);
408 "VF received unsupported(%u) mbx msg from PF",
413 crq->desc[crq->next_to_use].flag = 0;
414 hns3_mbx_ring_ptr_move_crq(crq);
417 /* Write back CMDQ_RQ header pointer, IMP need this pointer */
418 hns3_write_dev(hw, HNS3_CMDQ_RX_HEAD_REG, crq->next_to_use);
420 rte_spinlock_unlock(&hw->cmq.crq.lock);