1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #include <rte_ethdev_pci.h>
8 #include "hns3_ethdev.h"
10 #include "hns3_rxtx.h"
11 #include "hns3_regs.h"
13 #define MAX_SEPARATE_NUM 4
14 #define SEPARATOR_VALUE 0xFFFFFFFF
15 #define REG_NUM_PER_LINE 4
16 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(uint32_t))
18 static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_ADDR_L_REG,
19 HNS3_CMDQ_TX_ADDR_H_REG,
20 HNS3_CMDQ_TX_DEPTH_REG,
21 HNS3_CMDQ_TX_TAIL_REG,
22 HNS3_CMDQ_TX_HEAD_REG,
23 HNS3_CMDQ_RX_ADDR_L_REG,
24 HNS3_CMDQ_RX_ADDR_H_REG,
25 HNS3_CMDQ_RX_DEPTH_REG,
26 HNS3_CMDQ_RX_TAIL_REG,
27 HNS3_CMDQ_RX_HEAD_REG,
28 HNS3_VECTOR0_CMDQ_SRC_REG,
29 HNS3_CMDQ_INTR_STS_REG,
30 HNS3_CMDQ_INTR_EN_REG,
31 HNS3_CMDQ_INTR_GEN_REG};
33 static const uint32_t common_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
34 HNS3_VECTOR0_OTER_EN_REG,
35 HNS3_MISC_RESET_STS_REG,
36 HNS3_VECTOR0_OTHER_INT_STS_REG,
37 HNS3_GLOBAL_RESET_REG,
41 static const uint32_t common_vf_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
45 static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BASEADDR_L_REG,
46 HNS3_RING_RX_BASEADDR_H_REG,
47 HNS3_RING_RX_BD_NUM_REG,
48 HNS3_RING_RX_BD_LEN_REG,
50 HNS3_RING_RX_MERGE_EN_REG,
51 HNS3_RING_RX_TAIL_REG,
52 HNS3_RING_RX_HEAD_REG,
53 HNS3_RING_RX_FBDNUM_REG,
54 HNS3_RING_RX_OFFSET_REG,
55 HNS3_RING_RX_FBD_OFFSET_REG,
56 HNS3_RING_RX_STASH_REG,
57 HNS3_RING_RX_BD_ERR_REG,
58 HNS3_RING_TX_BASEADDR_L_REG,
59 HNS3_RING_TX_BASEADDR_H_REG,
60 HNS3_RING_TX_BD_NUM_REG,
62 HNS3_RING_TX_PRIORITY_REG,
64 HNS3_RING_TX_MERGE_EN_REG,
65 HNS3_RING_TX_TAIL_REG,
66 HNS3_RING_TX_HEAD_REG,
67 HNS3_RING_TX_FBDNUM_REG,
68 HNS3_RING_TX_OFFSET_REG,
69 HNS3_RING_TX_EBD_NUM_REG,
70 HNS3_RING_TX_EBD_OFFSET_REG,
71 HNS3_RING_TX_BD_ERR_REG,
74 static const uint32_t tqp_intr_reg_addrs[] = {HNS3_TQP_INTR_CTRL_REG,
75 HNS3_TQP_INTR_GL0_REG,
76 HNS3_TQP_INTR_GL1_REG,
77 HNS3_TQP_INTR_GL2_REG,
78 HNS3_TQP_INTR_RL_REG};
81 hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,
82 uint32_t *regs_num_64_bit)
84 struct hns3_cmd_desc desc;
87 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_REG_NUM, true);
88 ret = hns3_cmd_send(hw, &desc, 1);
90 hns3_err(hw, "Query register number cmd failed, ret = %d",
95 *regs_num_32_bit = rte_le_to_cpu_32(desc.data[0]);
96 *regs_num_64_bit = rte_le_to_cpu_32(desc.data[1]);
102 hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)
104 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
105 uint32_t cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
106 uint32_t regs_num_32_bit, regs_num_64_bit;
110 cmdq_lines = sizeof(cmdq_reg_addrs) / REG_LEN_PER_LINE + 1;
113 sizeof(common_vf_reg_addrs) / REG_LEN_PER_LINE + 1;
115 common_lines = sizeof(common_reg_addrs) / REG_LEN_PER_LINE + 1;
116 ring_lines = sizeof(ring_reg_addrs) / REG_LEN_PER_LINE + 1;
117 tqp_intr_lines = sizeof(tqp_intr_reg_addrs) / REG_LEN_PER_LINE + 1;
119 len = (cmdq_lines + common_lines + ring_lines * hw->tqps_num +
120 tqp_intr_lines * hw->num_msi) * REG_LEN_PER_LINE;
123 ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit);
125 hns3_err(hw, "Get register number failed, ret = %d.",
129 len += regs_num_32_bit * sizeof(uint32_t) +
130 regs_num_64_bit * sizeof(uint64_t);
138 hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)
140 #define HNS3_32_BIT_REG_RTN_DATANUM 8
141 #define HNS3_32_BIT_DESC_NODATA_LEN 2
142 struct hns3_cmd_desc *desc;
143 uint32_t *reg_val = data;
152 cmd_num = DIV_ROUND_UP(regs_num + HNS3_32_BIT_DESC_NODATA_LEN,
153 HNS3_32_BIT_REG_RTN_DATANUM);
154 desc = rte_zmalloc("hns3-32bit-regs",
155 sizeof(struct hns3_cmd_desc) * cmd_num, 0);
157 hns3_err(hw, "Failed to allocate %zx bytes needed to "
159 sizeof(struct hns3_cmd_desc) * cmd_num);
163 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_32_BIT_REG, true);
164 ret = hns3_cmd_send(hw, desc, cmd_num);
166 hns3_err(hw, "Query 32 bit register cmd failed, ret = %d",
172 for (i = 0; i < cmd_num; i++) {
174 desc_data = &desc[i].data[0];
175 n = HNS3_32_BIT_REG_RTN_DATANUM -
176 HNS3_32_BIT_DESC_NODATA_LEN;
178 desc_data = (uint32_t *)(&desc[i]);
179 n = HNS3_32_BIT_REG_RTN_DATANUM;
181 for (k = 0; k < n; k++) {
182 *reg_val++ = rte_le_to_cpu_32(*desc_data++);
195 hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)
197 #define HNS3_64_BIT_REG_RTN_DATANUM 4
198 #define HNS3_64_BIT_DESC_NODATA_LEN 1
199 struct hns3_cmd_desc *desc;
200 uint64_t *reg_val = data;
209 cmd_num = DIV_ROUND_UP(regs_num + HNS3_64_BIT_DESC_NODATA_LEN,
210 HNS3_64_BIT_REG_RTN_DATANUM);
211 desc = rte_zmalloc("hns3-64bit-regs",
212 sizeof(struct hns3_cmd_desc) * cmd_num, 0);
214 hns3_err(hw, "Failed to allocate %zx bytes needed to "
216 sizeof(struct hns3_cmd_desc) * cmd_num);
220 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_64_BIT_REG, true);
221 ret = hns3_cmd_send(hw, desc, cmd_num);
223 hns3_err(hw, "Query 64 bit register cmd failed, ret = %d",
229 for (i = 0; i < cmd_num; i++) {
231 desc_data = (uint64_t *)(&desc[i].data[0]);
232 n = HNS3_64_BIT_REG_RTN_DATANUM -
233 HNS3_64_BIT_DESC_NODATA_LEN;
235 desc_data = (uint64_t *)(&desc[i]);
236 n = HNS3_64_BIT_REG_RTN_DATANUM;
238 for (k = 0; k < n; k++) {
239 *reg_val++ = rte_le_to_cpu_64(*desc_data++);
252 hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data)
254 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
260 /* fetching per-PF registers values from PF PCIe register space */
261 reg_um = sizeof(cmdq_reg_addrs) / sizeof(uint32_t);
262 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
263 for (i = 0; i < reg_um; i++)
264 *data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]);
265 for (i = 0; i < separator_num; i++)
266 *data++ = SEPARATOR_VALUE;
269 reg_um = sizeof(common_vf_reg_addrs) / sizeof(uint32_t);
271 reg_um = sizeof(common_reg_addrs) / sizeof(uint32_t);
272 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
273 for (i = 0; i < reg_um; i++)
275 *data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]);
277 *data++ = hns3_read_dev(hw, common_reg_addrs[i]);
278 for (i = 0; i < separator_num; i++)
279 *data++ = SEPARATOR_VALUE;
281 reg_um = sizeof(ring_reg_addrs) / sizeof(uint32_t);
282 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
283 for (j = 0; j < hw->tqps_num; j++) {
284 reg_offset = hns3_get_tqp_reg_offset(j);
285 for (i = 0; i < reg_um; i++)
286 *data++ = hns3_read_dev(hw,
287 ring_reg_addrs[i] + reg_offset);
288 for (i = 0; i < separator_num; i++)
289 *data++ = SEPARATOR_VALUE;
292 reg_um = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t);
293 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
294 for (j = 0; j < hw->num_msi; j++) {
295 reg_offset = HNS3_TQP_INTR_REG_SIZE * j;
296 for (i = 0; i < reg_um; i++)
297 *data++ = hns3_read_dev(hw,
298 tqp_intr_reg_addrs[i] +
300 for (i = 0; i < separator_num; i++)
301 *data++ = SEPARATOR_VALUE;
306 hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
308 struct hns3_adapter *hns = eth_dev->data->dev_private;
309 struct hns3_hw *hw = &hns->hw;
310 uint32_t regs_num_32_bit;
311 uint32_t regs_num_64_bit;
317 hns3_err(hw, "the input parameter regs is NULL!");
321 ret = hns3_get_regs_length(hw, &length);
327 regs->length = length;
328 regs->width = sizeof(uint32_t);
332 /* Only full register dump is supported */
333 if (regs->length && regs->length != length)
336 /* fetching per-PF registers values from PF PCIe register space */
337 hns3_direct_access_regs(hw, data);
342 ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit);
344 hns3_err(hw, "Get register number failed, ret = %d", ret);
348 /* fetching PF common registers values from firmware */
349 ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data);
351 hns3_err(hw, "Get 32 bit register failed, ret = %d", ret);
355 data += regs_num_32_bit;
356 ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data);
358 hns3_err(hw, "Get 64 bit register failed, ret = %d", ret);