drivers/net/hns3/hns3_regs.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <rte_ethdev_pci.h>
   6 #include <rte_io.h>
   7
   8 #include "hns3_ethdev.h"
   9 #include "hns3_logs.h"
  10 #include "hns3_rxtx.h"
  11 #include "hns3_regs.h"
  12
  13 #define MAX_SEPARATE_NUM        4
  14 #define SEPARATOR_VALUE         0xFFFFFFFF
  15 #define REG_NUM_PER_LINE        4
  16 #define REG_LEN_PER_LINE        (REG_NUM_PER_LINE * sizeof(uint32_t))
  17
  18 static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_ADDR_L_REG,
  19                                           HNS3_CMDQ_TX_ADDR_H_REG,
  20                                           HNS3_CMDQ_TX_DEPTH_REG,
  21                                           HNS3_CMDQ_TX_TAIL_REG,
  22                                           HNS3_CMDQ_TX_HEAD_REG,
  23                                           HNS3_CMDQ_RX_ADDR_L_REG,
  24                                           HNS3_CMDQ_RX_ADDR_H_REG,
  25                                           HNS3_CMDQ_RX_DEPTH_REG,
  26                                           HNS3_CMDQ_RX_TAIL_REG,
  27                                           HNS3_CMDQ_RX_HEAD_REG,
  28                                           HNS3_VECTOR0_CMDQ_SRC_REG,
  29                                           HNS3_CMDQ_INTR_STS_REG,
  30                                           HNS3_CMDQ_INTR_EN_REG,
  31                                           HNS3_CMDQ_INTR_GEN_REG};
  32
  33 static const uint32_t common_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
  34                                             HNS3_VECTOR0_OTER_EN_REG,
  35                                             HNS3_MISC_RESET_STS_REG,
  36                                             HNS3_VECTOR0_OTHER_INT_STS_REG,
  37                                             HNS3_GLOBAL_RESET_REG,
  38                                             HNS3_FUN_RST_ING,
  39                                             HNS3_GRO_EN_REG};
  40
  41 static const uint32_t common_vf_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
  42                                                HNS3_FUN_RST_ING,
  43                                                HNS3_GRO_EN_REG};
  44
  45 static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BASEADDR_L_REG,
  46                                           HNS3_RING_RX_BASEADDR_H_REG,
  47                                           HNS3_RING_RX_BD_NUM_REG,
  48                                           HNS3_RING_RX_BD_LEN_REG,
  49                                           HNS3_RING_RX_EN_REG,
  50                                           HNS3_RING_RX_MERGE_EN_REG,
  51                                           HNS3_RING_RX_TAIL_REG,
  52                                           HNS3_RING_RX_HEAD_REG,
  53                                           HNS3_RING_RX_FBDNUM_REG,
  54                                           HNS3_RING_RX_OFFSET_REG,
  55                                           HNS3_RING_RX_FBD_OFFSET_REG,
  56                                           HNS3_RING_RX_STASH_REG,
  57                                           HNS3_RING_RX_BD_ERR_REG,
  58                                           HNS3_RING_TX_BASEADDR_L_REG,
  59                                           HNS3_RING_TX_BASEADDR_H_REG,
  60                                           HNS3_RING_TX_BD_NUM_REG,
  61                                           HNS3_RING_TX_EN_REG,
  62                                           HNS3_RING_TX_PRIORITY_REG,
  63                                           HNS3_RING_TX_TC_REG,
  64                                           HNS3_RING_TX_MERGE_EN_REG,
  65                                           HNS3_RING_TX_TAIL_REG,
  66                                           HNS3_RING_TX_HEAD_REG,
  67                                           HNS3_RING_TX_FBDNUM_REG,
  68                                           HNS3_RING_TX_OFFSET_REG,
  69                                           HNS3_RING_TX_EBD_NUM_REG,
  70                                           HNS3_RING_TX_EBD_OFFSET_REG,
  71                                           HNS3_RING_TX_BD_ERR_REG,
  72                                           HNS3_RING_EN_REG};
  73
  74 static const uint32_t tqp_intr_reg_addrs[] = {HNS3_TQP_INTR_CTRL_REG,
  75                                               HNS3_TQP_INTR_GL0_REG,
  76                                               HNS3_TQP_INTR_GL1_REG,
  77                                               HNS3_TQP_INTR_GL2_REG,
  78                                               HNS3_TQP_INTR_RL_REG};
  79
  80 static int
  81 hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,
  82                   uint32_t *regs_num_64_bit)
  83 {
  84         struct hns3_cmd_desc desc;
  85         int ret;
  86
  87         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_REG_NUM, true);
  88         ret = hns3_cmd_send(hw, &desc, 1);
  89         if (ret) {
  90                 hns3_err(hw, "Query register number cmd failed, ret = %d",
  91                          ret);
  92                 return ret;
  93         }
  94
  95         *regs_num_32_bit = rte_le_to_cpu_32(desc.data[0]);
  96         *regs_num_64_bit = rte_le_to_cpu_32(desc.data[1]);
  97
  98         return 0;
  99 }
 100
 101 static int
 102 hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)
 103 {
 104         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 105         uint32_t cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
 106         uint32_t regs_num_32_bit, regs_num_64_bit;
 107         uint32_t len;
 108         int ret;
 109
 110         cmdq_lines = sizeof(cmdq_reg_addrs) / REG_LEN_PER_LINE + 1;
 111         if (hns->is_vf)
 112                 common_lines =
 113                         sizeof(common_vf_reg_addrs) / REG_LEN_PER_LINE + 1;
 114         else
 115                 common_lines = sizeof(common_reg_addrs) / REG_LEN_PER_LINE + 1;
 116         ring_lines = sizeof(ring_reg_addrs) / REG_LEN_PER_LINE + 1;
 117         tqp_intr_lines = sizeof(tqp_intr_reg_addrs) / REG_LEN_PER_LINE + 1;
 118
 119         len = (cmdq_lines + common_lines + ring_lines * hw->tqps_num +
 120               tqp_intr_lines * hw->num_msi) * REG_LEN_PER_LINE;
 121
 122         if (!hns->is_vf) {
 123                 ret = hns3_get_regs_num(hw, &regs_num_32_bit, &regs_num_64_bit);
 124                 if (ret) {
 125                         hns3_err(hw, "Get register number failed, ret = %d.",
 126                                  ret);
 127                         return -ENOTSUP;
 128                 }
 129                 len += regs_num_32_bit * sizeof(uint32_t) +
 130                        regs_num_64_bit * sizeof(uint64_t);
 131         }
 132
 133         *length = len;
 134         return 0;
 135 }
 136
 137 static int
 138 hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)
 139 {
 140 #define HNS3_32_BIT_REG_RTN_DATANUM 8
 141 #define HNS3_32_BIT_DESC_NODATA_LEN 2
 142         struct hns3_cmd_desc *desc;
 143         uint32_t *reg_val = data;
 144         uint32_t *desc_data;
 145         int cmd_num;
 146         int i, k, n;
 147         int ret;
 148
 149         if (regs_num == 0)
 150                 return 0;
 151
 152         cmd_num = DIV_ROUND_UP(regs_num + HNS3_32_BIT_DESC_NODATA_LEN,
 153                                HNS3_32_BIT_REG_RTN_DATANUM);
 154         desc = rte_zmalloc("hns3-32bit-regs",
 155                            sizeof(struct hns3_cmd_desc) * cmd_num, 0);
 156         if (desc == NULL) {
 157                 hns3_err(hw, "Failed to allocate %zx bytes needed to "
 158                          "store 32bit regs",
 159                          sizeof(struct hns3_cmd_desc) * cmd_num);
 160                 return -ENOMEM;
 161         }
 162
 163         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_32_BIT_REG, true);
 164         ret = hns3_cmd_send(hw, desc, cmd_num);
 165         if (ret) {
 166                 hns3_err(hw, "Query 32 bit register cmd failed, ret = %d",
 167                          ret);
 168                 rte_free(desc);
 169                 return ret;
 170         }
 171
 172         for (i = 0; i < cmd_num; i++) {
 173                 if (i == 0) {
 174                         desc_data = &desc[i].data[0];
 175                         n = HNS3_32_BIT_REG_RTN_DATANUM -
 176                             HNS3_32_BIT_DESC_NODATA_LEN;
 177                 } else {
 178                         desc_data = (uint32_t *)(&desc[i]);
 179                         n = HNS3_32_BIT_REG_RTN_DATANUM;
 180                 }
 181                 for (k = 0; k < n; k++) {
 182                         *reg_val++ = rte_le_to_cpu_32(*desc_data++);
 183
 184                         regs_num--;
 185                         if (regs_num == 0)
 186                                 break;
 187                 }
 188         }
 189
 190         rte_free(desc);
 191         return 0;
 192 }
 193
 194 static int
 195 hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)
 196 {
 197 #define HNS3_64_BIT_REG_RTN_DATANUM 4
 198 #define HNS3_64_BIT_DESC_NODATA_LEN 1
 199         struct hns3_cmd_desc *desc;
 200         uint64_t *reg_val = data;
 201         uint64_t *desc_data;
 202         int cmd_num;
 203         int i, k, n;
 204         int ret;
 205
 206         if (regs_num == 0)
 207                 return 0;
 208
 209         cmd_num = DIV_ROUND_UP(regs_num + HNS3_64_BIT_DESC_NODATA_LEN,
 210                                HNS3_64_BIT_REG_RTN_DATANUM);
 211         desc = rte_zmalloc("hns3-64bit-regs",
 212                            sizeof(struct hns3_cmd_desc) * cmd_num, 0);
 213         if (desc == NULL) {
 214                 hns3_err(hw, "Failed to allocate %zx bytes needed to "
 215                          "store 64bit regs",
 216                          sizeof(struct hns3_cmd_desc) * cmd_num);
 217                 return -ENOMEM;
 218         }
 219
 220         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_64_BIT_REG, true);
 221         ret = hns3_cmd_send(hw, desc, cmd_num);
 222         if (ret) {
 223                 hns3_err(hw, "Query 64 bit register cmd failed, ret = %d",
 224                          ret);
 225                 rte_free(desc);
 226                 return ret;
 227         }
 228
 229         for (i = 0; i < cmd_num; i++) {
 230                 if (i == 0) {
 231                         desc_data = (uint64_t *)(&desc[i].data[0]);
 232                         n = HNS3_64_BIT_REG_RTN_DATANUM -
 233                             HNS3_64_BIT_DESC_NODATA_LEN;
 234                 } else {
 235                         desc_data = (uint64_t *)(&desc[i]);
 236                         n = HNS3_64_BIT_REG_RTN_DATANUM;
 237                 }
 238                 for (k = 0; k < n; k++) {
 239                         *reg_val++ = rte_le_to_cpu_64(*desc_data++);
 240
 241                         regs_num--;
 242                         if (!regs_num)
 243                                 break;
 244                 }
 245         }
 246
 247         rte_free(desc);
 248         return 0;
 249 }
 250
 251 static void
 252 hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data)
 253 {
 254         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 255         uint32_t reg_offset;
 256         int separator_num;
 257         int reg_um;
 258         int i, j;
 259
 260         /* fetching per-PF registers values from PF PCIe register space */
 261         reg_um = sizeof(cmdq_reg_addrs) / sizeof(uint32_t);
 262         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 263         for (i = 0; i < reg_um; i++)
 264                 *data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]);
 265         for (i = 0; i < separator_num; i++)
 266                 *data++ = SEPARATOR_VALUE;
 267
 268         if (hns->is_vf)
 269                 reg_um = sizeof(common_vf_reg_addrs) / sizeof(uint32_t);
 270         else
 271                 reg_um = sizeof(common_reg_addrs) / sizeof(uint32_t);
 272         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 273         for (i = 0; i < reg_um; i++)
 274                 if (hns->is_vf)
 275                         *data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]);
 276                 else
 277                         *data++ = hns3_read_dev(hw, common_reg_addrs[i]);
 278         for (i = 0; i < separator_num; i++)
 279                 *data++ = SEPARATOR_VALUE;
 280
 281         reg_um = sizeof(ring_reg_addrs) / sizeof(uint32_t);
 282         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 283         for (j = 0; j < hw->tqps_num; j++) {
 284                 reg_offset = hns3_get_tqp_reg_offset(j);
 285                 for (i = 0; i < reg_um; i++)
 286                         *data++ = hns3_read_dev(hw,
 287                                                 ring_reg_addrs[i] + reg_offset);
 288                 for (i = 0; i < separator_num; i++)
 289                         *data++ = SEPARATOR_VALUE;
 290         }
 291
 292         reg_um = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t);
 293         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 294         for (j = 0; j < hw->num_msi; j++) {
 295                 reg_offset = HNS3_TQP_INTR_REG_SIZE * j;
 296                 for (i = 0; i < reg_um; i++)
 297                         *data++ = hns3_read_dev(hw,
 298                                                 tqp_intr_reg_addrs[i] +
 299                                                 reg_offset);
 300                 for (i = 0; i < separator_num; i++)
 301                         *data++ = SEPARATOR_VALUE;
 302         }
 303 }
 304
 305 int
 306 hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
 307 {
 308         struct hns3_adapter *hns = eth_dev->data->dev_private;
 309         struct hns3_hw *hw = &hns->hw;
 310         uint32_t regs_num_32_bit;
 311         uint32_t regs_num_64_bit;
 312         uint32_t length;
 313         uint32_t *data;
 314         int ret;
 315
 316         if (regs == NULL) {
 317                 hns3_err(hw, "the input parameter regs is NULL!");
 318                 return -EINVAL;
 319         }
 320
 321         ret = hns3_get_regs_length(hw, &length);
 322         if (ret)
 323                 return ret;
 324
 325         data = regs->data;
 326         if (data == NULL) {
 327                 regs->length = length;
 328                 regs->width = sizeof(uint32_t);
 329                 return 0;
 330         }
 331
 332         /* Only full register dump is supported */
 333         if (regs->length && regs->length != length)
 334                 return -ENOTSUP;
 335
 336         /* fetching per-PF registers values from PF PCIe register space */
 337         hns3_direct_access_regs(hw, data);
 338
 339         if (hns->is_vf)
 340                 return 0;
 341
 342         ret = hns3_get_regs_num(hw, &regs_num_32_bit, &regs_num_64_bit);
 343         if (ret) {
 344                 hns3_err(hw, "Get register number failed, ret = %d", ret);
 345                 return ret;
 346         }
 347
 348         /* fetching PF common registers values from firmware */
 349         ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data);
 350         if (ret) {
 351                 hns3_err(hw, "Get 32 bit register failed, ret = %d", ret);
 352                 return ret;
 353         }
 354
 355         data += regs_num_32_bit;
 356         ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data);
 357         if (ret)
 358                 hns3_err(hw, "Get 64 bit register failed, ret = %d", ret);
 359
 360         return ret;
 361 }