1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
8 /* bar registers for cmdq */
9 #define HNS3_CMDQ_TX_ADDR_L_REG 0x27000
10 #define HNS3_CMDQ_TX_ADDR_H_REG 0x27004
11 #define HNS3_CMDQ_TX_DEPTH_REG 0x27008
12 #define HNS3_CMDQ_TX_TAIL_REG 0x27010
13 #define HNS3_CMDQ_TX_HEAD_REG 0x27014
14 #define HNS3_CMDQ_RX_ADDR_L_REG 0x27018
15 #define HNS3_CMDQ_RX_ADDR_H_REG 0x2701c
16 #define HNS3_CMDQ_RX_DEPTH_REG 0x27020
17 #define HNS3_CMDQ_RX_TAIL_REG 0x27024
18 #define HNS3_CMDQ_RX_HEAD_REG 0x27028
19 #define HNS3_CMDQ_INTR_STS_REG 0x27104
20 #define HNS3_CMDQ_INTR_EN_REG 0x27108
21 #define HNS3_CMDQ_INTR_GEN_REG 0x2710C
23 /* Vector0 interrupt CMDQ event source register(RW) */
24 #define HNS3_VECTOR0_CMDQ_SRC_REG 0x27100
25 /* Vector0 interrupt CMDQ event status register(RO) */
26 #define HNS3_VECTOR0_CMDQ_STAT_REG 0x27104
28 #define HNS3_VECTOR0_OTHER_INT_STS_REG 0x20800
30 #define HNS3_RAS_PF_OTHER_INT_STS_REG 0x20B00
31 #define HNS3_RAS_REG_NFE_MASK 0xFF00
33 #define HNS3_MISC_VECTOR_REG_BASE 0x20400
34 #define HNS3_VECTOR0_OTER_EN_REG 0x20600
35 #define HNS3_MISC_RESET_STS_REG 0x20700
36 #define HNS3_GLOBAL_RESET_REG 0x20A00
37 #define HNS3_FUN_RST_ING 0x20C00
38 #define HNS3_GRO_EN_REG 0x28000
40 #define HNS3_RPU_DROP_CNT_REG 0x28004
41 #define HNS3_RXD_ADV_LAYOUT_EN_REG 0x28008
43 /* Vector0 register bits for reset */
44 #define HNS3_VECTOR0_FUNCRESET_INT_B 0
45 #define HNS3_VECTOR0_GLOBALRESET_INT_B 5
46 #define HNS3_VECTOR0_CORERESET_INT_B 6
47 #define HNS3_VECTOR0_IMPRESET_INT_B 7
49 /* CMDQ register bits for RX event(=MBX event) */
50 #define HNS3_VECTOR0_RX_CMDQ_INT_B 1
51 #define HNS3_VECTOR0_REG_MSIX_MASK 0x1FF00
52 /* RST register bits for RESET event */
53 #define HNS3_VECTOR0_RST_INT_B 2
55 #define HNS3_VF_RST_ING 0x07008
56 #define HNS3_VF_RST_ING_BIT BIT(16)
58 /* bar registers for rcb */
59 #define HNS3_RING_RX_BASEADDR_L_REG 0x00000
60 #define HNS3_RING_RX_BASEADDR_H_REG 0x00004
61 #define HNS3_RING_RX_BD_NUM_REG 0x00008
62 #define HNS3_RING_RX_BD_LEN_REG 0x0000C
63 #define HNS3_RING_RX_MERGE_EN_REG 0x00014
64 #define HNS3_RING_RX_TAIL_REG 0x00018
65 #define HNS3_RING_RX_HEAD_REG 0x0001C
66 #define HNS3_RING_RX_FBDNUM_REG 0x00020
67 #define HNS3_RING_RX_OFFSET_REG 0x00024
68 #define HNS3_RING_RX_FBD_OFFSET_REG 0x00028
69 #define HNS3_RING_RX_PKTNUM_RECORD_REG 0x0002C
70 #define HNS3_RING_RX_STASH_REG 0x00030
71 #define HNS3_RING_RX_BD_ERR_REG 0x00034
73 #define HNS3_RING_TX_BASEADDR_L_REG 0x00040
74 #define HNS3_RING_TX_BASEADDR_H_REG 0x00044
75 #define HNS3_RING_TX_BD_NUM_REG 0x00048
76 #define HNS3_RING_TX_PRIORITY_REG 0x0004C
77 #define HNS3_RING_TX_TC_REG 0x00050
78 #define HNS3_RING_TX_MERGE_EN_REG 0x00054
79 #define HNS3_RING_TX_TAIL_REG 0x00058
80 #define HNS3_RING_TX_HEAD_REG 0x0005C
81 #define HNS3_RING_TX_FBDNUM_REG 0x00060
82 #define HNS3_RING_TX_OFFSET_REG 0x00064
83 #define HNS3_RING_TX_EBD_NUM_REG 0x00068
84 #define HNS3_RING_TX_PKTNUM_RECORD_REG 0x0006C
85 #define HNS3_RING_TX_EBD_OFFSET_REG 0x00070
86 #define HNS3_RING_TX_BD_ERR_REG 0x00074
88 #define HNS3_RING_EN_REG 0x00090
89 #define HNS3_RING_RX_EN_REG 0x00098
90 #define HNS3_RING_TX_EN_REG 0x000d4
92 #define HNS3_RING_EN_B 0
94 #define HNS3_TQP_REG_OFFSET 0x80000
95 #define HNS3_TQP_REG_SIZE 0x200
97 #define HNS3_TQP_EXT_REG_OFFSET 0x100
98 #define HNS3_MIN_EXTEND_QUEUE_ID 1024
100 /* bar registers for tqp interrupt */
101 #define HNS3_TQP_INTR_REG_BASE 0x20000
102 #define HNS3_TQP_INTR_EXT_REG_BASE 0x30000
103 #define HNS3_TQP_INTR_CTRL_REG 0
104 #define HNS3_TQP_INTR_GL0_REG 0x100
105 #define HNS3_TQP_INTR_GL1_REG 0x200
106 #define HNS3_TQP_INTR_GL2_REG 0x300
107 #define HNS3_TQP_INTR_RL_REG 0x900
108 #define HNS3_TQP_INTR_TX_QL_REG 0xe00
109 #define HNS3_TQP_INTR_RX_QL_REG 0xf00
110 #define HNS3_TQP_INTR_RL_EN_B 6
112 #define HNS3_MIN_EXT_TQP_INTR_ID 64
113 #define HNS3_TQP_INTR_LOW_ORDER_OFFSET 0x4
114 #define HNS3_TQP_INTR_HIGH_ORDER_OFFSET 0x1000
116 #define HNS3_TQP_INTR_GL_MAX 0x1FE0
117 #define HNS3_TQP_INTR_GL_DEFAULT 20
118 #define HNS3_TQP_INTR_GL_UNIT_1US BIT(31)
119 #define HNS3_TQP_INTR_RL_MAX 0xEC
120 #define HNS3_TQP_INTR_RL_ENABLE_MASK 0x40
121 #define HNS3_TQP_INTR_RL_DEFAULT 0
122 #define HNS3_TQP_INTR_QL_DEFAULT 0
124 /* Register bit for 1588 event */
125 #define HNS3_VECTOR0_1588_INT_B 0
127 #define HNS3_PTP_BASE_ADDRESS 0x29000
129 #define HNS3_TX_1588_SEQID_BACK (HNS3_PTP_BASE_ADDRESS + 0x0)
130 #define HNS3_TX_1588_TSP_BACK_0 (HNS3_PTP_BASE_ADDRESS + 0x4)
131 #define HNS3_TX_1588_TSP_BACK_1 (HNS3_PTP_BASE_ADDRESS + 0x8)
132 #define HNS3_TX_1588_TSP_BACK_2 (HNS3_PTP_BASE_ADDRESS + 0xc)
134 #define HNS3_TX_1588_BACK_TSP_CNT (HNS3_PTP_BASE_ADDRESS + 0x30)
136 #define HNS3_CFG_TIME_SYNC_H (HNS3_PTP_BASE_ADDRESS + 0x50)
137 #define HNS3_CFG_TIME_SYNC_M (HNS3_PTP_BASE_ADDRESS + 0x54)
138 #define HNS3_CFG_TIME_SYNC_L (HNS3_PTP_BASE_ADDRESS + 0x58)
139 #define HNS3_CFG_TIME_SYNC_RDY (HNS3_PTP_BASE_ADDRESS + 0x5c)
141 #define HNS3_CFG_TIME_CYC_EN (HNS3_PTP_BASE_ADDRESS + 0x70)
143 #define HNS3_CURR_TIME_OUT_H (HNS3_PTP_BASE_ADDRESS + 0x74)
144 #define HNS3_CURR_TIME_OUT_L (HNS3_PTP_BASE_ADDRESS + 0x78)
145 #define HNS3_CURR_TIME_OUT_NS (HNS3_PTP_BASE_ADDRESS + 0x7c)
147 /* gl_usec convert to hardware count, as writing each 1 represents 2us */
148 #define HNS3_GL_USEC_TO_REG(gl_usec) ((gl_usec) >> 1)
149 /* rl_usec convert to hardware count, as writing each 1 represents 4us */
150 #define HNS3_RL_USEC_TO_REG(rl_usec) ((rl_usec) >> 2)
152 int hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs);
153 #endif /* _HNS3_REGS_H_ */