1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #include <rte_bus_pci.h>
6 #include <rte_common.h>
7 #include <rte_cycles.h>
8 #include <rte_geneve.h>
10 #include <ethdev_driver.h>
13 #include <rte_malloc.h>
14 #if defined(RTE_ARCH_ARM64)
15 #include <rte_cpuflags.h>
19 #include "hns3_common.h"
20 #include "hns3_rxtx.h"
21 #include "hns3_regs.h"
22 #include "hns3_logs.h"
25 #define HNS3_CFG_DESC_NUM(num) ((num) / 8 - 1)
26 #define HNS3_RX_RING_PREFETCTH_MASK 3
29 hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq)
33 /* Note: Fake rx queue will not enter here */
34 if (rxq->sw_ring == NULL)
37 if (rxq->rx_rearm_nb == 0) {
38 for (i = 0; i < rxq->nb_rx_desc; i++) {
39 if (rxq->sw_ring[i].mbuf != NULL) {
40 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
41 rxq->sw_ring[i].mbuf = NULL;
45 for (i = rxq->next_to_use;
46 i != rxq->rx_rearm_start;
47 i = (i + 1) % rxq->nb_rx_desc) {
48 if (rxq->sw_ring[i].mbuf != NULL) {
49 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
50 rxq->sw_ring[i].mbuf = NULL;
55 for (i = 0; i < rxq->bulk_mbuf_num; i++)
56 rte_pktmbuf_free_seg(rxq->bulk_mbuf[i]);
57 rxq->bulk_mbuf_num = 0;
59 if (rxq->pkt_first_seg) {
60 rte_pktmbuf_free(rxq->pkt_first_seg);
61 rxq->pkt_first_seg = NULL;
66 hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq)
70 /* Note: Fake tx queue will not enter here */
72 for (i = 0; i < txq->nb_tx_desc; i++) {
73 if (txq->sw_ring[i].mbuf) {
74 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
75 txq->sw_ring[i].mbuf = NULL;
82 hns3_rx_queue_release(void *queue)
84 struct hns3_rx_queue *rxq = queue;
86 hns3_rx_queue_release_mbufs(rxq);
88 rte_memzone_free(rxq->mz);
89 rte_free(rxq->sw_ring);
95 hns3_tx_queue_release(void *queue)
97 struct hns3_tx_queue *txq = queue;
99 hns3_tx_queue_release_mbufs(txq);
101 rte_memzone_free(txq->mz);
102 rte_free(txq->sw_ring);
109 hns3_rx_queue_release_lock(void *queue)
111 struct hns3_rx_queue *rxq = queue;
112 struct hns3_adapter *hns;
118 rte_spinlock_lock(&hns->hw.lock);
119 hns3_rx_queue_release(queue);
120 rte_spinlock_unlock(&hns->hw.lock);
124 hns3_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t queue_id)
126 hns3_rx_queue_release_lock(dev->data->rx_queues[queue_id]);
130 hns3_tx_queue_release_lock(void *queue)
132 struct hns3_tx_queue *txq = queue;
133 struct hns3_adapter *hns;
139 rte_spinlock_lock(&hns->hw.lock);
140 hns3_tx_queue_release(queue);
141 rte_spinlock_unlock(&hns->hw.lock);
145 hns3_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t queue_id)
147 hns3_tx_queue_release_lock(dev->data->tx_queues[queue_id]);
151 hns3_fake_rx_queue_release(struct hns3_rx_queue *queue)
153 struct hns3_rx_queue *rxq = queue;
154 struct hns3_adapter *hns;
164 if (hw->fkq_data.rx_queues[idx]) {
165 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
166 hw->fkq_data.rx_queues[idx] = NULL;
169 /* free fake rx queue arrays */
170 if (idx == (hw->fkq_data.nb_fake_rx_queues - 1)) {
171 hw->fkq_data.nb_fake_rx_queues = 0;
172 rte_free(hw->fkq_data.rx_queues);
173 hw->fkq_data.rx_queues = NULL;
178 hns3_fake_tx_queue_release(struct hns3_tx_queue *queue)
180 struct hns3_tx_queue *txq = queue;
181 struct hns3_adapter *hns;
191 if (hw->fkq_data.tx_queues[idx]) {
192 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
193 hw->fkq_data.tx_queues[idx] = NULL;
196 /* free fake tx queue arrays */
197 if (idx == (hw->fkq_data.nb_fake_tx_queues - 1)) {
198 hw->fkq_data.nb_fake_tx_queues = 0;
199 rte_free(hw->fkq_data.tx_queues);
200 hw->fkq_data.tx_queues = NULL;
205 hns3_free_rx_queues(struct rte_eth_dev *dev)
207 struct hns3_adapter *hns = dev->data->dev_private;
208 struct hns3_fake_queue_data *fkq_data;
209 struct hns3_hw *hw = &hns->hw;
213 nb_rx_q = hw->data->nb_rx_queues;
214 for (i = 0; i < nb_rx_q; i++) {
215 if (dev->data->rx_queues[i]) {
216 hns3_rx_queue_release(dev->data->rx_queues[i]);
217 dev->data->rx_queues[i] = NULL;
221 /* Free fake Rx queues */
222 fkq_data = &hw->fkq_data;
223 for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) {
224 if (fkq_data->rx_queues[i])
225 hns3_fake_rx_queue_release(fkq_data->rx_queues[i]);
230 hns3_free_tx_queues(struct rte_eth_dev *dev)
232 struct hns3_adapter *hns = dev->data->dev_private;
233 struct hns3_fake_queue_data *fkq_data;
234 struct hns3_hw *hw = &hns->hw;
238 nb_tx_q = hw->data->nb_tx_queues;
239 for (i = 0; i < nb_tx_q; i++) {
240 if (dev->data->tx_queues[i]) {
241 hns3_tx_queue_release(dev->data->tx_queues[i]);
242 dev->data->tx_queues[i] = NULL;
246 /* Free fake Tx queues */
247 fkq_data = &hw->fkq_data;
248 for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) {
249 if (fkq_data->tx_queues[i])
250 hns3_fake_tx_queue_release(fkq_data->tx_queues[i]);
255 hns3_free_all_queues(struct rte_eth_dev *dev)
257 hns3_free_rx_queues(dev);
258 hns3_free_tx_queues(dev);
262 hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq)
264 struct rte_mbuf *mbuf;
268 for (i = 0; i < rxq->nb_rx_desc; i++) {
269 mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
270 if (unlikely(mbuf == NULL)) {
271 hns3_err(hw, "Failed to allocate RXD[%u] for rx queue!",
273 hns3_rx_queue_release_mbufs(rxq);
277 rte_mbuf_refcnt_set(mbuf, 1);
279 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
281 mbuf->port = rxq->port_id;
283 rxq->sw_ring[i].mbuf = mbuf;
284 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
285 rxq->rx_ring[i].addr = dma_addr;
286 rxq->rx_ring[i].rx.bd_base_info = 0;
293 hns3_buf_size2type(uint32_t buf_size)
299 bd_size_type = HNS3_BD_SIZE_512_TYPE;
302 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
305 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
308 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
315 hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)
317 uint32_t rx_buf_len = rxq->rx_buf_len;
318 uint64_t dma_addr = rxq->rx_ring_phys_addr;
320 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);
321 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,
322 (uint32_t)(dma_addr >> 32));
324 hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,
325 hns3_buf_size2type(rx_buf_len));
326 hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG,
327 HNS3_CFG_DESC_NUM(rxq->nb_rx_desc));
331 hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)
333 uint64_t dma_addr = txq->tx_ring_phys_addr;
335 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);
336 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,
337 (uint32_t)(dma_addr >> 32));
339 hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,
340 HNS3_CFG_DESC_NUM(txq->nb_tx_desc));
344 hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw)
346 uint16_t nb_rx_q = hw->data->nb_rx_queues;
347 uint16_t nb_tx_q = hw->data->nb_tx_queues;
348 struct hns3_rx_queue *rxq;
349 struct hns3_tx_queue *txq;
353 pvid_en = hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE;
354 for (i = 0; i < hw->cfg_max_queues; i++) {
356 rxq = hw->data->rx_queues[i];
358 rxq->pvid_sw_discard_en = pvid_en;
361 txq = hw->data->tx_queues[i];
363 txq->pvid_sw_shift_en = pvid_en;
369 hns3_stop_unused_queue(void *tqp_base, enum hns3_ring_type queue_type)
374 reg_offset = queue_type == HNS3_RING_TYPE_TX ?
375 HNS3_RING_TX_EN_REG : HNS3_RING_RX_EN_REG;
376 reg = hns3_read_reg(tqp_base, reg_offset);
377 reg &= ~BIT(HNS3_RING_EN_B);
378 hns3_write_reg(tqp_base, reg_offset, reg);
382 hns3_enable_all_queues(struct hns3_hw *hw, bool en)
384 uint16_t nb_rx_q = hw->data->nb_rx_queues;
385 uint16_t nb_tx_q = hw->data->nb_tx_queues;
386 struct hns3_rx_queue *rxq;
387 struct hns3_tx_queue *txq;
392 for (i = 0; i < hw->cfg_max_queues; i++) {
393 if (hns3_dev_get_support(hw, INDEP_TXRX)) {
394 rxq = i < nb_rx_q ? hw->data->rx_queues[i] : NULL;
395 txq = i < nb_tx_q ? hw->data->tx_queues[i] : NULL;
397 tqp_base = (void *)((char *)hw->io_base +
398 hns3_get_tqp_reg_offset(i));
400 * If queue struct is not initialized, it means the
401 * related HW ring has not been initialized yet.
402 * So, these queues should be disabled before enable
403 * the tqps to avoid a HW exception since the queues
404 * are enabled by default.
407 hns3_stop_unused_queue(tqp_base,
410 hns3_stop_unused_queue(tqp_base,
413 rxq = i < nb_rx_q ? hw->data->rx_queues[i] :
414 hw->fkq_data.rx_queues[i - nb_rx_q];
416 tqp_base = rxq->io_base;
419 * This is the master switch that used to control the enabling
420 * of a pair of Tx and Rx queues. Both the Rx and Tx point to
423 rcb_reg = hns3_read_reg(tqp_base, HNS3_RING_EN_REG);
425 rcb_reg |= BIT(HNS3_RING_EN_B);
427 rcb_reg &= ~BIT(HNS3_RING_EN_B);
428 hns3_write_reg(tqp_base, HNS3_RING_EN_REG, rcb_reg);
433 hns3_enable_txq(struct hns3_tx_queue *txq, bool en)
435 struct hns3_hw *hw = &txq->hns->hw;
438 if (hns3_dev_get_support(hw, INDEP_TXRX)) {
439 reg = hns3_read_dev(txq, HNS3_RING_TX_EN_REG);
441 reg |= BIT(HNS3_RING_EN_B);
443 reg &= ~BIT(HNS3_RING_EN_B);
444 hns3_write_dev(txq, HNS3_RING_TX_EN_REG, reg);
450 hns3_enable_rxq(struct hns3_rx_queue *rxq, bool en)
452 struct hns3_hw *hw = &rxq->hns->hw;
455 if (hns3_dev_get_support(hw, INDEP_TXRX)) {
456 reg = hns3_read_dev(rxq, HNS3_RING_RX_EN_REG);
458 reg |= BIT(HNS3_RING_EN_B);
460 reg &= ~BIT(HNS3_RING_EN_B);
461 hns3_write_dev(rxq, HNS3_RING_RX_EN_REG, reg);
467 hns3_start_all_txqs(struct rte_eth_dev *dev)
469 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
470 struct hns3_tx_queue *txq;
473 for (i = 0; i < dev->data->nb_tx_queues; i++) {
474 txq = hw->data->tx_queues[i];
476 hns3_err(hw, "Tx queue %u not available or setup.", i);
477 goto start_txqs_fail;
480 * Tx queue is enabled by default. Therefore, the Tx queues
481 * needs to be disabled when deferred_start is set. There is
482 * another master switch used to control the enabling of a pair
483 * of Tx and Rx queues. And the master switch is disabled by
486 if (txq->tx_deferred_start)
487 hns3_enable_txq(txq, false);
489 hns3_enable_txq(txq, true);
494 for (j = 0; j < i; j++) {
495 txq = hw->data->tx_queues[j];
496 hns3_enable_txq(txq, false);
502 hns3_start_all_rxqs(struct rte_eth_dev *dev)
504 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
505 struct hns3_rx_queue *rxq;
508 for (i = 0; i < dev->data->nb_rx_queues; i++) {
509 rxq = hw->data->rx_queues[i];
511 hns3_err(hw, "Rx queue %u not available or setup.", i);
512 goto start_rxqs_fail;
515 * Rx queue is enabled by default. Therefore, the Rx queues
516 * needs to be disabled when deferred_start is set. There is
517 * another master switch used to control the enabling of a pair
518 * of Tx and Rx queues. And the master switch is disabled by
521 if (rxq->rx_deferred_start)
522 hns3_enable_rxq(rxq, false);
524 hns3_enable_rxq(rxq, true);
529 for (j = 0; j < i; j++) {
530 rxq = hw->data->rx_queues[j];
531 hns3_enable_rxq(rxq, false);
537 hns3_restore_tqp_enable_state(struct hns3_hw *hw)
539 struct hns3_rx_queue *rxq;
540 struct hns3_tx_queue *txq;
543 for (i = 0; i < hw->data->nb_rx_queues; i++) {
544 rxq = hw->data->rx_queues[i];
546 hns3_enable_rxq(rxq, rxq->enabled);
549 for (i = 0; i < hw->data->nb_tx_queues; i++) {
550 txq = hw->data->tx_queues[i];
552 hns3_enable_txq(txq, txq->enabled);
557 hns3_stop_all_txqs(struct rte_eth_dev *dev)
559 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
560 struct hns3_tx_queue *txq;
563 for (i = 0; i < dev->data->nb_tx_queues; i++) {
564 txq = hw->data->tx_queues[i];
567 hns3_enable_txq(txq, false);
572 hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable)
574 struct hns3_cfg_com_tqp_queue_cmd *req;
575 struct hns3_cmd_desc desc;
578 req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data;
580 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false);
581 req->tqp_id = rte_cpu_to_le_16(queue_id);
583 hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0);
585 ret = hns3_cmd_send(hw, &desc, 1);
587 hns3_err(hw, "TQP enable fail, ret = %d", ret);
593 hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable)
595 struct hns3_reset_tqp_queue_cmd *req;
596 struct hns3_cmd_desc desc;
599 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false);
601 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
602 req->tqp_id = rte_cpu_to_le_16(queue_id);
603 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
604 ret = hns3_cmd_send(hw, &desc, 1);
606 hns3_err(hw, "send tqp reset cmd error, queue_id = %u, "
607 "ret = %d", queue_id, ret);
613 hns3_get_tqp_reset_status(struct hns3_hw *hw, uint16_t queue_id,
614 uint8_t *reset_status)
616 struct hns3_reset_tqp_queue_cmd *req;
617 struct hns3_cmd_desc desc;
620 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true);
622 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
623 req->tqp_id = rte_cpu_to_le_16(queue_id);
625 ret = hns3_cmd_send(hw, &desc, 1);
627 hns3_err(hw, "get tqp reset status error, queue_id = %u, "
628 "ret = %d.", queue_id, ret);
631 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
636 hns3pf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
638 #define HNS3_TQP_RESET_TRY_MS 200
639 uint16_t wait_time = 0;
640 uint8_t reset_status;
644 * In current version VF is not supported when PF is driven by DPDK
645 * driver, all task queue pairs are mapped to PF function, so PF's queue
646 * id is equals to the global queue id in PF range.
648 ret = hns3_send_reset_tqp_cmd(hw, queue_id, true);
650 hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret);
655 /* Wait for tqp hw reset */
656 rte_delay_ms(HNS3_POLL_RESPONE_MS);
657 wait_time += HNS3_POLL_RESPONE_MS;
658 ret = hns3_get_tqp_reset_status(hw, queue_id, &reset_status);
664 } while (wait_time < HNS3_TQP_RESET_TRY_MS);
668 hns3_err(hw, "reset tqp timeout, queue_id = %u, ret = %d",
673 ret = hns3_send_reset_tqp_cmd(hw, queue_id, false);
675 hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret);
680 hns3_send_reset_tqp_cmd(hw, queue_id, false);
685 hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
690 memcpy(msg_data, &queue_id, sizeof(uint16_t));
692 ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
693 sizeof(msg_data), true, NULL, 0);
695 hns3_err(hw, "fail to reset tqp, queue_id = %u, ret = %d.",
701 hns3_reset_rcb_cmd(struct hns3_hw *hw, uint8_t *reset_status)
703 struct hns3_reset_cmd *req;
704 struct hns3_cmd_desc desc;
707 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
708 req = (struct hns3_reset_cmd *)desc.data;
709 hns3_set_bit(req->fun_reset_rcb, HNS3_CFG_RESET_RCB_B, 1);
712 * The start qid should be the global qid of the first tqp of the
713 * function which should be reset in this port. Since our PF not
714 * support take over of VFs, so we only need to reset function 0,
715 * and its start qid is always 0.
717 req->fun_reset_rcb_vqid_start = rte_cpu_to_le_16(0);
718 req->fun_reset_rcb_vqid_num = rte_cpu_to_le_16(hw->cfg_max_queues);
720 ret = hns3_cmd_send(hw, &desc, 1);
722 hns3_err(hw, "fail to send rcb reset cmd, ret = %d.", ret);
726 *reset_status = req->fun_reset_rcb_return_status;
731 hns3pf_reset_all_tqps(struct hns3_hw *hw)
733 #define HNS3_RESET_RCB_NOT_SUPPORT 0U
734 #define HNS3_RESET_ALL_TQP_SUCCESS 1U
735 uint8_t reset_status;
739 ret = hns3_reset_rcb_cmd(hw, &reset_status);
744 * If the firmware version is low, it may not support the rcb reset
745 * which means reset all the tqps at a time. In this case, we should
746 * reset tqps one by one.
748 if (reset_status == HNS3_RESET_RCB_NOT_SUPPORT) {
749 for (i = 0; i < hw->cfg_max_queues; i++) {
750 ret = hns3pf_reset_tqp(hw, i);
753 "fail to reset tqp, queue_id = %d, ret = %d.",
758 } else if (reset_status != HNS3_RESET_ALL_TQP_SUCCESS) {
759 hns3_err(hw, "fail to reset all tqps, reset_status = %u.",
768 hns3vf_reset_all_tqps(struct hns3_hw *hw)
770 #define HNS3VF_RESET_ALL_TQP_DONE 1U
771 uint8_t reset_status;
776 memset(msg_data, 0, sizeof(uint16_t));
777 ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
778 sizeof(msg_data), true, &reset_status,
779 sizeof(reset_status));
781 hns3_err(hw, "fail to send rcb reset mbx, ret = %d.", ret);
785 if (reset_status == HNS3VF_RESET_ALL_TQP_DONE)
789 * If the firmware version or kernel PF version is low, it may not
790 * support the rcb reset which means reset all the tqps at a time.
791 * In this case, we should reset tqps one by one.
793 for (i = 1; i < hw->cfg_max_queues; i++) {
794 ret = hns3vf_reset_tqp(hw, i);
803 hns3_reset_all_tqps(struct hns3_adapter *hns)
805 struct hns3_hw *hw = &hns->hw;
808 /* Disable all queues before reset all queues */
809 for (i = 0; i < hw->cfg_max_queues; i++) {
810 ret = hns3_tqp_enable(hw, i, false);
813 "fail to disable tqps before tqps reset, ret = %d.",
820 return hns3vf_reset_all_tqps(hw);
822 return hns3pf_reset_all_tqps(hw);
826 hns3_send_reset_queue_cmd(struct hns3_hw *hw, uint16_t queue_id,
827 enum hns3_ring_type queue_type, bool enable)
829 struct hns3_reset_tqp_queue_cmd *req;
830 struct hns3_cmd_desc desc;
834 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, false);
836 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
837 req->tqp_id = rte_cpu_to_le_16(queue_id);
838 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
839 req->queue_direction = rte_cpu_to_le_16(queue_direction);
840 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
842 ret = hns3_cmd_send(hw, &desc, 1);
844 hns3_err(hw, "send queue reset cmd error, queue_id = %u, "
845 "queue_type = %s, ret = %d.", queue_id,
846 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
851 hns3_get_queue_reset_status(struct hns3_hw *hw, uint16_t queue_id,
852 enum hns3_ring_type queue_type,
853 uint8_t *reset_status)
855 struct hns3_reset_tqp_queue_cmd *req;
856 struct hns3_cmd_desc desc;
860 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, true);
862 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
863 req->tqp_id = rte_cpu_to_le_16(queue_id);
864 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
865 req->queue_direction = rte_cpu_to_le_16(queue_direction);
867 ret = hns3_cmd_send(hw, &desc, 1);
869 hns3_err(hw, "get queue reset status error, queue_id = %u "
870 "queue_type = %s, ret = %d.", queue_id,
871 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
875 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
880 hns3_reset_queue(struct hns3_hw *hw, uint16_t queue_id,
881 enum hns3_ring_type queue_type)
883 #define HNS3_QUEUE_RESET_TRY_MS 200
884 struct hns3_tx_queue *txq;
885 struct hns3_rx_queue *rxq;
886 uint32_t reset_wait_times;
887 uint32_t max_wait_times;
888 uint8_t reset_status;
891 if (queue_type == HNS3_RING_TYPE_TX) {
892 txq = hw->data->tx_queues[queue_id];
893 hns3_enable_txq(txq, false);
895 rxq = hw->data->rx_queues[queue_id];
896 hns3_enable_rxq(rxq, false);
899 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, true);
901 hns3_err(hw, "send reset queue cmd fail, ret = %d.", ret);
905 reset_wait_times = 0;
906 max_wait_times = HNS3_QUEUE_RESET_TRY_MS / HNS3_POLL_RESPONE_MS;
907 while (reset_wait_times < max_wait_times) {
908 /* Wait for queue hw reset */
909 rte_delay_ms(HNS3_POLL_RESPONE_MS);
910 ret = hns3_get_queue_reset_status(hw, queue_id,
911 queue_type, &reset_status);
913 goto queue_reset_fail;
921 hns3_err(hw, "reset queue timeout, queue_id = %u, "
922 "queue_type = %s", queue_id,
923 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx");
925 goto queue_reset_fail;
928 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
930 hns3_err(hw, "deassert queue reset fail, ret = %d.", ret);
935 hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
940 hns3_get_tqp_intr_reg_offset(uint16_t tqp_intr_id)
944 /* Need an extend offset to config queues > 64 */
945 if (tqp_intr_id < HNS3_MIN_EXT_TQP_INTR_ID)
946 reg_offset = HNS3_TQP_INTR_REG_BASE +
947 tqp_intr_id * HNS3_TQP_INTR_LOW_ORDER_OFFSET;
949 reg_offset = HNS3_TQP_INTR_EXT_REG_BASE +
950 tqp_intr_id / HNS3_MIN_EXT_TQP_INTR_ID *
951 HNS3_TQP_INTR_HIGH_ORDER_OFFSET +
952 tqp_intr_id % HNS3_MIN_EXT_TQP_INTR_ID *
953 HNS3_TQP_INTR_LOW_ORDER_OFFSET;
959 hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
960 uint8_t gl_idx, uint16_t gl_value)
962 uint32_t offset[] = {HNS3_TQP_INTR_GL0_REG,
963 HNS3_TQP_INTR_GL1_REG,
964 HNS3_TQP_INTR_GL2_REG};
965 uint32_t addr, value;
967 if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX)
970 addr = offset[gl_idx] + hns3_get_tqp_intr_reg_offset(queue_id);
971 if (hw->intr.gl_unit == HNS3_INTR_COALESCE_GL_UINT_1US)
972 value = gl_value | HNS3_TQP_INTR_GL_UNIT_1US;
974 value = HNS3_GL_USEC_TO_REG(gl_value);
976 hns3_write_dev(hw, addr, value);
980 hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value)
982 uint32_t addr, value;
984 if (rl_value > HNS3_TQP_INTR_RL_MAX)
987 addr = HNS3_TQP_INTR_RL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
988 value = HNS3_RL_USEC_TO_REG(rl_value);
990 value |= HNS3_TQP_INTR_RL_ENABLE_MASK;
992 hns3_write_dev(hw, addr, value);
996 hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value)
1001 * int_ql_max == 0 means the hardware does not support QL,
1002 * QL regs config is not permitted if QL is not supported,
1005 if (hw->intr.int_ql_max == HNS3_INTR_QL_NONE)
1008 addr = HNS3_TQP_INTR_TX_QL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
1009 hns3_write_dev(hw, addr, ql_value);
1011 addr = HNS3_TQP_INTR_RX_QL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
1012 hns3_write_dev(hw, addr, ql_value);
1016 hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en)
1018 uint32_t addr, value;
1020 addr = HNS3_TQP_INTR_CTRL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
1023 hns3_write_dev(hw, addr, value);
1027 * Enable all rx queue interrupt when in interrupt rx mode.
1028 * This api was called before enable queue rx&tx (in normal start or reset
1029 * recover scenes), used to fix hardware rx queue interrupt enable was clear
1033 hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en)
1035 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1036 uint16_t nb_rx_q = hw->data->nb_rx_queues;
1039 if (dev->data->dev_conf.intr_conf.rxq == 0)
1042 for (i = 0; i < nb_rx_q; i++)
1043 hns3_queue_intr_enable(hw, i, en);
1047 hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1049 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1050 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1051 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1053 if (dev->data->dev_conf.intr_conf.rxq == 0)
1056 hns3_queue_intr_enable(hw, queue_id, true);
1058 return rte_intr_ack(intr_handle);
1062 hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1064 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1066 if (dev->data->dev_conf.intr_conf.rxq == 0)
1069 hns3_queue_intr_enable(hw, queue_id, false);
1075 hns3_init_rxq(struct hns3_adapter *hns, uint16_t idx)
1077 struct hns3_hw *hw = &hns->hw;
1078 struct hns3_rx_queue *rxq;
1081 PMD_INIT_FUNC_TRACE();
1083 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx];
1084 ret = hns3_alloc_rx_queue_mbufs(hw, rxq);
1086 hns3_err(hw, "fail to alloc mbuf for Rx queue %u, ret = %d.",
1091 rxq->next_to_use = 0;
1092 rxq->rx_rearm_start = 0;
1093 rxq->rx_free_hold = 0;
1094 rxq->rx_rearm_nb = 0;
1095 rxq->pkt_first_seg = NULL;
1096 rxq->pkt_last_seg = NULL;
1097 hns3_init_rx_queue_hw(rxq);
1098 hns3_rxq_vec_setup(rxq);
1104 hns3_init_fake_rxq(struct hns3_adapter *hns, uint16_t idx)
1106 struct hns3_hw *hw = &hns->hw;
1107 struct hns3_rx_queue *rxq;
1109 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx];
1110 rxq->next_to_use = 0;
1111 rxq->rx_free_hold = 0;
1112 rxq->rx_rearm_start = 0;
1113 rxq->rx_rearm_nb = 0;
1114 hns3_init_rx_queue_hw(rxq);
1118 hns3_init_txq(struct hns3_tx_queue *txq)
1120 struct hns3_desc *desc;
1124 desc = txq->tx_ring;
1125 for (i = 0; i < txq->nb_tx_desc; i++) {
1126 desc->tx.tp_fe_sc_vld_ra_ri = 0;
1130 txq->next_to_use = 0;
1131 txq->next_to_clean = 0;
1132 txq->tx_bd_ready = txq->nb_tx_desc - 1;
1133 hns3_init_tx_queue_hw(txq);
1137 hns3_init_tx_ring_tc(struct hns3_adapter *hns)
1139 struct hns3_hw *hw = &hns->hw;
1140 struct hns3_tx_queue *txq;
1143 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1144 struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i];
1147 if (!tc_queue->enable)
1150 for (j = 0; j < tc_queue->tqp_count; j++) {
1151 num = tc_queue->tqp_offset + j;
1152 txq = (struct hns3_tx_queue *)hw->data->tx_queues[num];
1156 hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc);
1162 hns3_init_rx_queues(struct hns3_adapter *hns)
1164 struct hns3_hw *hw = &hns->hw;
1165 struct hns3_rx_queue *rxq;
1169 /* Initialize RSS for queues */
1170 ret = hns3_config_rss(hns);
1172 hns3_err(hw, "failed to configure rss, ret = %d.", ret);
1176 for (i = 0; i < hw->data->nb_rx_queues; i++) {
1177 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i];
1179 hns3_err(hw, "Rx queue %u not available or setup.", i);
1183 if (rxq->rx_deferred_start)
1186 ret = hns3_init_rxq(hns, i);
1188 hns3_err(hw, "failed to init Rx queue %u, ret = %d.", i,
1194 for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++)
1195 hns3_init_fake_rxq(hns, i);
1200 for (j = 0; j < i; j++) {
1201 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j];
1202 hns3_rx_queue_release_mbufs(rxq);
1209 hns3_init_tx_queues(struct hns3_adapter *hns)
1211 struct hns3_hw *hw = &hns->hw;
1212 struct hns3_tx_queue *txq;
1215 for (i = 0; i < hw->data->nb_tx_queues; i++) {
1216 txq = (struct hns3_tx_queue *)hw->data->tx_queues[i];
1218 hns3_err(hw, "Tx queue %u not available or setup.", i);
1222 if (txq->tx_deferred_start)
1227 for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) {
1228 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i];
1231 hns3_init_tx_ring_tc(hns);
1238 * Note: just init and setup queues, and don't enable tqps.
1241 hns3_init_queues(struct hns3_adapter *hns, bool reset_queue)
1243 struct hns3_hw *hw = &hns->hw;
1247 ret = hns3_reset_all_tqps(hns);
1249 hns3_err(hw, "failed to reset all queues, ret = %d.",
1255 ret = hns3_init_rx_queues(hns);
1257 hns3_err(hw, "failed to init rx queues, ret = %d.", ret);
1261 ret = hns3_init_tx_queues(hns);
1263 hns3_dev_release_mbufs(hns);
1264 hns3_err(hw, "failed to init tx queues, ret = %d.", ret);
1271 hns3_start_tqps(struct hns3_hw *hw)
1273 struct hns3_tx_queue *txq;
1274 struct hns3_rx_queue *rxq;
1277 hns3_enable_all_queues(hw, true);
1279 for (i = 0; i < hw->data->nb_tx_queues; i++) {
1280 txq = hw->data->tx_queues[i];
1282 hw->data->tx_queue_state[i] =
1283 RTE_ETH_QUEUE_STATE_STARTED;
1286 for (i = 0; i < hw->data->nb_rx_queues; i++) {
1287 rxq = hw->data->rx_queues[i];
1289 hw->data->rx_queue_state[i] =
1290 RTE_ETH_QUEUE_STATE_STARTED;
1295 hns3_stop_tqps(struct hns3_hw *hw)
1299 hns3_enable_all_queues(hw, false);
1301 for (i = 0; i < hw->data->nb_tx_queues; i++)
1302 hw->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1304 for (i = 0; i < hw->data->nb_rx_queues; i++)
1305 hw->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1309 * Iterate over all Rx Queue, and call the callback() function for each Rx
1313 * The target eth dev.
1314 * @param[in] callback
1315 * The function to call for each queue.
1316 * if callback function return nonzero will stop iterate and return it's value
1318 * The arguments to provide the callback function with.
1321 * 0 on success, otherwise with errno set.
1324 hns3_rxq_iterate(struct rte_eth_dev *dev,
1325 int (*callback)(struct hns3_rx_queue *, void *), void *arg)
1330 if (dev->data->rx_queues == NULL)
1333 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1334 ret = callback(dev->data->rx_queues[i], arg);
1343 hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev,
1344 struct hns3_queue_info *q_info)
1346 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1347 const struct rte_memzone *rx_mz;
1348 struct hns3_rx_queue *rxq;
1349 unsigned int rx_desc;
1351 rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue),
1352 RTE_CACHE_LINE_SIZE, q_info->socket_id);
1354 hns3_err(hw, "Failed to allocate memory for No.%u rx ring!",
1359 /* Allocate rx ring hardware descriptors. */
1360 rxq->queue_id = q_info->idx;
1361 rxq->nb_rx_desc = q_info->nb_desc;
1364 * Allocate a litter more memory because rx vector functions
1365 * don't check boundaries each time.
1367 rx_desc = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
1368 sizeof(struct hns3_desc);
1369 rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
1370 rx_desc, HNS3_RING_BASE_ALIGN,
1372 if (rx_mz == NULL) {
1373 hns3_err(hw, "Failed to reserve DMA memory for No.%u rx ring!",
1375 hns3_rx_queue_release(rxq);
1379 rxq->rx_ring = (struct hns3_desc *)rx_mz->addr;
1380 rxq->rx_ring_phys_addr = rx_mz->iova;
1386 hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
1387 uint16_t nb_desc, unsigned int socket_id)
1389 struct hns3_adapter *hns = dev->data->dev_private;
1390 struct hns3_hw *hw = &hns->hw;
1391 struct hns3_queue_info q_info;
1392 struct hns3_rx_queue *rxq;
1395 if (hw->fkq_data.rx_queues[idx]) {
1396 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
1397 hw->fkq_data.rx_queues[idx] = NULL;
1401 q_info.socket_id = socket_id;
1402 q_info.nb_desc = nb_desc;
1403 q_info.type = "hns3 fake RX queue";
1404 q_info.ring_name = "rx_fake_ring";
1405 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1407 hns3_err(hw, "Failed to setup No.%u fake rx ring.", idx);
1411 /* Don't need alloc sw_ring, because upper applications don't use it */
1412 rxq->sw_ring = NULL;
1415 rxq->rx_deferred_start = false;
1416 rxq->port_id = dev->data->port_id;
1417 rxq->configured = true;
1418 nb_rx_q = dev->data->nb_rx_queues;
1419 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1420 (nb_rx_q + idx) * HNS3_TQP_REG_SIZE);
1421 rxq->rx_buf_len = HNS3_MIN_BD_BUF_SIZE;
1423 rte_spinlock_lock(&hw->lock);
1424 hw->fkq_data.rx_queues[idx] = rxq;
1425 rte_spinlock_unlock(&hw->lock);
1431 hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev,
1432 struct hns3_queue_info *q_info)
1434 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1435 const struct rte_memzone *tx_mz;
1436 struct hns3_tx_queue *txq;
1437 struct hns3_desc *desc;
1438 unsigned int tx_desc;
1441 txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue),
1442 RTE_CACHE_LINE_SIZE, q_info->socket_id);
1444 hns3_err(hw, "Failed to allocate memory for No.%u tx ring!",
1449 /* Allocate tx ring hardware descriptors. */
1450 txq->queue_id = q_info->idx;
1451 txq->nb_tx_desc = q_info->nb_desc;
1452 tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc);
1453 tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
1454 tx_desc, HNS3_RING_BASE_ALIGN,
1456 if (tx_mz == NULL) {
1457 hns3_err(hw, "Failed to reserve DMA memory for No.%u tx ring!",
1459 hns3_tx_queue_release(txq);
1463 txq->tx_ring = (struct hns3_desc *)tx_mz->addr;
1464 txq->tx_ring_phys_addr = tx_mz->iova;
1467 desc = txq->tx_ring;
1468 for (i = 0; i < txq->nb_tx_desc; i++) {
1469 desc->tx.tp_fe_sc_vld_ra_ri = 0;
1477 hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
1478 uint16_t nb_desc, unsigned int socket_id)
1480 struct hns3_adapter *hns = dev->data->dev_private;
1481 struct hns3_hw *hw = &hns->hw;
1482 struct hns3_queue_info q_info;
1483 struct hns3_tx_queue *txq;
1486 if (hw->fkq_data.tx_queues[idx] != NULL) {
1487 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
1488 hw->fkq_data.tx_queues[idx] = NULL;
1492 q_info.socket_id = socket_id;
1493 q_info.nb_desc = nb_desc;
1494 q_info.type = "hns3 fake TX queue";
1495 q_info.ring_name = "tx_fake_ring";
1496 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
1498 hns3_err(hw, "Failed to setup No.%u fake tx ring.", idx);
1502 /* Don't need alloc sw_ring, because upper applications don't use it */
1503 txq->sw_ring = NULL;
1507 txq->tx_deferred_start = false;
1508 txq->port_id = dev->data->port_id;
1509 txq->configured = true;
1510 nb_tx_q = dev->data->nb_tx_queues;
1511 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1512 (nb_tx_q + idx) * HNS3_TQP_REG_SIZE);
1514 rte_spinlock_lock(&hw->lock);
1515 hw->fkq_data.tx_queues[idx] = txq;
1516 rte_spinlock_unlock(&hw->lock);
1522 hns3_fake_rx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1524 uint16_t old_nb_queues = hw->fkq_data.nb_fake_rx_queues;
1528 if (hw->fkq_data.rx_queues == NULL && nb_queues != 0) {
1529 /* first time configuration */
1531 size = sizeof(hw->fkq_data.rx_queues[0]) * nb_queues;
1532 hw->fkq_data.rx_queues = rte_zmalloc("fake_rx_queues", size,
1533 RTE_CACHE_LINE_SIZE);
1534 if (hw->fkq_data.rx_queues == NULL) {
1535 hw->fkq_data.nb_fake_rx_queues = 0;
1538 } else if (hw->fkq_data.rx_queues != NULL && nb_queues != 0) {
1540 rxq = hw->fkq_data.rx_queues;
1541 for (i = nb_queues; i < old_nb_queues; i++)
1542 hns3_rx_queue_release_lock(rxq[i]);
1544 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
1545 RTE_CACHE_LINE_SIZE);
1548 if (nb_queues > old_nb_queues) {
1549 uint16_t new_qs = nb_queues - old_nb_queues;
1550 memset(rxq + old_nb_queues, 0, sizeof(rxq[0]) * new_qs);
1553 hw->fkq_data.rx_queues = rxq;
1554 } else if (hw->fkq_data.rx_queues != NULL && nb_queues == 0) {
1555 rxq = hw->fkq_data.rx_queues;
1556 for (i = nb_queues; i < old_nb_queues; i++)
1557 hns3_rx_queue_release_lock(rxq[i]);
1559 rte_free(hw->fkq_data.rx_queues);
1560 hw->fkq_data.rx_queues = NULL;
1563 hw->fkq_data.nb_fake_rx_queues = nb_queues;
1569 hns3_fake_tx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1571 uint16_t old_nb_queues = hw->fkq_data.nb_fake_tx_queues;
1575 if (hw->fkq_data.tx_queues == NULL && nb_queues != 0) {
1576 /* first time configuration */
1578 size = sizeof(hw->fkq_data.tx_queues[0]) * nb_queues;
1579 hw->fkq_data.tx_queues = rte_zmalloc("fake_tx_queues", size,
1580 RTE_CACHE_LINE_SIZE);
1581 if (hw->fkq_data.tx_queues == NULL) {
1582 hw->fkq_data.nb_fake_tx_queues = 0;
1585 } else if (hw->fkq_data.tx_queues != NULL && nb_queues != 0) {
1587 txq = hw->fkq_data.tx_queues;
1588 for (i = nb_queues; i < old_nb_queues; i++)
1589 hns3_tx_queue_release_lock(txq[i]);
1590 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1591 RTE_CACHE_LINE_SIZE);
1594 if (nb_queues > old_nb_queues) {
1595 uint16_t new_qs = nb_queues - old_nb_queues;
1596 memset(txq + old_nb_queues, 0, sizeof(txq[0]) * new_qs);
1599 hw->fkq_data.tx_queues = txq;
1600 } else if (hw->fkq_data.tx_queues != NULL && nb_queues == 0) {
1601 txq = hw->fkq_data.tx_queues;
1602 for (i = nb_queues; i < old_nb_queues; i++)
1603 hns3_tx_queue_release_lock(txq[i]);
1605 rte_free(hw->fkq_data.tx_queues);
1606 hw->fkq_data.tx_queues = NULL;
1608 hw->fkq_data.nb_fake_tx_queues = nb_queues;
1614 hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
1617 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1618 uint16_t rx_need_add_nb_q;
1619 uint16_t tx_need_add_nb_q;
1624 if (hns3_dev_get_support(hw, INDEP_TXRX))
1627 /* Setup new number of fake RX/TX queues and reconfigure device. */
1628 rx_need_add_nb_q = hw->cfg_max_queues - nb_rx_q;
1629 tx_need_add_nb_q = hw->cfg_max_queues - nb_tx_q;
1630 ret = hns3_fake_rx_queue_config(hw, rx_need_add_nb_q);
1632 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1636 ret = hns3_fake_tx_queue_config(hw, tx_need_add_nb_q);
1638 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1639 goto cfg_fake_tx_q_fail;
1642 /* Allocate and set up fake RX queue per Ethernet port. */
1643 port_id = hw->data->port_id;
1644 for (q = 0; q < rx_need_add_nb_q; q++) {
1645 ret = hns3_fake_rx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1646 rte_eth_dev_socket_id(port_id));
1648 goto setup_fake_rx_q_fail;
1651 /* Allocate and set up fake TX queue per Ethernet port. */
1652 for (q = 0; q < tx_need_add_nb_q; q++) {
1653 ret = hns3_fake_tx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1654 rte_eth_dev_socket_id(port_id));
1656 goto setup_fake_tx_q_fail;
1661 setup_fake_tx_q_fail:
1662 setup_fake_rx_q_fail:
1663 (void)hns3_fake_tx_queue_config(hw, 0);
1665 (void)hns3_fake_rx_queue_config(hw, 0);
1671 hns3_dev_release_mbufs(struct hns3_adapter *hns)
1673 struct rte_eth_dev_data *dev_data = hns->hw.data;
1674 struct hns3_rx_queue *rxq;
1675 struct hns3_tx_queue *txq;
1678 if (dev_data->rx_queues)
1679 for (i = 0; i < dev_data->nb_rx_queues; i++) {
1680 rxq = dev_data->rx_queues[i];
1683 hns3_rx_queue_release_mbufs(rxq);
1686 if (dev_data->tx_queues)
1687 for (i = 0; i < dev_data->nb_tx_queues; i++) {
1688 txq = dev_data->tx_queues[i];
1691 hns3_tx_queue_release_mbufs(txq);
1696 hns3_rx_buf_len_calc(struct rte_mempool *mp, uint16_t *rx_buf_len)
1698 uint16_t vld_buf_size;
1699 uint16_t num_hw_specs;
1703 * hns3 network engine only support to set 4 typical specification, and
1704 * different buffer size will affect the max packet_len and the max
1705 * number of segmentation when hw gro is turned on in receive side. The
1706 * relationship between them is as follows:
1707 * rx_buf_size | max_gro_pkt_len | max_gro_nb_seg
1708 * ---------------------|-------------------|----------------
1709 * HNS3_4K_BD_BUF_SIZE | 60KB | 15
1710 * HNS3_2K_BD_BUF_SIZE | 62KB | 31
1711 * HNS3_1K_BD_BUF_SIZE | 63KB | 63
1712 * HNS3_512_BD_BUF_SIZE | 31.5KB | 63
1714 static const uint16_t hw_rx_buf_size[] = {
1715 HNS3_4K_BD_BUF_SIZE,
1716 HNS3_2K_BD_BUF_SIZE,
1717 HNS3_1K_BD_BUF_SIZE,
1718 HNS3_512_BD_BUF_SIZE
1721 vld_buf_size = (uint16_t)(rte_pktmbuf_data_room_size(mp) -
1722 RTE_PKTMBUF_HEADROOM);
1723 if (vld_buf_size < HNS3_MIN_BD_BUF_SIZE)
1726 num_hw_specs = RTE_DIM(hw_rx_buf_size);
1727 for (i = 0; i < num_hw_specs; i++) {
1728 if (vld_buf_size >= hw_rx_buf_size[i]) {
1729 *rx_buf_len = hw_rx_buf_size[i];
1737 hns3_rxq_conf_runtime_check(struct hns3_hw *hw, uint16_t buf_size,
1740 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1741 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
1742 uint32_t frame_size = dev->data->mtu + HNS3_ETH_OVERHEAD;
1743 uint16_t min_vec_bds;
1746 * HNS3 hardware network engine set scattered as default. If the driver
1747 * is not work in scattered mode and the pkts greater than buf_size
1748 * but smaller than frame size will be distributed to multiple BDs.
1749 * Driver cannot handle this situation.
1751 if (!hw->data->scattered_rx && frame_size > buf_size) {
1752 hns3_err(hw, "frame size is not allowed to be set greater "
1753 "than rx_buf_len if scattered is off.");
1757 if (pkt_burst == hns3_recv_pkts_vec) {
1758 min_vec_bds = HNS3_DEFAULT_RXQ_REARM_THRESH +
1759 HNS3_DEFAULT_RX_BURST;
1760 if (nb_desc < min_vec_bds ||
1761 nb_desc % HNS3_DEFAULT_RXQ_REARM_THRESH) {
1762 hns3_err(hw, "if Rx burst mode is vector, "
1763 "number of descriptor is required to be "
1764 "bigger than min vector bds:%u, and could be "
1765 "divided by rxq rearm thresh:%u.",
1766 min_vec_bds, HNS3_DEFAULT_RXQ_REARM_THRESH);
1774 hns3_rx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_rxconf *conf,
1775 struct rte_mempool *mp, uint16_t nb_desc,
1780 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1781 nb_desc % HNS3_ALIGN_RING_DESC) {
1782 hns3_err(hw, "Number (%u) of rx descriptors is invalid",
1787 if (conf->rx_drop_en == 0)
1788 hns3_warn(hw, "if no descriptors available, packets are always "
1789 "dropped and rx_drop_en (1) is fixed on");
1791 if (hns3_rx_buf_len_calc(mp, buf_size)) {
1792 hns3_err(hw, "rxq mbufs' data room size (%u) is not enough! "
1793 "minimal data room size (%u).",
1794 rte_pktmbuf_data_room_size(mp),
1795 HNS3_MIN_BD_BUF_SIZE + RTE_PKTMBUF_HEADROOM);
1799 if (hw->data->dev_started) {
1800 ret = hns3_rxq_conf_runtime_check(hw, *buf_size, nb_desc);
1802 hns3_err(hw, "Rx queue runtime setup fail.");
1811 hns3_get_tqp_reg_offset(uint16_t queue_id)
1813 uint32_t reg_offset;
1815 /* Need an extend offset to config queue > 1024 */
1816 if (queue_id < HNS3_MIN_EXTEND_QUEUE_ID)
1817 reg_offset = HNS3_TQP_REG_OFFSET + queue_id * HNS3_TQP_REG_SIZE;
1819 reg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_EXT_REG_OFFSET +
1820 (queue_id - HNS3_MIN_EXTEND_QUEUE_ID) *
1827 hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1828 unsigned int socket_id, const struct rte_eth_rxconf *conf,
1829 struct rte_mempool *mp)
1831 struct hns3_adapter *hns = dev->data->dev_private;
1832 struct hns3_hw *hw = &hns->hw;
1833 struct hns3_queue_info q_info;
1834 struct hns3_rx_queue *rxq;
1835 uint16_t rx_buf_size;
1839 ret = hns3_rx_queue_conf_check(hw, conf, mp, nb_desc, &rx_buf_size);
1843 if (dev->data->rx_queues[idx]) {
1844 hns3_rx_queue_release(dev->data->rx_queues[idx]);
1845 dev->data->rx_queues[idx] = NULL;
1849 q_info.socket_id = socket_id;
1850 q_info.nb_desc = nb_desc;
1851 q_info.type = "hns3 RX queue";
1852 q_info.ring_name = "rx_ring";
1854 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1857 "Failed to alloc mem and reserve DMA mem for rx ring!");
1862 rxq->ptype_tbl = &hns->ptype_tbl;
1864 rxq->rx_free_thresh = (conf->rx_free_thresh > 0) ?
1865 conf->rx_free_thresh : HNS3_DEFAULT_RX_FREE_THRESH;
1867 rxq->rx_deferred_start = conf->rx_deferred_start;
1868 if (rxq->rx_deferred_start && !hns3_dev_get_support(hw, INDEP_TXRX)) {
1869 hns3_warn(hw, "deferred start is not supported.");
1870 rxq->rx_deferred_start = false;
1873 rx_entry_len = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
1874 sizeof(struct hns3_entry);
1875 rxq->sw_ring = rte_zmalloc_socket("hns3 RX sw ring", rx_entry_len,
1876 RTE_CACHE_LINE_SIZE, socket_id);
1877 if (rxq->sw_ring == NULL) {
1878 hns3_err(hw, "Failed to allocate memory for rx sw ring!");
1879 hns3_rx_queue_release(rxq);
1883 rxq->next_to_use = 0;
1884 rxq->rx_free_hold = 0;
1885 rxq->rx_rearm_start = 0;
1886 rxq->rx_rearm_nb = 0;
1887 rxq->pkt_first_seg = NULL;
1888 rxq->pkt_last_seg = NULL;
1889 rxq->port_id = dev->data->port_id;
1891 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
1892 * the pvid_sw_discard_en in the queue struct should not be changed,
1893 * because PVID-related operations do not need to be processed by PMD.
1894 * For hns3 VF device, whether it needs to process PVID depends
1895 * on the configuration of PF kernel mode netdevice driver. And the
1896 * related PF configuration is delivered through the mailbox and finally
1897 * reflected in port_base_vlan_cfg.
1899 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1900 rxq->pvid_sw_discard_en = hw->port_base_vlan_cfg.state ==
1901 HNS3_PORT_BASE_VLAN_ENABLE;
1903 rxq->pvid_sw_discard_en = false;
1904 rxq->ptype_en = hns3_dev_get_support(hw, RXD_ADV_LAYOUT) ? true : false;
1905 rxq->configured = true;
1906 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1907 idx * HNS3_TQP_REG_SIZE);
1908 rxq->io_base = (void *)((char *)hw->io_base +
1909 hns3_get_tqp_reg_offset(idx));
1910 rxq->io_head_reg = (volatile void *)((char *)rxq->io_base +
1911 HNS3_RING_RX_HEAD_REG);
1912 rxq->rx_buf_len = rx_buf_size;
1913 memset(&rxq->basic_stats, 0, sizeof(struct hns3_rx_basic_stats));
1914 memset(&rxq->err_stats, 0, sizeof(struct hns3_rx_bd_errors_stats));
1915 memset(&rxq->dfx_stats, 0, sizeof(struct hns3_rx_dfx_stats));
1917 /* CRC len set here is used for amending packet length */
1918 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
1919 rxq->crc_len = RTE_ETHER_CRC_LEN;
1923 rxq->bulk_mbuf_num = 0;
1925 rte_spinlock_lock(&hw->lock);
1926 dev->data->rx_queues[idx] = rxq;
1927 rte_spinlock_unlock(&hw->lock);
1933 hns3_rx_scattered_reset(struct rte_eth_dev *dev)
1935 struct hns3_adapter *hns = dev->data->dev_private;
1936 struct hns3_hw *hw = &hns->hw;
1939 dev->data->scattered_rx = false;
1943 hns3_rx_scattered_calc(struct rte_eth_dev *dev)
1945 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1946 struct hns3_adapter *hns = dev->data->dev_private;
1947 struct hns3_hw *hw = &hns->hw;
1948 struct hns3_rx_queue *rxq;
1951 if (dev->data->rx_queues == NULL)
1954 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
1955 rxq = dev->data->rx_queues[queue_id];
1956 if (hw->rx_buf_len == 0)
1957 hw->rx_buf_len = rxq->rx_buf_len;
1959 hw->rx_buf_len = RTE_MIN(hw->rx_buf_len,
1963 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER ||
1964 dev->data->mtu + HNS3_ETH_OVERHEAD > hw->rx_buf_len)
1965 dev->data->scattered_rx = true;
1969 hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1971 static const uint32_t ptypes[] = {
1973 RTE_PTYPE_L2_ETHER_LLDP,
1974 RTE_PTYPE_L2_ETHER_ARP,
1976 RTE_PTYPE_L3_IPV4_EXT,
1978 RTE_PTYPE_L3_IPV6_EXT,
1984 RTE_PTYPE_TUNNEL_GRE,
1985 RTE_PTYPE_INNER_L2_ETHER,
1986 RTE_PTYPE_INNER_L3_IPV4,
1987 RTE_PTYPE_INNER_L3_IPV6,
1988 RTE_PTYPE_INNER_L3_IPV4_EXT,
1989 RTE_PTYPE_INNER_L3_IPV6_EXT,
1990 RTE_PTYPE_INNER_L4_UDP,
1991 RTE_PTYPE_INNER_L4_TCP,
1992 RTE_PTYPE_INNER_L4_SCTP,
1993 RTE_PTYPE_INNER_L4_ICMP,
1994 RTE_PTYPE_TUNNEL_VXLAN,
1995 RTE_PTYPE_TUNNEL_NVGRE,
1998 static const uint32_t adv_layout_ptypes[] = {
2000 RTE_PTYPE_L2_ETHER_TIMESYNC,
2001 RTE_PTYPE_L2_ETHER_LLDP,
2002 RTE_PTYPE_L2_ETHER_ARP,
2003 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2004 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2006 RTE_PTYPE_L4_NONFRAG,
2012 RTE_PTYPE_TUNNEL_GRE,
2013 RTE_PTYPE_TUNNEL_GRENAT,
2014 RTE_PTYPE_INNER_L2_ETHER,
2015 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2016 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2017 RTE_PTYPE_INNER_L4_FRAG,
2018 RTE_PTYPE_INNER_L4_ICMP,
2019 RTE_PTYPE_INNER_L4_NONFRAG,
2020 RTE_PTYPE_INNER_L4_UDP,
2021 RTE_PTYPE_INNER_L4_TCP,
2022 RTE_PTYPE_INNER_L4_SCTP,
2023 RTE_PTYPE_INNER_L4_ICMP,
2026 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028 if (dev->rx_pkt_burst == hns3_recv_pkts_simple ||
2029 dev->rx_pkt_burst == hns3_recv_scattered_pkts ||
2030 dev->rx_pkt_burst == hns3_recv_pkts_vec ||
2031 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve) {
2032 if (hns3_dev_get_support(hw, RXD_ADV_LAYOUT))
2033 return adv_layout_ptypes;
2042 hns3_init_non_tunnel_ptype_tbl(struct hns3_ptype_table *tbl)
2044 tbl->l3table[0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
2045 tbl->l3table[1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
2046 tbl->l3table[2] = RTE_PTYPE_L2_ETHER_ARP;
2047 tbl->l3table[4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT;
2048 tbl->l3table[5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT;
2049 tbl->l3table[6] = RTE_PTYPE_L2_ETHER_LLDP;
2051 tbl->l4table[0] = RTE_PTYPE_L4_UDP;
2052 tbl->l4table[1] = RTE_PTYPE_L4_TCP;
2053 tbl->l4table[2] = RTE_PTYPE_TUNNEL_GRE;
2054 tbl->l4table[3] = RTE_PTYPE_L4_SCTP;
2055 tbl->l4table[4] = RTE_PTYPE_L4_IGMP;
2056 tbl->l4table[5] = RTE_PTYPE_L4_ICMP;
2060 hns3_init_tunnel_ptype_tbl(struct hns3_ptype_table *tbl)
2062 tbl->inner_l3table[0] = RTE_PTYPE_INNER_L2_ETHER |
2063 RTE_PTYPE_INNER_L3_IPV4;
2064 tbl->inner_l3table[1] = RTE_PTYPE_INNER_L2_ETHER |
2065 RTE_PTYPE_INNER_L3_IPV6;
2066 /* There is not a ptype for inner ARP/RARP */
2067 tbl->inner_l3table[2] = RTE_PTYPE_UNKNOWN;
2068 tbl->inner_l3table[3] = RTE_PTYPE_UNKNOWN;
2069 tbl->inner_l3table[4] = RTE_PTYPE_INNER_L2_ETHER |
2070 RTE_PTYPE_INNER_L3_IPV4_EXT;
2071 tbl->inner_l3table[5] = RTE_PTYPE_INNER_L2_ETHER |
2072 RTE_PTYPE_INNER_L3_IPV6_EXT;
2074 tbl->inner_l4table[0] = RTE_PTYPE_INNER_L4_UDP;
2075 tbl->inner_l4table[1] = RTE_PTYPE_INNER_L4_TCP;
2076 /* There is not a ptype for inner GRE */
2077 tbl->inner_l4table[2] = RTE_PTYPE_UNKNOWN;
2078 tbl->inner_l4table[3] = RTE_PTYPE_INNER_L4_SCTP;
2079 /* There is not a ptype for inner IGMP */
2080 tbl->inner_l4table[4] = RTE_PTYPE_UNKNOWN;
2081 tbl->inner_l4table[5] = RTE_PTYPE_INNER_L4_ICMP;
2083 tbl->ol3table[0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
2084 tbl->ol3table[1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
2085 tbl->ol3table[2] = RTE_PTYPE_UNKNOWN;
2086 tbl->ol3table[3] = RTE_PTYPE_UNKNOWN;
2087 tbl->ol3table[4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT;
2088 tbl->ol3table[5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT;
2090 tbl->ol4table[0] = RTE_PTYPE_UNKNOWN;
2091 tbl->ol4table[1] = RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN;
2092 tbl->ol4table[2] = RTE_PTYPE_TUNNEL_NVGRE;
2096 hns3_init_adv_layout_ptype(struct hns3_ptype_table *tbl)
2098 uint32_t *ptype = tbl->ptype;
2101 ptype[1] = RTE_PTYPE_L2_ETHER_ARP;
2102 ptype[3] = RTE_PTYPE_L2_ETHER_LLDP;
2103 ptype[8] = RTE_PTYPE_L2_ETHER_TIMESYNC;
2105 /* Non-tunnel IPv4 */
2106 ptype[17] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2108 ptype[18] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2109 RTE_PTYPE_L4_NONFRAG;
2110 ptype[19] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2112 ptype[20] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2114 ptype[21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2115 RTE_PTYPE_TUNNEL_GRE;
2116 ptype[22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2118 ptype[23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2120 ptype[24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2122 /* The next ptype is PTP over IPv4 + UDP */
2123 ptype[25] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2126 /* IPv4 --> GRE/Teredo/VXLAN */
2127 ptype[29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2128 RTE_PTYPE_TUNNEL_GRENAT;
2129 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2130 ptype[30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2131 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER;
2133 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2134 ptype[31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2135 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2136 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2137 RTE_PTYPE_INNER_L4_FRAG;
2138 ptype[32] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2139 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2140 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2141 RTE_PTYPE_INNER_L4_NONFRAG;
2142 ptype[33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2143 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2144 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2145 RTE_PTYPE_INNER_L4_UDP;
2146 ptype[34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2147 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2148 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2149 RTE_PTYPE_INNER_L4_TCP;
2150 ptype[35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2151 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2152 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2153 RTE_PTYPE_INNER_L4_SCTP;
2154 /* The next ptype's inner L4 is IGMP */
2155 ptype[36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2156 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2157 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
2158 ptype[37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2159 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2160 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2161 RTE_PTYPE_INNER_L4_ICMP;
2163 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2164 ptype[39] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2165 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2166 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2167 RTE_PTYPE_INNER_L4_FRAG;
2168 ptype[40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2169 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2170 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2171 RTE_PTYPE_INNER_L4_NONFRAG;
2172 ptype[41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2173 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2174 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2175 RTE_PTYPE_INNER_L4_UDP;
2176 ptype[42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2177 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2178 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2179 RTE_PTYPE_INNER_L4_TCP;
2180 ptype[43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2181 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2182 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2183 RTE_PTYPE_INNER_L4_SCTP;
2184 /* The next ptype's inner L4 is IGMP */
2185 ptype[44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2186 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2187 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
2188 ptype[45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2189 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2190 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2191 RTE_PTYPE_INNER_L4_ICMP;
2193 /* Non-tunnel IPv6 */
2194 ptype[111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2196 ptype[112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2197 RTE_PTYPE_L4_NONFRAG;
2198 ptype[113] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2200 ptype[114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2202 ptype[115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2203 RTE_PTYPE_TUNNEL_GRE;
2204 ptype[116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2206 ptype[117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2208 ptype[118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2210 /* Special for PTP over IPv6 + UDP */
2211 ptype[119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2214 /* IPv6 --> GRE/Teredo/VXLAN */
2215 ptype[123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2216 RTE_PTYPE_TUNNEL_GRENAT;
2217 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2218 ptype[124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2219 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER;
2221 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2222 ptype[125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2223 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2224 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2225 RTE_PTYPE_INNER_L4_FRAG;
2226 ptype[126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2227 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2228 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2229 RTE_PTYPE_INNER_L4_NONFRAG;
2230 ptype[127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2231 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2232 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2233 RTE_PTYPE_INNER_L4_UDP;
2234 ptype[128] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2235 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2236 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2237 RTE_PTYPE_INNER_L4_TCP;
2238 ptype[129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2239 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2240 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2241 RTE_PTYPE_INNER_L4_SCTP;
2242 /* The next ptype's inner L4 is IGMP */
2243 ptype[130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2244 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2245 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
2246 ptype[131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2247 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2248 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2249 RTE_PTYPE_INNER_L4_ICMP;
2251 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2252 ptype[133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2253 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2254 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2255 RTE_PTYPE_INNER_L4_FRAG;
2256 ptype[134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2257 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2258 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2259 RTE_PTYPE_INNER_L4_NONFRAG;
2260 ptype[135] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2261 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2262 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2263 RTE_PTYPE_INNER_L4_UDP;
2264 ptype[136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2265 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2266 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2267 RTE_PTYPE_INNER_L4_TCP;
2268 ptype[137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2269 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2270 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2271 RTE_PTYPE_INNER_L4_SCTP;
2272 /* The next ptype's inner L4 is IGMP */
2273 ptype[138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2274 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2275 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
2276 ptype[139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2277 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2278 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2279 RTE_PTYPE_INNER_L4_ICMP;
2283 hns3_init_rx_ptype_tble(struct rte_eth_dev *dev)
2285 struct hns3_adapter *hns = dev->data->dev_private;
2286 struct hns3_ptype_table *tbl = &hns->ptype_tbl;
2288 memset(tbl, 0, sizeof(*tbl));
2290 hns3_init_non_tunnel_ptype_tbl(tbl);
2291 hns3_init_tunnel_ptype_tbl(tbl);
2292 hns3_init_adv_layout_ptype(tbl);
2296 hns3_rxd_to_vlan_tci(struct hns3_rx_queue *rxq, struct rte_mbuf *mb,
2297 uint32_t l234_info, const struct hns3_desc *rxd)
2299 #define HNS3_STRP_STATUS_NUM 0x4
2301 #define HNS3_NO_STRP_VLAN_VLD 0x0
2302 #define HNS3_INNER_STRP_VLAN_VLD 0x1
2303 #define HNS3_OUTER_STRP_VLAN_VLD 0x2
2304 uint32_t strip_status;
2305 uint32_t report_mode;
2308 * Since HW limitation, the vlan tag will always be inserted into RX
2309 * descriptor when strip the tag from packet, driver needs to determine
2310 * reporting which tag to mbuf according to the PVID configuration
2311 * and vlan striped status.
2313 static const uint32_t report_type[][HNS3_STRP_STATUS_NUM] = {
2315 HNS3_NO_STRP_VLAN_VLD,
2316 HNS3_OUTER_STRP_VLAN_VLD,
2317 HNS3_INNER_STRP_VLAN_VLD,
2318 HNS3_OUTER_STRP_VLAN_VLD
2321 HNS3_NO_STRP_VLAN_VLD,
2322 HNS3_NO_STRP_VLAN_VLD,
2323 HNS3_NO_STRP_VLAN_VLD,
2324 HNS3_INNER_STRP_VLAN_VLD
2327 strip_status = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,
2328 HNS3_RXD_STRP_TAGP_S);
2329 report_mode = report_type[rxq->pvid_sw_discard_en][strip_status];
2330 switch (report_mode) {
2331 case HNS3_NO_STRP_VLAN_VLD:
2334 case HNS3_INNER_STRP_VLAN_VLD:
2335 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
2336 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.vlan_tag);
2338 case HNS3_OUTER_STRP_VLAN_VLD:
2339 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
2340 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.ot_vlan_tag);
2349 recalculate_data_len(struct rte_mbuf *first_seg, struct rte_mbuf *last_seg,
2350 struct rte_mbuf *rxm, struct hns3_rx_queue *rxq,
2353 uint8_t crc_len = rxq->crc_len;
2355 if (data_len <= crc_len) {
2356 rte_pktmbuf_free_seg(rxm);
2357 first_seg->nb_segs--;
2358 last_seg->data_len = (uint16_t)(last_seg->data_len -
2359 (crc_len - data_len));
2360 last_seg->next = NULL;
2362 rxm->data_len = (uint16_t)(data_len - crc_len);
2365 static inline struct rte_mbuf *
2366 hns3_rx_alloc_buffer(struct hns3_rx_queue *rxq)
2370 if (likely(rxq->bulk_mbuf_num > 0))
2371 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
2373 ret = rte_mempool_get_bulk(rxq->mb_pool, (void **)rxq->bulk_mbuf,
2374 HNS3_BULK_ALLOC_MBUF_NUM);
2375 if (likely(ret == 0)) {
2376 rxq->bulk_mbuf_num = HNS3_BULK_ALLOC_MBUF_NUM;
2377 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
2379 return rte_mbuf_raw_alloc(rxq->mb_pool);
2383 hns3_rx_ptp_timestamp_handle(struct hns3_rx_queue *rxq, struct rte_mbuf *mbuf,
2386 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(rxq->hns);
2388 mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP |
2389 RTE_MBUF_F_RX_IEEE1588_TMST;
2390 if (hns3_timestamp_rx_dynflag > 0) {
2391 *RTE_MBUF_DYNFIELD(mbuf, hns3_timestamp_dynfield_offset,
2392 rte_mbuf_timestamp_t *) = timestamp;
2393 mbuf->ol_flags |= hns3_timestamp_rx_dynflag;
2396 pf->rx_timestamp = timestamp;
2400 hns3_recv_pkts_simple(void *rx_queue,
2401 struct rte_mbuf **rx_pkts,
2404 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
2405 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
2406 struct hns3_rx_queue *rxq; /* RX queue */
2407 struct hns3_entry *sw_ring;
2408 struct hns3_entry *rxe;
2409 struct hns3_desc rxd;
2410 struct rte_mbuf *nmb; /* pointer of the new mbuf */
2411 struct rte_mbuf *rxm;
2412 uint32_t bd_base_info;
2424 rx_ring = rxq->rx_ring;
2425 sw_ring = rxq->sw_ring;
2426 rx_id = rxq->next_to_use;
2428 while (nb_rx < nb_pkts) {
2429 rxdp = &rx_ring[rx_id];
2430 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
2431 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
2434 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2435 (1u << HNS3_RXD_VLD_B)];
2437 nmb = hns3_rx_alloc_buffer(rxq);
2438 if (unlikely(nmb == NULL)) {
2441 port_id = rxq->port_id;
2442 rte_eth_devices[port_id].data->rx_mbuf_alloc_failed++;
2447 rxe = &sw_ring[rx_id];
2449 if (unlikely(rx_id == rxq->nb_rx_desc))
2452 rte_prefetch0(sw_ring[rx_id].mbuf);
2453 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
2454 rte_prefetch0(&rx_ring[rx_id]);
2455 rte_prefetch0(&sw_ring[rx_id]);
2462 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B)))
2463 hns3_rx_ptp_timestamp_handle(rxq, rxm,
2464 rte_le_to_cpu_64(rxdp->timestamp));
2466 dma_addr = rte_mbuf_data_iova_default(nmb);
2467 rxdp->addr = rte_cpu_to_le_64(dma_addr);
2468 rxdp->rx.bd_base_info = 0;
2470 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2471 rxm->pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.pkt_len)) -
2473 rxm->data_len = rxm->pkt_len;
2474 rxm->port = rxq->port_id;
2475 rxm->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
2476 rxm->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
2477 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
2479 rte_le_to_cpu_16(rxd.rx.fd_id);
2480 rxm->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
2485 /* Load remained descriptor data and extract necessary fields */
2486 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
2487 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
2488 ret = hns3_handle_bdinfo(rxq, rxm, bd_base_info, l234_info);
2492 rxm->packet_type = hns3_rx_calc_ptype(rxq, l234_info, ol_info);
2494 if (rxm->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC)
2495 rxm->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
2497 hns3_rxd_to_vlan_tci(rxq, rxm, l234_info, &rxd);
2499 /* Increment bytes counter */
2500 rxq->basic_stats.bytes += rxm->pkt_len;
2502 rx_pkts[nb_rx++] = rxm;
2505 rte_pktmbuf_free(rxm);
2508 rxq->next_to_use = rx_id;
2509 rxq->rx_free_hold += nb_rx_bd;
2510 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
2511 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
2512 rxq->rx_free_hold = 0;
2519 hns3_recv_scattered_pkts(void *rx_queue,
2520 struct rte_mbuf **rx_pkts,
2523 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
2524 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
2525 struct hns3_rx_queue *rxq; /* RX queue */
2526 struct hns3_entry *sw_ring;
2527 struct hns3_entry *rxe;
2528 struct rte_mbuf *first_seg;
2529 struct rte_mbuf *last_seg;
2530 struct hns3_desc rxd;
2531 struct rte_mbuf *nmb; /* pointer of the new mbuf */
2532 struct rte_mbuf *rxm;
2533 struct rte_eth_dev *dev;
2534 uint32_t bd_base_info;
2549 rx_id = rxq->next_to_use;
2550 rx_ring = rxq->rx_ring;
2551 sw_ring = rxq->sw_ring;
2552 first_seg = rxq->pkt_first_seg;
2553 last_seg = rxq->pkt_last_seg;
2555 while (nb_rx < nb_pkts) {
2556 rxdp = &rx_ring[rx_id];
2557 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
2558 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
2562 * The interactive process between software and hardware of
2563 * receiving a new packet in hns3 network engine:
2564 * 1. Hardware network engine firstly writes the packet content
2565 * to the memory pointed by the 'addr' field of the Rx Buffer
2566 * Descriptor, secondly fills the result of parsing the
2567 * packet include the valid field into the Rx Buffer
2568 * Descriptor in one write operation.
2569 * 2. Driver reads the Rx BD's valid field in the loop to check
2570 * whether it's valid, if valid then assign a new address to
2571 * the addr field, clear the valid field, get the other
2572 * information of the packet by parsing Rx BD's other fields,
2573 * finally write back the number of Rx BDs processed by the
2574 * driver to the HNS3_RING_RX_HEAD_REG register to inform
2576 * In the above process, the ordering is very important. We must
2577 * make sure that CPU read Rx BD's other fields only after the
2580 * There are two type of re-ordering: compiler re-ordering and
2581 * CPU re-ordering under the ARMv8 architecture.
2582 * 1. we use volatile to deal with compiler re-ordering, so you
2583 * can see that rx_ring/rxdp defined with volatile.
2584 * 2. we commonly use memory barrier to deal with CPU
2585 * re-ordering, but the cost is high.
2587 * In order to solve the high cost of using memory barrier, we
2588 * use the data dependency order under the ARMv8 architecture,
2591 * instr02: load B <- A
2592 * the instr02 will always execute after instr01.
2594 * To construct the data dependency ordering, we use the
2595 * following assignment:
2596 * rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2597 * (1u<<HNS3_RXD_VLD_B)]
2598 * Using gcc compiler under the ARMv8 architecture, the related
2599 * assembly code example as follows:
2600 * note: (1u << HNS3_RXD_VLD_B) equal 0x10
2601 * instr01: ldr w26, [x22, #28] --read bd_base_info
2602 * instr02: and w0, w26, #0x10 --calc bd_base_info & 0x10
2603 * instr03: sub w0, w0, #0x10 --calc (bd_base_info &
2605 * instr04: add x0, x22, x0, lsl #5 --calc copy source addr
2606 * instr05: ldp x2, x3, [x0]
2607 * instr06: stp x2, x3, [x29, #256] --copy BD's [0 ~ 15]B
2608 * instr07: ldp x4, x5, [x0, #16]
2609 * instr08: stp x4, x5, [x29, #272] --copy BD's [16 ~ 31]B
2610 * the instr05~08 depend on x0's value, x0 depent on w26's
2611 * value, the w26 is the bd_base_info, this form the data
2612 * dependency ordering.
2613 * note: if BD is valid, (bd_base_info & (1u<<HNS3_RXD_VLD_B)) -
2614 * (1u<<HNS3_RXD_VLD_B) will always zero, so the
2615 * assignment is correct.
2617 * So we use the data dependency ordering instead of memory
2618 * barrier to improve receive performance.
2620 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2621 (1u << HNS3_RXD_VLD_B)];
2623 nmb = hns3_rx_alloc_buffer(rxq);
2624 if (unlikely(nmb == NULL)) {
2625 dev = &rte_eth_devices[rxq->port_id];
2626 dev->data->rx_mbuf_alloc_failed++;
2631 rxe = &sw_ring[rx_id];
2633 if (unlikely(rx_id == rxq->nb_rx_desc))
2636 rte_prefetch0(sw_ring[rx_id].mbuf);
2637 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
2638 rte_prefetch0(&rx_ring[rx_id]);
2639 rte_prefetch0(&sw_ring[rx_id]);
2645 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B)))
2646 timestamp = rte_le_to_cpu_64(rxdp->timestamp);
2648 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2649 rxdp->rx.bd_base_info = 0;
2650 rxdp->addr = dma_addr;
2652 if (first_seg == NULL) {
2654 first_seg->nb_segs = 1;
2656 first_seg->nb_segs++;
2657 last_seg->next = rxm;
2660 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2661 rxm->data_len = rte_le_to_cpu_16(rxd.rx.size);
2663 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
2669 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B)))
2670 hns3_rx_ptp_timestamp_handle(rxq, first_seg, timestamp);
2673 * The last buffer of the received packet. packet len from
2674 * buffer description may contains CRC len, packet len should
2675 * subtract it, same as data len.
2677 first_seg->pkt_len = rte_le_to_cpu_16(rxd.rx.pkt_len);
2680 * This is the last buffer of the received packet. If the CRC
2681 * is not stripped by the hardware:
2682 * - Subtract the CRC length from the total packet length.
2683 * - If the last buffer only contains the whole CRC or a part
2684 * of it, free the mbuf associated to the last buffer. If part
2685 * of the CRC is also contained in the previous mbuf, subtract
2686 * the length of that CRC part from the data length of the
2690 if (unlikely(rxq->crc_len > 0)) {
2691 first_seg->pkt_len -= rxq->crc_len;
2692 recalculate_data_len(first_seg, last_seg, rxm, rxq,
2696 first_seg->port = rxq->port_id;
2697 first_seg->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
2698 first_seg->ol_flags = RTE_MBUF_F_RX_RSS_HASH;
2699 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
2700 first_seg->hash.fdir.hi =
2701 rte_le_to_cpu_16(rxd.rx.fd_id);
2702 first_seg->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
2705 gro_size = hns3_get_field(bd_base_info, HNS3_RXD_GRO_SIZE_M,
2706 HNS3_RXD_GRO_SIZE_S);
2707 if (gro_size != 0) {
2708 first_seg->ol_flags |= RTE_MBUF_F_RX_LRO;
2709 first_seg->tso_segsz = gro_size;
2712 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
2713 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
2714 ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info,
2719 first_seg->packet_type = hns3_rx_calc_ptype(rxq,
2720 l234_info, ol_info);
2722 if (first_seg->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC)
2723 rxm->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
2725 hns3_rxd_to_vlan_tci(rxq, first_seg, l234_info, &rxd);
2727 /* Increment bytes counter */
2728 rxq->basic_stats.bytes += first_seg->pkt_len;
2730 rx_pkts[nb_rx++] = first_seg;
2734 rte_pktmbuf_free(first_seg);
2738 rxq->next_to_use = rx_id;
2739 rxq->pkt_first_seg = first_seg;
2740 rxq->pkt_last_seg = last_seg;
2742 rxq->rx_free_hold += nb_rx_bd;
2743 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
2744 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
2745 rxq->rx_free_hold = 0;
2752 hns3_rxq_vec_setup(__rte_unused struct hns3_rx_queue *rxq)
2757 hns3_rx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
2763 hns3_recv_pkts_vec(__rte_unused void *tx_queue,
2764 __rte_unused struct rte_mbuf **rx_pkts,
2765 __rte_unused uint16_t nb_pkts)
2771 hns3_recv_pkts_vec_sve(__rte_unused void *tx_queue,
2772 __rte_unused struct rte_mbuf **rx_pkts,
2773 __rte_unused uint16_t nb_pkts)
2779 hns3_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2780 struct rte_eth_burst_mode *mode)
2782 static const struct {
2783 eth_rx_burst_t pkt_burst;
2786 { hns3_recv_pkts_simple, "Scalar Simple" },
2787 { hns3_recv_scattered_pkts, "Scalar Scattered" },
2788 { hns3_recv_pkts_vec, "Vector Neon" },
2789 { hns3_recv_pkts_vec_sve, "Vector Sve" },
2792 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2796 for (i = 0; i < RTE_DIM(burst_infos); i++) {
2797 if (pkt_burst == burst_infos[i].pkt_burst) {
2798 snprintf(mode->info, sizeof(mode->info), "%s",
2799 burst_infos[i].info);
2809 hns3_get_default_vec_support(void)
2811 #if defined(RTE_ARCH_ARM64)
2812 if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128)
2814 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON))
2821 hns3_get_sve_support(void)
2823 #if defined(RTE_HAS_SVE_ACLE)
2824 if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256)
2826 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE))
2832 static eth_rx_burst_t
2833 hns3_get_rx_function(struct rte_eth_dev *dev)
2835 struct hns3_adapter *hns = dev->data->dev_private;
2836 uint64_t offloads = dev->data->dev_conf.rxmode.offloads;
2837 bool vec_allowed, sve_allowed, simple_allowed;
2840 vec_support = hns3_rx_check_vec_support(dev) == 0;
2841 vec_allowed = vec_support && hns3_get_default_vec_support();
2842 sve_allowed = vec_support && hns3_get_sve_support();
2843 simple_allowed = !dev->data->scattered_rx &&
2844 (offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) == 0;
2846 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed)
2847 return hns3_recv_pkts_vec;
2848 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed)
2849 return hns3_recv_pkts_vec_sve;
2850 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed)
2851 return hns3_recv_pkts_simple;
2852 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_COMMON)
2853 return hns3_recv_scattered_pkts;
2856 return hns3_recv_pkts_vec;
2858 return hns3_recv_pkts_simple;
2860 return hns3_recv_scattered_pkts;
2864 hns3_tx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_txconf *conf,
2865 uint16_t nb_desc, uint16_t *tx_rs_thresh,
2866 uint16_t *tx_free_thresh, uint16_t idx)
2868 #define HNS3_TX_RS_FREE_THRESH_GAP 8
2869 uint16_t rs_thresh, free_thresh, fast_free_thresh;
2871 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
2872 nb_desc % HNS3_ALIGN_RING_DESC) {
2873 hns3_err(hw, "number (%u) of tx descriptors is invalid",
2878 rs_thresh = (conf->tx_rs_thresh > 0) ?
2879 conf->tx_rs_thresh : HNS3_DEFAULT_TX_RS_THRESH;
2880 free_thresh = (conf->tx_free_thresh > 0) ?
2881 conf->tx_free_thresh : HNS3_DEFAULT_TX_FREE_THRESH;
2882 if (rs_thresh + free_thresh > nb_desc || nb_desc % rs_thresh ||
2883 rs_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP ||
2884 free_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP) {
2885 hns3_err(hw, "tx_rs_thresh (%u) tx_free_thresh (%u) nb_desc "
2886 "(%u) of tx descriptors for port=%u queue=%u check "
2888 rs_thresh, free_thresh, nb_desc, hw->data->port_id,
2893 if (conf->tx_free_thresh == 0) {
2894 /* Fast free Tx memory buffer to improve cache hit rate */
2895 fast_free_thresh = nb_desc - rs_thresh;
2896 if (fast_free_thresh >=
2897 HNS3_TX_FAST_FREE_AHEAD + HNS3_DEFAULT_TX_FREE_THRESH)
2898 free_thresh = fast_free_thresh -
2899 HNS3_TX_FAST_FREE_AHEAD;
2902 *tx_rs_thresh = rs_thresh;
2903 *tx_free_thresh = free_thresh;
2908 hns3_tx_push_get_queue_tail_reg(struct rte_eth_dev *dev, uint16_t queue_id)
2910 #define HNS3_TX_PUSH_TQP_REGION_SIZE 0x10000
2911 #define HNS3_TX_PUSH_QUICK_DOORBELL_OFFSET 64
2912 #define HNS3_TX_PUSH_PCI_BAR_INDEX 4
2914 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2915 uint8_t bar_id = HNS3_TX_PUSH_PCI_BAR_INDEX;
2918 * If device support Tx push then its PCIe bar45 must exist, and DPDK
2919 * framework will mmap the bar45 default in PCI probe stage.
2921 * In the bar45, the first half is for RoCE (RDMA over Converged
2922 * Ethernet), and the second half is for NIC, every TQP occupy 64KB.
2924 * The quick doorbell located at 64B offset in the TQP region.
2926 return (char *)pci_dev->mem_resource[bar_id].addr +
2927 (pci_dev->mem_resource[bar_id].len >> 1) +
2928 HNS3_TX_PUSH_TQP_REGION_SIZE * queue_id +
2929 HNS3_TX_PUSH_QUICK_DOORBELL_OFFSET;
2933 hns3_tx_push_init(struct rte_eth_dev *dev)
2935 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936 volatile uint32_t *reg;
2939 if (!hns3_dev_get_support(hw, TX_PUSH))
2942 reg = (volatile uint32_t *)hns3_tx_push_get_queue_tail_reg(dev, 0);
2944 * Because the size of bar45 is about 8GB size, it may take a long time
2945 * to do the page fault in Tx process when work with vfio-pci, so use
2946 * one read operation to make kernel setup page table mapping for bar45
2947 * in the init stage.
2948 * Note: the bar45 is readable but the result is all 1.
2955 hns3_tx_push_queue_init(struct rte_eth_dev *dev,
2957 struct hns3_tx_queue *txq)
2959 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2960 if (!hns3_dev_get_support(hw, TX_PUSH)) {
2961 txq->tx_push_enable = false;
2965 txq->io_tail_reg = (volatile void *)hns3_tx_push_get_queue_tail_reg(dev,
2967 txq->tx_push_enable = true;
2971 hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
2972 unsigned int socket_id, const struct rte_eth_txconf *conf)
2974 struct hns3_adapter *hns = dev->data->dev_private;
2975 uint16_t tx_rs_thresh, tx_free_thresh;
2976 struct hns3_hw *hw = &hns->hw;
2977 struct hns3_queue_info q_info;
2978 struct hns3_tx_queue *txq;
2982 ret = hns3_tx_queue_conf_check(hw, conf, nb_desc,
2983 &tx_rs_thresh, &tx_free_thresh, idx);
2987 if (dev->data->tx_queues[idx] != NULL) {
2988 hns3_tx_queue_release(dev->data->tx_queues[idx]);
2989 dev->data->tx_queues[idx] = NULL;
2993 q_info.socket_id = socket_id;
2994 q_info.nb_desc = nb_desc;
2995 q_info.type = "hns3 TX queue";
2996 q_info.ring_name = "tx_ring";
2997 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
3000 "Failed to alloc mem and reserve DMA mem for tx ring!");
3004 txq->tx_deferred_start = conf->tx_deferred_start;
3005 if (txq->tx_deferred_start && !hns3_dev_get_support(hw, INDEP_TXRX)) {
3006 hns3_warn(hw, "deferred start is not supported.");
3007 txq->tx_deferred_start = false;
3010 tx_entry_len = sizeof(struct hns3_entry) * txq->nb_tx_desc;
3011 txq->sw_ring = rte_zmalloc_socket("hns3 TX sw ring", tx_entry_len,
3012 RTE_CACHE_LINE_SIZE, socket_id);
3013 if (txq->sw_ring == NULL) {
3014 hns3_err(hw, "Failed to allocate memory for tx sw ring!");
3015 hns3_tx_queue_release(txq);
3020 txq->next_to_use = 0;
3021 txq->next_to_clean = 0;
3022 txq->tx_bd_ready = txq->nb_tx_desc - 1;
3023 txq->tx_free_thresh = tx_free_thresh;
3024 txq->tx_rs_thresh = tx_rs_thresh;
3025 txq->free = rte_zmalloc_socket("hns3 TX mbuf free array",
3026 sizeof(struct rte_mbuf *) * txq->tx_rs_thresh,
3027 RTE_CACHE_LINE_SIZE, socket_id);
3029 hns3_err(hw, "failed to allocate tx mbuf free array!");
3030 hns3_tx_queue_release(txq);
3034 txq->port_id = dev->data->port_id;
3036 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
3037 * the pvid_sw_shift_en in the queue struct should not be changed,
3038 * because PVID-related operations do not need to be processed by PMD.
3039 * For hns3 VF device, whether it needs to process PVID depends
3040 * on the configuration of PF kernel mode netdev driver. And the
3041 * related PF configuration is delivered through the mailbox and finally
3042 * reflected in port_base_vlan_cfg.
3044 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
3045 txq->pvid_sw_shift_en = hw->port_base_vlan_cfg.state ==
3046 HNS3_PORT_BASE_VLAN_ENABLE;
3048 txq->pvid_sw_shift_en = false;
3049 txq->max_non_tso_bd_num = hw->max_non_tso_bd_num;
3050 txq->configured = true;
3051 txq->io_base = (void *)((char *)hw->io_base +
3052 hns3_get_tqp_reg_offset(idx));
3053 txq->io_tail_reg = (volatile void *)((char *)txq->io_base +
3054 HNS3_RING_TX_TAIL_REG);
3055 txq->min_tx_pkt_len = hw->min_tx_pkt_len;
3056 txq->tso_mode = hw->tso_mode;
3057 txq->udp_cksum_mode = hw->udp_cksum_mode;
3058 txq->mbuf_fast_free_en = !!(dev->data->dev_conf.txmode.offloads &
3059 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE);
3060 memset(&txq->basic_stats, 0, sizeof(struct hns3_tx_basic_stats));
3061 memset(&txq->dfx_stats, 0, sizeof(struct hns3_tx_dfx_stats));
3064 * Call hns3_tx_push_queue_init after assigned io_tail_reg field because
3065 * it may overwrite the io_tail_reg field.
3067 hns3_tx_push_queue_init(dev, idx, txq);
3069 rte_spinlock_lock(&hw->lock);
3070 dev->data->tx_queues[idx] = txq;
3071 rte_spinlock_unlock(&hw->lock);
3077 hns3_tx_free_useless_buffer(struct hns3_tx_queue *txq)
3079 uint16_t tx_next_clean = txq->next_to_clean;
3080 uint16_t tx_next_use = txq->next_to_use;
3081 struct hns3_entry *tx_entry = &txq->sw_ring[tx_next_clean];
3082 struct hns3_desc *desc = &txq->tx_ring[tx_next_clean];
3085 if (tx_next_use >= tx_next_clean &&
3086 tx_next_use < tx_next_clean + txq->tx_rs_thresh)
3090 * All mbufs can be released only when the VLD bits of all
3091 * descriptors in a batch are cleared.
3093 for (i = 0; i < txq->tx_rs_thresh; i++) {
3094 if (desc[i].tx.tp_fe_sc_vld_ra_ri &
3095 rte_le_to_cpu_16(BIT(HNS3_TXD_VLD_B)))
3099 for (i = 0; i < txq->tx_rs_thresh; i++) {
3100 rte_pktmbuf_free_seg(tx_entry[i].mbuf);
3101 tx_entry[i].mbuf = NULL;
3104 /* Update numbers of available descriptor due to buffer freed */
3105 txq->tx_bd_ready += txq->tx_rs_thresh;
3106 txq->next_to_clean += txq->tx_rs_thresh;
3107 if (txq->next_to_clean >= txq->nb_tx_desc)
3108 txq->next_to_clean = 0;
3114 hns3_tx_free_required_buffer(struct hns3_tx_queue *txq, uint16_t required_bds)
3116 while (required_bds > txq->tx_bd_ready) {
3117 if (hns3_tx_free_useless_buffer(txq) != 0)
3124 hns3_config_gro(struct hns3_hw *hw, bool en)
3126 struct hns3_cfg_gro_status_cmd *req;
3127 struct hns3_cmd_desc desc;
3130 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
3131 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
3133 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
3135 ret = hns3_cmd_send(hw, &desc, 1);
3137 hns3_err(hw, "%s hardware GRO failed, ret = %d",
3138 en ? "enable" : "disable", ret);
3144 hns3_restore_gro_conf(struct hns3_hw *hw)
3150 offloads = hw->data->dev_conf.rxmode.offloads;
3151 gro_en = offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
3152 ret = hns3_config_gro(hw, gro_en);
3154 hns3_err(hw, "restore hardware GRO to %s failed, ret = %d",
3155 gro_en ? "enabled" : "disabled", ret);
3161 hns3_pkt_is_tso(struct rte_mbuf *m)
3163 return (m->tso_segsz != 0 && m->ol_flags & RTE_MBUF_F_TX_TCP_SEG);
3167 hns3_set_tso(struct hns3_desc *desc, uint32_t paylen, struct rte_mbuf *rxm)
3169 if (!hns3_pkt_is_tso(rxm))
3172 if (paylen <= rxm->tso_segsz)
3175 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(BIT(HNS3_TXD_TSO_B));
3176 desc->tx.mss = rte_cpu_to_le_16(rxm->tso_segsz);
3180 hns3_fill_per_desc(struct hns3_desc *desc, struct rte_mbuf *rxm)
3182 desc->addr = rte_mbuf_data_iova(rxm);
3183 desc->tx.send_size = rte_cpu_to_le_16(rte_pktmbuf_data_len(rxm));
3184 desc->tx.tp_fe_sc_vld_ra_ri |= rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B));
3188 hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc,
3189 struct rte_mbuf *rxm)
3191 uint64_t ol_flags = rxm->ol_flags;
3195 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len;
3196 hdr_len += (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ?
3197 rxm->outer_l2_len + rxm->outer_l3_len : 0;
3198 paylen = rxm->pkt_len - hdr_len;
3199 desc->tx.paylen_fd_dop_ol4cs |= rte_cpu_to_le_32(paylen);
3200 hns3_set_tso(desc, paylen, rxm);
3203 * Currently, hardware doesn't support more than two layers VLAN offload
3204 * in Tx direction based on hns3 network engine. So when the number of
3205 * VLANs in the packets represented by rxm plus the number of VLAN
3206 * offload by hardware such as PVID etc, exceeds two, the packets will
3207 * be discarded or the original VLAN of the packets will be overwritten
3208 * by hardware. When the PF PVID is enabled by calling the API function
3209 * named rte_eth_dev_set_vlan_pvid or the VF PVID is enabled by the hns3
3210 * PF kernel ether driver, the outer VLAN tag will always be the PVID.
3211 * To avoid the VLAN of Tx descriptor is overwritten by PVID, it should
3212 * be added to the position close to the IP header when PVID is enabled.
3214 if (!txq->pvid_sw_shift_en &&
3215 ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {
3216 desc->tx.ol_type_vlan_len_msec |=
3217 rte_cpu_to_le_32(BIT(HNS3_TXD_OVLAN_B));
3218 if (ol_flags & RTE_MBUF_F_TX_QINQ)
3219 desc->tx.outer_vlan_tag =
3220 rte_cpu_to_le_16(rxm->vlan_tci_outer);
3222 desc->tx.outer_vlan_tag =
3223 rte_cpu_to_le_16(rxm->vlan_tci);
3226 if (ol_flags & RTE_MBUF_F_TX_QINQ ||
3227 ((ol_flags & RTE_MBUF_F_TX_VLAN) && txq->pvid_sw_shift_en)) {
3228 desc->tx.type_cs_vlan_tso_len |=
3229 rte_cpu_to_le_32(BIT(HNS3_TXD_VLAN_B));
3230 desc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci);
3233 if (ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)
3234 desc->tx.tp_fe_sc_vld_ra_ri |=
3235 rte_cpu_to_le_16(BIT(HNS3_TXD_TSYN_B));
3239 hns3_tx_alloc_mbufs(struct rte_mempool *mb_pool, uint16_t nb_new_buf,
3240 struct rte_mbuf **alloc_mbuf)
3242 #define MAX_NON_TSO_BD_PER_PKT 18
3243 struct rte_mbuf *pkt_segs[MAX_NON_TSO_BD_PER_PKT];
3246 /* Allocate enough mbufs */
3247 if (rte_mempool_get_bulk(mb_pool, (void **)pkt_segs, nb_new_buf))
3250 for (i = 0; i < nb_new_buf - 1; i++)
3251 pkt_segs[i]->next = pkt_segs[i + 1];
3253 pkt_segs[nb_new_buf - 1]->next = NULL;
3254 pkt_segs[0]->nb_segs = nb_new_buf;
3255 *alloc_mbuf = pkt_segs[0];
3261 hns3_pktmbuf_copy_hdr(struct rte_mbuf *new_pkt, struct rte_mbuf *old_pkt)
3263 new_pkt->ol_flags = old_pkt->ol_flags;
3264 new_pkt->pkt_len = rte_pktmbuf_pkt_len(old_pkt);
3265 new_pkt->outer_l2_len = old_pkt->outer_l2_len;
3266 new_pkt->outer_l3_len = old_pkt->outer_l3_len;
3267 new_pkt->l2_len = old_pkt->l2_len;
3268 new_pkt->l3_len = old_pkt->l3_len;
3269 new_pkt->l4_len = old_pkt->l4_len;
3270 new_pkt->vlan_tci_outer = old_pkt->vlan_tci_outer;
3271 new_pkt->vlan_tci = old_pkt->vlan_tci;
3275 hns3_reassemble_tx_pkts(struct rte_mbuf *tx_pkt, struct rte_mbuf **new_pkt,
3276 uint8_t max_non_tso_bd_num)
3278 struct rte_mempool *mb_pool;
3279 struct rte_mbuf *new_mbuf;
3280 struct rte_mbuf *temp_new;
3281 struct rte_mbuf *temp;
3282 uint16_t last_buf_len;
3283 uint16_t nb_new_buf;
3293 mb_pool = tx_pkt->pool;
3294 buf_size = tx_pkt->buf_len - RTE_PKTMBUF_HEADROOM;
3295 nb_new_buf = (rte_pktmbuf_pkt_len(tx_pkt) - 1) / buf_size + 1;
3296 if (nb_new_buf > max_non_tso_bd_num)
3299 last_buf_len = rte_pktmbuf_pkt_len(tx_pkt) % buf_size;
3300 if (last_buf_len == 0)
3301 last_buf_len = buf_size;
3303 /* Allocate enough mbufs */
3304 ret = hns3_tx_alloc_mbufs(mb_pool, nb_new_buf, &new_mbuf);
3308 /* Copy the original packet content to the new mbufs */
3310 s = rte_pktmbuf_mtod(temp, char *);
3311 len_s = rte_pktmbuf_data_len(temp);
3312 temp_new = new_mbuf;
3313 while (temp != NULL && temp_new != NULL) {
3314 d = rte_pktmbuf_mtod(temp_new, char *);
3315 buf_len = temp_new->next == NULL ? last_buf_len : buf_size;
3319 len = RTE_MIN(len_s, len_d);
3323 len_d = len_d - len;
3324 len_s = len_s - len;
3330 s = rte_pktmbuf_mtod(temp, char *);
3331 len_s = rte_pktmbuf_data_len(temp);
3335 temp_new->data_len = buf_len;
3336 temp_new = temp_new->next;
3338 hns3_pktmbuf_copy_hdr(new_mbuf, tx_pkt);
3340 /* free original mbufs */
3341 rte_pktmbuf_free(tx_pkt);
3343 *new_pkt = new_mbuf;
3349 hns3_parse_outer_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec)
3351 uint32_t tmp = *ol_type_vlan_len_msec;
3352 uint64_t ol_flags = m->ol_flags;
3354 /* (outer) IP header type */
3355 if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV4) {
3356 if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM)
3357 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M,
3358 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_CSUM);
3360 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M,
3361 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_NO_CSUM);
3362 } else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6) {
3363 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
3366 /* OL3 header size, defined in 4 bytes */
3367 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
3368 m->outer_l3_len >> HNS3_L3_LEN_UNIT);
3369 *ol_type_vlan_len_msec = tmp;
3373 hns3_parse_inner_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec,
3374 uint32_t *type_cs_vlan_tso_len)
3376 #define HNS3_NVGRE_HLEN 8
3377 uint32_t tmp_outer = *ol_type_vlan_len_msec;
3378 uint32_t tmp_inner = *type_cs_vlan_tso_len;
3379 uint64_t ol_flags = m->ol_flags;
3380 uint16_t inner_l2_len;
3382 switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
3383 case RTE_MBUF_F_TX_TUNNEL_VXLAN_GPE:
3384 case RTE_MBUF_F_TX_TUNNEL_GENEVE:
3385 case RTE_MBUF_F_TX_TUNNEL_VXLAN:
3386 /* MAC in UDP tunnelling packet, include VxLAN and GENEVE */
3387 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M,
3388 HNS3_TXD_TUNTYPE_S, HNS3_TUN_MAC_IN_UDP);
3390 * The inner l2 length of mbuf is the sum of outer l4 length,
3391 * tunneling header length and inner l2 length for a tunnel
3392 * packet. But in hns3 tx descriptor, the tunneling header
3393 * length is contained in the field of outer L4 length.
3394 * Therefore, driver need to calculate the outer L4 length and
3397 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M,
3399 (uint8_t)RTE_ETHER_VXLAN_HLEN >>
3402 inner_l2_len = m->l2_len - RTE_ETHER_VXLAN_HLEN;
3404 case RTE_MBUF_F_TX_TUNNEL_GRE:
3405 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M,
3406 HNS3_TXD_TUNTYPE_S, HNS3_TUN_NVGRE);
3408 * For NVGRE tunnel packet, the outer L4 is empty. So only
3409 * fill the NVGRE header length to the outer L4 field.
3411 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M,
3413 (uint8_t)HNS3_NVGRE_HLEN >> HNS3_L4_LEN_UNIT);
3415 inner_l2_len = m->l2_len - HNS3_NVGRE_HLEN;
3418 /* For non UDP / GRE tunneling, drop the tunnel packet */
3422 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
3423 inner_l2_len >> HNS3_L2_LEN_UNIT);
3424 /* OL2 header size, defined in 2 bytes */
3425 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
3426 m->outer_l2_len >> HNS3_L2_LEN_UNIT);
3428 *type_cs_vlan_tso_len = tmp_inner;
3429 *ol_type_vlan_len_msec = tmp_outer;
3435 hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m,
3436 uint16_t tx_desc_id)
3438 struct hns3_desc *tx_ring = txq->tx_ring;
3439 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3440 uint64_t ol_flags = m->ol_flags;
3441 uint32_t tmp_outer = 0;
3442 uint32_t tmp_inner = 0;
3447 * The tunnel header is contained in the inner L2 header field of the
3448 * mbuf, but for hns3 descriptor, it is contained in the outer L4. So,
3449 * there is a need that switching between them. To avoid multiple
3450 * calculations, the length of the L2 header include the outer and
3451 * inner, will be filled during the parsing of tunnel packets.
3453 if (!(ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)) {
3455 * For non tunnel type the tunnel type id is 0, so no need to
3456 * assign a value to it. Only the inner(normal) L2 header length
3459 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M,
3460 HNS3_TXD_L2LEN_S, m->l2_len >> HNS3_L2_LEN_UNIT);
3463 * If outer csum is not offload, the outer length may be filled
3464 * with 0. And the length of the outer header is added to the
3465 * inner l2_len. It would lead a cksum error. So driver has to
3466 * calculate the header length.
3468 if (unlikely(!(ol_flags &
3469 (RTE_MBUF_F_TX_OUTER_IP_CKSUM | RTE_MBUF_F_TX_OUTER_UDP_CKSUM)) &&
3470 m->outer_l2_len == 0)) {
3471 struct rte_net_hdr_lens hdr_len;
3472 (void)rte_net_get_ptype(m, &hdr_len,
3473 RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK);
3474 m->outer_l3_len = hdr_len.l3_len;
3475 m->outer_l2_len = hdr_len.l2_len;
3476 m->l2_len = m->l2_len - hdr_len.l2_len - hdr_len.l3_len;
3478 hns3_parse_outer_params(m, &tmp_outer);
3479 ret = hns3_parse_inner_params(m, &tmp_outer, &tmp_inner);
3484 desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp_outer);
3485 desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp_inner);
3486 tmp_ol4cs = ol_flags & RTE_MBUF_F_TX_OUTER_UDP_CKSUM ?
3487 BIT(HNS3_TXD_OL4CS_B) : 0;
3488 desc->tx.paylen_fd_dop_ol4cs = rte_cpu_to_le_32(tmp_ol4cs);
3494 hns3_parse_l3_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len)
3496 uint64_t ol_flags = m->ol_flags;
3500 tmp = *type_cs_vlan_tso_len;
3501 if (ol_flags & RTE_MBUF_F_TX_IPV4)
3502 l3_type = HNS3_L3T_IPV4;
3503 else if (ol_flags & RTE_MBUF_F_TX_IPV6)
3504 l3_type = HNS3_L3T_IPV6;
3506 l3_type = HNS3_L3T_NONE;
3508 /* inner(/normal) L3 header size, defined in 4 bytes */
3509 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
3510 m->l3_len >> HNS3_L3_LEN_UNIT);
3512 tmp |= hns3_gen_field_val(HNS3_TXD_L3T_M, HNS3_TXD_L3T_S, l3_type);
3514 /* Enable L3 checksum offloads */
3515 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM)
3516 tmp |= BIT(HNS3_TXD_L3CS_B);
3517 *type_cs_vlan_tso_len = tmp;
3521 hns3_parse_l4_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len)
3523 uint64_t ol_flags = m->ol_flags;
3525 /* Enable L4 checksum offloads */
3526 switch (ol_flags & (RTE_MBUF_F_TX_L4_MASK | RTE_MBUF_F_TX_TCP_SEG)) {
3527 case RTE_MBUF_F_TX_TCP_CKSUM | RTE_MBUF_F_TX_TCP_SEG:
3528 case RTE_MBUF_F_TX_TCP_CKSUM:
3529 case RTE_MBUF_F_TX_TCP_SEG:
3530 tmp = *type_cs_vlan_tso_len;
3531 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3534 case RTE_MBUF_F_TX_UDP_CKSUM:
3535 tmp = *type_cs_vlan_tso_len;
3536 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3539 case RTE_MBUF_F_TX_SCTP_CKSUM:
3540 tmp = *type_cs_vlan_tso_len;
3541 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3547 tmp |= BIT(HNS3_TXD_L4CS_B);
3548 tmp |= hns3_gen_field_val(HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
3549 m->l4_len >> HNS3_L4_LEN_UNIT);
3550 *type_cs_vlan_tso_len = tmp;
3554 hns3_txd_enable_checksum(struct hns3_tx_queue *txq, struct rte_mbuf *m,
3555 uint16_t tx_desc_id)
3557 struct hns3_desc *tx_ring = txq->tx_ring;
3558 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3561 hns3_parse_l3_cksum_params(m, &value);
3562 hns3_parse_l4_cksum_params(m, &value);
3564 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(value);
3568 hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num,
3569 uint32_t max_non_tso_bd_num)
3571 struct rte_mbuf *m_first = tx_pkts;
3572 struct rte_mbuf *m_last = tx_pkts;
3573 uint32_t tot_len = 0;
3578 * Hardware requires that the sum of the data length of every 8
3579 * consecutive buffers is greater than MSS in hns3 network engine.
3580 * We simplify it by ensuring pkt_headlen + the first 8 consecutive
3581 * frags greater than gso header len + mss, and the remaining 7
3582 * consecutive frags greater than MSS except the last 7 frags.
3584 if (bd_num <= max_non_tso_bd_num)
3587 for (i = 0; m_last && i < max_non_tso_bd_num - 1;
3588 i++, m_last = m_last->next)
3589 tot_len += m_last->data_len;
3594 /* ensure the first 8 frags is greater than mss + header */
3595 hdr_len = tx_pkts->l2_len + tx_pkts->l3_len + tx_pkts->l4_len;
3596 hdr_len += (tx_pkts->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ?
3597 tx_pkts->outer_l2_len + tx_pkts->outer_l3_len : 0;
3598 if (tot_len + m_last->data_len < tx_pkts->tso_segsz + hdr_len)
3602 * ensure the sum of the data length of every 7 consecutive buffer
3603 * is greater than mss except the last one.
3605 for (i = 0; m_last && i < bd_num - max_non_tso_bd_num; i++) {
3606 tot_len -= m_first->data_len;
3607 tot_len += m_last->data_len;
3609 if (tot_len < tx_pkts->tso_segsz)
3612 m_first = m_first->next;
3613 m_last = m_last->next;
3620 hns3_outer_ipv4_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags,
3623 struct rte_ipv4_hdr *ipv4_hdr;
3624 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
3626 if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM)
3627 ipv4_hdr->hdr_checksum = 0;
3628 if (ol_flags & RTE_MBUF_F_TX_OUTER_UDP_CKSUM) {
3629 struct rte_udp_hdr *udp_hdr;
3631 * If OUTER_UDP_CKSUM is support, HW can calculate the pseudo
3632 * header for TSO packets
3634 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
3636 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3637 m->outer_l2_len + m->outer_l3_len);
3638 udp_hdr->dgram_cksum = rte_ipv4_phdr_cksum(ipv4_hdr, ol_flags);
3642 *l4_proto = ipv4_hdr->next_proto_id;
3647 hns3_outer_ipv6_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags,
3650 struct rte_ipv6_hdr *ipv6_hdr;
3651 ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *,
3653 if (ol_flags & RTE_MBUF_F_TX_OUTER_UDP_CKSUM) {
3654 struct rte_udp_hdr *udp_hdr;
3656 * If OUTER_UDP_CKSUM is support, HW can calculate the pseudo
3657 * header for TSO packets
3659 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
3661 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3662 m->outer_l2_len + m->outer_l3_len);
3663 udp_hdr->dgram_cksum = rte_ipv6_phdr_cksum(ipv6_hdr, ol_flags);
3667 *l4_proto = ipv6_hdr->proto;
3672 hns3_outer_header_cksum_prepare(struct rte_mbuf *m)
3674 uint64_t ol_flags = m->ol_flags;
3675 uint32_t paylen, hdr_len, l4_proto;
3676 struct rte_udp_hdr *udp_hdr;
3678 if (!(ol_flags & (RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_OUTER_IPV6)))
3681 if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV4) {
3682 if (hns3_outer_ipv4_cksum_prepared(m, ol_flags, &l4_proto))
3685 if (hns3_outer_ipv6_cksum_prepared(m, ol_flags, &l4_proto))
3689 /* driver should ensure the outer udp cksum is 0 for TUNNEL TSO */
3690 if (l4_proto == IPPROTO_UDP && (ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
3691 hdr_len = m->l2_len + m->l3_len + m->l4_len;
3692 hdr_len += m->outer_l2_len + m->outer_l3_len;
3693 paylen = m->pkt_len - hdr_len;
3694 if (paylen <= m->tso_segsz)
3696 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3699 udp_hdr->dgram_cksum = 0;
3704 hns3_check_tso_pkt_valid(struct rte_mbuf *m)
3706 uint32_t tmp_data_len_sum = 0;
3707 uint16_t nb_buf = m->nb_segs;
3708 uint32_t paylen, hdr_len;
3709 struct rte_mbuf *m_seg;
3712 if (nb_buf > HNS3_MAX_TSO_BD_PER_PKT)
3715 hdr_len = m->l2_len + m->l3_len + m->l4_len;
3716 hdr_len += (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ?
3717 m->outer_l2_len + m->outer_l3_len : 0;
3718 if (hdr_len > HNS3_MAX_TSO_HDR_SIZE)
3721 paylen = m->pkt_len - hdr_len;
3722 if (paylen > HNS3_MAX_BD_PAYLEN)
3726 * The TSO header (include outer and inner L2, L3 and L4 header)
3727 * should be provided by three descriptors in maximum in hns3 network
3731 for (i = 0; m_seg != NULL && i < HNS3_MAX_TSO_HDR_BD_NUM && i < nb_buf;
3732 i++, m_seg = m_seg->next) {
3733 tmp_data_len_sum += m_seg->data_len;
3736 if (hdr_len > tmp_data_len_sum)
3742 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3744 hns3_vld_vlan_chk(struct hns3_tx_queue *txq, struct rte_mbuf *m)
3746 struct rte_ether_hdr *eh;
3747 struct rte_vlan_hdr *vh;
3749 if (!txq->pvid_sw_shift_en)
3753 * Due to hardware limitations, we only support two-layer VLAN hardware
3754 * offload in Tx direction based on hns3 network engine, so when PVID is
3755 * enabled, QinQ insert is no longer supported.
3756 * And when PVID is enabled, in the following two cases:
3757 * i) packets with more than two VLAN tags.
3758 * ii) packets with one VLAN tag while the hardware VLAN insert is
3760 * The packets will be regarded as abnormal packets and discarded by
3761 * hardware in Tx direction. For debugging purposes, a validation check
3762 * for these types of packets is added to the '.tx_pkt_prepare' ops
3763 * implementation function named hns3_prep_pkts to inform users that
3764 * these packets will be discarded.
3766 if (m->ol_flags & RTE_MBUF_F_TX_QINQ)
3769 eh = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
3770 if (eh->ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
3771 if (m->ol_flags & RTE_MBUF_F_TX_VLAN)
3774 /* Ensure the incoming packet is not a QinQ packet */
3775 vh = (struct rte_vlan_hdr *)(eh + 1);
3776 if (vh->eth_proto == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN))
3785 hns3_udp_cksum_help(struct rte_mbuf *m)
3787 uint64_t ol_flags = m->ol_flags;
3791 if (ol_flags & RTE_MBUF_F_TX_IPV4) {
3792 struct rte_ipv4_hdr *ipv4_hdr = rte_pktmbuf_mtod_offset(m,
3793 struct rte_ipv4_hdr *, m->l2_len);
3794 l4_len = rte_be_to_cpu_16(ipv4_hdr->total_length) - m->l3_len;
3796 struct rte_ipv6_hdr *ipv6_hdr = rte_pktmbuf_mtod_offset(m,
3797 struct rte_ipv6_hdr *, m->l2_len);
3798 l4_len = rte_be_to_cpu_16(ipv6_hdr->payload_len);
3801 rte_raw_cksum_mbuf(m, m->l2_len + m->l3_len, l4_len, &cksum);
3805 * RFC 768:If the computed checksum is zero for UDP, it is transmitted
3811 return (uint16_t)cksum;
3815 hns3_validate_tunnel_cksum(struct hns3_tx_queue *tx_queue, struct rte_mbuf *m)
3817 uint64_t ol_flags = m->ol_flags;
3818 struct rte_udp_hdr *udp_hdr;
3821 if (tx_queue->udp_cksum_mode == HNS3_SPECIAL_PORT_HW_CKSUM_MODE ||
3822 ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK ||
3823 (ol_flags & RTE_MBUF_F_TX_L4_MASK) != RTE_MBUF_F_TX_UDP_CKSUM)
3826 * A UDP packet with the same dst_port as VXLAN\VXLAN_GPE\GENEVE will
3827 * be recognized as a tunnel packet in HW. In this case, if UDP CKSUM
3828 * offload is set and the tunnel mask has not been set, the CKSUM will
3829 * be wrong since the header length is wrong and driver should complete
3830 * the CKSUM to avoid CKSUM error.
3832 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3833 m->l2_len + m->l3_len);
3834 dst_port = rte_be_to_cpu_16(udp_hdr->dst_port);
3836 case RTE_VXLAN_DEFAULT_PORT:
3837 case RTE_VXLAN_GPE_DEFAULT_PORT:
3838 case RTE_GENEVE_DEFAULT_PORT:
3839 udp_hdr->dgram_cksum = hns3_udp_cksum_help(m);
3840 m->ol_flags = ol_flags & ~RTE_MBUF_F_TX_L4_MASK;
3848 hns3_prep_pkt_proc(struct hns3_tx_queue *tx_queue, struct rte_mbuf *m)
3852 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3853 ret = rte_validate_tx_offload(m);
3859 ret = hns3_vld_vlan_chk(tx_queue, m);
3865 if (hns3_pkt_is_tso(m)) {
3866 if (hns3_pkt_need_linearized(m, m->nb_segs,
3867 tx_queue->max_non_tso_bd_num) ||
3868 hns3_check_tso_pkt_valid(m)) {
3873 if (tx_queue->tso_mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) {
3875 * (tso mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) means
3876 * hardware support recalculate the TCP pseudo header
3877 * checksum of packets that need TSO, so network driver
3878 * software not need to recalculate it.
3880 hns3_outer_header_cksum_prepare(m);
3885 ret = rte_net_intel_cksum_prepare(m);
3891 if (!hns3_validate_tunnel_cksum(tx_queue, m))
3894 hns3_outer_header_cksum_prepare(m);
3900 hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3906 for (i = 0; i < nb_pkts; i++) {
3908 if (hns3_prep_pkt_proc(tx_queue, m))
3916 hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
3919 struct hns3_desc *tx_ring = txq->tx_ring;
3920 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3922 /* Enable checksum offloading */
3923 if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK) {
3924 /* Fill in tunneling parameters if necessary */
3925 if (hns3_parse_tunneling_params(txq, m, tx_desc_id)) {
3926 txq->dfx_stats.unsupported_tunnel_pkt_cnt++;
3930 hns3_txd_enable_checksum(txq, m, tx_desc_id);
3932 /* clear the control bit */
3933 desc->tx.type_cs_vlan_tso_len = 0;
3934 desc->tx.ol_type_vlan_len_msec = 0;
3941 hns3_check_non_tso_pkt(uint16_t nb_buf, struct rte_mbuf **m_seg,
3942 struct rte_mbuf *tx_pkt, struct hns3_tx_queue *txq)
3944 uint8_t max_non_tso_bd_num;
3945 struct rte_mbuf *new_pkt;
3948 if (hns3_pkt_is_tso(*m_seg))
3952 * If packet length is greater than HNS3_MAX_FRAME_LEN
3953 * driver support, the packet will be ignored.
3955 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) > HNS3_MAX_FRAME_LEN)) {
3956 txq->dfx_stats.over_length_pkt_cnt++;
3960 max_non_tso_bd_num = txq->max_non_tso_bd_num;
3961 if (unlikely(nb_buf > max_non_tso_bd_num)) {
3962 txq->dfx_stats.exceed_limit_bd_pkt_cnt++;
3963 ret = hns3_reassemble_tx_pkts(tx_pkt, &new_pkt,
3964 max_non_tso_bd_num);
3966 txq->dfx_stats.exceed_limit_bd_reassem_fail++;
3976 hns3_tx_free_buffer_simple(struct hns3_tx_queue *txq)
3978 struct hns3_entry *tx_entry;
3979 struct hns3_desc *desc;
3980 uint16_t tx_next_clean;
3984 if (HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) < txq->tx_rs_thresh)
3988 * All mbufs can be released only when the VLD bits of all
3989 * descriptors in a batch are cleared.
3991 tx_next_clean = (txq->next_to_clean + txq->tx_rs_thresh - 1) %
3993 desc = &txq->tx_ring[tx_next_clean];
3994 for (i = 0; i < txq->tx_rs_thresh; i++) {
3995 if (rte_le_to_cpu_16(desc->tx.tp_fe_sc_vld_ra_ri) &
3996 BIT(HNS3_TXD_VLD_B))
4001 tx_entry = &txq->sw_ring[txq->next_to_clean];
4003 if (txq->mbuf_fast_free_en) {
4004 rte_mempool_put_bulk(tx_entry->mbuf->pool,
4005 (void **)tx_entry, txq->tx_rs_thresh);
4006 for (i = 0; i < txq->tx_rs_thresh; i++)
4007 tx_entry[i].mbuf = NULL;
4011 for (i = 0; i < txq->tx_rs_thresh; i++)
4012 rte_prefetch0((tx_entry + i)->mbuf);
4013 for (i = 0; i < txq->tx_rs_thresh; i++, tx_entry++) {
4014 rte_mempool_put(tx_entry->mbuf->pool, tx_entry->mbuf);
4015 tx_entry->mbuf = NULL;
4019 txq->next_to_clean = (tx_next_clean + 1) % txq->nb_tx_desc;
4020 txq->tx_bd_ready += txq->tx_rs_thresh;
4025 hns3_tx_backup_1mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
4027 tx_entry->mbuf = pkts[0];
4031 hns3_tx_backup_4mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
4033 hns3_tx_backup_1mbuf(&tx_entry[0], &pkts[0]);
4034 hns3_tx_backup_1mbuf(&tx_entry[1], &pkts[1]);
4035 hns3_tx_backup_1mbuf(&tx_entry[2], &pkts[2]);
4036 hns3_tx_backup_1mbuf(&tx_entry[3], &pkts[3]);
4040 hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
4042 #define PER_LOOP_NUM 4
4043 uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
4047 for (i = 0; i < PER_LOOP_NUM; i++, txdp++, pkts++) {
4048 dma_addr = rte_mbuf_data_iova(*pkts);
4049 txdp->addr = rte_cpu_to_le_64(dma_addr);
4050 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
4051 txdp->tx.paylen_fd_dop_ol4cs = 0;
4052 txdp->tx.type_cs_vlan_tso_len = 0;
4053 txdp->tx.ol_type_vlan_len_msec = 0;
4054 if (unlikely((*pkts)->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST))
4055 bd_flag |= BIT(HNS3_TXD_TSYN_B);
4056 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
4061 hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
4063 uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
4066 dma_addr = rte_mbuf_data_iova(*pkts);
4067 txdp->addr = rte_cpu_to_le_64(dma_addr);
4068 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
4069 txdp->tx.paylen_fd_dop_ol4cs = 0;
4070 txdp->tx.type_cs_vlan_tso_len = 0;
4071 txdp->tx.ol_type_vlan_len_msec = 0;
4072 if (unlikely((*pkts)->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST))
4073 bd_flag |= BIT(HNS3_TXD_TSYN_B);
4074 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
4078 hns3_tx_fill_hw_ring(struct hns3_tx_queue *txq,
4079 struct rte_mbuf **pkts,
4082 #define PER_LOOP_NUM 4
4083 #define PER_LOOP_MASK (PER_LOOP_NUM - 1)
4084 struct hns3_desc *txdp = &txq->tx_ring[txq->next_to_use];
4085 struct hns3_entry *tx_entry = &txq->sw_ring[txq->next_to_use];
4086 const uint32_t mainpart = (nb_pkts & ((uint32_t)~PER_LOOP_MASK));
4087 const uint32_t leftover = (nb_pkts & ((uint32_t)PER_LOOP_MASK));
4090 for (i = 0; i < mainpart; i += PER_LOOP_NUM) {
4091 hns3_tx_backup_4mbuf(tx_entry + i, pkts + i);
4092 hns3_tx_setup_4bd(txdp + i, pkts + i);
4094 /* Increment bytes counter */
4096 for (j = 0; j < PER_LOOP_NUM; j++)
4097 txq->basic_stats.bytes += pkts[i + j]->pkt_len;
4099 if (unlikely(leftover > 0)) {
4100 for (i = 0; i < leftover; i++) {
4101 hns3_tx_backup_1mbuf(tx_entry + mainpart + i,
4102 pkts + mainpart + i);
4103 hns3_tx_setup_1bd(txdp + mainpart + i,
4104 pkts + mainpart + i);
4106 /* Increment bytes counter */
4107 txq->basic_stats.bytes += pkts[mainpart + i]->pkt_len;
4113 hns3_xmit_pkts_simple(void *tx_queue,
4114 struct rte_mbuf **tx_pkts,
4117 struct hns3_tx_queue *txq = tx_queue;
4120 hns3_tx_free_buffer_simple(txq);
4122 nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts);
4123 if (unlikely(nb_pkts == 0)) {
4124 if (txq->tx_bd_ready == 0)
4125 txq->dfx_stats.queue_full_cnt++;
4129 txq->tx_bd_ready -= nb_pkts;
4130 if (txq->next_to_use + nb_pkts > txq->nb_tx_desc) {
4131 nb_tx = txq->nb_tx_desc - txq->next_to_use;
4132 hns3_tx_fill_hw_ring(txq, tx_pkts, nb_tx);
4133 txq->next_to_use = 0;
4136 hns3_tx_fill_hw_ring(txq, tx_pkts + nb_tx, nb_pkts - nb_tx);
4137 txq->next_to_use += nb_pkts - nb_tx;
4139 hns3_write_txq_tail_reg(txq, nb_pkts);
4145 hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
4147 struct hns3_tx_queue *txq = tx_queue;
4148 struct hns3_entry *tx_bak_pkt;
4149 struct hns3_desc *tx_ring;
4150 struct rte_mbuf *tx_pkt;
4151 struct rte_mbuf *m_seg;
4152 struct hns3_desc *desc;
4153 uint32_t nb_hold = 0;
4154 uint16_t tx_next_use;
4155 uint16_t tx_pkt_num;
4161 if (txq->tx_bd_ready < txq->tx_free_thresh)
4162 (void)hns3_tx_free_useless_buffer(txq);
4164 tx_next_use = txq->next_to_use;
4165 tx_bd_max = txq->nb_tx_desc;
4166 tx_pkt_num = nb_pkts;
4167 tx_ring = txq->tx_ring;
4170 tx_bak_pkt = &txq->sw_ring[tx_next_use];
4171 for (nb_tx = 0; nb_tx < tx_pkt_num; nb_tx++) {
4172 tx_pkt = *tx_pkts++;
4174 nb_buf = tx_pkt->nb_segs;
4176 if (nb_buf > txq->tx_bd_ready) {
4177 /* Try to release the required MBUF, but avoid releasing
4178 * all MBUFs, otherwise, the MBUFs will be released for
4179 * a long time and may cause jitter.
4181 if (hns3_tx_free_required_buffer(txq, nb_buf) != 0) {
4182 txq->dfx_stats.queue_full_cnt++;
4188 * If packet length is less than minimum packet length supported
4189 * by hardware in Tx direction, driver need to pad it to avoid
4192 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) <
4193 txq->min_tx_pkt_len)) {
4197 add_len = txq->min_tx_pkt_len -
4198 rte_pktmbuf_pkt_len(tx_pkt);
4199 appended = rte_pktmbuf_append(tx_pkt, add_len);
4200 if (appended == NULL) {
4201 txq->dfx_stats.pkt_padding_fail_cnt++;
4205 memset(appended, 0, add_len);
4210 if (hns3_check_non_tso_pkt(nb_buf, &m_seg, tx_pkt, txq))
4213 if (hns3_parse_cksum(txq, tx_next_use, m_seg))
4217 desc = &tx_ring[tx_next_use];
4220 * If the packet is divided into multiple Tx Buffer Descriptors,
4221 * only need to fill vlan, paylen and tso into the first Tx
4222 * Buffer Descriptor.
4224 hns3_fill_first_desc(txq, desc, m_seg);
4227 desc = &tx_ring[tx_next_use];
4229 * Fill valid bits, DMA address and data length for each
4230 * Tx Buffer Descriptor.
4232 hns3_fill_per_desc(desc, m_seg);
4233 tx_bak_pkt->mbuf = m_seg;
4234 m_seg = m_seg->next;
4237 if (tx_next_use >= tx_bd_max) {
4239 tx_bak_pkt = txq->sw_ring;
4243 } while (m_seg != NULL);
4245 /* Add end flag for the last Tx Buffer Descriptor */
4246 desc->tx.tp_fe_sc_vld_ra_ri |=
4247 rte_cpu_to_le_16(BIT(HNS3_TXD_FE_B));
4249 /* Increment bytes counter */
4250 txq->basic_stats.bytes += tx_pkt->pkt_len;
4252 txq->next_to_use = tx_next_use;
4253 txq->tx_bd_ready -= i;
4259 hns3_write_txq_tail_reg(txq, nb_hold);
4265 hns3_tx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
4271 hns3_xmit_pkts_vec(__rte_unused void *tx_queue,
4272 __rte_unused struct rte_mbuf **tx_pkts,
4273 __rte_unused uint16_t nb_pkts)
4279 hns3_xmit_pkts_vec_sve(void __rte_unused * tx_queue,
4280 struct rte_mbuf __rte_unused **tx_pkts,
4281 uint16_t __rte_unused nb_pkts)
4287 hns3_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
4288 struct rte_eth_burst_mode *mode)
4290 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
4291 const char *info = NULL;
4293 if (pkt_burst == hns3_xmit_pkts_simple)
4294 info = "Scalar Simple";
4295 else if (pkt_burst == hns3_xmit_pkts)
4297 else if (pkt_burst == hns3_xmit_pkts_vec)
4298 info = "Vector Neon";
4299 else if (pkt_burst == hns3_xmit_pkts_vec_sve)
4300 info = "Vector Sve";
4305 snprintf(mode->info, sizeof(mode->info), "%s", info);
4311 hns3_tx_check_simple_support(struct rte_eth_dev *dev)
4313 uint64_t offloads = dev->data->dev_conf.txmode.offloads;
4315 return (offloads == (offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE));
4319 hns3_get_tx_prep_needed(struct rte_eth_dev *dev)
4321 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4323 /* always perform tx_prepare when debug */
4326 #define HNS3_DEV_TX_CSKUM_TSO_OFFLOAD_MASK (\
4327 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | \
4328 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | \
4329 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \
4330 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | \
4331 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
4332 RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM | \
4333 RTE_ETH_TX_OFFLOAD_TCP_TSO | \
4334 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | \
4335 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | \
4336 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO)
4338 uint64_t tx_offload = dev->data->dev_conf.txmode.offloads;
4339 if (tx_offload & HNS3_DEV_TX_CSKUM_TSO_OFFLOAD_MASK)
4347 hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep)
4349 struct hns3_adapter *hns = dev->data->dev_private;
4350 bool vec_allowed, sve_allowed, simple_allowed;
4351 bool vec_support, tx_prepare_needed;
4353 vec_support = hns3_tx_check_vec_support(dev) == 0;
4354 vec_allowed = vec_support && hns3_get_default_vec_support();
4355 sve_allowed = vec_support && hns3_get_sve_support();
4356 simple_allowed = hns3_tx_check_simple_support(dev);
4357 tx_prepare_needed = hns3_get_tx_prep_needed(dev);
4361 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed)
4362 return hns3_xmit_pkts_vec;
4363 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed)
4364 return hns3_xmit_pkts_vec_sve;
4365 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed)
4366 return hns3_xmit_pkts_simple;
4367 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_COMMON) {
4368 if (tx_prepare_needed)
4369 *prep = hns3_prep_pkts;
4370 return hns3_xmit_pkts;
4374 return hns3_xmit_pkts_vec;
4376 return hns3_xmit_pkts_simple;
4378 if (tx_prepare_needed)
4379 *prep = hns3_prep_pkts;
4380 return hns3_xmit_pkts;
4384 hns3_trace_rxtx_function(struct rte_eth_dev *dev)
4386 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4387 struct rte_eth_burst_mode rx_mode;
4388 struct rte_eth_burst_mode tx_mode;
4390 memset(&rx_mode, 0, sizeof(rx_mode));
4391 memset(&tx_mode, 0, sizeof(tx_mode));
4392 (void)hns3_rx_burst_mode_get(dev, 0, &rx_mode);
4393 (void)hns3_tx_burst_mode_get(dev, 0, &tx_mode);
4395 hns3_dbg(hw, "using rx_pkt_burst: %s, tx_pkt_burst: %s.",
4396 rx_mode.info, tx_mode.info);
4400 hns3_eth_dev_fp_ops_config(const struct rte_eth_dev *dev)
4402 struct rte_eth_fp_ops *fpo = rte_eth_fp_ops;
4403 uint16_t port_id = dev->data->port_id;
4405 fpo[port_id].rx_pkt_burst = dev->rx_pkt_burst;
4406 fpo[port_id].tx_pkt_burst = dev->tx_pkt_burst;
4407 fpo[port_id].tx_pkt_prepare = dev->tx_pkt_prepare;
4408 fpo[port_id].rx_descriptor_status = dev->rx_descriptor_status;
4409 fpo[port_id].tx_descriptor_status = dev->tx_descriptor_status;
4413 hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)
4415 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
4416 struct hns3_adapter *hns = eth_dev->data->dev_private;
4417 eth_tx_prep_t prep = NULL;
4419 if (hns->hw.adapter_state == HNS3_NIC_STARTED &&
4420 __atomic_load_n(&hns->hw.reset.resetting, __ATOMIC_RELAXED) == 0) {
4421 eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev);
4422 eth_dev->rx_descriptor_status = hns3_dev_rx_descriptor_status;
4423 eth_dev->tx_pkt_burst = hw->set_link_down ?
4424 rte_eth_pkt_burst_dummy :
4425 hns3_get_tx_function(eth_dev, &prep);
4426 eth_dev->tx_pkt_prepare = prep;
4427 eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status;
4428 hns3_trace_rxtx_function(eth_dev);
4430 eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy;
4431 eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
4432 eth_dev->tx_pkt_prepare = NULL;
4435 hns3_eth_dev_fp_ops_config(eth_dev);
4439 hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
4440 struct rte_eth_rxq_info *qinfo)
4442 struct hns3_rx_queue *rxq = dev->data->rx_queues[queue_id];
4444 qinfo->mp = rxq->mb_pool;
4445 qinfo->nb_desc = rxq->nb_rx_desc;
4446 qinfo->scattered_rx = dev->data->scattered_rx;
4447 /* Report the HW Rx buffer length to user */
4448 qinfo->rx_buf_size = rxq->rx_buf_len;
4451 * If there are no available Rx buffer descriptors, incoming packets
4452 * are always dropped by hardware based on hns3 network engine.
4454 qinfo->conf.rx_drop_en = 1;
4455 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
4456 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
4457 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
4461 hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
4462 struct rte_eth_txq_info *qinfo)
4464 struct hns3_tx_queue *txq = dev->data->tx_queues[queue_id];
4466 qinfo->nb_desc = txq->nb_tx_desc;
4467 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
4468 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
4469 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
4470 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
4474 hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4476 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4477 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id];
4478 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4481 if (!hns3_dev_get_support(hw, INDEP_TXRX))
4484 rte_spinlock_lock(&hw->lock);
4485 ret = hns3_reset_queue(hw, rx_queue_id, HNS3_RING_TYPE_RX);
4487 hns3_err(hw, "fail to reset Rx queue %u, ret = %d.",
4489 rte_spinlock_unlock(&hw->lock);
4493 ret = hns3_init_rxq(hns, rx_queue_id);
4495 hns3_err(hw, "fail to init Rx queue %u, ret = %d.",
4497 rte_spinlock_unlock(&hw->lock);
4501 hns3_enable_rxq(rxq, true);
4502 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
4503 rte_spinlock_unlock(&hw->lock);
4509 hns3_reset_sw_rxq(struct hns3_rx_queue *rxq)
4511 rxq->next_to_use = 0;
4512 rxq->rx_rearm_start = 0;
4513 rxq->rx_free_hold = 0;
4514 rxq->rx_rearm_nb = 0;
4515 rxq->pkt_first_seg = NULL;
4516 rxq->pkt_last_seg = NULL;
4517 memset(&rxq->rx_ring[0], 0, rxq->nb_rx_desc * sizeof(struct hns3_desc));
4518 hns3_rxq_vec_setup(rxq);
4522 hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4524 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4525 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id];
4527 if (!hns3_dev_get_support(hw, INDEP_TXRX))
4530 rte_spinlock_lock(&hw->lock);
4531 hns3_enable_rxq(rxq, false);
4533 hns3_rx_queue_release_mbufs(rxq);
4535 hns3_reset_sw_rxq(rxq);
4536 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
4537 rte_spinlock_unlock(&hw->lock);
4543 hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4545 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4546 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id];
4549 if (!hns3_dev_get_support(hw, INDEP_TXRX))
4552 rte_spinlock_lock(&hw->lock);
4553 ret = hns3_reset_queue(hw, tx_queue_id, HNS3_RING_TYPE_TX);
4555 hns3_err(hw, "fail to reset Tx queue %u, ret = %d.",
4557 rte_spinlock_unlock(&hw->lock);
4562 hns3_enable_txq(txq, true);
4563 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
4564 rte_spinlock_unlock(&hw->lock);
4570 hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4572 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4573 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id];
4575 if (!hns3_dev_get_support(hw, INDEP_TXRX))
4578 rte_spinlock_lock(&hw->lock);
4579 hns3_enable_txq(txq, false);
4580 hns3_tx_queue_release_mbufs(txq);
4582 * All the mbufs in sw_ring are released and all the pointers in sw_ring
4583 * are set to NULL. If this queue is still called by upper layer,
4584 * residual SW status of this txq may cause these pointers in sw_ring
4585 * which have been set to NULL to be released again. To avoid it,
4589 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
4590 rte_spinlock_unlock(&hw->lock);
4596 hns3_tx_done_cleanup_full(struct hns3_tx_queue *txq, uint32_t free_cnt)
4601 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
4602 free_cnt = txq->nb_tx_desc;
4604 if (txq->tx_rs_thresh == 0)
4607 round_cnt = rounddown(free_cnt, txq->tx_rs_thresh);
4608 for (idx = 0; idx < round_cnt; idx += txq->tx_rs_thresh) {
4609 if (hns3_tx_free_useless_buffer(txq) != 0)
4617 hns3_tx_done_cleanup(void *txq, uint32_t free_cnt)
4619 struct hns3_tx_queue *q = (struct hns3_tx_queue *)txq;
4620 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
4622 if (dev->tx_pkt_burst == hns3_xmit_pkts)
4623 return hns3_tx_done_cleanup_full(q, free_cnt);
4624 else if (dev->tx_pkt_burst == rte_eth_pkt_burst_dummy)
4631 hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
4633 volatile struct hns3_desc *rxdp;
4634 struct hns3_rx_queue *rxq;
4635 struct rte_eth_dev *dev;
4636 uint32_t bd_base_info;
4639 rxq = (struct hns3_rx_queue *)rx_queue;
4640 if (offset >= rxq->nb_rx_desc)
4643 desc_id = (rxq->next_to_use + offset) % rxq->nb_rx_desc;
4644 rxdp = &rxq->rx_ring[desc_id];
4645 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
4646 dev = &rte_eth_devices[rxq->port_id];
4647 if (dev->rx_pkt_burst == hns3_recv_pkts_simple ||
4648 dev->rx_pkt_burst == hns3_recv_scattered_pkts) {
4649 if (offset >= rxq->nb_rx_desc - rxq->rx_free_hold)
4650 return RTE_ETH_RX_DESC_UNAVAIL;
4651 } else if (dev->rx_pkt_burst == hns3_recv_pkts_vec ||
4652 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve) {
4653 if (offset >= rxq->nb_rx_desc - rxq->rx_rearm_nb)
4654 return RTE_ETH_RX_DESC_UNAVAIL;
4656 return RTE_ETH_RX_DESC_UNAVAIL;
4659 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
4660 return RTE_ETH_RX_DESC_AVAIL;
4662 return RTE_ETH_RX_DESC_DONE;
4666 hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
4668 volatile struct hns3_desc *txdp;
4669 struct hns3_tx_queue *txq;
4670 struct rte_eth_dev *dev;
4673 txq = (struct hns3_tx_queue *)tx_queue;
4674 if (offset >= txq->nb_tx_desc)
4677 dev = &rte_eth_devices[txq->port_id];
4678 if (dev->tx_pkt_burst != hns3_xmit_pkts_simple &&
4679 dev->tx_pkt_burst != hns3_xmit_pkts &&
4680 dev->tx_pkt_burst != hns3_xmit_pkts_vec_sve &&
4681 dev->tx_pkt_burst != hns3_xmit_pkts_vec)
4682 return RTE_ETH_TX_DESC_UNAVAIL;
4684 desc_id = (txq->next_to_use + offset) % txq->nb_tx_desc;
4685 txdp = &txq->tx_ring[desc_id];
4686 if (txdp->tx.tp_fe_sc_vld_ra_ri & rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)))
4687 return RTE_ETH_TX_DESC_FULL;
4689 return RTE_ETH_TX_DESC_DONE;
4693 hns3_rx_queue_count(void *rx_queue)
4696 * Number of BDs that have been processed by the driver
4697 * but have not been notified to the hardware.
4699 uint32_t driver_hold_bd_num;
4700 struct hns3_rx_queue *rxq;
4701 const struct rte_eth_dev *dev;
4705 dev = &rte_eth_devices[rxq->port_id];
4707 fbd_num = hns3_read_dev(rxq, HNS3_RING_RX_FBDNUM_REG);
4708 if (dev->rx_pkt_burst == hns3_recv_pkts_vec ||
4709 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve)
4710 driver_hold_bd_num = rxq->rx_rearm_nb;
4712 driver_hold_bd_num = rxq->rx_free_hold;
4714 if (fbd_num <= driver_hold_bd_num)
4717 return fbd_num - driver_hold_bd_num;
4721 hns3_enable_rxd_adv_layout(struct hns3_hw *hw)
4724 * If the hardware support rxd advanced layout, then driver enable it
4727 if (hns3_dev_get_support(hw, RXD_ADV_LAYOUT))
4728 hns3_write_dev(hw, HNS3_RXD_ADV_LAYOUT_EN_REG, 1);
4732 hns3_stop_tx_datapath(struct rte_eth_dev *dev)
4734 dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
4735 dev->tx_pkt_prepare = NULL;
4736 hns3_eth_dev_fp_ops_config(dev);
4738 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
4742 /* Disable tx datapath on secondary process. */
4743 hns3_mp_req_stop_tx(dev);
4744 /* Prevent crashes when queues are still in use. */
4745 rte_delay_ms(dev->data->nb_tx_queues);
4749 hns3_start_tx_datapath(struct rte_eth_dev *dev)
4751 eth_tx_prep_t prep = NULL;
4753 dev->tx_pkt_burst = hns3_get_tx_function(dev, &prep);
4754 dev->tx_pkt_prepare = prep;
4755 hns3_eth_dev_fp_ops_config(dev);
4757 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
4760 hns3_mp_req_start_tx(dev);