1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
11 #include <rte_bus_pci.h>
12 #include <rte_byteorder.h>
13 #include <rte_common.h>
14 #include <rte_cycles.h>
17 #include <rte_ether.h>
18 #include <rte_vxlan.h>
19 #include <rte_ethdev_driver.h>
24 #include <rte_malloc.h>
27 #include "hns3_ethdev.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_regs.h"
30 #include "hns3_logs.h"
32 #define HNS3_CFG_DESC_NUM(num) ((num) / 8 - 1)
33 #define DEFAULT_RX_FREE_THRESH 32
36 hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq)
40 /* Note: Fake rx queue will not enter here */
42 for (i = 0; i < rxq->nb_rx_desc; i++) {
43 if (rxq->sw_ring[i].mbuf) {
44 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
45 rxq->sw_ring[i].mbuf = NULL;
52 hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq)
56 /* Note: Fake rx queue will not enter here */
58 for (i = 0; i < txq->nb_tx_desc; i++) {
59 if (txq->sw_ring[i].mbuf) {
60 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
61 txq->sw_ring[i].mbuf = NULL;
68 hns3_rx_queue_release(void *queue)
70 struct hns3_rx_queue *rxq = queue;
72 hns3_rx_queue_release_mbufs(rxq);
74 rte_memzone_free(rxq->mz);
76 rte_free(rxq->sw_ring);
82 hns3_tx_queue_release(void *queue)
84 struct hns3_tx_queue *txq = queue;
86 hns3_tx_queue_release_mbufs(txq);
88 rte_memzone_free(txq->mz);
90 rte_free(txq->sw_ring);
96 hns3_dev_rx_queue_release(void *queue)
98 struct hns3_rx_queue *rxq = queue;
99 struct hns3_adapter *hns;
105 rte_spinlock_lock(&hns->hw.lock);
106 hns3_rx_queue_release(queue);
107 rte_spinlock_unlock(&hns->hw.lock);
111 hns3_dev_tx_queue_release(void *queue)
113 struct hns3_tx_queue *txq = queue;
114 struct hns3_adapter *hns;
120 rte_spinlock_lock(&hns->hw.lock);
121 hns3_tx_queue_release(queue);
122 rte_spinlock_unlock(&hns->hw.lock);
126 hns3_fake_rx_queue_release(struct hns3_rx_queue *queue)
128 struct hns3_rx_queue *rxq = queue;
129 struct hns3_adapter *hns;
139 if (hw->fkq_data.rx_queues[idx]) {
140 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
141 hw->fkq_data.rx_queues[idx] = NULL;
144 /* free fake rx queue arrays */
145 if (idx == (hw->fkq_data.nb_fake_rx_queues - 1)) {
146 hw->fkq_data.nb_fake_rx_queues = 0;
147 rte_free(hw->fkq_data.rx_queues);
148 hw->fkq_data.rx_queues = NULL;
153 hns3_fake_tx_queue_release(struct hns3_tx_queue *queue)
155 struct hns3_tx_queue *txq = queue;
156 struct hns3_adapter *hns;
166 if (hw->fkq_data.tx_queues[idx]) {
167 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
168 hw->fkq_data.tx_queues[idx] = NULL;
171 /* free fake tx queue arrays */
172 if (idx == (hw->fkq_data.nb_fake_tx_queues - 1)) {
173 hw->fkq_data.nb_fake_tx_queues = 0;
174 rte_free(hw->fkq_data.tx_queues);
175 hw->fkq_data.tx_queues = NULL;
180 hns3_free_rx_queues(struct rte_eth_dev *dev)
182 struct hns3_adapter *hns = dev->data->dev_private;
183 struct hns3_fake_queue_data *fkq_data;
184 struct hns3_hw *hw = &hns->hw;
188 nb_rx_q = hw->data->nb_rx_queues;
189 for (i = 0; i < nb_rx_q; i++) {
190 if (dev->data->rx_queues[i]) {
191 hns3_rx_queue_release(dev->data->rx_queues[i]);
192 dev->data->rx_queues[i] = NULL;
196 /* Free fake Rx queues */
197 fkq_data = &hw->fkq_data;
198 for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) {
199 if (fkq_data->rx_queues[i])
200 hns3_fake_rx_queue_release(fkq_data->rx_queues[i]);
205 hns3_free_tx_queues(struct rte_eth_dev *dev)
207 struct hns3_adapter *hns = dev->data->dev_private;
208 struct hns3_fake_queue_data *fkq_data;
209 struct hns3_hw *hw = &hns->hw;
213 nb_tx_q = hw->data->nb_tx_queues;
214 for (i = 0; i < nb_tx_q; i++) {
215 if (dev->data->tx_queues[i]) {
216 hns3_tx_queue_release(dev->data->tx_queues[i]);
217 dev->data->tx_queues[i] = NULL;
221 /* Free fake Tx queues */
222 fkq_data = &hw->fkq_data;
223 for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) {
224 if (fkq_data->tx_queues[i])
225 hns3_fake_tx_queue_release(fkq_data->tx_queues[i]);
230 hns3_free_all_queues(struct rte_eth_dev *dev)
232 hns3_free_rx_queues(dev);
233 hns3_free_tx_queues(dev);
237 hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq)
239 struct rte_mbuf *mbuf;
243 for (i = 0; i < rxq->nb_rx_desc; i++) {
244 mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
245 if (unlikely(mbuf == NULL)) {
246 hns3_err(hw, "Failed to allocate RXD[%d] for rx queue!",
248 hns3_rx_queue_release_mbufs(rxq);
252 rte_mbuf_refcnt_set(mbuf, 1);
254 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
256 mbuf->port = rxq->port_id;
258 rxq->sw_ring[i].mbuf = mbuf;
259 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
260 rxq->rx_ring[i].addr = dma_addr;
261 rxq->rx_ring[i].rx.bd_base_info = 0;
268 hns3_buf_size2type(uint32_t buf_size)
274 bd_size_type = HNS3_BD_SIZE_512_TYPE;
277 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
280 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
283 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
290 hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)
292 uint32_t rx_buf_len = rxq->rx_buf_len;
293 uint64_t dma_addr = rxq->rx_ring_phys_addr;
295 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);
296 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,
297 (uint32_t)((dma_addr >> 31) >> 1));
299 hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,
300 hns3_buf_size2type(rx_buf_len));
301 hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG,
302 HNS3_CFG_DESC_NUM(rxq->nb_rx_desc));
306 hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)
308 uint64_t dma_addr = txq->tx_ring_phys_addr;
310 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);
311 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,
312 (uint32_t)((dma_addr >> 31) >> 1));
314 hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,
315 HNS3_CFG_DESC_NUM(txq->nb_tx_desc));
319 hns3_enable_all_queues(struct hns3_hw *hw, bool en)
321 uint16_t nb_rx_q = hw->data->nb_rx_queues;
322 uint16_t nb_tx_q = hw->data->nb_tx_queues;
323 struct hns3_rx_queue *rxq;
324 struct hns3_tx_queue *txq;
328 for (i = 0; i < hw->cfg_max_queues; i++) {
330 rxq = hw->data->rx_queues[i];
332 rxq = hw->fkq_data.rx_queues[i - nb_rx_q];
334 txq = hw->data->tx_queues[i];
336 txq = hw->fkq_data.tx_queues[i - nb_tx_q];
337 if (rxq == NULL || txq == NULL ||
338 (en && (rxq->rx_deferred_start || txq->tx_deferred_start)))
341 rcb_reg = hns3_read_dev(rxq, HNS3_RING_EN_REG);
343 rcb_reg |= BIT(HNS3_RING_EN_B);
345 rcb_reg &= ~BIT(HNS3_RING_EN_B);
346 hns3_write_dev(rxq, HNS3_RING_EN_REG, rcb_reg);
351 hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable)
353 struct hns3_cfg_com_tqp_queue_cmd *req;
354 struct hns3_cmd_desc desc;
357 req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data;
359 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false);
360 req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
362 hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0);
364 ret = hns3_cmd_send(hw, &desc, 1);
366 hns3_err(hw, "TQP enable fail, ret = %d", ret);
372 hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable)
374 struct hns3_reset_tqp_queue_cmd *req;
375 struct hns3_cmd_desc desc;
378 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false);
380 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
381 req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
382 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
384 ret = hns3_cmd_send(hw, &desc, 1);
386 hns3_err(hw, "Send tqp reset cmd error, ret = %d", ret);
392 hns3_get_reset_status(struct hns3_hw *hw, uint16_t queue_id)
394 struct hns3_reset_tqp_queue_cmd *req;
395 struct hns3_cmd_desc desc;
398 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true);
400 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
401 req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
403 ret = hns3_cmd_send(hw, &desc, 1);
405 hns3_err(hw, "Get reset status error, ret =%d", ret);
409 return hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
413 hns3_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
415 #define HNS3_TQP_RESET_TRY_MS 200
420 ret = hns3_tqp_enable(hw, queue_id, false);
425 * In current version VF is not supported when PF is driven by DPDK
426 * driver, all task queue pairs are mapped to PF function, so PF's queue
427 * id is equals to the global queue id in PF range.
429 ret = hns3_send_reset_tqp_cmd(hw, queue_id, true);
431 hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret);
435 end = get_timeofday_ms() + HNS3_TQP_RESET_TRY_MS;
437 /* Wait for tqp hw reset */
438 rte_delay_ms(HNS3_POLL_RESPONE_MS);
439 reset_status = hns3_get_reset_status(hw, queue_id);
444 } while (get_timeofday_ms() < end);
447 hns3_err(hw, "Reset TQP fail, ret = %d", ret);
451 ret = hns3_send_reset_tqp_cmd(hw, queue_id, false);
453 hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret);
459 hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
464 /* Disable VF's queue before send queue reset msg to PF */
465 ret = hns3_tqp_enable(hw, queue_id, false);
469 memcpy(msg_data, &queue_id, sizeof(uint16_t));
471 return hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
472 sizeof(msg_data), true, NULL, 0);
476 hns3_reset_queue(struct hns3_adapter *hns, uint16_t queue_id)
478 struct hns3_hw *hw = &hns->hw;
480 return hns3vf_reset_tqp(hw, queue_id);
482 return hns3_reset_tqp(hw, queue_id);
486 hns3_reset_all_queues(struct hns3_adapter *hns)
488 struct hns3_hw *hw = &hns->hw;
491 for (i = 0; i < hw->cfg_max_queues; i++) {
492 ret = hns3_reset_queue(hns, i);
494 hns3_err(hw, "Failed to reset No.%d queue: %d", i, ret);
502 hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
503 uint8_t gl_idx, uint16_t gl_value)
505 uint32_t offset[] = {HNS3_TQP_INTR_GL0_REG,
506 HNS3_TQP_INTR_GL1_REG,
507 HNS3_TQP_INTR_GL2_REG};
508 uint32_t addr, value;
510 if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX)
513 addr = offset[gl_idx] + queue_id * HNS3_TQP_INTR_REG_SIZE;
514 value = HNS3_GL_USEC_TO_REG(gl_value);
516 hns3_write_dev(hw, addr, value);
520 hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value)
522 uint32_t addr, value;
524 if (rl_value > HNS3_TQP_INTR_RL_MAX)
527 addr = HNS3_TQP_INTR_RL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
528 value = HNS3_RL_USEC_TO_REG(rl_value);
530 value |= HNS3_TQP_INTR_RL_ENABLE_MASK;
532 hns3_write_dev(hw, addr, value);
536 hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en)
538 uint32_t addr, value;
540 addr = HNS3_TQP_INTR_CTRL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
543 hns3_write_dev(hw, addr, value);
547 hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
549 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
550 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
551 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
553 if (dev->data->dev_conf.intr_conf.rxq == 0)
556 hns3_queue_intr_enable(hw, queue_id, true);
558 return rte_intr_ack(intr_handle);
562 hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
564 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
566 if (dev->data->dev_conf.intr_conf.rxq == 0)
569 hns3_queue_intr_enable(hw, queue_id, false);
575 hns3_dev_rx_queue_start(struct hns3_adapter *hns, uint16_t idx)
577 struct hns3_hw *hw = &hns->hw;
578 struct hns3_rx_queue *rxq;
581 PMD_INIT_FUNC_TRACE();
583 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx];
584 ret = hns3_alloc_rx_queue_mbufs(hw, rxq);
586 hns3_err(hw, "Failed to alloc mbuf for No.%d rx queue: %d",
591 rxq->next_to_use = 0;
592 rxq->next_to_clean = 0;
594 hns3_init_rx_queue_hw(rxq);
600 hns3_fake_rx_queue_start(struct hns3_adapter *hns, uint16_t idx)
602 struct hns3_hw *hw = &hns->hw;
603 struct hns3_rx_queue *rxq;
605 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx];
606 rxq->next_to_use = 0;
607 rxq->next_to_clean = 0;
609 hns3_init_rx_queue_hw(rxq);
613 hns3_init_tx_queue(struct hns3_tx_queue *queue)
615 struct hns3_tx_queue *txq = queue;
616 struct hns3_desc *desc;
621 for (i = 0; i < txq->nb_tx_desc; i++) {
622 desc->tx.tp_fe_sc_vld_ra_ri = 0;
626 txq->next_to_use = 0;
627 txq->next_to_clean = 0;
628 txq->tx_bd_ready = txq->nb_tx_desc - 1;
629 hns3_init_tx_queue_hw(txq);
633 hns3_dev_tx_queue_start(struct hns3_adapter *hns, uint16_t idx)
635 struct hns3_hw *hw = &hns->hw;
636 struct hns3_tx_queue *txq;
638 txq = (struct hns3_tx_queue *)hw->data->tx_queues[idx];
639 hns3_init_tx_queue(txq);
643 hns3_fake_tx_queue_start(struct hns3_adapter *hns, uint16_t idx)
645 struct hns3_hw *hw = &hns->hw;
646 struct hns3_tx_queue *txq;
648 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[idx];
649 hns3_init_tx_queue(txq);
653 hns3_init_tx_ring_tc(struct hns3_adapter *hns)
655 struct hns3_hw *hw = &hns->hw;
656 struct hns3_tx_queue *txq;
659 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
660 struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i];
663 if (!tc_queue->enable)
666 for (j = 0; j < tc_queue->tqp_count; j++) {
667 num = tc_queue->tqp_offset + j;
668 txq = (struct hns3_tx_queue *)hw->data->tx_queues[num];
672 hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc);
678 hns3_start_rx_queues(struct hns3_adapter *hns)
680 struct hns3_hw *hw = &hns->hw;
681 struct hns3_rx_queue *rxq;
685 /* Initialize RSS for queues */
686 ret = hns3_config_rss(hns);
688 hns3_err(hw, "Failed to configure rss %d", ret);
692 for (i = 0; i < hw->data->nb_rx_queues; i++) {
693 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i];
694 if (rxq == NULL || rxq->rx_deferred_start)
696 ret = hns3_dev_rx_queue_start(hns, i);
698 hns3_err(hw, "Failed to start No.%d rx queue: %d", i,
704 for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++) {
705 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[i];
706 if (rxq == NULL || rxq->rx_deferred_start)
708 hns3_fake_rx_queue_start(hns, i);
713 for (j = 0; j < i; j++) {
714 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j];
715 hns3_rx_queue_release_mbufs(rxq);
722 hns3_start_tx_queues(struct hns3_adapter *hns)
724 struct hns3_hw *hw = &hns->hw;
725 struct hns3_tx_queue *txq;
728 for (i = 0; i < hw->data->nb_tx_queues; i++) {
729 txq = (struct hns3_tx_queue *)hw->data->tx_queues[i];
730 if (txq == NULL || txq->tx_deferred_start)
732 hns3_dev_tx_queue_start(hns, i);
735 for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) {
736 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i];
737 if (txq == NULL || txq->tx_deferred_start)
739 hns3_fake_tx_queue_start(hns, i);
742 hns3_init_tx_ring_tc(hns);
746 hns3_start_queues(struct hns3_adapter *hns, bool reset_queue)
748 struct hns3_hw *hw = &hns->hw;
752 ret = hns3_reset_all_queues(hns);
754 hns3_err(hw, "Failed to reset all queues %d", ret);
759 ret = hns3_start_rx_queues(hns);
761 hns3_err(hw, "Failed to start rx queues: %d", ret);
765 hns3_start_tx_queues(hns);
766 hns3_enable_all_queues(hw, true);
772 hns3_stop_queues(struct hns3_adapter *hns, bool reset_queue)
774 struct hns3_hw *hw = &hns->hw;
777 hns3_enable_all_queues(hw, false);
779 ret = hns3_reset_all_queues(hns);
781 hns3_err(hw, "Failed to reset all queues %d", ret);
789 hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev,
790 struct hns3_queue_info *q_info)
792 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
793 const struct rte_memzone *rx_mz;
794 struct hns3_rx_queue *rxq;
795 unsigned int rx_desc;
797 rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue),
798 RTE_CACHE_LINE_SIZE, q_info->socket_id);
800 hns3_err(hw, "Failed to allocate memory for No.%d rx ring!",
805 /* Allocate rx ring hardware descriptors. */
806 rxq->queue_id = q_info->idx;
807 rxq->nb_rx_desc = q_info->nb_desc;
808 rx_desc = rxq->nb_rx_desc * sizeof(struct hns3_desc);
809 rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
810 rx_desc, HNS3_RING_BASE_ALIGN,
813 hns3_err(hw, "Failed to reserve DMA memory for No.%d rx ring!",
815 hns3_rx_queue_release(rxq);
819 rxq->rx_ring = (struct hns3_desc *)rx_mz->addr;
820 rxq->rx_ring_phys_addr = rx_mz->iova;
822 hns3_dbg(hw, "No.%d rx descriptors iova 0x%" PRIx64, q_info->idx,
823 rxq->rx_ring_phys_addr);
829 hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
830 uint16_t nb_desc, unsigned int socket_id)
832 struct hns3_adapter *hns = dev->data->dev_private;
833 struct hns3_hw *hw = &hns->hw;
834 struct hns3_queue_info q_info;
835 struct hns3_rx_queue *rxq;
838 if (hw->fkq_data.rx_queues[idx]) {
839 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
840 hw->fkq_data.rx_queues[idx] = NULL;
844 q_info.socket_id = socket_id;
845 q_info.nb_desc = nb_desc;
846 q_info.type = "hns3 fake RX queue";
847 q_info.ring_name = "rx_fake_ring";
848 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
850 hns3_err(hw, "Failed to setup No.%d fake rx ring.", idx);
854 /* Don't need alloc sw_ring, because upper applications don't use it */
858 rxq->rx_deferred_start = false;
859 rxq->port_id = dev->data->port_id;
860 rxq->configured = true;
861 nb_rx_q = dev->data->nb_rx_queues;
862 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
863 (nb_rx_q + idx) * HNS3_TQP_REG_SIZE);
864 rxq->rx_buf_len = hw->rx_buf_len;
866 rte_spinlock_lock(&hw->lock);
867 hw->fkq_data.rx_queues[idx] = rxq;
868 rte_spinlock_unlock(&hw->lock);
874 hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev,
875 struct hns3_queue_info *q_info)
877 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
878 const struct rte_memzone *tx_mz;
879 struct hns3_tx_queue *txq;
880 struct hns3_desc *desc;
881 unsigned int tx_desc;
884 txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue),
885 RTE_CACHE_LINE_SIZE, q_info->socket_id);
887 hns3_err(hw, "Failed to allocate memory for No.%d tx ring!",
892 /* Allocate tx ring hardware descriptors. */
893 txq->queue_id = q_info->idx;
894 txq->nb_tx_desc = q_info->nb_desc;
895 tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc);
896 tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
897 tx_desc, HNS3_RING_BASE_ALIGN,
900 hns3_err(hw, "Failed to reserve DMA memory for No.%d tx ring!",
902 hns3_tx_queue_release(txq);
906 txq->tx_ring = (struct hns3_desc *)tx_mz->addr;
907 txq->tx_ring_phys_addr = tx_mz->iova;
909 hns3_dbg(hw, "No.%d tx descriptors iova 0x%" PRIx64, q_info->idx,
910 txq->tx_ring_phys_addr);
914 for (i = 0; i < txq->nb_tx_desc; i++) {
915 desc->tx.tp_fe_sc_vld_ra_ri = 0;
923 hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
924 uint16_t nb_desc, unsigned int socket_id)
926 struct hns3_adapter *hns = dev->data->dev_private;
927 struct hns3_hw *hw = &hns->hw;
928 struct hns3_queue_info q_info;
929 struct hns3_tx_queue *txq;
932 if (hw->fkq_data.tx_queues[idx] != NULL) {
933 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
934 hw->fkq_data.tx_queues[idx] = NULL;
938 q_info.socket_id = socket_id;
939 q_info.nb_desc = nb_desc;
940 q_info.type = "hns3 fake TX queue";
941 q_info.ring_name = "tx_fake_ring";
942 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
944 hns3_err(hw, "Failed to setup No.%d fake tx ring.", idx);
948 /* Don't need alloc sw_ring, because upper applications don't use it */
952 txq->tx_deferred_start = false;
953 txq->port_id = dev->data->port_id;
954 txq->configured = true;
955 nb_tx_q = dev->data->nb_tx_queues;
956 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
957 (nb_tx_q + idx) * HNS3_TQP_REG_SIZE);
959 rte_spinlock_lock(&hw->lock);
960 hw->fkq_data.tx_queues[idx] = txq;
961 rte_spinlock_unlock(&hw->lock);
967 hns3_fake_rx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
969 uint16_t old_nb_queues = hw->fkq_data.nb_fake_rx_queues;
973 if (hw->fkq_data.rx_queues == NULL && nb_queues != 0) {
974 /* first time configuration */
976 size = sizeof(hw->fkq_data.rx_queues[0]) * nb_queues;
977 hw->fkq_data.rx_queues = rte_zmalloc("fake_rx_queues", size,
978 RTE_CACHE_LINE_SIZE);
979 if (hw->fkq_data.rx_queues == NULL) {
980 hw->fkq_data.nb_fake_rx_queues = 0;
983 } else if (hw->fkq_data.rx_queues != NULL && nb_queues != 0) {
985 rxq = hw->fkq_data.rx_queues;
986 for (i = nb_queues; i < old_nb_queues; i++)
987 hns3_dev_rx_queue_release(rxq[i]);
989 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
990 RTE_CACHE_LINE_SIZE);
993 if (nb_queues > old_nb_queues) {
994 uint16_t new_qs = nb_queues - old_nb_queues;
995 memset(rxq + old_nb_queues, 0, sizeof(rxq[0]) * new_qs);
998 hw->fkq_data.rx_queues = rxq;
999 } else if (hw->fkq_data.rx_queues != NULL && nb_queues == 0) {
1000 rxq = hw->fkq_data.rx_queues;
1001 for (i = nb_queues; i < old_nb_queues; i++)
1002 hns3_dev_rx_queue_release(rxq[i]);
1004 rte_free(hw->fkq_data.rx_queues);
1005 hw->fkq_data.rx_queues = NULL;
1008 hw->fkq_data.nb_fake_rx_queues = nb_queues;
1014 hns3_fake_tx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1016 uint16_t old_nb_queues = hw->fkq_data.nb_fake_tx_queues;
1020 if (hw->fkq_data.tx_queues == NULL && nb_queues != 0) {
1021 /* first time configuration */
1023 size = sizeof(hw->fkq_data.tx_queues[0]) * nb_queues;
1024 hw->fkq_data.tx_queues = rte_zmalloc("fake_tx_queues", size,
1025 RTE_CACHE_LINE_SIZE);
1026 if (hw->fkq_data.tx_queues == NULL) {
1027 hw->fkq_data.nb_fake_tx_queues = 0;
1030 } else if (hw->fkq_data.tx_queues != NULL && nb_queues != 0) {
1032 txq = hw->fkq_data.tx_queues;
1033 for (i = nb_queues; i < old_nb_queues; i++)
1034 hns3_dev_tx_queue_release(txq[i]);
1035 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1036 RTE_CACHE_LINE_SIZE);
1039 if (nb_queues > old_nb_queues) {
1040 uint16_t new_qs = nb_queues - old_nb_queues;
1041 memset(txq + old_nb_queues, 0, sizeof(txq[0]) * new_qs);
1044 hw->fkq_data.tx_queues = txq;
1045 } else if (hw->fkq_data.tx_queues != NULL && nb_queues == 0) {
1046 txq = hw->fkq_data.tx_queues;
1047 for (i = nb_queues; i < old_nb_queues; i++)
1048 hns3_dev_tx_queue_release(txq[i]);
1050 rte_free(hw->fkq_data.tx_queues);
1051 hw->fkq_data.tx_queues = NULL;
1053 hw->fkq_data.nb_fake_tx_queues = nb_queues;
1059 hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
1062 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1063 uint16_t rx_need_add_nb_q;
1064 uint16_t tx_need_add_nb_q;
1069 /* Setup new number of fake RX/TX queues and reconfigure device. */
1070 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
1071 rx_need_add_nb_q = hw->cfg_max_queues - nb_rx_q;
1072 tx_need_add_nb_q = hw->cfg_max_queues - nb_tx_q;
1073 ret = hns3_fake_rx_queue_config(hw, rx_need_add_nb_q);
1075 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1076 goto cfg_fake_rx_q_fail;
1079 ret = hns3_fake_tx_queue_config(hw, tx_need_add_nb_q);
1081 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1082 goto cfg_fake_tx_q_fail;
1085 /* Allocate and set up fake RX queue per Ethernet port. */
1086 port_id = hw->data->port_id;
1087 for (q = 0; q < rx_need_add_nb_q; q++) {
1088 ret = hns3_fake_rx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1089 rte_eth_dev_socket_id(port_id));
1091 goto setup_fake_rx_q_fail;
1094 /* Allocate and set up fake TX queue per Ethernet port. */
1095 for (q = 0; q < tx_need_add_nb_q; q++) {
1096 ret = hns3_fake_tx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1097 rte_eth_dev_socket_id(port_id));
1099 goto setup_fake_tx_q_fail;
1104 setup_fake_tx_q_fail:
1105 setup_fake_rx_q_fail:
1106 (void)hns3_fake_tx_queue_config(hw, 0);
1108 (void)hns3_fake_rx_queue_config(hw, 0);
1110 hw->cfg_max_queues = 0;
1116 hns3_dev_release_mbufs(struct hns3_adapter *hns)
1118 struct rte_eth_dev_data *dev_data = hns->hw.data;
1119 struct hns3_rx_queue *rxq;
1120 struct hns3_tx_queue *txq;
1123 if (dev_data->rx_queues)
1124 for (i = 0; i < dev_data->nb_rx_queues; i++) {
1125 rxq = dev_data->rx_queues[i];
1126 if (rxq == NULL || rxq->rx_deferred_start)
1128 hns3_rx_queue_release_mbufs(rxq);
1131 if (dev_data->tx_queues)
1132 for (i = 0; i < dev_data->nb_tx_queues; i++) {
1133 txq = dev_data->tx_queues[i];
1134 if (txq == NULL || txq->tx_deferred_start)
1136 hns3_tx_queue_release_mbufs(txq);
1141 hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1142 unsigned int socket_id, const struct rte_eth_rxconf *conf,
1143 struct rte_mempool *mp)
1145 struct hns3_adapter *hns = dev->data->dev_private;
1146 struct hns3_hw *hw = &hns->hw;
1147 struct hns3_queue_info q_info;
1148 struct hns3_rx_queue *rxq;
1151 if (dev->data->dev_started) {
1152 hns3_err(hw, "rx_queue_setup after dev_start no supported");
1156 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1157 nb_desc % HNS3_ALIGN_RING_DESC) {
1158 hns3_err(hw, "Number (%u) of rx descriptors is invalid",
1163 if (dev->data->rx_queues[idx]) {
1164 hns3_rx_queue_release(dev->data->rx_queues[idx]);
1165 dev->data->rx_queues[idx] = NULL;
1169 q_info.socket_id = socket_id;
1170 q_info.nb_desc = nb_desc;
1171 q_info.type = "hns3 RX queue";
1172 q_info.ring_name = "rx_ring";
1173 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1176 "Failed to alloc mem and reserve DMA mem for rx ring!");
1182 if (conf->rx_free_thresh <= 0)
1183 rxq->rx_free_thresh = DEFAULT_RX_FREE_THRESH;
1185 rxq->rx_free_thresh = conf->rx_free_thresh;
1186 rxq->rx_deferred_start = conf->rx_deferred_start;
1188 rx_entry_len = sizeof(struct hns3_entry) * rxq->nb_rx_desc;
1189 rxq->sw_ring = rte_zmalloc_socket("hns3 RX sw ring", rx_entry_len,
1190 RTE_CACHE_LINE_SIZE, socket_id);
1191 if (rxq->sw_ring == NULL) {
1192 hns3_err(hw, "Failed to allocate memory for rx sw ring!");
1193 hns3_rx_queue_release(rxq);
1197 rxq->next_to_use = 0;
1198 rxq->next_to_clean = 0;
1199 rxq->nb_rx_hold = 0;
1200 rxq->pkt_first_seg = NULL;
1201 rxq->pkt_last_seg = NULL;
1202 rxq->port_id = dev->data->port_id;
1203 rxq->configured = true;
1204 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1205 idx * HNS3_TQP_REG_SIZE);
1206 rxq->rx_buf_len = hw->rx_buf_len;
1208 rxq->pkt_len_errors = 0;
1209 rxq->l3_csum_erros = 0;
1210 rxq->l4_csum_erros = 0;
1211 rxq->ol3_csum_erros = 0;
1212 rxq->ol4_csum_erros = 0;
1214 rte_spinlock_lock(&hw->lock);
1215 dev->data->rx_queues[idx] = rxq;
1216 rte_spinlock_unlock(&hw->lock);
1221 static inline uint32_t
1222 rxd_pkt_info_to_pkt_type(uint32_t pkt_info, uint32_t ol_info)
1224 #define HNS3_L2TBL_NUM 4
1225 #define HNS3_L3TBL_NUM 16
1226 #define HNS3_L4TBL_NUM 16
1227 #define HNS3_OL3TBL_NUM 16
1228 #define HNS3_OL4TBL_NUM 16
1229 uint32_t pkt_type = 0;
1230 uint32_t l2id, l3id, l4id;
1231 uint32_t ol3id, ol4id;
1233 static const uint32_t l2table[HNS3_L2TBL_NUM] = {
1235 RTE_PTYPE_L2_ETHER_VLAN,
1236 RTE_PTYPE_L2_ETHER_QINQ,
1240 static const uint32_t l3table[HNS3_L3TBL_NUM] = {
1243 RTE_PTYPE_L2_ETHER_ARP,
1245 RTE_PTYPE_L3_IPV4_EXT,
1246 RTE_PTYPE_L3_IPV6_EXT,
1247 RTE_PTYPE_L2_ETHER_LLDP,
1248 0, 0, 0, 0, 0, 0, 0, 0, 0
1251 static const uint32_t l4table[HNS3_L4TBL_NUM] = {
1254 RTE_PTYPE_TUNNEL_GRE,
1258 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1261 static const uint32_t inner_l2table[HNS3_L2TBL_NUM] = {
1262 RTE_PTYPE_INNER_L2_ETHER,
1263 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1264 RTE_PTYPE_INNER_L2_ETHER_QINQ,
1268 static const uint32_t inner_l3table[HNS3_L3TBL_NUM] = {
1269 RTE_PTYPE_INNER_L3_IPV4,
1270 RTE_PTYPE_INNER_L3_IPV6,
1272 RTE_PTYPE_INNER_L2_ETHER,
1273 RTE_PTYPE_INNER_L3_IPV4_EXT,
1274 RTE_PTYPE_INNER_L3_IPV6_EXT,
1275 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1278 static const uint32_t inner_l4table[HNS3_L4TBL_NUM] = {
1279 RTE_PTYPE_INNER_L4_UDP,
1280 RTE_PTYPE_INNER_L4_TCP,
1281 RTE_PTYPE_TUNNEL_GRE,
1282 RTE_PTYPE_INNER_L4_SCTP,
1284 RTE_PTYPE_INNER_L4_ICMP,
1285 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1288 static const uint32_t ol3table[HNS3_OL3TBL_NUM] = {
1292 RTE_PTYPE_L3_IPV4_EXT,
1293 RTE_PTYPE_L3_IPV6_EXT,
1294 0, 0, 0, 0, 0, 0, 0, 0, 0,
1298 static const uint32_t ol4table[HNS3_OL4TBL_NUM] = {
1300 RTE_PTYPE_TUNNEL_VXLAN,
1301 RTE_PTYPE_TUNNEL_NVGRE,
1302 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1305 l2id = hns3_get_field(pkt_info, HNS3_RXD_STRP_TAGP_M,
1306 HNS3_RXD_STRP_TAGP_S);
1307 l3id = hns3_get_field(pkt_info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
1308 l4id = hns3_get_field(pkt_info, HNS3_RXD_L4ID_M, HNS3_RXD_L4ID_S);
1309 ol3id = hns3_get_field(ol_info, HNS3_RXD_OL3ID_M, HNS3_RXD_OL3ID_S);
1310 ol4id = hns3_get_field(ol_info, HNS3_RXD_OL4ID_M, HNS3_RXD_OL4ID_S);
1312 if (ol4table[ol4id])
1313 pkt_type |= (inner_l2table[l2id] | inner_l3table[l3id] |
1314 inner_l4table[l4id] | ol3table[ol3id] |
1317 pkt_type |= (l2table[l2id] | l3table[l3id] | l4table[l4id]);
1322 hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1324 static const uint32_t ptypes[] = {
1326 RTE_PTYPE_L2_ETHER_VLAN,
1327 RTE_PTYPE_L2_ETHER_QINQ,
1328 RTE_PTYPE_L2_ETHER_LLDP,
1329 RTE_PTYPE_L2_ETHER_ARP,
1331 RTE_PTYPE_L3_IPV4_EXT,
1333 RTE_PTYPE_L3_IPV6_EXT,
1339 RTE_PTYPE_TUNNEL_GRE,
1343 if (dev->rx_pkt_burst == hns3_recv_pkts)
1350 hns3_clean_rx_buffers(struct hns3_rx_queue *rxq, int count)
1352 rxq->next_to_use += count;
1353 if (rxq->next_to_use >= rxq->nb_rx_desc)
1354 rxq->next_to_use -= rxq->nb_rx_desc;
1356 hns3_write_dev(rxq, HNS3_RING_RX_HEAD_REG, count);
1360 hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,
1361 uint32_t bd_base_info, uint32_t l234_info,
1362 uint32_t *cksum_err)
1366 if (unlikely(l234_info & BIT(HNS3_RXD_L2E_B))) {
1371 if (unlikely(rxm->pkt_len == 0 ||
1372 (l234_info & BIT(HNS3_RXD_TRUNCAT_B)))) {
1373 rxq->pkt_len_errors++;
1377 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B)) {
1378 if (unlikely(l234_info & BIT(HNS3_RXD_L3E_B))) {
1379 rxm->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1380 rxq->l3_csum_erros++;
1381 tmp |= HNS3_L3_CKSUM_ERR;
1384 if (unlikely(l234_info & BIT(HNS3_RXD_L4E_B))) {
1385 rxm->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1386 rxq->l4_csum_erros++;
1387 tmp |= HNS3_L4_CKSUM_ERR;
1390 if (unlikely(l234_info & BIT(HNS3_RXD_OL3E_B))) {
1391 rxq->ol3_csum_erros++;
1392 tmp |= HNS3_OUTER_L3_CKSUM_ERR;
1395 if (unlikely(l234_info & BIT(HNS3_RXD_OL4E_B))) {
1396 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
1397 rxq->ol4_csum_erros++;
1398 tmp |= HNS3_OUTER_L4_CKSUM_ERR;
1407 hns3_rx_set_cksum_flag(struct rte_mbuf *rxm, uint64_t packet_type,
1408 const uint32_t cksum_err)
1410 if (unlikely((packet_type & RTE_PTYPE_TUNNEL_MASK))) {
1411 if (likely(packet_type & RTE_PTYPE_INNER_L3_MASK) &&
1412 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
1413 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1414 if (likely(packet_type & RTE_PTYPE_INNER_L4_MASK) &&
1415 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
1416 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1417 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
1418 (cksum_err & HNS3_OUTER_L4_CKSUM_ERR) == 0)
1419 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
1421 if (likely(packet_type & RTE_PTYPE_L3_MASK) &&
1422 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
1423 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1424 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
1425 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
1426 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1431 hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1433 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
1434 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
1435 struct hns3_rx_queue *rxq; /* RX queue */
1436 struct hns3_entry *sw_ring;
1437 struct hns3_entry *rxe;
1438 struct rte_mbuf *first_seg;
1439 struct rte_mbuf *last_seg;
1440 struct hns3_desc rxd;
1441 struct rte_mbuf *nmb; /* pointer of the new mbuf */
1442 struct rte_mbuf *rxm;
1443 struct rte_eth_dev *dev;
1444 uint32_t bd_base_info;
1459 dev = &rte_eth_devices[rxq->port_id];
1461 rx_id = rxq->next_to_clean;
1462 rx_ring = rxq->rx_ring;
1463 first_seg = rxq->pkt_first_seg;
1464 last_seg = rxq->pkt_last_seg;
1465 sw_ring = rxq->sw_ring;
1467 while (nb_rx < nb_pkts) {
1468 rxdp = &rx_ring[rx_id];
1469 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
1470 if (unlikely(!hns3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
1473 * The interactive process between software and hardware of
1474 * receiving a new packet in hns3 network engine:
1475 * 1. Hardware network engine firstly writes the packet content
1476 * to the memory pointed by the 'addr' field of the Rx Buffer
1477 * Descriptor, secondly fills the result of parsing the
1478 * packet include the valid field into the Rx Buffer
1479 * Descriptor in one write operation.
1480 * 2. Driver reads the Rx BD's valid field in the loop to check
1481 * whether it's valid, if valid then assign a new address to
1482 * the addr field, clear the valid field, get the other
1483 * information of the packet by parsing Rx BD's other fields,
1484 * finally write back the number of Rx BDs processed by the
1485 * driver to the HNS3_RING_RX_HEAD_REG register to inform
1487 * In the above process, the ordering is very important. We must
1488 * make sure that CPU read Rx BD's other fields only after the
1491 * There are two type of re-ordering: compiler re-ordering and
1492 * CPU re-ordering under the ARMv8 architecture.
1493 * 1. we use volatile to deal with compiler re-ordering, so you
1494 * can see that rx_ring/rxdp defined with volatile.
1495 * 2. we commonly use memory barrier to deal with CPU
1496 * re-ordering, but the cost is high.
1498 * In order to solve the high cost of using memory barrier, we
1499 * use the data dependency order under the ARMv8 architecture,
1502 * instr02: load B <- A
1503 * the instr02 will always execute after instr01.
1505 * To construct the data dependency ordering, we use the
1506 * following assignment:
1507 * rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
1508 * (1u<<HNS3_RXD_VLD_B)]
1509 * Using gcc compiler under the ARMv8 architecture, the related
1510 * assembly code example as follows:
1511 * note: (1u << HNS3_RXD_VLD_B) equal 0x10
1512 * instr01: ldr w26, [x22, #28] --read bd_base_info
1513 * instr02: and w0, w26, #0x10 --calc bd_base_info & 0x10
1514 * instr03: sub w0, w0, #0x10 --calc (bd_base_info &
1516 * instr04: add x0, x22, x0, lsl #5 --calc copy source addr
1517 * instr05: ldp x2, x3, [x0]
1518 * instr06: stp x2, x3, [x29, #256] --copy BD's [0 ~ 15]B
1519 * instr07: ldp x4, x5, [x0, #16]
1520 * instr08: stp x4, x5, [x29, #272] --copy BD's [16 ~ 31]B
1521 * the instr05~08 depend on x0's value, x0 depent on w26's
1522 * value, the w26 is the bd_base_info, this form the data
1523 * dependency ordering.
1524 * note: if BD is valid, (bd_base_info & (1u<<HNS3_RXD_VLD_B)) -
1525 * (1u<<HNS3_RXD_VLD_B) will always zero, so the
1526 * assignment is correct.
1528 * So we use the data dependency ordering instead of memory
1529 * barrier to improve receive performance.
1531 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
1532 (1u << HNS3_RXD_VLD_B)];
1534 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1535 if (unlikely(nmb == NULL)) {
1536 dev->data->rx_mbuf_alloc_failed++;
1541 rxe = &sw_ring[rx_id];
1543 if (unlikely(rx_id == rxq->nb_rx_desc))
1546 rte_prefetch0(sw_ring[rx_id].mbuf);
1547 if ((rx_id & 0x3) == 0) {
1548 rte_prefetch0(&rx_ring[rx_id]);
1549 rte_prefetch0(&sw_ring[rx_id]);
1555 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1556 rxdp->rx.bd_base_info = 0;
1557 rxdp->addr = dma_addr;
1559 /* Load remained descriptor data and extract necessary fields */
1560 data_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.size));
1561 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
1562 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
1564 if (first_seg == NULL) {
1566 first_seg->nb_segs = 1;
1568 first_seg->nb_segs++;
1569 last_seg->next = rxm;
1572 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1573 rxm->data_len = data_len;
1575 if (!hns3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
1580 /* The last buffer of the received packet */
1581 pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.pkt_len));
1582 first_seg->pkt_len = pkt_len;
1583 first_seg->port = rxq->port_id;
1584 first_seg->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
1585 first_seg->ol_flags = PKT_RX_RSS_HASH;
1586 if (unlikely(hns3_get_bit(bd_base_info, HNS3_RXD_LUM_B))) {
1587 first_seg->hash.fdir.hi =
1588 rte_le_to_cpu_32(rxd.rx.fd_id);
1589 first_seg->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1593 ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info,
1594 l234_info, &cksum_err);
1598 first_seg->packet_type = rxd_pkt_info_to_pkt_type(l234_info,
1601 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B))
1602 hns3_rx_set_cksum_flag(first_seg,
1603 first_seg->packet_type,
1606 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.rx.vlan_tag);
1607 first_seg->vlan_tci_outer =
1608 rte_le_to_cpu_16(rxd.rx.ot_vlan_tag);
1609 rx_pkts[nb_rx++] = first_seg;
1613 rte_pktmbuf_free(first_seg);
1617 rxq->next_to_clean = rx_id;
1618 rxq->pkt_first_seg = first_seg;
1619 rxq->pkt_last_seg = last_seg;
1621 nb_rx_bd = nb_rx_bd + rxq->nb_rx_hold;
1622 if (nb_rx_bd > rxq->rx_free_thresh) {
1623 hns3_clean_rx_buffers(rxq, nb_rx_bd);
1626 rxq->nb_rx_hold = nb_rx_bd;
1632 hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1633 unsigned int socket_id, const struct rte_eth_txconf *conf)
1635 struct hns3_adapter *hns = dev->data->dev_private;
1636 struct hns3_hw *hw = &hns->hw;
1637 struct hns3_queue_info q_info;
1638 struct hns3_tx_queue *txq;
1641 if (dev->data->dev_started) {
1642 hns3_err(hw, "tx_queue_setup after dev_start no supported");
1646 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1647 nb_desc % HNS3_ALIGN_RING_DESC) {
1648 hns3_err(hw, "Number (%u) of tx descriptors is invalid",
1653 if (dev->data->tx_queues[idx] != NULL) {
1654 hns3_tx_queue_release(dev->data->tx_queues[idx]);
1655 dev->data->tx_queues[idx] = NULL;
1659 q_info.socket_id = socket_id;
1660 q_info.nb_desc = nb_desc;
1661 q_info.type = "hns3 TX queue";
1662 q_info.ring_name = "tx_ring";
1663 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
1666 "Failed to alloc mem and reserve DMA mem for tx ring!");
1670 txq->tx_deferred_start = conf->tx_deferred_start;
1671 tx_entry_len = sizeof(struct hns3_entry) * txq->nb_tx_desc;
1672 txq->sw_ring = rte_zmalloc_socket("hns3 TX sw ring", tx_entry_len,
1673 RTE_CACHE_LINE_SIZE, socket_id);
1674 if (txq->sw_ring == NULL) {
1675 hns3_err(hw, "Failed to allocate memory for tx sw ring!");
1676 hns3_tx_queue_release(txq);
1681 txq->next_to_use = 0;
1682 txq->next_to_clean = 0;
1683 txq->tx_bd_ready = txq->nb_tx_desc - 1;
1684 txq->port_id = dev->data->port_id;
1685 txq->configured = true;
1686 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1687 idx * HNS3_TQP_REG_SIZE);
1688 rte_spinlock_lock(&hw->lock);
1689 dev->data->tx_queues[idx] = txq;
1690 rte_spinlock_unlock(&hw->lock);
1696 hns3_queue_xmit(struct hns3_tx_queue *txq, uint32_t buf_num)
1698 hns3_write_dev(txq, HNS3_RING_TX_TAIL_REG, buf_num);
1702 hns3_tx_free_useless_buffer(struct hns3_tx_queue *txq)
1704 uint16_t tx_next_clean = txq->next_to_clean;
1705 uint16_t tx_next_use = txq->next_to_use;
1706 uint16_t tx_bd_ready = txq->tx_bd_ready;
1707 uint16_t tx_bd_max = txq->nb_tx_desc;
1708 struct hns3_entry *tx_bak_pkt = &txq->sw_ring[tx_next_clean];
1709 struct hns3_desc *desc = &txq->tx_ring[tx_next_clean];
1710 struct rte_mbuf *mbuf;
1712 while ((!hns3_get_bit(desc->tx.tp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B)) &&
1713 tx_next_use != tx_next_clean) {
1714 mbuf = tx_bak_pkt->mbuf;
1716 rte_pktmbuf_free_seg(mbuf);
1717 tx_bak_pkt->mbuf = NULL;
1725 if (tx_next_clean >= tx_bd_max) {
1727 desc = txq->tx_ring;
1728 tx_bak_pkt = txq->sw_ring;
1732 txq->next_to_clean = tx_next_clean;
1733 txq->tx_bd_ready = tx_bd_ready;
1737 hns3_tso_proc_tunnel(struct hns3_desc *desc, uint64_t ol_flags,
1738 struct rte_mbuf *rxm, uint8_t *l2_len)
1744 tun_flags = ol_flags & PKT_TX_TUNNEL_MASK;
1748 otmp = rte_le_to_cpu_32(desc->tx.ol_type_vlan_len_msec);
1749 switch (tun_flags) {
1750 case PKT_TX_TUNNEL_GENEVE:
1751 case PKT_TX_TUNNEL_VXLAN:
1752 *l2_len = rxm->l2_len - RTE_ETHER_VXLAN_HLEN;
1754 case PKT_TX_TUNNEL_GRE:
1756 * OL4 header size, defined in 4 Bytes, it contains outer
1757 * L4(GRE) length and tunneling length.
1759 ol4_len = hns3_get_field(otmp, HNS3_TXD_L4LEN_M,
1761 *l2_len = rxm->l2_len - (ol4_len << HNS3_L4_LEN_UNIT);
1764 /* For non UDP / GRE tunneling, drop the tunnel packet */
1767 hns3_set_field(otmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
1768 rxm->outer_l2_len >> HNS3_L2_LEN_UNIT);
1769 desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(otmp);
1775 hns3_set_tso(struct hns3_desc *desc,
1776 uint64_t ol_flags, struct rte_mbuf *rxm)
1778 uint32_t paylen, hdr_len;
1780 uint8_t l2_len = rxm->l2_len;
1782 if (!(ol_flags & PKT_TX_TCP_SEG))
1785 if (hns3_tso_proc_tunnel(desc, ol_flags, rxm, &l2_len))
1788 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len;
1789 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
1790 rxm->outer_l2_len + rxm->outer_l3_len : 0;
1791 paylen = rxm->pkt_len - hdr_len;
1792 if (paylen <= rxm->tso_segsz)
1795 tmp = rte_le_to_cpu_32(desc->tx.type_cs_vlan_tso_len);
1796 hns3_set_bit(tmp, HNS3_TXD_TSO_B, 1);
1797 hns3_set_bit(tmp, HNS3_TXD_L3CS_B, 1);
1798 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S, HNS3_L4T_TCP);
1799 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
1800 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
1801 sizeof(struct rte_tcp_hdr) >> HNS3_L4_LEN_UNIT);
1802 hns3_set_field(tmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
1803 l2_len >> HNS3_L2_LEN_UNIT);
1804 desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp);
1805 desc->tx.mss = rte_cpu_to_le_16(rxm->tso_segsz);
1809 fill_desc(struct hns3_tx_queue *txq, uint16_t tx_desc_id, struct rte_mbuf *rxm,
1810 bool first, int offset)
1812 struct hns3_desc *tx_ring = txq->tx_ring;
1813 struct hns3_desc *desc = &tx_ring[tx_desc_id];
1814 uint8_t frag_end = rxm->next == NULL ? 1 : 0;
1815 uint64_t ol_flags = rxm->ol_flags;
1816 uint16_t size = rxm->data_len;
1822 desc->addr = rte_mbuf_data_iova(rxm) + offset;
1823 desc->tx.send_size = rte_cpu_to_le_16(size);
1824 hns3_set_bit(rrcfv, HNS3_TXD_VLD_B, 1);
1827 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len;
1828 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
1829 rxm->outer_l2_len + rxm->outer_l3_len : 0;
1830 paylen = rxm->pkt_len - hdr_len;
1831 desc->tx.paylen = rte_cpu_to_le_32(paylen);
1832 hns3_set_tso(desc, ol_flags, rxm);
1835 hns3_set_bit(rrcfv, HNS3_TXD_FE_B, frag_end);
1836 desc->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(rrcfv);
1839 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1840 tmp = rte_le_to_cpu_32(desc->tx.type_cs_vlan_tso_len);
1841 hns3_set_bit(tmp, HNS3_TXD_VLAN_B, 1);
1842 desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp);
1843 desc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci);
1846 if (ol_flags & PKT_TX_QINQ_PKT) {
1847 tmp = rte_le_to_cpu_32(desc->tx.ol_type_vlan_len_msec);
1848 hns3_set_bit(tmp, HNS3_TXD_OVLAN_B, 1);
1849 desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp);
1850 desc->tx.outer_vlan_tag =
1851 rte_cpu_to_le_16(rxm->vlan_tci_outer);
1857 hns3_tx_alloc_mbufs(struct hns3_tx_queue *txq, struct rte_mempool *mb_pool,
1858 uint16_t nb_new_buf, struct rte_mbuf **alloc_mbuf)
1860 struct rte_mbuf *new_mbuf = NULL;
1861 struct rte_eth_dev *dev;
1862 struct rte_mbuf *temp;
1866 /* Allocate enough mbufs */
1867 for (i = 0; i < nb_new_buf; i++) {
1868 temp = rte_pktmbuf_alloc(mb_pool);
1869 if (unlikely(temp == NULL)) {
1870 dev = &rte_eth_devices[txq->port_id];
1871 hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872 hns3_err(hw, "Failed to alloc TX mbuf port_id=%d,"
1873 "queue_id=%d in reassemble tx pkts.",
1874 txq->port_id, txq->queue_id);
1875 rte_pktmbuf_free(new_mbuf);
1878 temp->next = new_mbuf;
1882 if (new_mbuf == NULL)
1885 new_mbuf->nb_segs = nb_new_buf;
1886 *alloc_mbuf = new_mbuf;
1892 hns3_reassemble_tx_pkts(void *tx_queue, struct rte_mbuf *tx_pkt,
1893 struct rte_mbuf **new_pkt)
1895 struct hns3_tx_queue *txq = tx_queue;
1896 struct rte_mempool *mb_pool;
1897 struct rte_mbuf *new_mbuf;
1898 struct rte_mbuf *temp_new;
1899 struct rte_mbuf *temp;
1900 uint16_t last_buf_len;
1901 uint16_t nb_new_buf;
1912 mb_pool = tx_pkt->pool;
1913 buf_size = tx_pkt->buf_len - RTE_PKTMBUF_HEADROOM;
1914 nb_new_buf = (tx_pkt->pkt_len - 1) / buf_size + 1;
1916 last_buf_len = tx_pkt->pkt_len % buf_size;
1917 if (last_buf_len == 0)
1918 last_buf_len = buf_size;
1920 /* Allocate enough mbufs */
1921 ret = hns3_tx_alloc_mbufs(txq, mb_pool, nb_new_buf, &new_mbuf);
1925 /* Copy the original packet content to the new mbufs */
1927 s = rte_pktmbuf_mtod(temp, char *);
1928 len_s = temp->data_len;
1929 temp_new = new_mbuf;
1930 for (i = 0; i < nb_new_buf; i++) {
1931 d = rte_pktmbuf_mtod(temp_new, char *);
1932 if (i < nb_new_buf - 1)
1935 buf_len = last_buf_len;
1939 len = RTE_MIN(len_s, len_d);
1943 len_d = len_d - len;
1944 len_s = len_s - len;
1950 s = rte_pktmbuf_mtod(temp, char *);
1951 len_s = temp->data_len;
1955 temp_new->data_len = buf_len;
1956 temp_new = temp_new->next;
1959 /* free original mbufs */
1960 rte_pktmbuf_free(tx_pkt);
1962 *new_pkt = new_mbuf;
1968 hns3_parse_outer_params(uint64_t ol_flags, uint32_t *ol_type_vlan_len_msec)
1970 uint32_t tmp = *ol_type_vlan_len_msec;
1972 /* (outer) IP header type */
1973 if (ol_flags & PKT_TX_OUTER_IPV4) {
1974 /* OL3 header size, defined in 4 bytes */
1975 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
1976 sizeof(struct rte_ipv4_hdr) >> HNS3_L3_LEN_UNIT);
1977 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
1978 hns3_set_field(tmp, HNS3_TXD_OL3T_M,
1979 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_CSUM);
1981 hns3_set_field(tmp, HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
1982 HNS3_OL3T_IPV4_NO_CSUM);
1983 } else if (ol_flags & PKT_TX_OUTER_IPV6) {
1984 hns3_set_field(tmp, HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
1986 /* OL3 header size, defined in 4 bytes */
1987 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
1988 sizeof(struct rte_ipv6_hdr) >> HNS3_L3_LEN_UNIT);
1991 *ol_type_vlan_len_msec = tmp;
1995 hns3_parse_inner_params(uint64_t ol_flags, uint32_t *ol_type_vlan_len_msec,
1996 struct rte_net_hdr_lens *hdr_lens)
1998 uint32_t tmp = *ol_type_vlan_len_msec;
2001 /* OL2 header size, defined in 2 bytes */
2002 hns3_set_field(tmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2003 sizeof(struct rte_ether_hdr) >> HNS3_L2_LEN_UNIT);
2005 /* L4TUNT: L4 Tunneling Type */
2006 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2007 case PKT_TX_TUNNEL_GENEVE:
2008 case PKT_TX_TUNNEL_VXLAN:
2009 /* MAC in UDP tunnelling packet, include VxLAN */
2010 hns3_set_field(tmp, HNS3_TXD_TUNTYPE_M, HNS3_TXD_TUNTYPE_S,
2011 HNS3_TUN_MAC_IN_UDP);
2013 * OL4 header size, defined in 4 Bytes, it contains outer
2014 * L4(UDP) length and tunneling length.
2016 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2017 (uint8_t)RTE_ETHER_VXLAN_HLEN >>
2020 case PKT_TX_TUNNEL_GRE:
2021 hns3_set_field(tmp, HNS3_TXD_TUNTYPE_M, HNS3_TXD_TUNTYPE_S,
2024 * OL4 header size, defined in 4 Bytes, it contains outer
2025 * L4(GRE) length and tunneling length.
2027 l4_len = hdr_lens->l4_len + hdr_lens->tunnel_len;
2028 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2029 l4_len >> HNS3_L4_LEN_UNIT);
2032 /* For non UDP / GRE tunneling, drop the tunnel packet */
2036 *ol_type_vlan_len_msec = tmp;
2042 hns3_parse_tunneling_params(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
2044 struct rte_net_hdr_lens *hdr_lens)
2046 struct hns3_desc *tx_ring = txq->tx_ring;
2047 struct hns3_desc *desc = &tx_ring[tx_desc_id];
2051 hns3_parse_outer_params(ol_flags, &value);
2052 ret = hns3_parse_inner_params(ol_flags, &value, hdr_lens);
2056 desc->tx.ol_type_vlan_len_msec |= rte_cpu_to_le_32(value);
2062 hns3_parse_l3_cksum_params(uint64_t ol_flags, uint32_t *type_cs_vlan_tso_len)
2066 /* Enable L3 checksum offloads */
2067 if (ol_flags & PKT_TX_IPV4) {
2068 tmp = *type_cs_vlan_tso_len;
2069 hns3_set_field(tmp, HNS3_TXD_L3T_M, HNS3_TXD_L3T_S,
2071 /* inner(/normal) L3 header size, defined in 4 bytes */
2072 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2073 sizeof(struct rte_ipv4_hdr) >> HNS3_L3_LEN_UNIT);
2074 if (ol_flags & PKT_TX_IP_CKSUM)
2075 hns3_set_bit(tmp, HNS3_TXD_L3CS_B, 1);
2076 *type_cs_vlan_tso_len = tmp;
2077 } else if (ol_flags & PKT_TX_IPV6) {
2078 tmp = *type_cs_vlan_tso_len;
2079 /* L3T, IPv6 don't do checksum */
2080 hns3_set_field(tmp, HNS3_TXD_L3T_M, HNS3_TXD_L3T_S,
2082 /* inner(/normal) L3 header size, defined in 4 bytes */
2083 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2084 sizeof(struct rte_ipv6_hdr) >> HNS3_L3_LEN_UNIT);
2085 *type_cs_vlan_tso_len = tmp;
2090 hns3_parse_l4_cksum_params(uint64_t ol_flags, uint32_t *type_cs_vlan_tso_len)
2094 /* Enable L4 checksum offloads */
2095 switch (ol_flags & PKT_TX_L4_MASK) {
2096 case PKT_TX_TCP_CKSUM:
2097 tmp = *type_cs_vlan_tso_len;
2098 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
2100 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2101 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2102 sizeof(struct rte_tcp_hdr) >> HNS3_L4_LEN_UNIT);
2103 *type_cs_vlan_tso_len = tmp;
2105 case PKT_TX_UDP_CKSUM:
2106 tmp = *type_cs_vlan_tso_len;
2107 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
2109 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2110 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2111 sizeof(struct rte_udp_hdr) >> HNS3_L4_LEN_UNIT);
2112 *type_cs_vlan_tso_len = tmp;
2114 case PKT_TX_SCTP_CKSUM:
2115 tmp = *type_cs_vlan_tso_len;
2116 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
2118 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2119 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2120 sizeof(struct rte_sctp_hdr) >> HNS3_L4_LEN_UNIT);
2121 *type_cs_vlan_tso_len = tmp;
2129 hns3_txd_enable_checksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
2132 struct hns3_desc *tx_ring = txq->tx_ring;
2133 struct hns3_desc *desc = &tx_ring[tx_desc_id];
2136 /* inner(/normal) L2 header size, defined in 2 bytes */
2137 hns3_set_field(value, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2138 sizeof(struct rte_ether_hdr) >> HNS3_L2_LEN_UNIT);
2140 hns3_parse_l3_cksum_params(ol_flags, &value);
2141 hns3_parse_l4_cksum_params(ol_flags, &value);
2143 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(value);
2147 hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num)
2149 struct rte_mbuf *m_first = tx_pkts;
2150 struct rte_mbuf *m_last = tx_pkts;
2151 uint32_t tot_len = 0;
2156 * Hardware requires that the sum of the data length of every 8
2157 * consecutive buffers is greater than MSS in hns3 network engine.
2158 * We simplify it by ensuring pkt_headlen + the first 8 consecutive
2159 * frags greater than gso header len + mss, and the remaining 7
2160 * consecutive frags greater than MSS except the last 7 frags.
2162 if (bd_num <= HNS3_MAX_NON_TSO_BD_PER_PKT)
2165 for (i = 0; m_last && i < HNS3_MAX_NON_TSO_BD_PER_PKT - 1;
2166 i++, m_last = m_last->next)
2167 tot_len += m_last->data_len;
2172 /* ensure the first 8 frags is greater than mss + header */
2173 hdr_len = tx_pkts->l2_len + tx_pkts->l3_len + tx_pkts->l4_len;
2174 hdr_len += (tx_pkts->ol_flags & PKT_TX_TUNNEL_MASK) ?
2175 tx_pkts->outer_l2_len + tx_pkts->outer_l3_len : 0;
2176 if (tot_len + m_last->data_len < tx_pkts->tso_segsz + hdr_len)
2180 * ensure the sum of the data length of every 7 consecutive buffer
2181 * is greater than mss except the last one.
2183 for (i = 0; m_last && i < bd_num - HNS3_MAX_NON_TSO_BD_PER_PKT; i++) {
2184 tot_len -= m_first->data_len;
2185 tot_len += m_last->data_len;
2187 if (tot_len < tx_pkts->tso_segsz)
2190 m_first = m_first->next;
2191 m_last = m_last->next;
2198 hns3_outer_header_cksum_prepare(struct rte_mbuf *m)
2200 uint64_t ol_flags = m->ol_flags;
2201 struct rte_ipv4_hdr *ipv4_hdr;
2202 struct rte_udp_hdr *udp_hdr;
2203 uint32_t paylen, hdr_len;
2205 if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6)))
2208 if (ol_flags & PKT_TX_IPV4) {
2209 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2212 if (ol_flags & PKT_TX_IP_CKSUM)
2213 ipv4_hdr->hdr_checksum = 0;
2216 if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_UDP_CKSUM &&
2217 ol_flags & PKT_TX_TCP_SEG) {
2218 hdr_len = m->l2_len + m->l3_len + m->l4_len;
2219 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
2220 m->outer_l2_len + m->outer_l3_len : 0;
2221 paylen = m->pkt_len - hdr_len;
2222 if (paylen <= m->tso_segsz)
2224 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
2227 udp_hdr->dgram_cksum = 0;
2232 hns3_pkt_is_tso(struct rte_mbuf *m)
2234 return (m->tso_segsz != 0 && m->ol_flags & PKT_TX_TCP_SEG);
2238 hns3_check_tso_pkt_valid(struct rte_mbuf *m)
2240 uint32_t tmp_data_len_sum = 0;
2241 uint16_t nb_buf = m->nb_segs;
2242 uint32_t paylen, hdr_len;
2243 struct rte_mbuf *m_seg;
2246 if (nb_buf > HNS3_MAX_TSO_BD_PER_PKT)
2249 hdr_len = m->l2_len + m->l3_len + m->l4_len;
2250 hdr_len += (m->ol_flags & PKT_TX_TUNNEL_MASK) ?
2251 m->outer_l2_len + m->outer_l3_len : 0;
2252 if (hdr_len > HNS3_MAX_TSO_HDR_SIZE)
2255 paylen = m->pkt_len - hdr_len;
2256 if (paylen > HNS3_MAX_BD_PAYLEN)
2260 * The TSO header (include outer and inner L2, L3 and L4 header)
2261 * should be provided by three descriptors in maximum in hns3 network
2265 for (i = 0; m_seg != NULL && i < HNS3_MAX_TSO_HDR_BD_NUM && i < nb_buf;
2266 i++, m_seg = m_seg->next) {
2267 tmp_data_len_sum += m_seg->data_len;
2270 if (hdr_len > tmp_data_len_sum)
2277 hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2284 for (i = 0; i < nb_pkts; i++) {
2287 /* check the size of packet */
2288 if (m->pkt_len < RTE_ETHER_MIN_LEN) {
2293 if (hns3_pkt_is_tso(m) &&
2294 (hns3_pkt_need_linearized(m, m->nb_segs) ||
2295 hns3_check_tso_pkt_valid(m))) {
2300 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2301 ret = rte_validate_tx_offload(m);
2307 ret = rte_net_intel_cksum_prepare(m);
2313 hns3_outer_header_cksum_prepare(m);
2320 hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
2321 const struct rte_mbuf *m, struct rte_net_hdr_lens *hdr_lens)
2323 /* Fill in tunneling parameters if necessary */
2324 if (m->ol_flags & PKT_TX_TUNNEL_MASK) {
2325 (void)rte_net_get_ptype(m, hdr_lens, RTE_PTYPE_ALL_MASK);
2326 if (hns3_parse_tunneling_params(txq, tx_desc_id, m->ol_flags,
2330 /* Enable checksum offloading */
2331 if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK)
2332 hns3_txd_enable_checksum(txq, tx_desc_id, m->ol_flags);
2338 hns3_check_non_tso_pkt(uint16_t nb_buf, struct rte_mbuf **m_seg,
2339 struct rte_mbuf *tx_pkt, struct hns3_tx_queue *txq)
2341 struct rte_mbuf *new_pkt;
2344 if (hns3_pkt_is_tso(*m_seg))
2348 * If packet length is greater than HNS3_MAX_FRAME_LEN
2349 * driver support, the packet will be ignored.
2351 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) > HNS3_MAX_FRAME_LEN))
2354 if (unlikely(nb_buf > HNS3_MAX_NON_TSO_BD_PER_PKT)) {
2355 ret = hns3_reassemble_tx_pkts(txq, tx_pkt, &new_pkt);
2365 hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2367 struct rte_net_hdr_lens hdr_lens = {0};
2368 struct hns3_tx_queue *txq = tx_queue;
2369 struct hns3_entry *tx_bak_pkt;
2370 struct rte_mbuf *tx_pkt;
2371 struct rte_mbuf *m_seg;
2372 uint32_t nb_hold = 0;
2373 uint16_t tx_next_use;
2374 uint16_t tx_pkt_num;
2380 /* free useless buffer */
2381 hns3_tx_free_useless_buffer(txq);
2383 tx_next_use = txq->next_to_use;
2384 tx_bd_max = txq->nb_tx_desc;
2385 tx_pkt_num = nb_pkts;
2388 tx_bak_pkt = &txq->sw_ring[tx_next_use];
2389 for (nb_tx = 0; nb_tx < tx_pkt_num; nb_tx++) {
2390 tx_pkt = *tx_pkts++;
2392 nb_buf = tx_pkt->nb_segs;
2394 if (nb_buf > txq->tx_bd_ready) {
2402 * If packet length is less than minimum packet size, driver
2405 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) < HNS3_MIN_PKT_SIZE)) {
2409 add_len = HNS3_MIN_PKT_SIZE -
2410 rte_pktmbuf_pkt_len(tx_pkt);
2411 appended = rte_pktmbuf_append(tx_pkt, add_len);
2412 if (appended == NULL)
2415 memset(appended, 0, add_len);
2420 if (hns3_check_non_tso_pkt(nb_buf, &m_seg, tx_pkt, txq))
2423 if (hns3_parse_cksum(txq, tx_next_use, m_seg, &hdr_lens))
2428 fill_desc(txq, tx_next_use, m_seg, (i == 0), 0);
2429 tx_bak_pkt->mbuf = m_seg;
2430 m_seg = m_seg->next;
2433 if (tx_next_use >= tx_bd_max) {
2435 tx_bak_pkt = txq->sw_ring;
2439 } while (m_seg != NULL);
2442 txq->next_to_use = tx_next_use;
2443 txq->tx_bd_ready -= i;
2449 hns3_queue_xmit(txq, nb_hold);
2455 hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused,
2456 struct rte_mbuf **pkts __rte_unused,
2457 uint16_t pkts_n __rte_unused)
2462 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)
2464 struct hns3_adapter *hns = eth_dev->data->dev_private;
2466 if (hns->hw.adapter_state == HNS3_NIC_STARTED &&
2467 rte_atomic16_read(&hns->hw.reset.resetting) == 0) {
2468 eth_dev->rx_pkt_burst = hns3_recv_pkts;
2469 eth_dev->tx_pkt_burst = hns3_xmit_pkts;
2470 eth_dev->tx_pkt_prepare = hns3_prep_pkts;
2472 eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst;
2473 eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
2474 eth_dev->tx_pkt_prepare = hns3_dummy_rxtx_burst;