1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
11 #include <rte_bus_pci.h>
12 #include <rte_byteorder.h>
13 #include <rte_common.h>
14 #include <rte_cycles.h>
17 #include <rte_ether.h>
18 #include <rte_vxlan.h>
19 #include <rte_ethdev_driver.h>
24 #include <rte_malloc.h>
27 #include "hns3_ethdev.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_regs.h"
30 #include "hns3_logs.h"
32 #define HNS3_CFG_DESC_NUM(num) ((num) / 8 - 1)
33 #define DEFAULT_RX_FREE_THRESH 32
36 hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq)
40 /* Note: Fake rx queue will not enter here */
42 for (i = 0; i < rxq->nb_rx_desc; i++) {
43 if (rxq->sw_ring[i].mbuf) {
44 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
45 rxq->sw_ring[i].mbuf = NULL;
52 hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq)
56 /* Note: Fake rx queue will not enter here */
58 for (i = 0; i < txq->nb_tx_desc; i++) {
59 if (txq->sw_ring[i].mbuf) {
60 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
61 txq->sw_ring[i].mbuf = NULL;
68 hns3_rx_queue_release(void *queue)
70 struct hns3_rx_queue *rxq = queue;
72 hns3_rx_queue_release_mbufs(rxq);
74 rte_memzone_free(rxq->mz);
76 rte_free(rxq->sw_ring);
82 hns3_tx_queue_release(void *queue)
84 struct hns3_tx_queue *txq = queue;
86 hns3_tx_queue_release_mbufs(txq);
88 rte_memzone_free(txq->mz);
90 rte_free(txq->sw_ring);
96 hns3_dev_rx_queue_release(void *queue)
98 struct hns3_rx_queue *rxq = queue;
99 struct hns3_adapter *hns;
105 rte_spinlock_lock(&hns->hw.lock);
106 hns3_rx_queue_release(queue);
107 rte_spinlock_unlock(&hns->hw.lock);
111 hns3_dev_tx_queue_release(void *queue)
113 struct hns3_tx_queue *txq = queue;
114 struct hns3_adapter *hns;
120 rte_spinlock_lock(&hns->hw.lock);
121 hns3_tx_queue_release(queue);
122 rte_spinlock_unlock(&hns->hw.lock);
126 hns3_fake_rx_queue_release(struct hns3_rx_queue *queue)
128 struct hns3_rx_queue *rxq = queue;
129 struct hns3_adapter *hns;
139 if (hw->fkq_data.rx_queues[idx]) {
140 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
141 hw->fkq_data.rx_queues[idx] = NULL;
144 /* free fake rx queue arrays */
145 if (idx == (hw->fkq_data.nb_fake_rx_queues - 1)) {
146 hw->fkq_data.nb_fake_rx_queues = 0;
147 rte_free(hw->fkq_data.rx_queues);
148 hw->fkq_data.rx_queues = NULL;
153 hns3_fake_tx_queue_release(struct hns3_tx_queue *queue)
155 struct hns3_tx_queue *txq = queue;
156 struct hns3_adapter *hns;
166 if (hw->fkq_data.tx_queues[idx]) {
167 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
168 hw->fkq_data.tx_queues[idx] = NULL;
171 /* free fake tx queue arrays */
172 if (idx == (hw->fkq_data.nb_fake_tx_queues - 1)) {
173 hw->fkq_data.nb_fake_tx_queues = 0;
174 rte_free(hw->fkq_data.tx_queues);
175 hw->fkq_data.tx_queues = NULL;
180 hns3_free_rx_queues(struct rte_eth_dev *dev)
182 struct hns3_adapter *hns = dev->data->dev_private;
183 struct hns3_fake_queue_data *fkq_data;
184 struct hns3_hw *hw = &hns->hw;
188 nb_rx_q = hw->data->nb_rx_queues;
189 for (i = 0; i < nb_rx_q; i++) {
190 if (dev->data->rx_queues[i]) {
191 hns3_rx_queue_release(dev->data->rx_queues[i]);
192 dev->data->rx_queues[i] = NULL;
196 /* Free fake Rx queues */
197 fkq_data = &hw->fkq_data;
198 for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) {
199 if (fkq_data->rx_queues[i])
200 hns3_fake_rx_queue_release(fkq_data->rx_queues[i]);
205 hns3_free_tx_queues(struct rte_eth_dev *dev)
207 struct hns3_adapter *hns = dev->data->dev_private;
208 struct hns3_fake_queue_data *fkq_data;
209 struct hns3_hw *hw = &hns->hw;
213 nb_tx_q = hw->data->nb_tx_queues;
214 for (i = 0; i < nb_tx_q; i++) {
215 if (dev->data->tx_queues[i]) {
216 hns3_tx_queue_release(dev->data->tx_queues[i]);
217 dev->data->tx_queues[i] = NULL;
221 /* Free fake Tx queues */
222 fkq_data = &hw->fkq_data;
223 for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) {
224 if (fkq_data->tx_queues[i])
225 hns3_fake_tx_queue_release(fkq_data->tx_queues[i]);
230 hns3_free_all_queues(struct rte_eth_dev *dev)
232 hns3_free_rx_queues(dev);
233 hns3_free_tx_queues(dev);
237 hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq)
239 struct rte_mbuf *mbuf;
243 for (i = 0; i < rxq->nb_rx_desc; i++) {
244 mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
245 if (unlikely(mbuf == NULL)) {
246 hns3_err(hw, "Failed to allocate RXD[%d] for rx queue!",
248 hns3_rx_queue_release_mbufs(rxq);
252 rte_mbuf_refcnt_set(mbuf, 1);
254 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
256 mbuf->port = rxq->port_id;
258 rxq->sw_ring[i].mbuf = mbuf;
259 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
260 rxq->rx_ring[i].addr = dma_addr;
261 rxq->rx_ring[i].rx.bd_base_info = 0;
268 hns3_buf_size2type(uint32_t buf_size)
274 bd_size_type = HNS3_BD_SIZE_512_TYPE;
277 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
280 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
283 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
290 hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)
292 uint32_t rx_buf_len = rxq->rx_buf_len;
293 uint64_t dma_addr = rxq->rx_ring_phys_addr;
295 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);
296 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,
297 (uint32_t)((dma_addr >> 31) >> 1));
299 hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,
300 hns3_buf_size2type(rx_buf_len));
301 hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG,
302 HNS3_CFG_DESC_NUM(rxq->nb_rx_desc));
306 hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)
308 uint64_t dma_addr = txq->tx_ring_phys_addr;
310 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);
311 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,
312 (uint32_t)((dma_addr >> 31) >> 1));
314 hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,
315 HNS3_CFG_DESC_NUM(txq->nb_tx_desc));
319 hns3_update_all_queues_pvid_state(struct hns3_hw *hw)
321 uint16_t nb_rx_q = hw->data->nb_rx_queues;
322 uint16_t nb_tx_q = hw->data->nb_tx_queues;
323 struct hns3_rx_queue *rxq;
324 struct hns3_tx_queue *txq;
328 pvid_state = hw->port_base_vlan_cfg.state;
329 for (i = 0; i < hw->cfg_max_queues; i++) {
331 rxq = hw->data->rx_queues[i];
333 rxq->pvid_state = pvid_state;
336 txq = hw->data->tx_queues[i];
338 txq->pvid_state = pvid_state;
344 hns3_enable_all_queues(struct hns3_hw *hw, bool en)
346 uint16_t nb_rx_q = hw->data->nb_rx_queues;
347 uint16_t nb_tx_q = hw->data->nb_tx_queues;
348 struct hns3_rx_queue *rxq;
349 struct hns3_tx_queue *txq;
353 for (i = 0; i < hw->cfg_max_queues; i++) {
355 rxq = hw->data->rx_queues[i];
357 rxq = hw->fkq_data.rx_queues[i - nb_rx_q];
359 txq = hw->data->tx_queues[i];
361 txq = hw->fkq_data.tx_queues[i - nb_tx_q];
362 if (rxq == NULL || txq == NULL ||
363 (en && (rxq->rx_deferred_start || txq->tx_deferred_start)))
366 rcb_reg = hns3_read_dev(rxq, HNS3_RING_EN_REG);
368 rcb_reg |= BIT(HNS3_RING_EN_B);
370 rcb_reg &= ~BIT(HNS3_RING_EN_B);
371 hns3_write_dev(rxq, HNS3_RING_EN_REG, rcb_reg);
376 hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable)
378 struct hns3_cfg_com_tqp_queue_cmd *req;
379 struct hns3_cmd_desc desc;
382 req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data;
384 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false);
385 req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
387 hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0);
389 ret = hns3_cmd_send(hw, &desc, 1);
391 hns3_err(hw, "TQP enable fail, ret = %d", ret);
397 hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable)
399 struct hns3_reset_tqp_queue_cmd *req;
400 struct hns3_cmd_desc desc;
403 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false);
405 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
406 req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
407 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
409 ret = hns3_cmd_send(hw, &desc, 1);
411 hns3_err(hw, "Send tqp reset cmd error, ret = %d", ret);
417 hns3_get_reset_status(struct hns3_hw *hw, uint16_t queue_id)
419 struct hns3_reset_tqp_queue_cmd *req;
420 struct hns3_cmd_desc desc;
423 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true);
425 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
426 req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
428 ret = hns3_cmd_send(hw, &desc, 1);
430 hns3_err(hw, "Get reset status error, ret =%d", ret);
434 return hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
438 hns3_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
440 #define HNS3_TQP_RESET_TRY_MS 200
445 ret = hns3_tqp_enable(hw, queue_id, false);
450 * In current version VF is not supported when PF is driven by DPDK
451 * driver, all task queue pairs are mapped to PF function, so PF's queue
452 * id is equals to the global queue id in PF range.
454 ret = hns3_send_reset_tqp_cmd(hw, queue_id, true);
456 hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret);
460 end = get_timeofday_ms() + HNS3_TQP_RESET_TRY_MS;
462 /* Wait for tqp hw reset */
463 rte_delay_ms(HNS3_POLL_RESPONE_MS);
464 reset_status = hns3_get_reset_status(hw, queue_id);
469 } while (get_timeofday_ms() < end);
472 hns3_err(hw, "Reset TQP fail, ret = %d", ret);
476 ret = hns3_send_reset_tqp_cmd(hw, queue_id, false);
478 hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret);
484 hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
489 /* Disable VF's queue before send queue reset msg to PF */
490 ret = hns3_tqp_enable(hw, queue_id, false);
494 memcpy(msg_data, &queue_id, sizeof(uint16_t));
496 return hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
497 sizeof(msg_data), true, NULL, 0);
501 hns3_reset_queue(struct hns3_adapter *hns, uint16_t queue_id)
503 struct hns3_hw *hw = &hns->hw;
505 return hns3vf_reset_tqp(hw, queue_id);
507 return hns3_reset_tqp(hw, queue_id);
511 hns3_reset_all_queues(struct hns3_adapter *hns)
513 struct hns3_hw *hw = &hns->hw;
516 for (i = 0; i < hw->cfg_max_queues; i++) {
517 ret = hns3_reset_queue(hns, i);
519 hns3_err(hw, "Failed to reset No.%d queue: %d", i, ret);
527 hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
528 uint8_t gl_idx, uint16_t gl_value)
530 uint32_t offset[] = {HNS3_TQP_INTR_GL0_REG,
531 HNS3_TQP_INTR_GL1_REG,
532 HNS3_TQP_INTR_GL2_REG};
533 uint32_t addr, value;
535 if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX)
538 addr = offset[gl_idx] + queue_id * HNS3_TQP_INTR_REG_SIZE;
539 if (hw->intr.gl_unit == HNS3_INTR_COALESCE_GL_UINT_1US)
540 value = gl_value | HNS3_TQP_INTR_GL_UNIT_1US;
542 value = HNS3_GL_USEC_TO_REG(gl_value);
544 hns3_write_dev(hw, addr, value);
548 hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value)
550 uint32_t addr, value;
552 if (rl_value > HNS3_TQP_INTR_RL_MAX)
555 addr = HNS3_TQP_INTR_RL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
556 value = HNS3_RL_USEC_TO_REG(rl_value);
558 value |= HNS3_TQP_INTR_RL_ENABLE_MASK;
560 hns3_write_dev(hw, addr, value);
564 hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value)
568 if (hw->intr.coalesce_mode == HNS3_INTR_COALESCE_NON_QL)
571 addr = HNS3_TQP_INTR_TX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
572 hns3_write_dev(hw, addr, ql_value);
574 addr = HNS3_TQP_INTR_RX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
575 hns3_write_dev(hw, addr, ql_value);
579 hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en)
581 uint32_t addr, value;
583 addr = HNS3_TQP_INTR_CTRL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
586 hns3_write_dev(hw, addr, value);
590 * Enable all rx queue interrupt when in interrupt rx mode.
591 * This api was called before enable queue rx&tx (in normal start or reset
592 * recover scenes), used to fix hardware rx queue interrupt enable was clear
596 hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en)
598 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
599 uint16_t nb_rx_q = hw->data->nb_rx_queues;
602 if (dev->data->dev_conf.intr_conf.rxq == 0)
605 for (i = 0; i < nb_rx_q; i++)
606 hns3_queue_intr_enable(hw, i, en);
610 hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
612 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
613 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
614 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
616 if (dev->data->dev_conf.intr_conf.rxq == 0)
619 hns3_queue_intr_enable(hw, queue_id, true);
621 return rte_intr_ack(intr_handle);
625 hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
627 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
629 if (dev->data->dev_conf.intr_conf.rxq == 0)
632 hns3_queue_intr_enable(hw, queue_id, false);
638 hns3_dev_rx_queue_start(struct hns3_adapter *hns, uint16_t idx)
640 struct hns3_hw *hw = &hns->hw;
641 struct hns3_rx_queue *rxq;
644 PMD_INIT_FUNC_TRACE();
646 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx];
647 ret = hns3_alloc_rx_queue_mbufs(hw, rxq);
649 hns3_err(hw, "Failed to alloc mbuf for No.%d rx queue: %d",
654 rxq->next_to_use = 0;
655 rxq->next_to_clean = 0;
657 hns3_init_rx_queue_hw(rxq);
663 hns3_fake_rx_queue_start(struct hns3_adapter *hns, uint16_t idx)
665 struct hns3_hw *hw = &hns->hw;
666 struct hns3_rx_queue *rxq;
668 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx];
669 rxq->next_to_use = 0;
670 rxq->next_to_clean = 0;
672 hns3_init_rx_queue_hw(rxq);
676 hns3_init_tx_queue(struct hns3_tx_queue *queue)
678 struct hns3_tx_queue *txq = queue;
679 struct hns3_desc *desc;
684 for (i = 0; i < txq->nb_tx_desc; i++) {
685 desc->tx.tp_fe_sc_vld_ra_ri = 0;
689 txq->next_to_use = 0;
690 txq->next_to_clean = 0;
691 txq->tx_bd_ready = txq->nb_tx_desc - 1;
692 hns3_init_tx_queue_hw(txq);
696 hns3_dev_tx_queue_start(struct hns3_adapter *hns, uint16_t idx)
698 struct hns3_hw *hw = &hns->hw;
699 struct hns3_tx_queue *txq;
701 txq = (struct hns3_tx_queue *)hw->data->tx_queues[idx];
702 hns3_init_tx_queue(txq);
706 hns3_fake_tx_queue_start(struct hns3_adapter *hns, uint16_t idx)
708 struct hns3_hw *hw = &hns->hw;
709 struct hns3_tx_queue *txq;
711 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[idx];
712 hns3_init_tx_queue(txq);
716 hns3_init_tx_ring_tc(struct hns3_adapter *hns)
718 struct hns3_hw *hw = &hns->hw;
719 struct hns3_tx_queue *txq;
722 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
723 struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i];
726 if (!tc_queue->enable)
729 for (j = 0; j < tc_queue->tqp_count; j++) {
730 num = tc_queue->tqp_offset + j;
731 txq = (struct hns3_tx_queue *)hw->data->tx_queues[num];
735 hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc);
741 hns3_start_rx_queues(struct hns3_adapter *hns)
743 struct hns3_hw *hw = &hns->hw;
744 struct hns3_rx_queue *rxq;
748 /* Initialize RSS for queues */
749 ret = hns3_config_rss(hns);
751 hns3_err(hw, "Failed to configure rss %d", ret);
755 for (i = 0; i < hw->data->nb_rx_queues; i++) {
756 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i];
757 if (rxq == NULL || rxq->rx_deferred_start)
759 ret = hns3_dev_rx_queue_start(hns, i);
761 hns3_err(hw, "Failed to start No.%d rx queue: %d", i,
767 for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++) {
768 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[i];
769 if (rxq == NULL || rxq->rx_deferred_start)
771 hns3_fake_rx_queue_start(hns, i);
776 for (j = 0; j < i; j++) {
777 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j];
778 hns3_rx_queue_release_mbufs(rxq);
785 hns3_start_tx_queues(struct hns3_adapter *hns)
787 struct hns3_hw *hw = &hns->hw;
788 struct hns3_tx_queue *txq;
791 for (i = 0; i < hw->data->nb_tx_queues; i++) {
792 txq = (struct hns3_tx_queue *)hw->data->tx_queues[i];
793 if (txq == NULL || txq->tx_deferred_start)
795 hns3_dev_tx_queue_start(hns, i);
798 for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) {
799 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i];
800 if (txq == NULL || txq->tx_deferred_start)
802 hns3_fake_tx_queue_start(hns, i);
805 hns3_init_tx_ring_tc(hns);
810 * Note: just init and setup queues, and don't enable queue rx&tx.
813 hns3_start_queues(struct hns3_adapter *hns, bool reset_queue)
815 struct hns3_hw *hw = &hns->hw;
819 ret = hns3_reset_all_queues(hns);
821 hns3_err(hw, "Failed to reset all queues %d", ret);
826 ret = hns3_start_rx_queues(hns);
828 hns3_err(hw, "Failed to start rx queues: %d", ret);
832 hns3_start_tx_queues(hns);
838 hns3_stop_queues(struct hns3_adapter *hns, bool reset_queue)
840 struct hns3_hw *hw = &hns->hw;
843 hns3_enable_all_queues(hw, false);
845 ret = hns3_reset_all_queues(hns);
847 hns3_err(hw, "Failed to reset all queues %d", ret);
855 hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev,
856 struct hns3_queue_info *q_info)
858 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
859 const struct rte_memzone *rx_mz;
860 struct hns3_rx_queue *rxq;
861 unsigned int rx_desc;
863 rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue),
864 RTE_CACHE_LINE_SIZE, q_info->socket_id);
866 hns3_err(hw, "Failed to allocate memory for No.%d rx ring!",
871 /* Allocate rx ring hardware descriptors. */
872 rxq->queue_id = q_info->idx;
873 rxq->nb_rx_desc = q_info->nb_desc;
874 rx_desc = rxq->nb_rx_desc * sizeof(struct hns3_desc);
875 rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
876 rx_desc, HNS3_RING_BASE_ALIGN,
879 hns3_err(hw, "Failed to reserve DMA memory for No.%d rx ring!",
881 hns3_rx_queue_release(rxq);
885 rxq->rx_ring = (struct hns3_desc *)rx_mz->addr;
886 rxq->rx_ring_phys_addr = rx_mz->iova;
888 hns3_dbg(hw, "No.%d rx descriptors iova 0x%" PRIx64, q_info->idx,
889 rxq->rx_ring_phys_addr);
895 hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
896 uint16_t nb_desc, unsigned int socket_id)
898 struct hns3_adapter *hns = dev->data->dev_private;
899 struct hns3_hw *hw = &hns->hw;
900 struct hns3_queue_info q_info;
901 struct hns3_rx_queue *rxq;
904 if (hw->fkq_data.rx_queues[idx]) {
905 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
906 hw->fkq_data.rx_queues[idx] = NULL;
910 q_info.socket_id = socket_id;
911 q_info.nb_desc = nb_desc;
912 q_info.type = "hns3 fake RX queue";
913 q_info.ring_name = "rx_fake_ring";
914 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
916 hns3_err(hw, "Failed to setup No.%d fake rx ring.", idx);
920 /* Don't need alloc sw_ring, because upper applications don't use it */
924 rxq->rx_deferred_start = false;
925 rxq->port_id = dev->data->port_id;
926 rxq->configured = true;
927 nb_rx_q = dev->data->nb_rx_queues;
928 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
929 (nb_rx_q + idx) * HNS3_TQP_REG_SIZE);
930 rxq->rx_buf_len = HNS3_MIN_BD_BUF_SIZE;
932 rte_spinlock_lock(&hw->lock);
933 hw->fkq_data.rx_queues[idx] = rxq;
934 rte_spinlock_unlock(&hw->lock);
940 hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev,
941 struct hns3_queue_info *q_info)
943 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
944 const struct rte_memzone *tx_mz;
945 struct hns3_tx_queue *txq;
946 struct hns3_desc *desc;
947 unsigned int tx_desc;
950 txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue),
951 RTE_CACHE_LINE_SIZE, q_info->socket_id);
953 hns3_err(hw, "Failed to allocate memory for No.%d tx ring!",
958 /* Allocate tx ring hardware descriptors. */
959 txq->queue_id = q_info->idx;
960 txq->nb_tx_desc = q_info->nb_desc;
961 tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc);
962 tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
963 tx_desc, HNS3_RING_BASE_ALIGN,
966 hns3_err(hw, "Failed to reserve DMA memory for No.%d tx ring!",
968 hns3_tx_queue_release(txq);
972 txq->tx_ring = (struct hns3_desc *)tx_mz->addr;
973 txq->tx_ring_phys_addr = tx_mz->iova;
975 hns3_dbg(hw, "No.%d tx descriptors iova 0x%" PRIx64, q_info->idx,
976 txq->tx_ring_phys_addr);
980 for (i = 0; i < txq->nb_tx_desc; i++) {
981 desc->tx.tp_fe_sc_vld_ra_ri = 0;
989 hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
990 uint16_t nb_desc, unsigned int socket_id)
992 struct hns3_adapter *hns = dev->data->dev_private;
993 struct hns3_hw *hw = &hns->hw;
994 struct hns3_queue_info q_info;
995 struct hns3_tx_queue *txq;
998 if (hw->fkq_data.tx_queues[idx] != NULL) {
999 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
1000 hw->fkq_data.tx_queues[idx] = NULL;
1004 q_info.socket_id = socket_id;
1005 q_info.nb_desc = nb_desc;
1006 q_info.type = "hns3 fake TX queue";
1007 q_info.ring_name = "tx_fake_ring";
1008 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
1010 hns3_err(hw, "Failed to setup No.%d fake tx ring.", idx);
1014 /* Don't need alloc sw_ring, because upper applications don't use it */
1015 txq->sw_ring = NULL;
1018 txq->tx_deferred_start = false;
1019 txq->port_id = dev->data->port_id;
1020 txq->configured = true;
1021 nb_tx_q = dev->data->nb_tx_queues;
1022 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1023 (nb_tx_q + idx) * HNS3_TQP_REG_SIZE);
1025 rte_spinlock_lock(&hw->lock);
1026 hw->fkq_data.tx_queues[idx] = txq;
1027 rte_spinlock_unlock(&hw->lock);
1033 hns3_fake_rx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1035 uint16_t old_nb_queues = hw->fkq_data.nb_fake_rx_queues;
1039 if (hw->fkq_data.rx_queues == NULL && nb_queues != 0) {
1040 /* first time configuration */
1042 size = sizeof(hw->fkq_data.rx_queues[0]) * nb_queues;
1043 hw->fkq_data.rx_queues = rte_zmalloc("fake_rx_queues", size,
1044 RTE_CACHE_LINE_SIZE);
1045 if (hw->fkq_data.rx_queues == NULL) {
1046 hw->fkq_data.nb_fake_rx_queues = 0;
1049 } else if (hw->fkq_data.rx_queues != NULL && nb_queues != 0) {
1051 rxq = hw->fkq_data.rx_queues;
1052 for (i = nb_queues; i < old_nb_queues; i++)
1053 hns3_dev_rx_queue_release(rxq[i]);
1055 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
1056 RTE_CACHE_LINE_SIZE);
1059 if (nb_queues > old_nb_queues) {
1060 uint16_t new_qs = nb_queues - old_nb_queues;
1061 memset(rxq + old_nb_queues, 0, sizeof(rxq[0]) * new_qs);
1064 hw->fkq_data.rx_queues = rxq;
1065 } else if (hw->fkq_data.rx_queues != NULL && nb_queues == 0) {
1066 rxq = hw->fkq_data.rx_queues;
1067 for (i = nb_queues; i < old_nb_queues; i++)
1068 hns3_dev_rx_queue_release(rxq[i]);
1070 rte_free(hw->fkq_data.rx_queues);
1071 hw->fkq_data.rx_queues = NULL;
1074 hw->fkq_data.nb_fake_rx_queues = nb_queues;
1080 hns3_fake_tx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1082 uint16_t old_nb_queues = hw->fkq_data.nb_fake_tx_queues;
1086 if (hw->fkq_data.tx_queues == NULL && nb_queues != 0) {
1087 /* first time configuration */
1089 size = sizeof(hw->fkq_data.tx_queues[0]) * nb_queues;
1090 hw->fkq_data.tx_queues = rte_zmalloc("fake_tx_queues", size,
1091 RTE_CACHE_LINE_SIZE);
1092 if (hw->fkq_data.tx_queues == NULL) {
1093 hw->fkq_data.nb_fake_tx_queues = 0;
1096 } else if (hw->fkq_data.tx_queues != NULL && nb_queues != 0) {
1098 txq = hw->fkq_data.tx_queues;
1099 for (i = nb_queues; i < old_nb_queues; i++)
1100 hns3_dev_tx_queue_release(txq[i]);
1101 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1102 RTE_CACHE_LINE_SIZE);
1105 if (nb_queues > old_nb_queues) {
1106 uint16_t new_qs = nb_queues - old_nb_queues;
1107 memset(txq + old_nb_queues, 0, sizeof(txq[0]) * new_qs);
1110 hw->fkq_data.tx_queues = txq;
1111 } else if (hw->fkq_data.tx_queues != NULL && nb_queues == 0) {
1112 txq = hw->fkq_data.tx_queues;
1113 for (i = nb_queues; i < old_nb_queues; i++)
1114 hns3_dev_tx_queue_release(txq[i]);
1116 rte_free(hw->fkq_data.tx_queues);
1117 hw->fkq_data.tx_queues = NULL;
1119 hw->fkq_data.nb_fake_tx_queues = nb_queues;
1125 hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
1128 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1129 uint16_t rx_need_add_nb_q;
1130 uint16_t tx_need_add_nb_q;
1135 /* Setup new number of fake RX/TX queues and reconfigure device. */
1136 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
1137 rx_need_add_nb_q = hw->cfg_max_queues - nb_rx_q;
1138 tx_need_add_nb_q = hw->cfg_max_queues - nb_tx_q;
1139 ret = hns3_fake_rx_queue_config(hw, rx_need_add_nb_q);
1141 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1142 goto cfg_fake_rx_q_fail;
1145 ret = hns3_fake_tx_queue_config(hw, tx_need_add_nb_q);
1147 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1148 goto cfg_fake_tx_q_fail;
1151 /* Allocate and set up fake RX queue per Ethernet port. */
1152 port_id = hw->data->port_id;
1153 for (q = 0; q < rx_need_add_nb_q; q++) {
1154 ret = hns3_fake_rx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1155 rte_eth_dev_socket_id(port_id));
1157 goto setup_fake_rx_q_fail;
1160 /* Allocate and set up fake TX queue per Ethernet port. */
1161 for (q = 0; q < tx_need_add_nb_q; q++) {
1162 ret = hns3_fake_tx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1163 rte_eth_dev_socket_id(port_id));
1165 goto setup_fake_tx_q_fail;
1170 setup_fake_tx_q_fail:
1171 setup_fake_rx_q_fail:
1172 (void)hns3_fake_tx_queue_config(hw, 0);
1174 (void)hns3_fake_rx_queue_config(hw, 0);
1176 hw->cfg_max_queues = 0;
1182 hns3_dev_release_mbufs(struct hns3_adapter *hns)
1184 struct rte_eth_dev_data *dev_data = hns->hw.data;
1185 struct hns3_rx_queue *rxq;
1186 struct hns3_tx_queue *txq;
1189 if (dev_data->rx_queues)
1190 for (i = 0; i < dev_data->nb_rx_queues; i++) {
1191 rxq = dev_data->rx_queues[i];
1192 if (rxq == NULL || rxq->rx_deferred_start)
1194 hns3_rx_queue_release_mbufs(rxq);
1197 if (dev_data->tx_queues)
1198 for (i = 0; i < dev_data->nb_tx_queues; i++) {
1199 txq = dev_data->tx_queues[i];
1200 if (txq == NULL || txq->tx_deferred_start)
1202 hns3_tx_queue_release_mbufs(txq);
1207 hns3_rx_buf_len_calc(struct rte_mempool *mp, uint16_t *rx_buf_len)
1209 uint16_t vld_buf_size;
1210 uint16_t num_hw_specs;
1214 * hns3 network engine only support to set 4 typical specification, and
1215 * different buffer size will affect the max packet_len and the max
1216 * number of segmentation when hw gro is turned on in receive side. The
1217 * relationship between them is as follows:
1218 * rx_buf_size | max_gro_pkt_len | max_gro_nb_seg
1219 * ---------------------|-------------------|----------------
1220 * HNS3_4K_BD_BUF_SIZE | 60KB | 15
1221 * HNS3_2K_BD_BUF_SIZE | 62KB | 31
1222 * HNS3_1K_BD_BUF_SIZE | 63KB | 63
1223 * HNS3_512_BD_BUF_SIZE | 31.5KB | 63
1225 static const uint16_t hw_rx_buf_size[] = {
1226 HNS3_4K_BD_BUF_SIZE,
1227 HNS3_2K_BD_BUF_SIZE,
1228 HNS3_1K_BD_BUF_SIZE,
1229 HNS3_512_BD_BUF_SIZE
1232 vld_buf_size = (uint16_t)(rte_pktmbuf_data_room_size(mp) -
1233 RTE_PKTMBUF_HEADROOM);
1235 if (vld_buf_size < HNS3_MIN_BD_BUF_SIZE)
1238 num_hw_specs = RTE_DIM(hw_rx_buf_size);
1239 for (i = 0; i < num_hw_specs; i++) {
1240 if (vld_buf_size >= hw_rx_buf_size[i]) {
1241 *rx_buf_len = hw_rx_buf_size[i];
1249 hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1250 unsigned int socket_id, const struct rte_eth_rxconf *conf,
1251 struct rte_mempool *mp)
1253 struct hns3_adapter *hns = dev->data->dev_private;
1254 struct hns3_hw *hw = &hns->hw;
1255 struct hns3_queue_info q_info;
1256 struct hns3_rx_queue *rxq;
1257 uint16_t rx_buf_size;
1260 if (dev->data->dev_started) {
1261 hns3_err(hw, "rx_queue_setup after dev_start no supported");
1265 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1266 nb_desc % HNS3_ALIGN_RING_DESC) {
1267 hns3_err(hw, "Number (%u) of rx descriptors is invalid",
1272 if (conf->rx_drop_en == 0)
1273 hns3_warn(hw, "if there are no available Rx descriptors,"
1274 "incoming packets are always dropped. input parameter"
1275 " conf->rx_drop_en(%u) is uneffective.",
1278 if (dev->data->rx_queues[idx]) {
1279 hns3_rx_queue_release(dev->data->rx_queues[idx]);
1280 dev->data->rx_queues[idx] = NULL;
1284 q_info.socket_id = socket_id;
1285 q_info.nb_desc = nb_desc;
1286 q_info.type = "hns3 RX queue";
1287 q_info.ring_name = "rx_ring";
1289 if (hns3_rx_buf_len_calc(mp, &rx_buf_size)) {
1290 hns3_err(hw, "rxq mbufs' data room size:%u is not enough! "
1291 "minimal data room size:%u.",
1292 rte_pktmbuf_data_room_size(mp),
1293 HNS3_MIN_BD_BUF_SIZE + RTE_PKTMBUF_HEADROOM);
1297 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1300 "Failed to alloc mem and reserve DMA mem for rx ring!");
1306 if (conf->rx_free_thresh <= 0)
1307 rxq->rx_free_thresh = DEFAULT_RX_FREE_THRESH;
1309 rxq->rx_free_thresh = conf->rx_free_thresh;
1310 rxq->rx_deferred_start = conf->rx_deferred_start;
1312 rx_entry_len = sizeof(struct hns3_entry) * rxq->nb_rx_desc;
1313 rxq->sw_ring = rte_zmalloc_socket("hns3 RX sw ring", rx_entry_len,
1314 RTE_CACHE_LINE_SIZE, socket_id);
1315 if (rxq->sw_ring == NULL) {
1316 hns3_err(hw, "Failed to allocate memory for rx sw ring!");
1317 hns3_rx_queue_release(rxq);
1321 rxq->next_to_use = 0;
1322 rxq->next_to_clean = 0;
1323 rxq->nb_rx_hold = 0;
1324 rxq->pkt_first_seg = NULL;
1325 rxq->pkt_last_seg = NULL;
1326 rxq->port_id = dev->data->port_id;
1327 rxq->pvid_state = hw->port_base_vlan_cfg.state;
1328 rxq->configured = true;
1329 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1330 idx * HNS3_TQP_REG_SIZE);
1331 rxq->rx_buf_len = rx_buf_size;
1333 rxq->pkt_len_errors = 0;
1334 rxq->l3_csum_erros = 0;
1335 rxq->l4_csum_erros = 0;
1336 rxq->ol3_csum_erros = 0;
1337 rxq->ol4_csum_erros = 0;
1339 /* CRC len set here is used for amending packet length */
1340 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1341 rxq->crc_len = RTE_ETHER_CRC_LEN;
1345 rte_spinlock_lock(&hw->lock);
1346 dev->data->rx_queues[idx] = rxq;
1347 rte_spinlock_unlock(&hw->lock);
1352 static inline uint32_t
1353 rxd_pkt_info_to_pkt_type(uint32_t pkt_info, uint32_t ol_info)
1355 #define HNS3_L2TBL_NUM 4
1356 #define HNS3_L3TBL_NUM 16
1357 #define HNS3_L4TBL_NUM 16
1358 #define HNS3_OL3TBL_NUM 16
1359 #define HNS3_OL4TBL_NUM 16
1360 uint32_t pkt_type = 0;
1361 uint32_t l2id, l3id, l4id;
1362 uint32_t ol3id, ol4id;
1364 static const uint32_t l2table[HNS3_L2TBL_NUM] = {
1366 RTE_PTYPE_L2_ETHER_QINQ,
1367 RTE_PTYPE_L2_ETHER_VLAN,
1368 RTE_PTYPE_L2_ETHER_VLAN
1371 static const uint32_t l3table[HNS3_L3TBL_NUM] = {
1374 RTE_PTYPE_L2_ETHER_ARP,
1376 RTE_PTYPE_L3_IPV4_EXT,
1377 RTE_PTYPE_L3_IPV6_EXT,
1378 RTE_PTYPE_L2_ETHER_LLDP,
1379 0, 0, 0, 0, 0, 0, 0, 0, 0
1382 static const uint32_t l4table[HNS3_L4TBL_NUM] = {
1385 RTE_PTYPE_TUNNEL_GRE,
1389 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1392 static const uint32_t inner_l2table[HNS3_L2TBL_NUM] = {
1393 RTE_PTYPE_INNER_L2_ETHER,
1394 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1395 RTE_PTYPE_INNER_L2_ETHER_QINQ,
1399 static const uint32_t inner_l3table[HNS3_L3TBL_NUM] = {
1400 RTE_PTYPE_INNER_L3_IPV4,
1401 RTE_PTYPE_INNER_L3_IPV6,
1403 RTE_PTYPE_INNER_L2_ETHER,
1404 RTE_PTYPE_INNER_L3_IPV4_EXT,
1405 RTE_PTYPE_INNER_L3_IPV6_EXT,
1406 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1409 static const uint32_t inner_l4table[HNS3_L4TBL_NUM] = {
1410 RTE_PTYPE_INNER_L4_UDP,
1411 RTE_PTYPE_INNER_L4_TCP,
1412 RTE_PTYPE_TUNNEL_GRE,
1413 RTE_PTYPE_INNER_L4_SCTP,
1415 RTE_PTYPE_INNER_L4_ICMP,
1416 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1419 static const uint32_t ol3table[HNS3_OL3TBL_NUM] = {
1423 RTE_PTYPE_L3_IPV4_EXT,
1424 RTE_PTYPE_L3_IPV6_EXT,
1425 0, 0, 0, 0, 0, 0, 0, 0, 0,
1429 static const uint32_t ol4table[HNS3_OL4TBL_NUM] = {
1431 RTE_PTYPE_TUNNEL_VXLAN,
1432 RTE_PTYPE_TUNNEL_NVGRE,
1433 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1436 l2id = hns3_get_field(pkt_info, HNS3_RXD_STRP_TAGP_M,
1437 HNS3_RXD_STRP_TAGP_S);
1438 l3id = hns3_get_field(pkt_info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
1439 l4id = hns3_get_field(pkt_info, HNS3_RXD_L4ID_M, HNS3_RXD_L4ID_S);
1440 ol3id = hns3_get_field(ol_info, HNS3_RXD_OL3ID_M, HNS3_RXD_OL3ID_S);
1441 ol4id = hns3_get_field(ol_info, HNS3_RXD_OL4ID_M, HNS3_RXD_OL4ID_S);
1443 if (ol4table[ol4id])
1444 pkt_type |= (inner_l2table[l2id] | inner_l3table[l3id] |
1445 inner_l4table[l4id] | ol3table[ol3id] |
1448 pkt_type |= (l2table[l2id] | l3table[l3id] | l4table[l4id]);
1453 hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1455 static const uint32_t ptypes[] = {
1457 RTE_PTYPE_L2_ETHER_VLAN,
1458 RTE_PTYPE_L2_ETHER_QINQ,
1459 RTE_PTYPE_L2_ETHER_LLDP,
1460 RTE_PTYPE_L2_ETHER_ARP,
1462 RTE_PTYPE_L3_IPV4_EXT,
1464 RTE_PTYPE_L3_IPV6_EXT,
1470 RTE_PTYPE_TUNNEL_GRE,
1474 if (dev->rx_pkt_burst == hns3_recv_pkts)
1481 hns3_clean_rx_buffers(struct hns3_rx_queue *rxq, int count)
1483 rxq->next_to_use += count;
1484 if (rxq->next_to_use >= rxq->nb_rx_desc)
1485 rxq->next_to_use -= rxq->nb_rx_desc;
1487 hns3_write_dev(rxq, HNS3_RING_RX_HEAD_REG, count);
1491 hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,
1492 uint32_t bd_base_info, uint32_t l234_info,
1493 uint32_t *cksum_err)
1497 if (unlikely(l234_info & BIT(HNS3_RXD_L2E_B))) {
1502 if (unlikely(rxm->pkt_len == 0 ||
1503 (l234_info & BIT(HNS3_RXD_TRUNCAT_B)))) {
1504 rxq->pkt_len_errors++;
1508 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B)) {
1509 if (unlikely(l234_info & BIT(HNS3_RXD_L3E_B))) {
1510 rxm->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1511 rxq->l3_csum_erros++;
1512 tmp |= HNS3_L3_CKSUM_ERR;
1515 if (unlikely(l234_info & BIT(HNS3_RXD_L4E_B))) {
1516 rxm->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1517 rxq->l4_csum_erros++;
1518 tmp |= HNS3_L4_CKSUM_ERR;
1521 if (unlikely(l234_info & BIT(HNS3_RXD_OL3E_B))) {
1522 rxq->ol3_csum_erros++;
1523 tmp |= HNS3_OUTER_L3_CKSUM_ERR;
1526 if (unlikely(l234_info & BIT(HNS3_RXD_OL4E_B))) {
1527 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
1528 rxq->ol4_csum_erros++;
1529 tmp |= HNS3_OUTER_L4_CKSUM_ERR;
1538 hns3_rx_set_cksum_flag(struct rte_mbuf *rxm, uint64_t packet_type,
1539 const uint32_t cksum_err)
1541 if (unlikely((packet_type & RTE_PTYPE_TUNNEL_MASK))) {
1542 if (likely(packet_type & RTE_PTYPE_INNER_L3_MASK) &&
1543 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
1544 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1545 if (likely(packet_type & RTE_PTYPE_INNER_L4_MASK) &&
1546 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
1547 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1548 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
1549 (cksum_err & HNS3_OUTER_L4_CKSUM_ERR) == 0)
1550 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
1552 if (likely(packet_type & RTE_PTYPE_L3_MASK) &&
1553 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
1554 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1555 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
1556 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
1557 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1562 hns3_rxd_to_vlan_tci(struct hns3_rx_queue *rxq, struct rte_mbuf *mb,
1563 uint32_t l234_info, const struct hns3_desc *rxd)
1565 #define HNS3_STRP_STATUS_NUM 0x4
1567 #define HNS3_NO_STRP_VLAN_VLD 0x0
1568 #define HNS3_INNER_STRP_VLAN_VLD 0x1
1569 #define HNS3_OUTER_STRP_VLAN_VLD 0x2
1570 uint32_t strip_status;
1571 uint32_t report_mode;
1574 * Since HW limitation, the vlan tag will always be inserted into RX
1575 * descriptor when strip the tag from packet, driver needs to determine
1576 * reporting which tag to mbuf according to the PVID configuration
1577 * and vlan striped status.
1579 static const uint32_t report_type[][HNS3_STRP_STATUS_NUM] = {
1581 HNS3_NO_STRP_VLAN_VLD,
1582 HNS3_OUTER_STRP_VLAN_VLD,
1583 HNS3_INNER_STRP_VLAN_VLD,
1584 HNS3_OUTER_STRP_VLAN_VLD
1587 HNS3_NO_STRP_VLAN_VLD,
1588 HNS3_NO_STRP_VLAN_VLD,
1589 HNS3_NO_STRP_VLAN_VLD,
1590 HNS3_INNER_STRP_VLAN_VLD
1593 strip_status = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,
1594 HNS3_RXD_STRP_TAGP_S);
1595 report_mode = report_type[rxq->pvid_state][strip_status];
1596 switch (report_mode) {
1597 case HNS3_NO_STRP_VLAN_VLD:
1600 case HNS3_INNER_STRP_VLAN_VLD:
1601 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1602 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.vlan_tag);
1604 case HNS3_OUTER_STRP_VLAN_VLD:
1605 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1606 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.ot_vlan_tag);
1612 recalculate_data_len(struct rte_mbuf *first_seg, struct rte_mbuf *last_seg,
1613 struct rte_mbuf *rxm, struct hns3_rx_queue *rxq,
1616 uint8_t crc_len = rxq->crc_len;
1618 if (data_len <= crc_len) {
1619 rte_pktmbuf_free_seg(rxm);
1620 first_seg->nb_segs--;
1621 last_seg->data_len = (uint16_t)(last_seg->data_len -
1622 (crc_len - data_len));
1623 last_seg->next = NULL;
1625 rxm->data_len = (uint16_t)(data_len - crc_len);
1629 hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1631 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
1632 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
1633 struct hns3_rx_queue *rxq; /* RX queue */
1634 struct hns3_entry *sw_ring;
1635 struct hns3_entry *rxe;
1636 struct rte_mbuf *first_seg;
1637 struct rte_mbuf *last_seg;
1638 struct hns3_desc rxd;
1639 struct rte_mbuf *nmb; /* pointer of the new mbuf */
1640 struct rte_mbuf *rxm;
1641 struct rte_eth_dev *dev;
1642 uint32_t bd_base_info;
1659 rx_id = rxq->next_to_clean;
1660 rx_ring = rxq->rx_ring;
1661 first_seg = rxq->pkt_first_seg;
1662 last_seg = rxq->pkt_last_seg;
1663 sw_ring = rxq->sw_ring;
1665 while (nb_rx < nb_pkts) {
1666 rxdp = &rx_ring[rx_id];
1667 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
1668 if (unlikely(!hns3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
1671 * The interactive process between software and hardware of
1672 * receiving a new packet in hns3 network engine:
1673 * 1. Hardware network engine firstly writes the packet content
1674 * to the memory pointed by the 'addr' field of the Rx Buffer
1675 * Descriptor, secondly fills the result of parsing the
1676 * packet include the valid field into the Rx Buffer
1677 * Descriptor in one write operation.
1678 * 2. Driver reads the Rx BD's valid field in the loop to check
1679 * whether it's valid, if valid then assign a new address to
1680 * the addr field, clear the valid field, get the other
1681 * information of the packet by parsing Rx BD's other fields,
1682 * finally write back the number of Rx BDs processed by the
1683 * driver to the HNS3_RING_RX_HEAD_REG register to inform
1685 * In the above process, the ordering is very important. We must
1686 * make sure that CPU read Rx BD's other fields only after the
1689 * There are two type of re-ordering: compiler re-ordering and
1690 * CPU re-ordering under the ARMv8 architecture.
1691 * 1. we use volatile to deal with compiler re-ordering, so you
1692 * can see that rx_ring/rxdp defined with volatile.
1693 * 2. we commonly use memory barrier to deal with CPU
1694 * re-ordering, but the cost is high.
1696 * In order to solve the high cost of using memory barrier, we
1697 * use the data dependency order under the ARMv8 architecture,
1700 * instr02: load B <- A
1701 * the instr02 will always execute after instr01.
1703 * To construct the data dependency ordering, we use the
1704 * following assignment:
1705 * rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
1706 * (1u<<HNS3_RXD_VLD_B)]
1707 * Using gcc compiler under the ARMv8 architecture, the related
1708 * assembly code example as follows:
1709 * note: (1u << HNS3_RXD_VLD_B) equal 0x10
1710 * instr01: ldr w26, [x22, #28] --read bd_base_info
1711 * instr02: and w0, w26, #0x10 --calc bd_base_info & 0x10
1712 * instr03: sub w0, w0, #0x10 --calc (bd_base_info &
1714 * instr04: add x0, x22, x0, lsl #5 --calc copy source addr
1715 * instr05: ldp x2, x3, [x0]
1716 * instr06: stp x2, x3, [x29, #256] --copy BD's [0 ~ 15]B
1717 * instr07: ldp x4, x5, [x0, #16]
1718 * instr08: stp x4, x5, [x29, #272] --copy BD's [16 ~ 31]B
1719 * the instr05~08 depend on x0's value, x0 depent on w26's
1720 * value, the w26 is the bd_base_info, this form the data
1721 * dependency ordering.
1722 * note: if BD is valid, (bd_base_info & (1u<<HNS3_RXD_VLD_B)) -
1723 * (1u<<HNS3_RXD_VLD_B) will always zero, so the
1724 * assignment is correct.
1726 * So we use the data dependency ordering instead of memory
1727 * barrier to improve receive performance.
1729 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
1730 (1u << HNS3_RXD_VLD_B)];
1732 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1733 if (unlikely(nmb == NULL)) {
1734 dev = &rte_eth_devices[rxq->port_id];
1735 dev->data->rx_mbuf_alloc_failed++;
1740 rxe = &sw_ring[rx_id];
1742 if (unlikely(rx_id == rxq->nb_rx_desc))
1745 rte_prefetch0(sw_ring[rx_id].mbuf);
1746 if ((rx_id & 0x3) == 0) {
1747 rte_prefetch0(&rx_ring[rx_id]);
1748 rte_prefetch0(&sw_ring[rx_id]);
1754 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1755 rxdp->rx.bd_base_info = 0;
1756 rxdp->addr = dma_addr;
1759 * Load remained descriptor data and extract necessary fields.
1760 * Data size from buffer description may contains CRC len,
1761 * packet len should subtract it.
1763 data_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.size));
1764 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
1765 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
1767 if (first_seg == NULL) {
1769 first_seg->nb_segs = 1;
1771 first_seg->nb_segs++;
1772 last_seg->next = rxm;
1775 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1776 rxm->data_len = data_len;
1778 if (!hns3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
1784 * The last buffer of the received packet. packet len from
1785 * buffer description may contains CRC len, packet len should
1786 * subtract it, same as data len.
1788 pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.pkt_len));
1789 first_seg->pkt_len = pkt_len;
1792 * This is the last buffer of the received packet. If the CRC
1793 * is not stripped by the hardware:
1794 * - Subtract the CRC length from the total packet length.
1795 * - If the last buffer only contains the whole CRC or a part
1796 * of it, free the mbuf associated to the last buffer. If part
1797 * of the CRC is also contained in the previous mbuf, subtract
1798 * the length of that CRC part from the data length of the
1802 if (unlikely(rxq->crc_len > 0)) {
1803 first_seg->pkt_len -= rxq->crc_len;
1804 recalculate_data_len(first_seg, last_seg, rxm, rxq,
1808 first_seg->port = rxq->port_id;
1809 first_seg->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
1810 first_seg->ol_flags = PKT_RX_RSS_HASH;
1811 if (unlikely(hns3_get_bit(bd_base_info, HNS3_RXD_LUM_B))) {
1812 first_seg->hash.fdir.hi =
1813 rte_le_to_cpu_32(rxd.rx.fd_id);
1814 first_seg->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1817 gro_size = hns3_get_field(bd_base_info, HNS3_RXD_GRO_SIZE_M,
1818 HNS3_RXD_GRO_SIZE_S);
1819 if (gro_size != 0) {
1820 first_seg->ol_flags |= PKT_RX_LRO;
1821 first_seg->tso_segsz = gro_size;
1824 ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info,
1825 l234_info, &cksum_err);
1829 first_seg->packet_type = rxd_pkt_info_to_pkt_type(l234_info,
1832 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B))
1833 hns3_rx_set_cksum_flag(first_seg,
1834 first_seg->packet_type,
1836 hns3_rxd_to_vlan_tci(rxq, first_seg, l234_info, &rxd);
1838 rx_pkts[nb_rx++] = first_seg;
1842 rte_pktmbuf_free(first_seg);
1846 rxq->next_to_clean = rx_id;
1847 rxq->pkt_first_seg = first_seg;
1848 rxq->pkt_last_seg = last_seg;
1850 nb_rx_bd = nb_rx_bd + rxq->nb_rx_hold;
1851 if (nb_rx_bd > rxq->rx_free_thresh) {
1852 hns3_clean_rx_buffers(rxq, nb_rx_bd);
1855 rxq->nb_rx_hold = nb_rx_bd;
1861 hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1862 unsigned int socket_id, const struct rte_eth_txconf *conf)
1864 struct hns3_adapter *hns = dev->data->dev_private;
1865 struct hns3_hw *hw = &hns->hw;
1866 struct hns3_queue_info q_info;
1867 struct hns3_tx_queue *txq;
1870 if (dev->data->dev_started) {
1871 hns3_err(hw, "tx_queue_setup after dev_start no supported");
1875 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1876 nb_desc % HNS3_ALIGN_RING_DESC) {
1877 hns3_err(hw, "Number (%u) of tx descriptors is invalid",
1882 if (dev->data->tx_queues[idx] != NULL) {
1883 hns3_tx_queue_release(dev->data->tx_queues[idx]);
1884 dev->data->tx_queues[idx] = NULL;
1888 q_info.socket_id = socket_id;
1889 q_info.nb_desc = nb_desc;
1890 q_info.type = "hns3 TX queue";
1891 q_info.ring_name = "tx_ring";
1892 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
1895 "Failed to alloc mem and reserve DMA mem for tx ring!");
1899 txq->tx_deferred_start = conf->tx_deferred_start;
1900 tx_entry_len = sizeof(struct hns3_entry) * txq->nb_tx_desc;
1901 txq->sw_ring = rte_zmalloc_socket("hns3 TX sw ring", tx_entry_len,
1902 RTE_CACHE_LINE_SIZE, socket_id);
1903 if (txq->sw_ring == NULL) {
1904 hns3_err(hw, "Failed to allocate memory for tx sw ring!");
1905 hns3_tx_queue_release(txq);
1910 txq->next_to_use = 0;
1911 txq->next_to_clean = 0;
1912 txq->tx_bd_ready = txq->nb_tx_desc - 1;
1913 txq->port_id = dev->data->port_id;
1914 txq->pvid_state = hw->port_base_vlan_cfg.state;
1915 txq->configured = true;
1916 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1917 idx * HNS3_TQP_REG_SIZE);
1918 txq->min_tx_pkt_len = hw->min_tx_pkt_len;
1919 txq->over_length_pkt_cnt = 0;
1920 txq->exceed_limit_bd_pkt_cnt = 0;
1921 txq->exceed_limit_bd_reassem_fail = 0;
1922 txq->unsupported_tunnel_pkt_cnt = 0;
1923 txq->queue_full_cnt = 0;
1924 txq->pkt_padding_fail_cnt = 0;
1925 rte_spinlock_lock(&hw->lock);
1926 dev->data->tx_queues[idx] = txq;
1927 rte_spinlock_unlock(&hw->lock);
1933 hns3_queue_xmit(struct hns3_tx_queue *txq, uint32_t buf_num)
1935 hns3_write_dev(txq, HNS3_RING_TX_TAIL_REG, buf_num);
1939 hns3_tx_free_useless_buffer(struct hns3_tx_queue *txq)
1941 uint16_t tx_next_clean = txq->next_to_clean;
1942 uint16_t tx_next_use = txq->next_to_use;
1943 uint16_t tx_bd_ready = txq->tx_bd_ready;
1944 uint16_t tx_bd_max = txq->nb_tx_desc;
1945 struct hns3_entry *tx_bak_pkt = &txq->sw_ring[tx_next_clean];
1946 struct hns3_desc *desc = &txq->tx_ring[tx_next_clean];
1947 struct rte_mbuf *mbuf;
1949 while ((!hns3_get_bit(desc->tx.tp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B)) &&
1950 tx_next_use != tx_next_clean) {
1951 mbuf = tx_bak_pkt->mbuf;
1953 rte_pktmbuf_free_seg(mbuf);
1954 tx_bak_pkt->mbuf = NULL;
1962 if (tx_next_clean >= tx_bd_max) {
1964 desc = txq->tx_ring;
1965 tx_bak_pkt = txq->sw_ring;
1969 txq->next_to_clean = tx_next_clean;
1970 txq->tx_bd_ready = tx_bd_ready;
1974 hns3_tso_proc_tunnel(struct hns3_desc *desc, uint64_t ol_flags,
1975 struct rte_mbuf *rxm, uint8_t *l2_len)
1981 tun_flags = ol_flags & PKT_TX_TUNNEL_MASK;
1985 otmp = rte_le_to_cpu_32(desc->tx.ol_type_vlan_len_msec);
1986 switch (tun_flags) {
1987 case PKT_TX_TUNNEL_GENEVE:
1988 case PKT_TX_TUNNEL_VXLAN:
1989 *l2_len = rxm->l2_len - RTE_ETHER_VXLAN_HLEN;
1991 case PKT_TX_TUNNEL_GRE:
1993 * OL4 header size, defined in 4 Bytes, it contains outer
1994 * L4(GRE) length and tunneling length.
1996 ol4_len = hns3_get_field(otmp, HNS3_TXD_L4LEN_M,
1998 *l2_len = rxm->l2_len - (ol4_len << HNS3_L4_LEN_UNIT);
2001 /* For non UDP / GRE tunneling, drop the tunnel packet */
2004 hns3_set_field(otmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2005 rxm->outer_l2_len >> HNS3_L2_LEN_UNIT);
2006 desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(otmp);
2012 hns3_config_gro(struct hns3_hw *hw, bool en)
2014 struct hns3_cfg_gro_status_cmd *req;
2015 struct hns3_cmd_desc desc;
2018 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
2019 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
2021 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
2023 ret = hns3_cmd_send(hw, &desc, 1);
2025 hns3_err(hw, "%s hardware GRO failed, ret = %d",
2026 en ? "enable" : "disable", ret);
2032 hns3_restore_gro_conf(struct hns3_hw *hw)
2038 offloads = hw->data->dev_conf.rxmode.offloads;
2039 gro_en = offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2040 ret = hns3_config_gro(hw, gro_en);
2042 hns3_err(hw, "restore hardware GRO to %s failed, ret = %d",
2043 gro_en ? "enabled" : "disabled", ret);
2049 hns3_pkt_is_tso(struct rte_mbuf *m)
2051 return (m->tso_segsz != 0 && m->ol_flags & PKT_TX_TCP_SEG);
2055 hns3_set_tso(struct hns3_desc *desc, uint64_t ol_flags,
2056 uint32_t paylen, struct rte_mbuf *rxm)
2058 uint8_t l2_len = rxm->l2_len;
2061 if (!hns3_pkt_is_tso(rxm))
2064 if (hns3_tso_proc_tunnel(desc, ol_flags, rxm, &l2_len))
2067 if (paylen <= rxm->tso_segsz)
2070 tmp = rte_le_to_cpu_32(desc->tx.type_cs_vlan_tso_len);
2071 hns3_set_bit(tmp, HNS3_TXD_TSO_B, 1);
2072 hns3_set_bit(tmp, HNS3_TXD_L3CS_B, 1);
2073 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S, HNS3_L4T_TCP);
2074 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2075 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2076 sizeof(struct rte_tcp_hdr) >> HNS3_L4_LEN_UNIT);
2077 hns3_set_field(tmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2078 l2_len >> HNS3_L2_LEN_UNIT);
2079 desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp);
2080 desc->tx.mss = rte_cpu_to_le_16(rxm->tso_segsz);
2084 hns3_fill_per_desc(struct hns3_desc *desc, struct rte_mbuf *rxm)
2086 desc->addr = rte_mbuf_data_iova(rxm);
2087 desc->tx.send_size = rte_cpu_to_le_16(rte_pktmbuf_data_len(rxm));
2088 desc->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B));
2092 hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc,
2093 struct rte_mbuf *rxm)
2095 uint64_t ol_flags = rxm->ol_flags;
2099 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len;
2100 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
2101 rxm->outer_l2_len + rxm->outer_l3_len : 0;
2102 paylen = rxm->pkt_len - hdr_len;
2103 desc->tx.paylen = rte_cpu_to_le_32(paylen);
2104 hns3_set_tso(desc, ol_flags, paylen, rxm);
2107 * Currently, hardware doesn't support more than two layers VLAN offload
2108 * in Tx direction based on hns3 network engine. So when the number of
2109 * VLANs in the packets represented by rxm plus the number of VLAN
2110 * offload by hardware such as PVID etc, exceeds two, the packets will
2111 * be discarded or the original VLAN of the packets will be overwitted
2112 * by hardware. When the PF PVID is enabled by calling the API function
2113 * named rte_eth_dev_set_vlan_pvid or the VF PVID is enabled by the hns3
2114 * PF kernel ether driver, the outer VLAN tag will always be the PVID.
2115 * To avoid the VLAN of Tx descriptor is overwritten by PVID, it should
2116 * be added to the position close to the IP header when PVID is enabled.
2118 if (!txq->pvid_state && ol_flags & (PKT_TX_VLAN_PKT |
2120 desc->tx.ol_type_vlan_len_msec |=
2121 rte_cpu_to_le_32(BIT(HNS3_TXD_OVLAN_B));
2122 if (ol_flags & PKT_TX_QINQ_PKT)
2123 desc->tx.outer_vlan_tag =
2124 rte_cpu_to_le_16(rxm->vlan_tci_outer);
2126 desc->tx.outer_vlan_tag =
2127 rte_cpu_to_le_16(rxm->vlan_tci);
2130 if (ol_flags & PKT_TX_QINQ_PKT ||
2131 ((ol_flags & PKT_TX_VLAN_PKT) && txq->pvid_state)) {
2132 desc->tx.type_cs_vlan_tso_len |=
2133 rte_cpu_to_le_32(BIT(HNS3_TXD_VLAN_B));
2134 desc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci);
2139 hns3_tx_alloc_mbufs(struct hns3_tx_queue *txq, struct rte_mempool *mb_pool,
2140 uint16_t nb_new_buf, struct rte_mbuf **alloc_mbuf)
2142 struct rte_mbuf *new_mbuf = NULL;
2143 struct rte_eth_dev *dev;
2144 struct rte_mbuf *temp;
2148 /* Allocate enough mbufs */
2149 for (i = 0; i < nb_new_buf; i++) {
2150 temp = rte_pktmbuf_alloc(mb_pool);
2151 if (unlikely(temp == NULL)) {
2152 dev = &rte_eth_devices[txq->port_id];
2153 hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2154 hns3_err(hw, "Failed to alloc TX mbuf port_id=%d,"
2155 "queue_id=%d in reassemble tx pkts.",
2156 txq->port_id, txq->queue_id);
2157 rte_pktmbuf_free(new_mbuf);
2160 temp->next = new_mbuf;
2164 if (new_mbuf == NULL)
2167 new_mbuf->nb_segs = nb_new_buf;
2168 *alloc_mbuf = new_mbuf;
2174 hns3_pktmbuf_copy_hdr(struct rte_mbuf *new_pkt, struct rte_mbuf *old_pkt)
2176 new_pkt->ol_flags = old_pkt->ol_flags;
2177 new_pkt->pkt_len = rte_pktmbuf_pkt_len(old_pkt);
2178 new_pkt->outer_l2_len = old_pkt->outer_l2_len;
2179 new_pkt->outer_l3_len = old_pkt->outer_l3_len;
2180 new_pkt->l2_len = old_pkt->l2_len;
2181 new_pkt->l3_len = old_pkt->l3_len;
2182 new_pkt->l4_len = old_pkt->l4_len;
2183 new_pkt->vlan_tci_outer = old_pkt->vlan_tci_outer;
2184 new_pkt->vlan_tci = old_pkt->vlan_tci;
2188 hns3_reassemble_tx_pkts(void *tx_queue, struct rte_mbuf *tx_pkt,
2189 struct rte_mbuf **new_pkt)
2191 struct hns3_tx_queue *txq = tx_queue;
2192 struct rte_mempool *mb_pool;
2193 struct rte_mbuf *new_mbuf;
2194 struct rte_mbuf *temp_new;
2195 struct rte_mbuf *temp;
2196 uint16_t last_buf_len;
2197 uint16_t nb_new_buf;
2208 mb_pool = tx_pkt->pool;
2209 buf_size = tx_pkt->buf_len - RTE_PKTMBUF_HEADROOM;
2210 nb_new_buf = (rte_pktmbuf_pkt_len(tx_pkt) - 1) / buf_size + 1;
2211 if (nb_new_buf > HNS3_MAX_NON_TSO_BD_PER_PKT)
2214 last_buf_len = rte_pktmbuf_pkt_len(tx_pkt) % buf_size;
2215 if (last_buf_len == 0)
2216 last_buf_len = buf_size;
2218 /* Allocate enough mbufs */
2219 ret = hns3_tx_alloc_mbufs(txq, mb_pool, nb_new_buf, &new_mbuf);
2223 /* Copy the original packet content to the new mbufs */
2225 s = rte_pktmbuf_mtod(temp, char *);
2226 len_s = rte_pktmbuf_data_len(temp);
2227 temp_new = new_mbuf;
2228 for (i = 0; i < nb_new_buf; i++) {
2229 d = rte_pktmbuf_mtod(temp_new, char *);
2230 if (i < nb_new_buf - 1)
2233 buf_len = last_buf_len;
2237 len = RTE_MIN(len_s, len_d);
2241 len_d = len_d - len;
2242 len_s = len_s - len;
2248 s = rte_pktmbuf_mtod(temp, char *);
2249 len_s = rte_pktmbuf_data_len(temp);
2253 temp_new->data_len = buf_len;
2254 temp_new = temp_new->next;
2256 hns3_pktmbuf_copy_hdr(new_mbuf, tx_pkt);
2258 /* free original mbufs */
2259 rte_pktmbuf_free(tx_pkt);
2261 *new_pkt = new_mbuf;
2267 hns3_parse_outer_params(uint64_t ol_flags, uint32_t *ol_type_vlan_len_msec)
2269 uint32_t tmp = *ol_type_vlan_len_msec;
2271 /* (outer) IP header type */
2272 if (ol_flags & PKT_TX_OUTER_IPV4) {
2273 /* OL3 header size, defined in 4 bytes */
2274 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2275 sizeof(struct rte_ipv4_hdr) >> HNS3_L3_LEN_UNIT);
2276 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2277 hns3_set_field(tmp, HNS3_TXD_OL3T_M,
2278 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_CSUM);
2280 hns3_set_field(tmp, HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
2281 HNS3_OL3T_IPV4_NO_CSUM);
2282 } else if (ol_flags & PKT_TX_OUTER_IPV6) {
2283 hns3_set_field(tmp, HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
2285 /* OL3 header size, defined in 4 bytes */
2286 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2287 sizeof(struct rte_ipv6_hdr) >> HNS3_L3_LEN_UNIT);
2290 *ol_type_vlan_len_msec = tmp;
2294 hns3_parse_inner_params(uint64_t ol_flags, uint32_t *ol_type_vlan_len_msec,
2295 struct rte_net_hdr_lens *hdr_lens)
2297 uint32_t tmp = *ol_type_vlan_len_msec;
2300 /* OL2 header size, defined in 2 bytes */
2301 hns3_set_field(tmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2302 sizeof(struct rte_ether_hdr) >> HNS3_L2_LEN_UNIT);
2304 /* L4TUNT: L4 Tunneling Type */
2305 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2306 case PKT_TX_TUNNEL_GENEVE:
2307 case PKT_TX_TUNNEL_VXLAN:
2308 /* MAC in UDP tunnelling packet, include VxLAN */
2309 hns3_set_field(tmp, HNS3_TXD_TUNTYPE_M, HNS3_TXD_TUNTYPE_S,
2310 HNS3_TUN_MAC_IN_UDP);
2312 * OL4 header size, defined in 4 Bytes, it contains outer
2313 * L4(UDP) length and tunneling length.
2315 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2316 (uint8_t)RTE_ETHER_VXLAN_HLEN >>
2319 case PKT_TX_TUNNEL_GRE:
2320 hns3_set_field(tmp, HNS3_TXD_TUNTYPE_M, HNS3_TXD_TUNTYPE_S,
2323 * OL4 header size, defined in 4 Bytes, it contains outer
2324 * L4(GRE) length and tunneling length.
2326 l4_len = hdr_lens->l4_len + hdr_lens->tunnel_len;
2327 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2328 l4_len >> HNS3_L4_LEN_UNIT);
2331 /* For non UDP / GRE tunneling, drop the tunnel packet */
2335 *ol_type_vlan_len_msec = tmp;
2341 hns3_parse_tunneling_params(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
2343 struct rte_net_hdr_lens *hdr_lens)
2345 struct hns3_desc *tx_ring = txq->tx_ring;
2346 struct hns3_desc *desc = &tx_ring[tx_desc_id];
2350 hns3_parse_outer_params(ol_flags, &value);
2351 ret = hns3_parse_inner_params(ol_flags, &value, hdr_lens);
2355 desc->tx.ol_type_vlan_len_msec |= rte_cpu_to_le_32(value);
2361 hns3_parse_l3_cksum_params(uint64_t ol_flags, uint32_t *type_cs_vlan_tso_len)
2365 /* Enable L3 checksum offloads */
2366 if (ol_flags & PKT_TX_IPV4) {
2367 tmp = *type_cs_vlan_tso_len;
2368 hns3_set_field(tmp, HNS3_TXD_L3T_M, HNS3_TXD_L3T_S,
2370 /* inner(/normal) L3 header size, defined in 4 bytes */
2371 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2372 sizeof(struct rte_ipv4_hdr) >> HNS3_L3_LEN_UNIT);
2373 if (ol_flags & PKT_TX_IP_CKSUM)
2374 hns3_set_bit(tmp, HNS3_TXD_L3CS_B, 1);
2375 *type_cs_vlan_tso_len = tmp;
2376 } else if (ol_flags & PKT_TX_IPV6) {
2377 tmp = *type_cs_vlan_tso_len;
2378 /* L3T, IPv6 don't do checksum */
2379 hns3_set_field(tmp, HNS3_TXD_L3T_M, HNS3_TXD_L3T_S,
2381 /* inner(/normal) L3 header size, defined in 4 bytes */
2382 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2383 sizeof(struct rte_ipv6_hdr) >> HNS3_L3_LEN_UNIT);
2384 *type_cs_vlan_tso_len = tmp;
2389 hns3_parse_l4_cksum_params(uint64_t ol_flags, uint32_t *type_cs_vlan_tso_len)
2393 /* Enable L4 checksum offloads */
2394 switch (ol_flags & PKT_TX_L4_MASK) {
2395 case PKT_TX_TCP_CKSUM:
2396 tmp = *type_cs_vlan_tso_len;
2397 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
2399 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2400 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2401 sizeof(struct rte_tcp_hdr) >> HNS3_L4_LEN_UNIT);
2402 *type_cs_vlan_tso_len = tmp;
2404 case PKT_TX_UDP_CKSUM:
2405 tmp = *type_cs_vlan_tso_len;
2406 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
2408 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2409 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2410 sizeof(struct rte_udp_hdr) >> HNS3_L4_LEN_UNIT);
2411 *type_cs_vlan_tso_len = tmp;
2413 case PKT_TX_SCTP_CKSUM:
2414 tmp = *type_cs_vlan_tso_len;
2415 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
2417 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2418 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2419 sizeof(struct rte_sctp_hdr) >> HNS3_L4_LEN_UNIT);
2420 *type_cs_vlan_tso_len = tmp;
2428 hns3_txd_enable_checksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
2431 struct hns3_desc *tx_ring = txq->tx_ring;
2432 struct hns3_desc *desc = &tx_ring[tx_desc_id];
2435 /* inner(/normal) L2 header size, defined in 2 bytes */
2436 hns3_set_field(value, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2437 sizeof(struct rte_ether_hdr) >> HNS3_L2_LEN_UNIT);
2439 hns3_parse_l3_cksum_params(ol_flags, &value);
2440 hns3_parse_l4_cksum_params(ol_flags, &value);
2442 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(value);
2446 hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num)
2448 struct rte_mbuf *m_first = tx_pkts;
2449 struct rte_mbuf *m_last = tx_pkts;
2450 uint32_t tot_len = 0;
2455 * Hardware requires that the sum of the data length of every 8
2456 * consecutive buffers is greater than MSS in hns3 network engine.
2457 * We simplify it by ensuring pkt_headlen + the first 8 consecutive
2458 * frags greater than gso header len + mss, and the remaining 7
2459 * consecutive frags greater than MSS except the last 7 frags.
2461 if (bd_num <= HNS3_MAX_NON_TSO_BD_PER_PKT)
2464 for (i = 0; m_last && i < HNS3_MAX_NON_TSO_BD_PER_PKT - 1;
2465 i++, m_last = m_last->next)
2466 tot_len += m_last->data_len;
2471 /* ensure the first 8 frags is greater than mss + header */
2472 hdr_len = tx_pkts->l2_len + tx_pkts->l3_len + tx_pkts->l4_len;
2473 hdr_len += (tx_pkts->ol_flags & PKT_TX_TUNNEL_MASK) ?
2474 tx_pkts->outer_l2_len + tx_pkts->outer_l3_len : 0;
2475 if (tot_len + m_last->data_len < tx_pkts->tso_segsz + hdr_len)
2479 * ensure the sum of the data length of every 7 consecutive buffer
2480 * is greater than mss except the last one.
2482 for (i = 0; m_last && i < bd_num - HNS3_MAX_NON_TSO_BD_PER_PKT; i++) {
2483 tot_len -= m_first->data_len;
2484 tot_len += m_last->data_len;
2486 if (tot_len < tx_pkts->tso_segsz)
2489 m_first = m_first->next;
2490 m_last = m_last->next;
2497 hns3_outer_header_cksum_prepare(struct rte_mbuf *m)
2499 uint64_t ol_flags = m->ol_flags;
2500 struct rte_ipv4_hdr *ipv4_hdr;
2501 struct rte_udp_hdr *udp_hdr;
2502 uint32_t paylen, hdr_len;
2504 if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6)))
2507 if (ol_flags & PKT_TX_IPV4) {
2508 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2511 if (ol_flags & PKT_TX_IP_CKSUM)
2512 ipv4_hdr->hdr_checksum = 0;
2515 if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_UDP_CKSUM &&
2516 ol_flags & PKT_TX_TCP_SEG) {
2517 hdr_len = m->l2_len + m->l3_len + m->l4_len;
2518 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
2519 m->outer_l2_len + m->outer_l3_len : 0;
2520 paylen = m->pkt_len - hdr_len;
2521 if (paylen <= m->tso_segsz)
2523 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
2526 udp_hdr->dgram_cksum = 0;
2531 hns3_check_tso_pkt_valid(struct rte_mbuf *m)
2533 uint32_t tmp_data_len_sum = 0;
2534 uint16_t nb_buf = m->nb_segs;
2535 uint32_t paylen, hdr_len;
2536 struct rte_mbuf *m_seg;
2539 if (nb_buf > HNS3_MAX_TSO_BD_PER_PKT)
2542 hdr_len = m->l2_len + m->l3_len + m->l4_len;
2543 hdr_len += (m->ol_flags & PKT_TX_TUNNEL_MASK) ?
2544 m->outer_l2_len + m->outer_l3_len : 0;
2545 if (hdr_len > HNS3_MAX_TSO_HDR_SIZE)
2548 paylen = m->pkt_len - hdr_len;
2549 if (paylen > HNS3_MAX_BD_PAYLEN)
2553 * The TSO header (include outer and inner L2, L3 and L4 header)
2554 * should be provided by three descriptors in maximum in hns3 network
2558 for (i = 0; m_seg != NULL && i < HNS3_MAX_TSO_HDR_BD_NUM && i < nb_buf;
2559 i++, m_seg = m_seg->next) {
2560 tmp_data_len_sum += m_seg->data_len;
2563 if (hdr_len > tmp_data_len_sum)
2569 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2571 hns3_vld_vlan_chk(struct hns3_tx_queue *txq, struct rte_mbuf *m)
2573 struct rte_ether_hdr *eh;
2574 struct rte_vlan_hdr *vh;
2576 if (!txq->pvid_state)
2580 * Due to hardware limitations, we only support two-layer VLAN hardware
2581 * offload in Tx direction based on hns3 network engine, so when PVID is
2582 * enabled, QinQ insert is no longer supported.
2583 * And when PVID is enabled, in the following two cases:
2584 * i) packets with more than two VLAN tags.
2585 * ii) packets with one VLAN tag while the hardware VLAN insert is
2587 * The packets will be regarded as abnormal packets and discarded by
2588 * hardware in Tx direction. For debugging purposes, a validation check
2589 * for these types of packets is added to the '.tx_pkt_prepare' ops
2590 * implementation function named hns3_prep_pkts to inform users that
2591 * these packets will be discarded.
2593 if (m->ol_flags & PKT_TX_QINQ_PKT)
2596 eh = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
2597 if (eh->ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
2598 if (m->ol_flags & PKT_TX_VLAN_PKT)
2601 /* Ensure the incoming packet is not a QinQ packet */
2602 vh = (struct rte_vlan_hdr *)(eh + 1);
2603 if (vh->eth_proto == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN))
2612 hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2619 for (i = 0; i < nb_pkts; i++) {
2622 if (hns3_pkt_is_tso(m) &&
2623 (hns3_pkt_need_linearized(m, m->nb_segs) ||
2624 hns3_check_tso_pkt_valid(m))) {
2629 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2630 ret = rte_validate_tx_offload(m);
2636 if (hns3_vld_vlan_chk(tx_queue, m)) {
2641 ret = rte_net_intel_cksum_prepare(m);
2647 hns3_outer_header_cksum_prepare(m);
2654 hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
2655 const struct rte_mbuf *m, struct rte_net_hdr_lens *hdr_lens)
2657 /* Fill in tunneling parameters if necessary */
2658 if (m->ol_flags & PKT_TX_TUNNEL_MASK) {
2659 (void)rte_net_get_ptype(m, hdr_lens, RTE_PTYPE_ALL_MASK);
2660 if (hns3_parse_tunneling_params(txq, tx_desc_id, m->ol_flags,
2662 txq->unsupported_tunnel_pkt_cnt++;
2666 /* Enable checksum offloading */
2667 if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK)
2668 hns3_txd_enable_checksum(txq, tx_desc_id, m->ol_flags);
2674 hns3_check_non_tso_pkt(uint16_t nb_buf, struct rte_mbuf **m_seg,
2675 struct rte_mbuf *tx_pkt, struct hns3_tx_queue *txq)
2677 struct rte_mbuf *new_pkt;
2680 if (hns3_pkt_is_tso(*m_seg))
2684 * If packet length is greater than HNS3_MAX_FRAME_LEN
2685 * driver support, the packet will be ignored.
2687 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) > HNS3_MAX_FRAME_LEN)) {
2688 txq->over_length_pkt_cnt++;
2692 if (unlikely(nb_buf > HNS3_MAX_NON_TSO_BD_PER_PKT)) {
2693 txq->exceed_limit_bd_pkt_cnt++;
2694 ret = hns3_reassemble_tx_pkts(txq, tx_pkt, &new_pkt);
2696 txq->exceed_limit_bd_reassem_fail++;
2706 hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2708 struct rte_net_hdr_lens hdr_lens = {0};
2709 struct hns3_tx_queue *txq = tx_queue;
2710 struct hns3_entry *tx_bak_pkt;
2711 struct hns3_desc *tx_ring;
2712 struct rte_mbuf *tx_pkt;
2713 struct rte_mbuf *m_seg;
2714 struct hns3_desc *desc;
2715 uint32_t nb_hold = 0;
2716 uint16_t tx_next_use;
2717 uint16_t tx_pkt_num;
2723 /* free useless buffer */
2724 hns3_tx_free_useless_buffer(txq);
2726 tx_next_use = txq->next_to_use;
2727 tx_bd_max = txq->nb_tx_desc;
2728 tx_pkt_num = nb_pkts;
2729 tx_ring = txq->tx_ring;
2732 tx_bak_pkt = &txq->sw_ring[tx_next_use];
2733 for (nb_tx = 0; nb_tx < tx_pkt_num; nb_tx++) {
2734 tx_pkt = *tx_pkts++;
2736 nb_buf = tx_pkt->nb_segs;
2738 if (nb_buf > txq->tx_bd_ready) {
2739 txq->queue_full_cnt++;
2747 * If packet length is less than minimum packet length supported
2748 * by hardware in Tx direction, driver need to pad it to avoid
2751 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) <
2752 txq->min_tx_pkt_len)) {
2756 add_len = txq->min_tx_pkt_len -
2757 rte_pktmbuf_pkt_len(tx_pkt);
2758 appended = rte_pktmbuf_append(tx_pkt, add_len);
2759 if (appended == NULL) {
2760 txq->pkt_padding_fail_cnt++;
2764 memset(appended, 0, add_len);
2769 if (hns3_check_non_tso_pkt(nb_buf, &m_seg, tx_pkt, txq))
2772 if (hns3_parse_cksum(txq, tx_next_use, m_seg, &hdr_lens))
2776 desc = &tx_ring[tx_next_use];
2779 * If the packet is divided into multiple Tx Buffer Descriptors,
2780 * only need to fill vlan, paylen and tso into the first Tx
2781 * Buffer Descriptor.
2783 hns3_fill_first_desc(txq, desc, m_seg);
2786 desc = &tx_ring[tx_next_use];
2788 * Fill valid bits, DMA address and data length for each
2789 * Tx Buffer Descriptor.
2791 hns3_fill_per_desc(desc, m_seg);
2792 tx_bak_pkt->mbuf = m_seg;
2793 m_seg = m_seg->next;
2796 if (tx_next_use >= tx_bd_max) {
2798 tx_bak_pkt = txq->sw_ring;
2802 } while (m_seg != NULL);
2804 /* Add end flag for the last Tx Buffer Descriptor */
2805 desc->tx.tp_fe_sc_vld_ra_ri |=
2806 rte_cpu_to_le_16(BIT(HNS3_TXD_FE_B));
2809 txq->next_to_use = tx_next_use;
2810 txq->tx_bd_ready -= i;
2816 hns3_queue_xmit(txq, nb_hold);
2822 hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused,
2823 struct rte_mbuf **pkts __rte_unused,
2824 uint16_t pkts_n __rte_unused)
2829 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)
2831 struct hns3_adapter *hns = eth_dev->data->dev_private;
2833 if (hns->hw.adapter_state == HNS3_NIC_STARTED &&
2834 rte_atomic16_read(&hns->hw.reset.resetting) == 0) {
2835 eth_dev->rx_pkt_burst = hns3_recv_pkts;
2836 eth_dev->tx_pkt_burst = hns3_xmit_pkts;
2837 eth_dev->tx_pkt_prepare = hns3_prep_pkts;
2839 eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst;
2840 eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
2841 eth_dev->tx_pkt_prepare = hns3_dummy_rxtx_burst;
2846 hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2847 struct rte_eth_rxq_info *qinfo)
2849 struct hns3_rx_queue *rxq = dev->data->rx_queues[queue_id];
2851 qinfo->mp = rxq->mb_pool;
2852 qinfo->nb_desc = rxq->nb_rx_desc;
2853 qinfo->scattered_rx = dev->data->scattered_rx;
2856 * If there are no available Rx buffer descriptors, incoming packets
2857 * are always dropped by hardware based on hns3 network engine.
2859 qinfo->conf.rx_drop_en = 1;
2860 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2861 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2862 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2866 hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2867 struct rte_eth_txq_info *qinfo)
2869 struct hns3_tx_queue *txq = dev->data->tx_queues[queue_id];
2871 qinfo->nb_desc = txq->nb_tx_desc;
2872 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
2873 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;