1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #include <rte_bus_pci.h>
6 #include <rte_common.h>
7 #include <rte_cycles.h>
8 #include <rte_geneve.h>
10 #include <ethdev_driver.h>
13 #include <rte_malloc.h>
14 #if defined(RTE_ARCH_ARM64)
15 #include <rte_cpuflags.h>
19 #include "hns3_ethdev.h"
20 #include "hns3_rxtx.h"
21 #include "hns3_regs.h"
22 #include "hns3_logs.h"
25 #define HNS3_CFG_DESC_NUM(num) ((num) / 8 - 1)
26 #define HNS3_RX_RING_PREFETCTH_MASK 3
29 hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq)
33 /* Note: Fake rx queue will not enter here */
34 if (rxq->sw_ring == NULL)
37 if (rxq->rx_rearm_nb == 0) {
38 for (i = 0; i < rxq->nb_rx_desc; i++) {
39 if (rxq->sw_ring[i].mbuf != NULL) {
40 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
41 rxq->sw_ring[i].mbuf = NULL;
45 for (i = rxq->next_to_use;
46 i != rxq->rx_rearm_start;
47 i = (i + 1) % rxq->nb_rx_desc) {
48 if (rxq->sw_ring[i].mbuf != NULL) {
49 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
50 rxq->sw_ring[i].mbuf = NULL;
55 for (i = 0; i < rxq->bulk_mbuf_num; i++)
56 rte_pktmbuf_free_seg(rxq->bulk_mbuf[i]);
57 rxq->bulk_mbuf_num = 0;
59 if (rxq->pkt_first_seg) {
60 rte_pktmbuf_free(rxq->pkt_first_seg);
61 rxq->pkt_first_seg = NULL;
66 hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq)
70 /* Note: Fake tx queue will not enter here */
72 for (i = 0; i < txq->nb_tx_desc; i++) {
73 if (txq->sw_ring[i].mbuf) {
74 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
75 txq->sw_ring[i].mbuf = NULL;
82 hns3_rx_queue_release(void *queue)
84 struct hns3_rx_queue *rxq = queue;
86 hns3_rx_queue_release_mbufs(rxq);
88 rte_memzone_free(rxq->mz);
90 rte_free(rxq->sw_ring);
96 hns3_tx_queue_release(void *queue)
98 struct hns3_tx_queue *txq = queue;
100 hns3_tx_queue_release_mbufs(txq);
102 rte_memzone_free(txq->mz);
104 rte_free(txq->sw_ring);
112 hns3_dev_rx_queue_release(void *queue)
114 struct hns3_rx_queue *rxq = queue;
115 struct hns3_adapter *hns;
121 rte_spinlock_lock(&hns->hw.lock);
122 hns3_rx_queue_release(queue);
123 rte_spinlock_unlock(&hns->hw.lock);
127 hns3_dev_tx_queue_release(void *queue)
129 struct hns3_tx_queue *txq = queue;
130 struct hns3_adapter *hns;
136 rte_spinlock_lock(&hns->hw.lock);
137 hns3_tx_queue_release(queue);
138 rte_spinlock_unlock(&hns->hw.lock);
142 hns3_fake_rx_queue_release(struct hns3_rx_queue *queue)
144 struct hns3_rx_queue *rxq = queue;
145 struct hns3_adapter *hns;
155 if (hw->fkq_data.rx_queues[idx]) {
156 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
157 hw->fkq_data.rx_queues[idx] = NULL;
160 /* free fake rx queue arrays */
161 if (idx == (hw->fkq_data.nb_fake_rx_queues - 1)) {
162 hw->fkq_data.nb_fake_rx_queues = 0;
163 rte_free(hw->fkq_data.rx_queues);
164 hw->fkq_data.rx_queues = NULL;
169 hns3_fake_tx_queue_release(struct hns3_tx_queue *queue)
171 struct hns3_tx_queue *txq = queue;
172 struct hns3_adapter *hns;
182 if (hw->fkq_data.tx_queues[idx]) {
183 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
184 hw->fkq_data.tx_queues[idx] = NULL;
187 /* free fake tx queue arrays */
188 if (idx == (hw->fkq_data.nb_fake_tx_queues - 1)) {
189 hw->fkq_data.nb_fake_tx_queues = 0;
190 rte_free(hw->fkq_data.tx_queues);
191 hw->fkq_data.tx_queues = NULL;
196 hns3_free_rx_queues(struct rte_eth_dev *dev)
198 struct hns3_adapter *hns = dev->data->dev_private;
199 struct hns3_fake_queue_data *fkq_data;
200 struct hns3_hw *hw = &hns->hw;
204 nb_rx_q = hw->data->nb_rx_queues;
205 for (i = 0; i < nb_rx_q; i++) {
206 if (dev->data->rx_queues[i]) {
207 hns3_rx_queue_release(dev->data->rx_queues[i]);
208 dev->data->rx_queues[i] = NULL;
212 /* Free fake Rx queues */
213 fkq_data = &hw->fkq_data;
214 for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) {
215 if (fkq_data->rx_queues[i])
216 hns3_fake_rx_queue_release(fkq_data->rx_queues[i]);
221 hns3_free_tx_queues(struct rte_eth_dev *dev)
223 struct hns3_adapter *hns = dev->data->dev_private;
224 struct hns3_fake_queue_data *fkq_data;
225 struct hns3_hw *hw = &hns->hw;
229 nb_tx_q = hw->data->nb_tx_queues;
230 for (i = 0; i < nb_tx_q; i++) {
231 if (dev->data->tx_queues[i]) {
232 hns3_tx_queue_release(dev->data->tx_queues[i]);
233 dev->data->tx_queues[i] = NULL;
237 /* Free fake Tx queues */
238 fkq_data = &hw->fkq_data;
239 for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) {
240 if (fkq_data->tx_queues[i])
241 hns3_fake_tx_queue_release(fkq_data->tx_queues[i]);
246 hns3_free_all_queues(struct rte_eth_dev *dev)
248 hns3_free_rx_queues(dev);
249 hns3_free_tx_queues(dev);
253 hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq)
255 struct rte_mbuf *mbuf;
259 for (i = 0; i < rxq->nb_rx_desc; i++) {
260 mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
261 if (unlikely(mbuf == NULL)) {
262 hns3_err(hw, "Failed to allocate RXD[%u] for rx queue!",
264 hns3_rx_queue_release_mbufs(rxq);
268 rte_mbuf_refcnt_set(mbuf, 1);
270 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
272 mbuf->port = rxq->port_id;
274 rxq->sw_ring[i].mbuf = mbuf;
275 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
276 rxq->rx_ring[i].addr = dma_addr;
277 rxq->rx_ring[i].rx.bd_base_info = 0;
284 hns3_buf_size2type(uint32_t buf_size)
290 bd_size_type = HNS3_BD_SIZE_512_TYPE;
293 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
296 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
299 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
306 hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)
308 uint32_t rx_buf_len = rxq->rx_buf_len;
309 uint64_t dma_addr = rxq->rx_ring_phys_addr;
311 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);
312 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,
313 (uint32_t)((dma_addr >> 31) >> 1));
315 hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,
316 hns3_buf_size2type(rx_buf_len));
317 hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG,
318 HNS3_CFG_DESC_NUM(rxq->nb_rx_desc));
322 hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)
324 uint64_t dma_addr = txq->tx_ring_phys_addr;
326 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);
327 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,
328 (uint32_t)((dma_addr >> 31) >> 1));
330 hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,
331 HNS3_CFG_DESC_NUM(txq->nb_tx_desc));
335 hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw)
337 uint16_t nb_rx_q = hw->data->nb_rx_queues;
338 uint16_t nb_tx_q = hw->data->nb_tx_queues;
339 struct hns3_rx_queue *rxq;
340 struct hns3_tx_queue *txq;
344 pvid_en = hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE;
345 for (i = 0; i < hw->cfg_max_queues; i++) {
347 rxq = hw->data->rx_queues[i];
349 rxq->pvid_sw_discard_en = pvid_en;
352 txq = hw->data->tx_queues[i];
354 txq->pvid_sw_shift_en = pvid_en;
360 hns3_stop_unused_queue(void *tqp_base, enum hns3_ring_type queue_type)
365 reg_offset = queue_type == HNS3_RING_TYPE_TX ?
366 HNS3_RING_TX_EN_REG : HNS3_RING_RX_EN_REG;
367 reg = hns3_read_reg(tqp_base, reg_offset);
368 reg &= ~BIT(HNS3_RING_EN_B);
369 hns3_write_reg(tqp_base, reg_offset, reg);
373 hns3_enable_all_queues(struct hns3_hw *hw, bool en)
375 uint16_t nb_rx_q = hw->data->nb_rx_queues;
376 uint16_t nb_tx_q = hw->data->nb_tx_queues;
377 struct hns3_rx_queue *rxq;
378 struct hns3_tx_queue *txq;
383 for (i = 0; i < hw->cfg_max_queues; i++) {
384 if (hns3_dev_indep_txrx_supported(hw)) {
385 rxq = i < nb_rx_q ? hw->data->rx_queues[i] : NULL;
386 txq = i < nb_tx_q ? hw->data->tx_queues[i] : NULL;
388 tqp_base = (void *)((char *)hw->io_base +
389 hns3_get_tqp_reg_offset(i));
391 * If queue struct is not initialized, it means the
392 * related HW ring has not been initialized yet.
393 * So, these queues should be disabled before enable
394 * the tqps to avoid a HW exception since the queues
395 * are enabled by default.
398 hns3_stop_unused_queue(tqp_base,
401 hns3_stop_unused_queue(tqp_base,
404 rxq = i < nb_rx_q ? hw->data->rx_queues[i] :
405 hw->fkq_data.rx_queues[i - nb_rx_q];
407 tqp_base = rxq->io_base;
410 * This is the master switch that used to control the enabling
411 * of a pair of Tx and Rx queues. Both the Rx and Tx point to
414 rcb_reg = hns3_read_reg(tqp_base, HNS3_RING_EN_REG);
416 rcb_reg |= BIT(HNS3_RING_EN_B);
418 rcb_reg &= ~BIT(HNS3_RING_EN_B);
419 hns3_write_reg(tqp_base, HNS3_RING_EN_REG, rcb_reg);
424 hns3_enable_txq(struct hns3_tx_queue *txq, bool en)
426 struct hns3_hw *hw = &txq->hns->hw;
429 if (hns3_dev_indep_txrx_supported(hw)) {
430 reg = hns3_read_dev(txq, HNS3_RING_TX_EN_REG);
432 reg |= BIT(HNS3_RING_EN_B);
434 reg &= ~BIT(HNS3_RING_EN_B);
435 hns3_write_dev(txq, HNS3_RING_TX_EN_REG, reg);
441 hns3_enable_rxq(struct hns3_rx_queue *rxq, bool en)
443 struct hns3_hw *hw = &rxq->hns->hw;
446 if (hns3_dev_indep_txrx_supported(hw)) {
447 reg = hns3_read_dev(rxq, HNS3_RING_RX_EN_REG);
449 reg |= BIT(HNS3_RING_EN_B);
451 reg &= ~BIT(HNS3_RING_EN_B);
452 hns3_write_dev(rxq, HNS3_RING_RX_EN_REG, reg);
458 hns3_start_all_txqs(struct rte_eth_dev *dev)
460 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
461 struct hns3_tx_queue *txq;
464 for (i = 0; i < dev->data->nb_tx_queues; i++) {
465 txq = hw->data->tx_queues[i];
467 hns3_err(hw, "Tx queue %u not available or setup.", i);
468 goto start_txqs_fail;
471 * Tx queue is enabled by default. Therefore, the Tx queues
472 * needs to be disabled when deferred_start is set. There is
473 * another master switch used to control the enabling of a pair
474 * of Tx and Rx queues. And the master switch is disabled by
477 if (txq->tx_deferred_start)
478 hns3_enable_txq(txq, false);
480 hns3_enable_txq(txq, true);
485 for (j = 0; j < i; j++) {
486 txq = hw->data->tx_queues[j];
487 hns3_enable_txq(txq, false);
493 hns3_start_all_rxqs(struct rte_eth_dev *dev)
495 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
496 struct hns3_rx_queue *rxq;
499 for (i = 0; i < dev->data->nb_rx_queues; i++) {
500 rxq = hw->data->rx_queues[i];
502 hns3_err(hw, "Rx queue %u not available or setup.", i);
503 goto start_rxqs_fail;
506 * Rx queue is enabled by default. Therefore, the Rx queues
507 * needs to be disabled when deferred_start is set. There is
508 * another master switch used to control the enabling of a pair
509 * of Tx and Rx queues. And the master switch is disabled by
512 if (rxq->rx_deferred_start)
513 hns3_enable_rxq(rxq, false);
515 hns3_enable_rxq(rxq, true);
520 for (j = 0; j < i; j++) {
521 rxq = hw->data->rx_queues[j];
522 hns3_enable_rxq(rxq, false);
528 hns3_restore_tqp_enable_state(struct hns3_hw *hw)
530 struct hns3_rx_queue *rxq;
531 struct hns3_tx_queue *txq;
534 for (i = 0; i < hw->data->nb_rx_queues; i++) {
535 rxq = hw->data->rx_queues[i];
537 hns3_enable_rxq(rxq, rxq->enabled);
540 for (i = 0; i < hw->data->nb_tx_queues; i++) {
541 txq = hw->data->tx_queues[i];
543 hns3_enable_txq(txq, txq->enabled);
548 hns3_stop_all_txqs(struct rte_eth_dev *dev)
550 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
551 struct hns3_tx_queue *txq;
554 for (i = 0; i < dev->data->nb_tx_queues; i++) {
555 txq = hw->data->tx_queues[i];
558 hns3_enable_txq(txq, false);
563 hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable)
565 struct hns3_cfg_com_tqp_queue_cmd *req;
566 struct hns3_cmd_desc desc;
569 req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data;
571 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false);
572 req->tqp_id = rte_cpu_to_le_16(queue_id);
574 hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0);
576 ret = hns3_cmd_send(hw, &desc, 1);
578 hns3_err(hw, "TQP enable fail, ret = %d", ret);
584 hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable)
586 struct hns3_reset_tqp_queue_cmd *req;
587 struct hns3_cmd_desc desc;
590 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false);
592 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
593 req->tqp_id = rte_cpu_to_le_16(queue_id);
594 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
595 ret = hns3_cmd_send(hw, &desc, 1);
597 hns3_err(hw, "send tqp reset cmd error, queue_id = %u, "
598 "ret = %d", queue_id, ret);
604 hns3_get_tqp_reset_status(struct hns3_hw *hw, uint16_t queue_id,
605 uint8_t *reset_status)
607 struct hns3_reset_tqp_queue_cmd *req;
608 struct hns3_cmd_desc desc;
611 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true);
613 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
614 req->tqp_id = rte_cpu_to_le_16(queue_id);
616 ret = hns3_cmd_send(hw, &desc, 1);
618 hns3_err(hw, "get tqp reset status error, queue_id = %u, "
619 "ret = %d.", queue_id, ret);
622 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
627 hns3pf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
629 #define HNS3_TQP_RESET_TRY_MS 200
630 uint16_t wait_time = 0;
631 uint8_t reset_status;
635 * In current version VF is not supported when PF is driven by DPDK
636 * driver, all task queue pairs are mapped to PF function, so PF's queue
637 * id is equals to the global queue id in PF range.
639 ret = hns3_send_reset_tqp_cmd(hw, queue_id, true);
641 hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret);
646 /* Wait for tqp hw reset */
647 rte_delay_ms(HNS3_POLL_RESPONE_MS);
648 wait_time += HNS3_POLL_RESPONE_MS;
649 ret = hns3_get_tqp_reset_status(hw, queue_id, &reset_status);
655 } while (wait_time < HNS3_TQP_RESET_TRY_MS);
659 hns3_err(hw, "reset tqp timeout, queue_id = %u, ret = %d",
664 ret = hns3_send_reset_tqp_cmd(hw, queue_id, false);
666 hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret);
671 hns3_send_reset_tqp_cmd(hw, queue_id, false);
676 hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
681 memcpy(msg_data, &queue_id, sizeof(uint16_t));
683 ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
684 sizeof(msg_data), true, NULL, 0);
686 hns3_err(hw, "fail to reset tqp, queue_id = %u, ret = %d.",
692 hns3_reset_rcb_cmd(struct hns3_hw *hw, uint8_t *reset_status)
694 struct hns3_reset_cmd *req;
695 struct hns3_cmd_desc desc;
698 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
699 req = (struct hns3_reset_cmd *)desc.data;
700 hns3_set_bit(req->fun_reset_rcb, HNS3_CFG_RESET_RCB_B, 1);
703 * The start qid should be the global qid of the first tqp of the
704 * function which should be reset in this port. Since our PF not
705 * support take over of VFs, so we only need to reset function 0,
706 * and its start qid is always 0.
708 req->fun_reset_rcb_vqid_start = rte_cpu_to_le_16(0);
709 req->fun_reset_rcb_vqid_num = rte_cpu_to_le_16(hw->cfg_max_queues);
711 ret = hns3_cmd_send(hw, &desc, 1);
713 hns3_err(hw, "fail to send rcb reset cmd, ret = %d.", ret);
717 *reset_status = req->fun_reset_rcb_return_status;
722 hns3pf_reset_all_tqps(struct hns3_hw *hw)
724 #define HNS3_RESET_RCB_NOT_SUPPORT 0U
725 #define HNS3_RESET_ALL_TQP_SUCCESS 1U
726 uint8_t reset_status;
730 ret = hns3_reset_rcb_cmd(hw, &reset_status);
735 * If the firmware version is low, it may not support the rcb reset
736 * which means reset all the tqps at a time. In this case, we should
737 * reset tqps one by one.
739 if (reset_status == HNS3_RESET_RCB_NOT_SUPPORT) {
740 for (i = 0; i < hw->cfg_max_queues; i++) {
741 ret = hns3pf_reset_tqp(hw, i);
744 "fail to reset tqp, queue_id = %d, ret = %d.",
749 } else if (reset_status != HNS3_RESET_ALL_TQP_SUCCESS) {
750 hns3_err(hw, "fail to reset all tqps, reset_status = %u.",
759 hns3vf_reset_all_tqps(struct hns3_hw *hw)
761 #define HNS3VF_RESET_ALL_TQP_DONE 1U
762 uint8_t reset_status;
767 memset(msg_data, 0, sizeof(uint16_t));
768 ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
769 sizeof(msg_data), true, &reset_status,
770 sizeof(reset_status));
772 hns3_err(hw, "fail to send rcb reset mbx, ret = %d.", ret);
776 if (reset_status == HNS3VF_RESET_ALL_TQP_DONE)
780 * If the firmware version or kernel PF version is low, it may not
781 * support the rcb reset which means reset all the tqps at a time.
782 * In this case, we should reset tqps one by one.
784 for (i = 1; i < hw->cfg_max_queues; i++) {
785 ret = hns3vf_reset_tqp(hw, i);
794 hns3_reset_all_tqps(struct hns3_adapter *hns)
796 struct hns3_hw *hw = &hns->hw;
799 /* Disable all queues before reset all queues */
800 for (i = 0; i < hw->cfg_max_queues; i++) {
801 ret = hns3_tqp_enable(hw, i, false);
804 "fail to disable tqps before tqps reset, ret = %d.",
811 return hns3vf_reset_all_tqps(hw);
813 return hns3pf_reset_all_tqps(hw);
817 hns3_send_reset_queue_cmd(struct hns3_hw *hw, uint16_t queue_id,
818 enum hns3_ring_type queue_type, bool enable)
820 struct hns3_reset_tqp_queue_cmd *req;
821 struct hns3_cmd_desc desc;
825 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, false);
827 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
828 req->tqp_id = rte_cpu_to_le_16(queue_id);
829 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
830 req->queue_direction = rte_cpu_to_le_16(queue_direction);
831 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
833 ret = hns3_cmd_send(hw, &desc, 1);
835 hns3_err(hw, "send queue reset cmd error, queue_id = %u, "
836 "queue_type = %s, ret = %d.", queue_id,
837 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
842 hns3_get_queue_reset_status(struct hns3_hw *hw, uint16_t queue_id,
843 enum hns3_ring_type queue_type,
844 uint8_t *reset_status)
846 struct hns3_reset_tqp_queue_cmd *req;
847 struct hns3_cmd_desc desc;
851 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, true);
853 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
854 req->tqp_id = rte_cpu_to_le_16(queue_id);
855 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
856 req->queue_direction = rte_cpu_to_le_16(queue_direction);
858 ret = hns3_cmd_send(hw, &desc, 1);
860 hns3_err(hw, "get queue reset status error, queue_id = %u "
861 "queue_type = %s, ret = %d.", queue_id,
862 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
866 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
871 hns3_reset_queue(struct hns3_hw *hw, uint16_t queue_id,
872 enum hns3_ring_type queue_type)
874 #define HNS3_QUEUE_RESET_TRY_MS 200
875 struct hns3_tx_queue *txq;
876 struct hns3_rx_queue *rxq;
877 uint32_t reset_wait_times;
878 uint32_t max_wait_times;
879 uint8_t reset_status;
882 if (queue_type == HNS3_RING_TYPE_TX) {
883 txq = hw->data->tx_queues[queue_id];
884 hns3_enable_txq(txq, false);
886 rxq = hw->data->rx_queues[queue_id];
887 hns3_enable_rxq(rxq, false);
890 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, true);
892 hns3_err(hw, "send reset queue cmd fail, ret = %d.", ret);
896 reset_wait_times = 0;
897 max_wait_times = HNS3_QUEUE_RESET_TRY_MS / HNS3_POLL_RESPONE_MS;
898 while (reset_wait_times < max_wait_times) {
899 /* Wait for queue hw reset */
900 rte_delay_ms(HNS3_POLL_RESPONE_MS);
901 ret = hns3_get_queue_reset_status(hw, queue_id,
902 queue_type, &reset_status);
904 goto queue_reset_fail;
912 hns3_err(hw, "reset queue timeout, queue_id = %u, "
913 "queue_type = %s", queue_id,
914 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx");
916 goto queue_reset_fail;
919 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
921 hns3_err(hw, "deassert queue reset fail, ret = %d.", ret);
926 hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
931 hns3_get_tqp_intr_reg_offset(uint16_t tqp_intr_id)
935 /* Need an extend offset to config queues > 64 */
936 if (tqp_intr_id < HNS3_MIN_EXT_TQP_INTR_ID)
937 reg_offset = HNS3_TQP_INTR_REG_BASE +
938 tqp_intr_id * HNS3_TQP_INTR_LOW_ORDER_OFFSET;
940 reg_offset = HNS3_TQP_INTR_EXT_REG_BASE +
941 tqp_intr_id / HNS3_MIN_EXT_TQP_INTR_ID *
942 HNS3_TQP_INTR_HIGH_ORDER_OFFSET +
943 tqp_intr_id % HNS3_MIN_EXT_TQP_INTR_ID *
944 HNS3_TQP_INTR_LOW_ORDER_OFFSET;
950 hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
951 uint8_t gl_idx, uint16_t gl_value)
953 uint32_t offset[] = {HNS3_TQP_INTR_GL0_REG,
954 HNS3_TQP_INTR_GL1_REG,
955 HNS3_TQP_INTR_GL2_REG};
956 uint32_t addr, value;
958 if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX)
961 addr = offset[gl_idx] + hns3_get_tqp_intr_reg_offset(queue_id);
962 if (hw->intr.gl_unit == HNS3_INTR_COALESCE_GL_UINT_1US)
963 value = gl_value | HNS3_TQP_INTR_GL_UNIT_1US;
965 value = HNS3_GL_USEC_TO_REG(gl_value);
967 hns3_write_dev(hw, addr, value);
971 hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value)
973 uint32_t addr, value;
975 if (rl_value > HNS3_TQP_INTR_RL_MAX)
978 addr = HNS3_TQP_INTR_RL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
979 value = HNS3_RL_USEC_TO_REG(rl_value);
981 value |= HNS3_TQP_INTR_RL_ENABLE_MASK;
983 hns3_write_dev(hw, addr, value);
987 hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value)
992 * int_ql_max == 0 means the hardware does not support QL,
993 * QL regs config is not permitted if QL is not supported,
996 if (hw->intr.int_ql_max == HNS3_INTR_QL_NONE)
999 addr = HNS3_TQP_INTR_TX_QL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
1000 hns3_write_dev(hw, addr, ql_value);
1002 addr = HNS3_TQP_INTR_RX_QL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
1003 hns3_write_dev(hw, addr, ql_value);
1007 hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en)
1009 uint32_t addr, value;
1011 addr = HNS3_TQP_INTR_CTRL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
1014 hns3_write_dev(hw, addr, value);
1018 * Enable all rx queue interrupt when in interrupt rx mode.
1019 * This api was called before enable queue rx&tx (in normal start or reset
1020 * recover scenes), used to fix hardware rx queue interrupt enable was clear
1024 hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en)
1026 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1027 uint16_t nb_rx_q = hw->data->nb_rx_queues;
1030 if (dev->data->dev_conf.intr_conf.rxq == 0)
1033 for (i = 0; i < nb_rx_q; i++)
1034 hns3_queue_intr_enable(hw, i, en);
1038 hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1040 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1041 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1042 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044 if (dev->data->dev_conf.intr_conf.rxq == 0)
1047 hns3_queue_intr_enable(hw, queue_id, true);
1049 return rte_intr_ack(intr_handle);
1053 hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1055 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1057 if (dev->data->dev_conf.intr_conf.rxq == 0)
1060 hns3_queue_intr_enable(hw, queue_id, false);
1066 hns3_init_rxq(struct hns3_adapter *hns, uint16_t idx)
1068 struct hns3_hw *hw = &hns->hw;
1069 struct hns3_rx_queue *rxq;
1072 PMD_INIT_FUNC_TRACE();
1074 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx];
1075 ret = hns3_alloc_rx_queue_mbufs(hw, rxq);
1077 hns3_err(hw, "fail to alloc mbuf for Rx queue %u, ret = %d.",
1082 rxq->next_to_use = 0;
1083 rxq->rx_rearm_start = 0;
1084 rxq->rx_free_hold = 0;
1085 rxq->rx_rearm_nb = 0;
1086 rxq->pkt_first_seg = NULL;
1087 rxq->pkt_last_seg = NULL;
1088 hns3_init_rx_queue_hw(rxq);
1089 hns3_rxq_vec_setup(rxq);
1095 hns3_init_fake_rxq(struct hns3_adapter *hns, uint16_t idx)
1097 struct hns3_hw *hw = &hns->hw;
1098 struct hns3_rx_queue *rxq;
1100 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx];
1101 rxq->next_to_use = 0;
1102 rxq->rx_free_hold = 0;
1103 rxq->rx_rearm_start = 0;
1104 rxq->rx_rearm_nb = 0;
1105 hns3_init_rx_queue_hw(rxq);
1109 hns3_init_txq(struct hns3_tx_queue *txq)
1111 struct hns3_desc *desc;
1115 desc = txq->tx_ring;
1116 for (i = 0; i < txq->nb_tx_desc; i++) {
1117 desc->tx.tp_fe_sc_vld_ra_ri = 0;
1121 txq->next_to_use = 0;
1122 txq->next_to_clean = 0;
1123 txq->tx_bd_ready = txq->nb_tx_desc - 1;
1124 hns3_init_tx_queue_hw(txq);
1128 hns3_init_tx_ring_tc(struct hns3_adapter *hns)
1130 struct hns3_hw *hw = &hns->hw;
1131 struct hns3_tx_queue *txq;
1134 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1135 struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i];
1138 if (!tc_queue->enable)
1141 for (j = 0; j < tc_queue->tqp_count; j++) {
1142 num = tc_queue->tqp_offset + j;
1143 txq = (struct hns3_tx_queue *)hw->data->tx_queues[num];
1147 hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc);
1153 hns3_init_rx_queues(struct hns3_adapter *hns)
1155 struct hns3_hw *hw = &hns->hw;
1156 struct hns3_rx_queue *rxq;
1160 /* Initialize RSS for queues */
1161 ret = hns3_config_rss(hns);
1163 hns3_err(hw, "failed to configure rss, ret = %d.", ret);
1167 for (i = 0; i < hw->data->nb_rx_queues; i++) {
1168 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i];
1170 hns3_err(hw, "Rx queue %u not available or setup.", i);
1174 if (rxq->rx_deferred_start)
1177 ret = hns3_init_rxq(hns, i);
1179 hns3_err(hw, "failed to init Rx queue %u, ret = %d.", i,
1185 for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++)
1186 hns3_init_fake_rxq(hns, i);
1191 for (j = 0; j < i; j++) {
1192 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j];
1193 hns3_rx_queue_release_mbufs(rxq);
1200 hns3_init_tx_queues(struct hns3_adapter *hns)
1202 struct hns3_hw *hw = &hns->hw;
1203 struct hns3_tx_queue *txq;
1206 for (i = 0; i < hw->data->nb_tx_queues; i++) {
1207 txq = (struct hns3_tx_queue *)hw->data->tx_queues[i];
1209 hns3_err(hw, "Tx queue %u not available or setup.", i);
1213 if (txq->tx_deferred_start)
1218 for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) {
1219 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i];
1222 hns3_init_tx_ring_tc(hns);
1229 * Note: just init and setup queues, and don't enable tqps.
1232 hns3_init_queues(struct hns3_adapter *hns, bool reset_queue)
1234 struct hns3_hw *hw = &hns->hw;
1238 ret = hns3_reset_all_tqps(hns);
1240 hns3_err(hw, "failed to reset all queues, ret = %d.",
1246 ret = hns3_init_rx_queues(hns);
1248 hns3_err(hw, "failed to init rx queues, ret = %d.", ret);
1252 ret = hns3_init_tx_queues(hns);
1254 hns3_dev_release_mbufs(hns);
1255 hns3_err(hw, "failed to init tx queues, ret = %d.", ret);
1262 hns3_start_tqps(struct hns3_hw *hw)
1264 struct hns3_tx_queue *txq;
1265 struct hns3_rx_queue *rxq;
1268 hns3_enable_all_queues(hw, true);
1270 for (i = 0; i < hw->data->nb_tx_queues; i++) {
1271 txq = hw->data->tx_queues[i];
1273 hw->data->tx_queue_state[i] =
1274 RTE_ETH_QUEUE_STATE_STARTED;
1277 for (i = 0; i < hw->data->nb_rx_queues; i++) {
1278 rxq = hw->data->rx_queues[i];
1280 hw->data->rx_queue_state[i] =
1281 RTE_ETH_QUEUE_STATE_STARTED;
1286 hns3_stop_tqps(struct hns3_hw *hw)
1290 hns3_enable_all_queues(hw, false);
1292 for (i = 0; i < hw->data->nb_tx_queues; i++)
1293 hw->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1295 for (i = 0; i < hw->data->nb_rx_queues; i++)
1296 hw->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1300 * Iterate over all Rx Queue, and call the callback() function for each Rx
1304 * The target eth dev.
1305 * @param[in] callback
1306 * The function to call for each queue.
1307 * if callback function return nonzero will stop iterate and return it's value
1309 * The arguments to provide the callback function with.
1312 * 0 on success, otherwise with errno set.
1315 hns3_rxq_iterate(struct rte_eth_dev *dev,
1316 int (*callback)(struct hns3_rx_queue *, void *), void *arg)
1321 if (dev->data->rx_queues == NULL)
1324 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1325 ret = callback(dev->data->rx_queues[i], arg);
1334 hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev,
1335 struct hns3_queue_info *q_info)
1337 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1338 const struct rte_memzone *rx_mz;
1339 struct hns3_rx_queue *rxq;
1340 unsigned int rx_desc;
1342 rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue),
1343 RTE_CACHE_LINE_SIZE, q_info->socket_id);
1345 hns3_err(hw, "Failed to allocate memory for No.%u rx ring!",
1350 /* Allocate rx ring hardware descriptors. */
1351 rxq->queue_id = q_info->idx;
1352 rxq->nb_rx_desc = q_info->nb_desc;
1355 * Allocate a litter more memory because rx vector functions
1356 * don't check boundaries each time.
1358 rx_desc = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
1359 sizeof(struct hns3_desc);
1360 rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
1361 rx_desc, HNS3_RING_BASE_ALIGN,
1363 if (rx_mz == NULL) {
1364 hns3_err(hw, "Failed to reserve DMA memory for No.%u rx ring!",
1366 hns3_rx_queue_release(rxq);
1370 rxq->rx_ring = (struct hns3_desc *)rx_mz->addr;
1371 rxq->rx_ring_phys_addr = rx_mz->iova;
1373 hns3_dbg(hw, "No.%u rx descriptors iova 0x%" PRIx64, q_info->idx,
1374 rxq->rx_ring_phys_addr);
1380 hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
1381 uint16_t nb_desc, unsigned int socket_id)
1383 struct hns3_adapter *hns = dev->data->dev_private;
1384 struct hns3_hw *hw = &hns->hw;
1385 struct hns3_queue_info q_info;
1386 struct hns3_rx_queue *rxq;
1389 if (hw->fkq_data.rx_queues[idx]) {
1390 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
1391 hw->fkq_data.rx_queues[idx] = NULL;
1395 q_info.socket_id = socket_id;
1396 q_info.nb_desc = nb_desc;
1397 q_info.type = "hns3 fake RX queue";
1398 q_info.ring_name = "rx_fake_ring";
1399 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1401 hns3_err(hw, "Failed to setup No.%u fake rx ring.", idx);
1405 /* Don't need alloc sw_ring, because upper applications don't use it */
1406 rxq->sw_ring = NULL;
1409 rxq->rx_deferred_start = false;
1410 rxq->port_id = dev->data->port_id;
1411 rxq->configured = true;
1412 nb_rx_q = dev->data->nb_rx_queues;
1413 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1414 (nb_rx_q + idx) * HNS3_TQP_REG_SIZE);
1415 rxq->rx_buf_len = HNS3_MIN_BD_BUF_SIZE;
1417 rte_spinlock_lock(&hw->lock);
1418 hw->fkq_data.rx_queues[idx] = rxq;
1419 rte_spinlock_unlock(&hw->lock);
1425 hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev,
1426 struct hns3_queue_info *q_info)
1428 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1429 const struct rte_memzone *tx_mz;
1430 struct hns3_tx_queue *txq;
1431 struct hns3_desc *desc;
1432 unsigned int tx_desc;
1435 txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue),
1436 RTE_CACHE_LINE_SIZE, q_info->socket_id);
1438 hns3_err(hw, "Failed to allocate memory for No.%u tx ring!",
1443 /* Allocate tx ring hardware descriptors. */
1444 txq->queue_id = q_info->idx;
1445 txq->nb_tx_desc = q_info->nb_desc;
1446 tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc);
1447 tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
1448 tx_desc, HNS3_RING_BASE_ALIGN,
1450 if (tx_mz == NULL) {
1451 hns3_err(hw, "Failed to reserve DMA memory for No.%u tx ring!",
1453 hns3_tx_queue_release(txq);
1457 txq->tx_ring = (struct hns3_desc *)tx_mz->addr;
1458 txq->tx_ring_phys_addr = tx_mz->iova;
1460 hns3_dbg(hw, "No.%u tx descriptors iova 0x%" PRIx64, q_info->idx,
1461 txq->tx_ring_phys_addr);
1464 desc = txq->tx_ring;
1465 for (i = 0; i < txq->nb_tx_desc; i++) {
1466 desc->tx.tp_fe_sc_vld_ra_ri = 0;
1474 hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
1475 uint16_t nb_desc, unsigned int socket_id)
1477 struct hns3_adapter *hns = dev->data->dev_private;
1478 struct hns3_hw *hw = &hns->hw;
1479 struct hns3_queue_info q_info;
1480 struct hns3_tx_queue *txq;
1483 if (hw->fkq_data.tx_queues[idx] != NULL) {
1484 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
1485 hw->fkq_data.tx_queues[idx] = NULL;
1489 q_info.socket_id = socket_id;
1490 q_info.nb_desc = nb_desc;
1491 q_info.type = "hns3 fake TX queue";
1492 q_info.ring_name = "tx_fake_ring";
1493 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
1495 hns3_err(hw, "Failed to setup No.%u fake tx ring.", idx);
1499 /* Don't need alloc sw_ring, because upper applications don't use it */
1500 txq->sw_ring = NULL;
1504 txq->tx_deferred_start = false;
1505 txq->port_id = dev->data->port_id;
1506 txq->configured = true;
1507 nb_tx_q = dev->data->nb_tx_queues;
1508 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1509 (nb_tx_q + idx) * HNS3_TQP_REG_SIZE);
1511 rte_spinlock_lock(&hw->lock);
1512 hw->fkq_data.tx_queues[idx] = txq;
1513 rte_spinlock_unlock(&hw->lock);
1519 hns3_fake_rx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1521 uint16_t old_nb_queues = hw->fkq_data.nb_fake_rx_queues;
1525 if (hw->fkq_data.rx_queues == NULL && nb_queues != 0) {
1526 /* first time configuration */
1528 size = sizeof(hw->fkq_data.rx_queues[0]) * nb_queues;
1529 hw->fkq_data.rx_queues = rte_zmalloc("fake_rx_queues", size,
1530 RTE_CACHE_LINE_SIZE);
1531 if (hw->fkq_data.rx_queues == NULL) {
1532 hw->fkq_data.nb_fake_rx_queues = 0;
1535 } else if (hw->fkq_data.rx_queues != NULL && nb_queues != 0) {
1537 rxq = hw->fkq_data.rx_queues;
1538 for (i = nb_queues; i < old_nb_queues; i++)
1539 hns3_dev_rx_queue_release(rxq[i]);
1541 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
1542 RTE_CACHE_LINE_SIZE);
1545 if (nb_queues > old_nb_queues) {
1546 uint16_t new_qs = nb_queues - old_nb_queues;
1547 memset(rxq + old_nb_queues, 0, sizeof(rxq[0]) * new_qs);
1550 hw->fkq_data.rx_queues = rxq;
1551 } else if (hw->fkq_data.rx_queues != NULL && nb_queues == 0) {
1552 rxq = hw->fkq_data.rx_queues;
1553 for (i = nb_queues; i < old_nb_queues; i++)
1554 hns3_dev_rx_queue_release(rxq[i]);
1556 rte_free(hw->fkq_data.rx_queues);
1557 hw->fkq_data.rx_queues = NULL;
1560 hw->fkq_data.nb_fake_rx_queues = nb_queues;
1566 hns3_fake_tx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1568 uint16_t old_nb_queues = hw->fkq_data.nb_fake_tx_queues;
1572 if (hw->fkq_data.tx_queues == NULL && nb_queues != 0) {
1573 /* first time configuration */
1575 size = sizeof(hw->fkq_data.tx_queues[0]) * nb_queues;
1576 hw->fkq_data.tx_queues = rte_zmalloc("fake_tx_queues", size,
1577 RTE_CACHE_LINE_SIZE);
1578 if (hw->fkq_data.tx_queues == NULL) {
1579 hw->fkq_data.nb_fake_tx_queues = 0;
1582 } else if (hw->fkq_data.tx_queues != NULL && nb_queues != 0) {
1584 txq = hw->fkq_data.tx_queues;
1585 for (i = nb_queues; i < old_nb_queues; i++)
1586 hns3_dev_tx_queue_release(txq[i]);
1587 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1588 RTE_CACHE_LINE_SIZE);
1591 if (nb_queues > old_nb_queues) {
1592 uint16_t new_qs = nb_queues - old_nb_queues;
1593 memset(txq + old_nb_queues, 0, sizeof(txq[0]) * new_qs);
1596 hw->fkq_data.tx_queues = txq;
1597 } else if (hw->fkq_data.tx_queues != NULL && nb_queues == 0) {
1598 txq = hw->fkq_data.tx_queues;
1599 for (i = nb_queues; i < old_nb_queues; i++)
1600 hns3_dev_tx_queue_release(txq[i]);
1602 rte_free(hw->fkq_data.tx_queues);
1603 hw->fkq_data.tx_queues = NULL;
1605 hw->fkq_data.nb_fake_tx_queues = nb_queues;
1611 hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
1614 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1615 uint16_t rx_need_add_nb_q;
1616 uint16_t tx_need_add_nb_q;
1621 if (hns3_dev_indep_txrx_supported(hw))
1624 /* Setup new number of fake RX/TX queues and reconfigure device. */
1625 rx_need_add_nb_q = hw->cfg_max_queues - nb_rx_q;
1626 tx_need_add_nb_q = hw->cfg_max_queues - nb_tx_q;
1627 ret = hns3_fake_rx_queue_config(hw, rx_need_add_nb_q);
1629 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1633 ret = hns3_fake_tx_queue_config(hw, tx_need_add_nb_q);
1635 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1636 goto cfg_fake_tx_q_fail;
1639 /* Allocate and set up fake RX queue per Ethernet port. */
1640 port_id = hw->data->port_id;
1641 for (q = 0; q < rx_need_add_nb_q; q++) {
1642 ret = hns3_fake_rx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1643 rte_eth_dev_socket_id(port_id));
1645 goto setup_fake_rx_q_fail;
1648 /* Allocate and set up fake TX queue per Ethernet port. */
1649 for (q = 0; q < tx_need_add_nb_q; q++) {
1650 ret = hns3_fake_tx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1651 rte_eth_dev_socket_id(port_id));
1653 goto setup_fake_tx_q_fail;
1658 setup_fake_tx_q_fail:
1659 setup_fake_rx_q_fail:
1660 (void)hns3_fake_tx_queue_config(hw, 0);
1662 (void)hns3_fake_rx_queue_config(hw, 0);
1668 hns3_dev_release_mbufs(struct hns3_adapter *hns)
1670 struct rte_eth_dev_data *dev_data = hns->hw.data;
1671 struct hns3_rx_queue *rxq;
1672 struct hns3_tx_queue *txq;
1675 if (dev_data->rx_queues)
1676 for (i = 0; i < dev_data->nb_rx_queues; i++) {
1677 rxq = dev_data->rx_queues[i];
1680 hns3_rx_queue_release_mbufs(rxq);
1683 if (dev_data->tx_queues)
1684 for (i = 0; i < dev_data->nb_tx_queues; i++) {
1685 txq = dev_data->tx_queues[i];
1688 hns3_tx_queue_release_mbufs(txq);
1693 hns3_rx_buf_len_calc(struct rte_mempool *mp, uint16_t *rx_buf_len)
1695 uint16_t vld_buf_size;
1696 uint16_t num_hw_specs;
1700 * hns3 network engine only support to set 4 typical specification, and
1701 * different buffer size will affect the max packet_len and the max
1702 * number of segmentation when hw gro is turned on in receive side. The
1703 * relationship between them is as follows:
1704 * rx_buf_size | max_gro_pkt_len | max_gro_nb_seg
1705 * ---------------------|-------------------|----------------
1706 * HNS3_4K_BD_BUF_SIZE | 60KB | 15
1707 * HNS3_2K_BD_BUF_SIZE | 62KB | 31
1708 * HNS3_1K_BD_BUF_SIZE | 63KB | 63
1709 * HNS3_512_BD_BUF_SIZE | 31.5KB | 63
1711 static const uint16_t hw_rx_buf_size[] = {
1712 HNS3_4K_BD_BUF_SIZE,
1713 HNS3_2K_BD_BUF_SIZE,
1714 HNS3_1K_BD_BUF_SIZE,
1715 HNS3_512_BD_BUF_SIZE
1718 vld_buf_size = (uint16_t)(rte_pktmbuf_data_room_size(mp) -
1719 RTE_PKTMBUF_HEADROOM);
1720 if (vld_buf_size < HNS3_MIN_BD_BUF_SIZE)
1723 num_hw_specs = RTE_DIM(hw_rx_buf_size);
1724 for (i = 0; i < num_hw_specs; i++) {
1725 if (vld_buf_size >= hw_rx_buf_size[i]) {
1726 *rx_buf_len = hw_rx_buf_size[i];
1734 hns3_rxq_conf_runtime_check(struct hns3_hw *hw, uint16_t buf_size,
1737 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1738 struct rte_eth_rxmode *rxmode = &hw->data->dev_conf.rxmode;
1739 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
1740 uint16_t min_vec_bds;
1743 * HNS3 hardware network engine set scattered as default. If the driver
1744 * is not work in scattered mode and the pkts greater than buf_size
1745 * but smaller than max_rx_pkt_len will be distributed to multiple BDs.
1746 * Driver cannot handle this situation.
1748 if (!hw->data->scattered_rx && rxmode->max_rx_pkt_len > buf_size) {
1749 hns3_err(hw, "max_rx_pkt_len is not allowed to be set greater "
1750 "than rx_buf_len if scattered is off.");
1754 if (pkt_burst == hns3_recv_pkts_vec) {
1755 min_vec_bds = HNS3_DEFAULT_RXQ_REARM_THRESH +
1756 HNS3_DEFAULT_RX_BURST;
1757 if (nb_desc < min_vec_bds ||
1758 nb_desc % HNS3_DEFAULT_RXQ_REARM_THRESH) {
1759 hns3_err(hw, "if Rx burst mode is vector, "
1760 "number of descriptor is required to be "
1761 "bigger than min vector bds:%u, and could be "
1762 "divided by rxq rearm thresh:%u.",
1763 min_vec_bds, HNS3_DEFAULT_RXQ_REARM_THRESH);
1771 hns3_rx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_rxconf *conf,
1772 struct rte_mempool *mp, uint16_t nb_desc,
1777 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1778 nb_desc % HNS3_ALIGN_RING_DESC) {
1779 hns3_err(hw, "Number (%u) of rx descriptors is invalid",
1784 if (conf->rx_drop_en == 0)
1785 hns3_warn(hw, "if no descriptors available, packets are always "
1786 "dropped and rx_drop_en (1) is fixed on");
1788 if (hns3_rx_buf_len_calc(mp, buf_size)) {
1789 hns3_err(hw, "rxq mbufs' data room size (%u) is not enough! "
1790 "minimal data room size (%u).",
1791 rte_pktmbuf_data_room_size(mp),
1792 HNS3_MIN_BD_BUF_SIZE + RTE_PKTMBUF_HEADROOM);
1796 if (hw->data->dev_started) {
1797 ret = hns3_rxq_conf_runtime_check(hw, *buf_size, nb_desc);
1799 hns3_err(hw, "Rx queue runtime setup fail.");
1808 hns3_get_tqp_reg_offset(uint16_t queue_id)
1810 uint32_t reg_offset;
1812 /* Need an extend offset to config queue > 1024 */
1813 if (queue_id < HNS3_MIN_EXTEND_QUEUE_ID)
1814 reg_offset = HNS3_TQP_REG_OFFSET + queue_id * HNS3_TQP_REG_SIZE;
1816 reg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_EXT_REG_OFFSET +
1817 (queue_id - HNS3_MIN_EXTEND_QUEUE_ID) *
1824 hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1825 unsigned int socket_id, const struct rte_eth_rxconf *conf,
1826 struct rte_mempool *mp)
1828 struct hns3_adapter *hns = dev->data->dev_private;
1829 struct hns3_hw *hw = &hns->hw;
1830 struct hns3_queue_info q_info;
1831 struct hns3_rx_queue *rxq;
1832 uint16_t rx_buf_size;
1836 ret = hns3_rx_queue_conf_check(hw, conf, mp, nb_desc, &rx_buf_size);
1840 if (dev->data->rx_queues[idx]) {
1841 hns3_rx_queue_release(dev->data->rx_queues[idx]);
1842 dev->data->rx_queues[idx] = NULL;
1846 q_info.socket_id = socket_id;
1847 q_info.nb_desc = nb_desc;
1848 q_info.type = "hns3 RX queue";
1849 q_info.ring_name = "rx_ring";
1851 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1854 "Failed to alloc mem and reserve DMA mem for rx ring!");
1859 rxq->ptype_tbl = &hns->ptype_tbl;
1861 rxq->rx_free_thresh = (conf->rx_free_thresh > 0) ?
1862 conf->rx_free_thresh : HNS3_DEFAULT_RX_FREE_THRESH;
1864 rxq->rx_deferred_start = conf->rx_deferred_start;
1865 if (rxq->rx_deferred_start && !hns3_dev_indep_txrx_supported(hw)) {
1866 hns3_warn(hw, "deferred start is not supported.");
1867 rxq->rx_deferred_start = false;
1870 rx_entry_len = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
1871 sizeof(struct hns3_entry);
1872 rxq->sw_ring = rte_zmalloc_socket("hns3 RX sw ring", rx_entry_len,
1873 RTE_CACHE_LINE_SIZE, socket_id);
1874 if (rxq->sw_ring == NULL) {
1875 hns3_err(hw, "Failed to allocate memory for rx sw ring!");
1876 hns3_rx_queue_release(rxq);
1880 rxq->next_to_use = 0;
1881 rxq->rx_free_hold = 0;
1882 rxq->rx_rearm_start = 0;
1883 rxq->rx_rearm_nb = 0;
1884 rxq->pkt_first_seg = NULL;
1885 rxq->pkt_last_seg = NULL;
1886 rxq->port_id = dev->data->port_id;
1888 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
1889 * the pvid_sw_discard_en in the queue struct should not be changed,
1890 * because PVID-related operations do not need to be processed by PMD
1891 * driver. For hns3 VF device, whether it needs to process PVID depends
1892 * on the configuration of PF kernel mode netdevice driver. And the
1893 * related PF configuration is delivered through the mailbox and finally
1894 * reflectd in port_base_vlan_cfg.
1896 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1897 rxq->pvid_sw_discard_en = hw->port_base_vlan_cfg.state ==
1898 HNS3_PORT_BASE_VLAN_ENABLE;
1900 rxq->pvid_sw_discard_en = false;
1901 rxq->ptype_en = hns3_dev_rxd_adv_layout_supported(hw) ? true : false;
1902 rxq->configured = true;
1903 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1904 idx * HNS3_TQP_REG_SIZE);
1905 rxq->io_base = (void *)((char *)hw->io_base +
1906 hns3_get_tqp_reg_offset(idx));
1907 rxq->io_head_reg = (volatile void *)((char *)rxq->io_base +
1908 HNS3_RING_RX_HEAD_REG);
1909 rxq->rx_buf_len = rx_buf_size;
1910 memset(&rxq->basic_stats, 0, sizeof(struct hns3_rx_basic_stats));
1911 memset(&rxq->err_stats, 0, sizeof(struct hns3_rx_bd_errors_stats));
1912 memset(&rxq->dfx_stats, 0, sizeof(struct hns3_rx_dfx_stats));
1914 /* CRC len set here is used for amending packet length */
1915 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1916 rxq->crc_len = RTE_ETHER_CRC_LEN;
1920 rxq->bulk_mbuf_num = 0;
1922 rte_spinlock_lock(&hw->lock);
1923 dev->data->rx_queues[idx] = rxq;
1924 rte_spinlock_unlock(&hw->lock);
1930 hns3_rx_scattered_reset(struct rte_eth_dev *dev)
1932 struct hns3_adapter *hns = dev->data->dev_private;
1933 struct hns3_hw *hw = &hns->hw;
1936 dev->data->scattered_rx = false;
1940 hns3_rx_scattered_calc(struct rte_eth_dev *dev)
1942 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1943 struct hns3_adapter *hns = dev->data->dev_private;
1944 struct hns3_hw *hw = &hns->hw;
1945 struct hns3_rx_queue *rxq;
1948 if (dev->data->rx_queues == NULL)
1951 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
1952 rxq = dev->data->rx_queues[queue_id];
1953 if (hw->rx_buf_len == 0)
1954 hw->rx_buf_len = rxq->rx_buf_len;
1956 hw->rx_buf_len = RTE_MIN(hw->rx_buf_len,
1960 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_SCATTER ||
1961 dev_conf->rxmode.max_rx_pkt_len > hw->rx_buf_len)
1962 dev->data->scattered_rx = true;
1966 hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1968 static const uint32_t ptypes[] = {
1970 RTE_PTYPE_L2_ETHER_LLDP,
1971 RTE_PTYPE_L2_ETHER_ARP,
1973 RTE_PTYPE_L3_IPV4_EXT,
1975 RTE_PTYPE_L3_IPV6_EXT,
1981 RTE_PTYPE_TUNNEL_GRE,
1982 RTE_PTYPE_INNER_L2_ETHER,
1983 RTE_PTYPE_INNER_L3_IPV4,
1984 RTE_PTYPE_INNER_L3_IPV6,
1985 RTE_PTYPE_INNER_L3_IPV4_EXT,
1986 RTE_PTYPE_INNER_L3_IPV6_EXT,
1987 RTE_PTYPE_INNER_L4_UDP,
1988 RTE_PTYPE_INNER_L4_TCP,
1989 RTE_PTYPE_INNER_L4_SCTP,
1990 RTE_PTYPE_INNER_L4_ICMP,
1991 RTE_PTYPE_TUNNEL_VXLAN,
1992 RTE_PTYPE_TUNNEL_NVGRE,
1995 static const uint32_t adv_layout_ptypes[] = {
1997 RTE_PTYPE_L2_ETHER_TIMESYNC,
1998 RTE_PTYPE_L2_ETHER_LLDP,
1999 RTE_PTYPE_L2_ETHER_ARP,
2000 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2001 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2003 RTE_PTYPE_L4_NONFRAG,
2009 RTE_PTYPE_TUNNEL_GRE,
2010 RTE_PTYPE_TUNNEL_GRENAT,
2011 RTE_PTYPE_INNER_L2_ETHER,
2012 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2013 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2014 RTE_PTYPE_INNER_L4_FRAG,
2015 RTE_PTYPE_INNER_L4_ICMP,
2016 RTE_PTYPE_INNER_L4_NONFRAG,
2017 RTE_PTYPE_INNER_L4_UDP,
2018 RTE_PTYPE_INNER_L4_TCP,
2019 RTE_PTYPE_INNER_L4_SCTP,
2020 RTE_PTYPE_INNER_L4_ICMP,
2023 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025 if (dev->rx_pkt_burst == hns3_recv_pkts_simple ||
2026 dev->rx_pkt_burst == hns3_recv_scattered_pkts ||
2027 dev->rx_pkt_burst == hns3_recv_pkts_vec ||
2028 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve) {
2029 if (hns3_dev_rxd_adv_layout_supported(hw))
2030 return adv_layout_ptypes;
2039 hns3_init_non_tunnel_ptype_tbl(struct hns3_ptype_table *tbl)
2041 tbl->l3table[0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
2042 tbl->l3table[1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
2043 tbl->l3table[2] = RTE_PTYPE_L2_ETHER_ARP;
2044 tbl->l3table[4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT;
2045 tbl->l3table[5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT;
2046 tbl->l3table[6] = RTE_PTYPE_L2_ETHER_LLDP;
2048 tbl->l4table[0] = RTE_PTYPE_L4_UDP;
2049 tbl->l4table[1] = RTE_PTYPE_L4_TCP;
2050 tbl->l4table[2] = RTE_PTYPE_TUNNEL_GRE;
2051 tbl->l4table[3] = RTE_PTYPE_L4_SCTP;
2052 tbl->l4table[4] = RTE_PTYPE_L4_IGMP;
2053 tbl->l4table[5] = RTE_PTYPE_L4_ICMP;
2057 hns3_init_tunnel_ptype_tbl(struct hns3_ptype_table *tbl)
2059 tbl->inner_l3table[0] = RTE_PTYPE_INNER_L2_ETHER |
2060 RTE_PTYPE_INNER_L3_IPV4;
2061 tbl->inner_l3table[1] = RTE_PTYPE_INNER_L2_ETHER |
2062 RTE_PTYPE_INNER_L3_IPV6;
2063 /* There is not a ptype for inner ARP/RARP */
2064 tbl->inner_l3table[2] = RTE_PTYPE_UNKNOWN;
2065 tbl->inner_l3table[3] = RTE_PTYPE_UNKNOWN;
2066 tbl->inner_l3table[4] = RTE_PTYPE_INNER_L2_ETHER |
2067 RTE_PTYPE_INNER_L3_IPV4_EXT;
2068 tbl->inner_l3table[5] = RTE_PTYPE_INNER_L2_ETHER |
2069 RTE_PTYPE_INNER_L3_IPV6_EXT;
2071 tbl->inner_l4table[0] = RTE_PTYPE_INNER_L4_UDP;
2072 tbl->inner_l4table[1] = RTE_PTYPE_INNER_L4_TCP;
2073 /* There is not a ptype for inner GRE */
2074 tbl->inner_l4table[2] = RTE_PTYPE_UNKNOWN;
2075 tbl->inner_l4table[3] = RTE_PTYPE_INNER_L4_SCTP;
2076 /* There is not a ptype for inner IGMP */
2077 tbl->inner_l4table[4] = RTE_PTYPE_UNKNOWN;
2078 tbl->inner_l4table[5] = RTE_PTYPE_INNER_L4_ICMP;
2080 tbl->ol3table[0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
2081 tbl->ol3table[1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
2082 tbl->ol3table[2] = RTE_PTYPE_UNKNOWN;
2083 tbl->ol3table[3] = RTE_PTYPE_UNKNOWN;
2084 tbl->ol3table[4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT;
2085 tbl->ol3table[5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT;
2087 tbl->ol4table[0] = RTE_PTYPE_UNKNOWN;
2088 tbl->ol4table[1] = RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN;
2089 tbl->ol4table[2] = RTE_PTYPE_TUNNEL_NVGRE;
2093 hns3_init_adv_layout_ptype(struct hns3_ptype_table *tbl)
2095 uint32_t *ptype = tbl->ptype;
2098 ptype[1] = RTE_PTYPE_L2_ETHER_ARP;
2099 ptype[3] = RTE_PTYPE_L2_ETHER_LLDP;
2100 ptype[8] = RTE_PTYPE_L2_ETHER_TIMESYNC;
2102 /* Non-tunnel IPv4 */
2103 ptype[17] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2105 ptype[18] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2106 RTE_PTYPE_L4_NONFRAG;
2107 ptype[19] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2109 ptype[20] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2111 ptype[21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2112 RTE_PTYPE_TUNNEL_GRE;
2113 ptype[22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2115 ptype[23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2117 ptype[24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2119 /* The next ptype is PTP over IPv4 + UDP */
2120 ptype[25] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2123 /* IPv4 --> GRE/Teredo/VXLAN */
2124 ptype[29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2125 RTE_PTYPE_TUNNEL_GRENAT;
2126 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2127 ptype[30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2128 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER;
2130 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2131 ptype[31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2132 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2133 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2134 RTE_PTYPE_INNER_L4_FRAG;
2135 ptype[32] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2136 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2137 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2138 RTE_PTYPE_INNER_L4_NONFRAG;
2139 ptype[33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2140 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2141 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2142 RTE_PTYPE_INNER_L4_UDP;
2143 ptype[34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2144 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2145 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2146 RTE_PTYPE_INNER_L4_TCP;
2147 ptype[35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2148 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2149 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2150 RTE_PTYPE_INNER_L4_SCTP;
2151 /* The next ptype's inner L4 is IGMP */
2152 ptype[36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2153 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2154 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
2155 ptype[37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2156 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2157 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2158 RTE_PTYPE_INNER_L4_ICMP;
2160 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2161 ptype[39] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2162 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2163 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2164 RTE_PTYPE_INNER_L4_FRAG;
2165 ptype[40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2166 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2167 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2168 RTE_PTYPE_INNER_L4_NONFRAG;
2169 ptype[41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2170 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2171 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2172 RTE_PTYPE_INNER_L4_UDP;
2173 ptype[42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2174 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2175 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2176 RTE_PTYPE_INNER_L4_TCP;
2177 ptype[43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2178 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2179 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2180 RTE_PTYPE_INNER_L4_SCTP;
2181 /* The next ptype's inner L4 is IGMP */
2182 ptype[44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2183 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2184 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
2185 ptype[45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2186 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2187 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2188 RTE_PTYPE_INNER_L4_ICMP;
2190 /* Non-tunnel IPv6 */
2191 ptype[111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2193 ptype[112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2194 RTE_PTYPE_L4_NONFRAG;
2195 ptype[113] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2197 ptype[114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2199 ptype[115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2200 RTE_PTYPE_TUNNEL_GRE;
2201 ptype[116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2203 ptype[117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2205 ptype[118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2207 /* Special for PTP over IPv6 + UDP */
2208 ptype[119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2211 /* IPv6 --> GRE/Teredo/VXLAN */
2212 ptype[123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2213 RTE_PTYPE_TUNNEL_GRENAT;
2214 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2215 ptype[124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2216 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER;
2218 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2219 ptype[125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2220 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2221 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2222 RTE_PTYPE_INNER_L4_FRAG;
2223 ptype[126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2224 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2225 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2226 RTE_PTYPE_INNER_L4_NONFRAG;
2227 ptype[127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2228 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2229 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2230 RTE_PTYPE_INNER_L4_UDP;
2231 ptype[128] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2232 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2233 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2234 RTE_PTYPE_INNER_L4_TCP;
2235 ptype[129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2236 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2237 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2238 RTE_PTYPE_INNER_L4_SCTP;
2239 /* The next ptype's inner L4 is IGMP */
2240 ptype[130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2241 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2242 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
2243 ptype[131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2244 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2245 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2246 RTE_PTYPE_INNER_L4_ICMP;
2248 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2249 ptype[133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2250 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2251 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2252 RTE_PTYPE_INNER_L4_FRAG;
2253 ptype[134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2254 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2255 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2256 RTE_PTYPE_INNER_L4_NONFRAG;
2257 ptype[135] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2258 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2259 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2260 RTE_PTYPE_INNER_L4_UDP;
2261 ptype[136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2262 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2263 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2264 RTE_PTYPE_INNER_L4_TCP;
2265 ptype[137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2266 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2267 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2268 RTE_PTYPE_INNER_L4_SCTP;
2269 /* The next ptype's inner L4 is IGMP */
2270 ptype[138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2271 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2272 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
2273 ptype[139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2274 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2275 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2276 RTE_PTYPE_INNER_L4_ICMP;
2280 hns3_init_rx_ptype_tble(struct rte_eth_dev *dev)
2282 struct hns3_adapter *hns = dev->data->dev_private;
2283 struct hns3_ptype_table *tbl = &hns->ptype_tbl;
2285 memset(tbl, 0, sizeof(*tbl));
2287 hns3_init_non_tunnel_ptype_tbl(tbl);
2288 hns3_init_tunnel_ptype_tbl(tbl);
2289 hns3_init_adv_layout_ptype(tbl);
2293 hns3_rxd_to_vlan_tci(struct hns3_rx_queue *rxq, struct rte_mbuf *mb,
2294 uint32_t l234_info, const struct hns3_desc *rxd)
2296 #define HNS3_STRP_STATUS_NUM 0x4
2298 #define HNS3_NO_STRP_VLAN_VLD 0x0
2299 #define HNS3_INNER_STRP_VLAN_VLD 0x1
2300 #define HNS3_OUTER_STRP_VLAN_VLD 0x2
2301 uint32_t strip_status;
2302 uint32_t report_mode;
2305 * Since HW limitation, the vlan tag will always be inserted into RX
2306 * descriptor when strip the tag from packet, driver needs to determine
2307 * reporting which tag to mbuf according to the PVID configuration
2308 * and vlan striped status.
2310 static const uint32_t report_type[][HNS3_STRP_STATUS_NUM] = {
2312 HNS3_NO_STRP_VLAN_VLD,
2313 HNS3_OUTER_STRP_VLAN_VLD,
2314 HNS3_INNER_STRP_VLAN_VLD,
2315 HNS3_OUTER_STRP_VLAN_VLD
2318 HNS3_NO_STRP_VLAN_VLD,
2319 HNS3_NO_STRP_VLAN_VLD,
2320 HNS3_NO_STRP_VLAN_VLD,
2321 HNS3_INNER_STRP_VLAN_VLD
2324 strip_status = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,
2325 HNS3_RXD_STRP_TAGP_S);
2326 report_mode = report_type[rxq->pvid_sw_discard_en][strip_status];
2327 switch (report_mode) {
2328 case HNS3_NO_STRP_VLAN_VLD:
2331 case HNS3_INNER_STRP_VLAN_VLD:
2332 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2333 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.vlan_tag);
2335 case HNS3_OUTER_STRP_VLAN_VLD:
2336 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2337 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.ot_vlan_tag);
2346 recalculate_data_len(struct rte_mbuf *first_seg, struct rte_mbuf *last_seg,
2347 struct rte_mbuf *rxm, struct hns3_rx_queue *rxq,
2350 uint8_t crc_len = rxq->crc_len;
2352 if (data_len <= crc_len) {
2353 rte_pktmbuf_free_seg(rxm);
2354 first_seg->nb_segs--;
2355 last_seg->data_len = (uint16_t)(last_seg->data_len -
2356 (crc_len - data_len));
2357 last_seg->next = NULL;
2359 rxm->data_len = (uint16_t)(data_len - crc_len);
2362 static inline struct rte_mbuf *
2363 hns3_rx_alloc_buffer(struct hns3_rx_queue *rxq)
2367 if (likely(rxq->bulk_mbuf_num > 0))
2368 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
2370 ret = rte_mempool_get_bulk(rxq->mb_pool, (void **)rxq->bulk_mbuf,
2371 HNS3_BULK_ALLOC_MBUF_NUM);
2372 if (likely(ret == 0)) {
2373 rxq->bulk_mbuf_num = HNS3_BULK_ALLOC_MBUF_NUM;
2374 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
2376 return rte_mbuf_raw_alloc(rxq->mb_pool);
2380 hns3_rx_ptp_timestamp_handle(struct hns3_rx_queue *rxq, struct rte_mbuf *mbuf,
2381 volatile struct hns3_desc *rxd)
2383 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(rxq->hns);
2384 uint64_t timestamp = rte_le_to_cpu_64(rxd->timestamp);
2386 mbuf->ol_flags |= PKT_RX_IEEE1588_PTP | PKT_RX_IEEE1588_TMST;
2387 if (hns3_timestamp_rx_dynflag > 0) {
2388 *RTE_MBUF_DYNFIELD(mbuf, hns3_timestamp_dynfield_offset,
2389 rte_mbuf_timestamp_t *) = timestamp;
2390 mbuf->ol_flags |= hns3_timestamp_rx_dynflag;
2393 pf->rx_timestamp = timestamp;
2397 hns3_recv_pkts_simple(void *rx_queue,
2398 struct rte_mbuf **rx_pkts,
2401 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
2402 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
2403 struct hns3_rx_queue *rxq; /* RX queue */
2404 struct hns3_entry *sw_ring;
2405 struct hns3_entry *rxe;
2406 struct hns3_desc rxd;
2407 struct rte_mbuf *nmb; /* pointer of the new mbuf */
2408 struct rte_mbuf *rxm;
2409 uint32_t bd_base_info;
2421 rx_ring = rxq->rx_ring;
2422 sw_ring = rxq->sw_ring;
2423 rx_id = rxq->next_to_use;
2425 while (nb_rx < nb_pkts) {
2426 rxdp = &rx_ring[rx_id];
2427 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
2428 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
2431 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2432 (1u << HNS3_RXD_VLD_B)];
2434 nmb = hns3_rx_alloc_buffer(rxq);
2435 if (unlikely(nmb == NULL)) {
2438 port_id = rxq->port_id;
2439 rte_eth_devices[port_id].data->rx_mbuf_alloc_failed++;
2444 rxe = &sw_ring[rx_id];
2446 if (unlikely(rx_id == rxq->nb_rx_desc))
2449 rte_prefetch0(sw_ring[rx_id].mbuf);
2450 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
2451 rte_prefetch0(&rx_ring[rx_id]);
2452 rte_prefetch0(&sw_ring[rx_id]);
2459 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B)))
2460 hns3_rx_ptp_timestamp_handle(rxq, rxm, rxdp);
2462 dma_addr = rte_mbuf_data_iova_default(nmb);
2463 rxdp->addr = rte_cpu_to_le_64(dma_addr);
2464 rxdp->rx.bd_base_info = 0;
2466 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2467 rxm->pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.pkt_len)) -
2469 rxm->data_len = rxm->pkt_len;
2470 rxm->port = rxq->port_id;
2471 rxm->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
2472 rxm->ol_flags |= PKT_RX_RSS_HASH;
2473 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
2475 rte_le_to_cpu_16(rxd.rx.fd_id);
2476 rxm->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
2481 /* Load remained descriptor data and extract necessary fields */
2482 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
2483 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
2484 ret = hns3_handle_bdinfo(rxq, rxm, bd_base_info, l234_info);
2488 rxm->packet_type = hns3_rx_calc_ptype(rxq, l234_info, ol_info);
2490 if (rxm->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC)
2491 rxm->ol_flags |= PKT_RX_IEEE1588_PTP;
2493 hns3_rxd_to_vlan_tci(rxq, rxm, l234_info, &rxd);
2495 /* Increment bytes counter */
2496 rxq->basic_stats.bytes += rxm->pkt_len;
2498 rx_pkts[nb_rx++] = rxm;
2501 rte_pktmbuf_free(rxm);
2504 rxq->next_to_use = rx_id;
2505 rxq->rx_free_hold += nb_rx_bd;
2506 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
2507 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
2508 rxq->rx_free_hold = 0;
2515 hns3_recv_scattered_pkts(void *rx_queue,
2516 struct rte_mbuf **rx_pkts,
2519 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
2520 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
2521 struct hns3_rx_queue *rxq; /* RX queue */
2522 struct hns3_entry *sw_ring;
2523 struct hns3_entry *rxe;
2524 struct rte_mbuf *first_seg;
2525 struct rte_mbuf *last_seg;
2526 struct hns3_desc rxd;
2527 struct rte_mbuf *nmb; /* pointer of the new mbuf */
2528 struct rte_mbuf *rxm;
2529 struct rte_eth_dev *dev;
2530 uint32_t bd_base_info;
2544 rx_id = rxq->next_to_use;
2545 rx_ring = rxq->rx_ring;
2546 sw_ring = rxq->sw_ring;
2547 first_seg = rxq->pkt_first_seg;
2548 last_seg = rxq->pkt_last_seg;
2550 while (nb_rx < nb_pkts) {
2551 rxdp = &rx_ring[rx_id];
2552 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
2553 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
2557 * The interactive process between software and hardware of
2558 * receiving a new packet in hns3 network engine:
2559 * 1. Hardware network engine firstly writes the packet content
2560 * to the memory pointed by the 'addr' field of the Rx Buffer
2561 * Descriptor, secondly fills the result of parsing the
2562 * packet include the valid field into the Rx Buffer
2563 * Descriptor in one write operation.
2564 * 2. Driver reads the Rx BD's valid field in the loop to check
2565 * whether it's valid, if valid then assign a new address to
2566 * the addr field, clear the valid field, get the other
2567 * information of the packet by parsing Rx BD's other fields,
2568 * finally write back the number of Rx BDs processed by the
2569 * driver to the HNS3_RING_RX_HEAD_REG register to inform
2571 * In the above process, the ordering is very important. We must
2572 * make sure that CPU read Rx BD's other fields only after the
2575 * There are two type of re-ordering: compiler re-ordering and
2576 * CPU re-ordering under the ARMv8 architecture.
2577 * 1. we use volatile to deal with compiler re-ordering, so you
2578 * can see that rx_ring/rxdp defined with volatile.
2579 * 2. we commonly use memory barrier to deal with CPU
2580 * re-ordering, but the cost is high.
2582 * In order to solve the high cost of using memory barrier, we
2583 * use the data dependency order under the ARMv8 architecture,
2586 * instr02: load B <- A
2587 * the instr02 will always execute after instr01.
2589 * To construct the data dependency ordering, we use the
2590 * following assignment:
2591 * rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2592 * (1u<<HNS3_RXD_VLD_B)]
2593 * Using gcc compiler under the ARMv8 architecture, the related
2594 * assembly code example as follows:
2595 * note: (1u << HNS3_RXD_VLD_B) equal 0x10
2596 * instr01: ldr w26, [x22, #28] --read bd_base_info
2597 * instr02: and w0, w26, #0x10 --calc bd_base_info & 0x10
2598 * instr03: sub w0, w0, #0x10 --calc (bd_base_info &
2600 * instr04: add x0, x22, x0, lsl #5 --calc copy source addr
2601 * instr05: ldp x2, x3, [x0]
2602 * instr06: stp x2, x3, [x29, #256] --copy BD's [0 ~ 15]B
2603 * instr07: ldp x4, x5, [x0, #16]
2604 * instr08: stp x4, x5, [x29, #272] --copy BD's [16 ~ 31]B
2605 * the instr05~08 depend on x0's value, x0 depent on w26's
2606 * value, the w26 is the bd_base_info, this form the data
2607 * dependency ordering.
2608 * note: if BD is valid, (bd_base_info & (1u<<HNS3_RXD_VLD_B)) -
2609 * (1u<<HNS3_RXD_VLD_B) will always zero, so the
2610 * assignment is correct.
2612 * So we use the data dependency ordering instead of memory
2613 * barrier to improve receive performance.
2615 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2616 (1u << HNS3_RXD_VLD_B)];
2618 nmb = hns3_rx_alloc_buffer(rxq);
2619 if (unlikely(nmb == NULL)) {
2620 dev = &rte_eth_devices[rxq->port_id];
2621 dev->data->rx_mbuf_alloc_failed++;
2626 rxe = &sw_ring[rx_id];
2628 if (unlikely(rx_id == rxq->nb_rx_desc))
2631 rte_prefetch0(sw_ring[rx_id].mbuf);
2632 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
2633 rte_prefetch0(&rx_ring[rx_id]);
2634 rte_prefetch0(&sw_ring[rx_id]);
2640 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2641 rxdp->rx.bd_base_info = 0;
2642 rxdp->addr = dma_addr;
2644 if (first_seg == NULL) {
2646 first_seg->nb_segs = 1;
2648 first_seg->nb_segs++;
2649 last_seg->next = rxm;
2652 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2653 rxm->data_len = rte_le_to_cpu_16(rxd.rx.size);
2655 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
2661 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B)))
2662 hns3_rx_ptp_timestamp_handle(rxq, first_seg, rxdp);
2665 * The last buffer of the received packet. packet len from
2666 * buffer description may contains CRC len, packet len should
2667 * subtract it, same as data len.
2669 first_seg->pkt_len = rte_le_to_cpu_16(rxd.rx.pkt_len);
2672 * This is the last buffer of the received packet. If the CRC
2673 * is not stripped by the hardware:
2674 * - Subtract the CRC length from the total packet length.
2675 * - If the last buffer only contains the whole CRC or a part
2676 * of it, free the mbuf associated to the last buffer. If part
2677 * of the CRC is also contained in the previous mbuf, subtract
2678 * the length of that CRC part from the data length of the
2682 if (unlikely(rxq->crc_len > 0)) {
2683 first_seg->pkt_len -= rxq->crc_len;
2684 recalculate_data_len(first_seg, last_seg, rxm, rxq,
2688 first_seg->port = rxq->port_id;
2689 first_seg->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
2690 first_seg->ol_flags = PKT_RX_RSS_HASH;
2691 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
2692 first_seg->hash.fdir.hi =
2693 rte_le_to_cpu_16(rxd.rx.fd_id);
2694 first_seg->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
2697 gro_size = hns3_get_field(bd_base_info, HNS3_RXD_GRO_SIZE_M,
2698 HNS3_RXD_GRO_SIZE_S);
2699 if (gro_size != 0) {
2700 first_seg->ol_flags |= PKT_RX_LRO;
2701 first_seg->tso_segsz = gro_size;
2704 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
2705 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
2706 ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info,
2711 first_seg->packet_type = hns3_rx_calc_ptype(rxq,
2712 l234_info, ol_info);
2714 if (first_seg->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC)
2715 rxm->ol_flags |= PKT_RX_IEEE1588_PTP;
2717 hns3_rxd_to_vlan_tci(rxq, first_seg, l234_info, &rxd);
2719 /* Increment bytes counter */
2720 rxq->basic_stats.bytes += first_seg->pkt_len;
2722 rx_pkts[nb_rx++] = first_seg;
2726 rte_pktmbuf_free(first_seg);
2730 rxq->next_to_use = rx_id;
2731 rxq->pkt_first_seg = first_seg;
2732 rxq->pkt_last_seg = last_seg;
2734 rxq->rx_free_hold += nb_rx_bd;
2735 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
2736 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
2737 rxq->rx_free_hold = 0;
2744 hns3_rxq_vec_setup(__rte_unused struct hns3_rx_queue *rxq)
2749 hns3_rx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
2755 hns3_recv_pkts_vec(__rte_unused void *tx_queue,
2756 __rte_unused struct rte_mbuf **rx_pkts,
2757 __rte_unused uint16_t nb_pkts)
2763 hns3_recv_pkts_vec_sve(__rte_unused void *tx_queue,
2764 __rte_unused struct rte_mbuf **rx_pkts,
2765 __rte_unused uint16_t nb_pkts)
2771 hns3_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2772 struct rte_eth_burst_mode *mode)
2774 static const struct {
2775 eth_rx_burst_t pkt_burst;
2778 { hns3_recv_pkts_simple, "Scalar Simple" },
2779 { hns3_recv_scattered_pkts, "Scalar Scattered" },
2780 { hns3_recv_pkts_vec, "Vector Neon" },
2781 { hns3_recv_pkts_vec_sve, "Vector Sve" },
2784 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2788 for (i = 0; i < RTE_DIM(burst_infos); i++) {
2789 if (pkt_burst == burst_infos[i].pkt_burst) {
2790 snprintf(mode->info, sizeof(mode->info), "%s",
2791 burst_infos[i].info);
2801 hns3_get_default_vec_support(void)
2803 #if defined(RTE_ARCH_ARM64)
2804 if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128)
2806 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON))
2813 hns3_get_sve_support(void)
2815 #if defined(RTE_HAS_SVE_ACLE)
2816 if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256)
2818 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE))
2824 static eth_rx_burst_t
2825 hns3_get_rx_function(struct rte_eth_dev *dev)
2827 struct hns3_adapter *hns = dev->data->dev_private;
2828 uint64_t offloads = dev->data->dev_conf.rxmode.offloads;
2829 bool vec_allowed, sve_allowed, simple_allowed;
2832 vec_support = hns3_rx_check_vec_support(dev) == 0;
2833 vec_allowed = vec_support && hns3_get_default_vec_support();
2834 sve_allowed = vec_support && hns3_get_sve_support();
2835 simple_allowed = !dev->data->scattered_rx &&
2836 (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0;
2838 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed)
2839 return hns3_recv_pkts_vec;
2840 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed)
2841 return hns3_recv_pkts_vec_sve;
2842 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed)
2843 return hns3_recv_pkts_simple;
2844 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_COMMON)
2845 return hns3_recv_scattered_pkts;
2848 return hns3_recv_pkts_vec;
2850 return hns3_recv_pkts_simple;
2852 return hns3_recv_scattered_pkts;
2856 hns3_tx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_txconf *conf,
2857 uint16_t nb_desc, uint16_t *tx_rs_thresh,
2858 uint16_t *tx_free_thresh, uint16_t idx)
2860 #define HNS3_TX_RS_FREE_THRESH_GAP 8
2861 uint16_t rs_thresh, free_thresh, fast_free_thresh;
2863 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
2864 nb_desc % HNS3_ALIGN_RING_DESC) {
2865 hns3_err(hw, "number (%u) of tx descriptors is invalid",
2870 rs_thresh = (conf->tx_rs_thresh > 0) ?
2871 conf->tx_rs_thresh : HNS3_DEFAULT_TX_RS_THRESH;
2872 free_thresh = (conf->tx_free_thresh > 0) ?
2873 conf->tx_free_thresh : HNS3_DEFAULT_TX_FREE_THRESH;
2874 if (rs_thresh + free_thresh > nb_desc || nb_desc % rs_thresh ||
2875 rs_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP ||
2876 free_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP) {
2877 hns3_err(hw, "tx_rs_thresh (%u) tx_free_thresh (%u) nb_desc "
2878 "(%u) of tx descriptors for port=%u queue=%u check "
2880 rs_thresh, free_thresh, nb_desc, hw->data->port_id,
2885 if (conf->tx_free_thresh == 0) {
2886 /* Fast free Tx memory buffer to improve cache hit rate */
2887 fast_free_thresh = nb_desc - rs_thresh;
2888 if (fast_free_thresh >=
2889 HNS3_TX_FAST_FREE_AHEAD + HNS3_DEFAULT_TX_FREE_THRESH)
2890 free_thresh = fast_free_thresh -
2891 HNS3_TX_FAST_FREE_AHEAD;
2894 *tx_rs_thresh = rs_thresh;
2895 *tx_free_thresh = free_thresh;
2900 hns3_tx_push_get_queue_tail_reg(struct rte_eth_dev *dev, uint16_t queue_id)
2902 #define HNS3_TX_PUSH_TQP_REGION_SIZE 0x10000
2903 #define HNS3_TX_PUSH_QUICK_DOORBELL_OFFSET 64
2904 #define HNS3_TX_PUSH_PCI_BAR_INDEX 4
2906 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2907 uint8_t bar_id = HNS3_TX_PUSH_PCI_BAR_INDEX;
2910 * If device support Tx push then its PCIe bar45 must exist, and DPDK
2911 * framework will mmap the bar45 default in PCI probe stage.
2913 * In the bar45, the first half is for RoCE (RDMA over Converged
2914 * Ethernet), and the second half is for NIC, every TQP occupy 64KB.
2916 * The quick doorbell located at 64B offset in the TQP region.
2918 return (char *)pci_dev->mem_resource[bar_id].addr +
2919 (pci_dev->mem_resource[bar_id].len >> 1) +
2920 HNS3_TX_PUSH_TQP_REGION_SIZE * queue_id +
2921 HNS3_TX_PUSH_QUICK_DOORBELL_OFFSET;
2925 hns3_tx_push_init(struct rte_eth_dev *dev)
2927 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2928 volatile uint32_t *reg;
2931 if (!hns3_dev_tx_push_supported(hw))
2934 reg = (volatile uint32_t *)hns3_tx_push_get_queue_tail_reg(dev, 0);
2936 * Because the size of bar45 is about 8GB size, it may take a long time
2937 * to do the page fault in Tx process when work with vfio-pci, so use
2938 * one read operation to make kernel setup page table mapping for bar45
2939 * in the init stage.
2940 * Note: the bar45 is readable but the result is all 1.
2947 hns3_tx_push_queue_init(struct rte_eth_dev *dev,
2949 struct hns3_tx_queue *txq)
2951 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952 if (!hns3_dev_tx_push_supported(hw)) {
2953 txq->tx_push_enable = false;
2957 txq->io_tail_reg = (volatile void *)hns3_tx_push_get_queue_tail_reg(dev,
2959 txq->tx_push_enable = true;
2963 hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
2964 unsigned int socket_id, const struct rte_eth_txconf *conf)
2966 struct hns3_adapter *hns = dev->data->dev_private;
2967 uint16_t tx_rs_thresh, tx_free_thresh;
2968 struct hns3_hw *hw = &hns->hw;
2969 struct hns3_queue_info q_info;
2970 struct hns3_tx_queue *txq;
2974 ret = hns3_tx_queue_conf_check(hw, conf, nb_desc,
2975 &tx_rs_thresh, &tx_free_thresh, idx);
2979 if (dev->data->tx_queues[idx] != NULL) {
2980 hns3_tx_queue_release(dev->data->tx_queues[idx]);
2981 dev->data->tx_queues[idx] = NULL;
2985 q_info.socket_id = socket_id;
2986 q_info.nb_desc = nb_desc;
2987 q_info.type = "hns3 TX queue";
2988 q_info.ring_name = "tx_ring";
2989 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
2992 "Failed to alloc mem and reserve DMA mem for tx ring!");
2996 txq->tx_deferred_start = conf->tx_deferred_start;
2997 if (txq->tx_deferred_start && !hns3_dev_indep_txrx_supported(hw)) {
2998 hns3_warn(hw, "deferred start is not supported.");
2999 txq->tx_deferred_start = false;
3002 tx_entry_len = sizeof(struct hns3_entry) * txq->nb_tx_desc;
3003 txq->sw_ring = rte_zmalloc_socket("hns3 TX sw ring", tx_entry_len,
3004 RTE_CACHE_LINE_SIZE, socket_id);
3005 if (txq->sw_ring == NULL) {
3006 hns3_err(hw, "Failed to allocate memory for tx sw ring!");
3007 hns3_tx_queue_release(txq);
3012 txq->next_to_use = 0;
3013 txq->next_to_clean = 0;
3014 txq->tx_bd_ready = txq->nb_tx_desc - 1;
3015 txq->tx_free_thresh = tx_free_thresh;
3016 txq->tx_rs_thresh = tx_rs_thresh;
3017 txq->free = rte_zmalloc_socket("hns3 TX mbuf free array",
3018 sizeof(struct rte_mbuf *) * txq->tx_rs_thresh,
3019 RTE_CACHE_LINE_SIZE, socket_id);
3021 hns3_err(hw, "failed to allocate tx mbuf free array!");
3022 hns3_tx_queue_release(txq);
3026 txq->port_id = dev->data->port_id;
3028 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
3029 * the pvid_sw_shift_en in the queue struct should not be changed,
3030 * because PVID-related operations do not need to be processed by PMD
3031 * driver. For hns3 VF device, whether it needs to process PVID depends
3032 * on the configuration of PF kernel mode netdev driver. And the
3033 * related PF configuration is delivered through the mailbox and finally
3034 * reflectd in port_base_vlan_cfg.
3036 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
3037 txq->pvid_sw_shift_en = hw->port_base_vlan_cfg.state ==
3038 HNS3_PORT_BASE_VLAN_ENABLE;
3040 txq->pvid_sw_shift_en = false;
3041 txq->max_non_tso_bd_num = hw->max_non_tso_bd_num;
3042 txq->configured = true;
3043 txq->io_base = (void *)((char *)hw->io_base +
3044 hns3_get_tqp_reg_offset(idx));
3045 txq->io_tail_reg = (volatile void *)((char *)txq->io_base +
3046 HNS3_RING_TX_TAIL_REG);
3047 txq->min_tx_pkt_len = hw->min_tx_pkt_len;
3048 txq->tso_mode = hw->tso_mode;
3049 txq->udp_cksum_mode = hw->udp_cksum_mode;
3050 memset(&txq->basic_stats, 0, sizeof(struct hns3_tx_basic_stats));
3051 memset(&txq->dfx_stats, 0, sizeof(struct hns3_tx_dfx_stats));
3054 * Call hns3_tx_push_queue_init after assigned io_tail_reg field because
3055 * it may overwrite the io_tail_reg field.
3057 hns3_tx_push_queue_init(dev, idx, txq);
3059 rte_spinlock_lock(&hw->lock);
3060 dev->data->tx_queues[idx] = txq;
3061 rte_spinlock_unlock(&hw->lock);
3067 hns3_tx_free_useless_buffer(struct hns3_tx_queue *txq)
3069 uint16_t tx_next_clean = txq->next_to_clean;
3070 uint16_t tx_next_use = txq->next_to_use;
3071 uint16_t tx_bd_ready = txq->tx_bd_ready;
3072 uint16_t tx_bd_max = txq->nb_tx_desc;
3073 struct hns3_entry *tx_bak_pkt = &txq->sw_ring[tx_next_clean];
3074 struct hns3_desc *desc = &txq->tx_ring[tx_next_clean];
3075 struct rte_mbuf *mbuf;
3077 while ((!(desc->tx.tp_fe_sc_vld_ra_ri &
3078 rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)))) &&
3079 tx_next_use != tx_next_clean) {
3080 mbuf = tx_bak_pkt->mbuf;
3082 rte_pktmbuf_free_seg(mbuf);
3083 tx_bak_pkt->mbuf = NULL;
3091 if (tx_next_clean >= tx_bd_max) {
3093 desc = txq->tx_ring;
3094 tx_bak_pkt = txq->sw_ring;
3098 txq->next_to_clean = tx_next_clean;
3099 txq->tx_bd_ready = tx_bd_ready;
3103 hns3_config_gro(struct hns3_hw *hw, bool en)
3105 struct hns3_cfg_gro_status_cmd *req;
3106 struct hns3_cmd_desc desc;
3109 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
3110 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
3112 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
3114 ret = hns3_cmd_send(hw, &desc, 1);
3116 hns3_err(hw, "%s hardware GRO failed, ret = %d",
3117 en ? "enable" : "disable", ret);
3123 hns3_restore_gro_conf(struct hns3_hw *hw)
3129 offloads = hw->data->dev_conf.rxmode.offloads;
3130 gro_en = offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
3131 ret = hns3_config_gro(hw, gro_en);
3133 hns3_err(hw, "restore hardware GRO to %s failed, ret = %d",
3134 gro_en ? "enabled" : "disabled", ret);
3140 hns3_pkt_is_tso(struct rte_mbuf *m)
3142 return (m->tso_segsz != 0 && m->ol_flags & PKT_TX_TCP_SEG);
3146 hns3_set_tso(struct hns3_desc *desc, uint32_t paylen, struct rte_mbuf *rxm)
3148 if (!hns3_pkt_is_tso(rxm))
3151 if (paylen <= rxm->tso_segsz)
3154 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(BIT(HNS3_TXD_TSO_B));
3155 desc->tx.mss = rte_cpu_to_le_16(rxm->tso_segsz);
3159 hns3_fill_per_desc(struct hns3_desc *desc, struct rte_mbuf *rxm)
3161 desc->addr = rte_mbuf_data_iova(rxm);
3162 desc->tx.send_size = rte_cpu_to_le_16(rte_pktmbuf_data_len(rxm));
3163 desc->tx.tp_fe_sc_vld_ra_ri |= rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B));
3167 hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc,
3168 struct rte_mbuf *rxm)
3170 uint64_t ol_flags = rxm->ol_flags;
3174 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len;
3175 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
3176 rxm->outer_l2_len + rxm->outer_l3_len : 0;
3177 paylen = rxm->pkt_len - hdr_len;
3178 desc->tx.paylen_fd_dop_ol4cs |= rte_cpu_to_le_32(paylen);
3179 hns3_set_tso(desc, paylen, rxm);
3182 * Currently, hardware doesn't support more than two layers VLAN offload
3183 * in Tx direction based on hns3 network engine. So when the number of
3184 * VLANs in the packets represented by rxm plus the number of VLAN
3185 * offload by hardware such as PVID etc, exceeds two, the packets will
3186 * be discarded or the original VLAN of the packets will be overwitted
3187 * by hardware. When the PF PVID is enabled by calling the API function
3188 * named rte_eth_dev_set_vlan_pvid or the VF PVID is enabled by the hns3
3189 * PF kernel ether driver, the outer VLAN tag will always be the PVID.
3190 * To avoid the VLAN of Tx descriptor is overwritten by PVID, it should
3191 * be added to the position close to the IP header when PVID is enabled.
3193 if (!txq->pvid_sw_shift_en && ol_flags & (PKT_TX_VLAN_PKT |
3195 desc->tx.ol_type_vlan_len_msec |=
3196 rte_cpu_to_le_32(BIT(HNS3_TXD_OVLAN_B));
3197 if (ol_flags & PKT_TX_QINQ_PKT)
3198 desc->tx.outer_vlan_tag =
3199 rte_cpu_to_le_16(rxm->vlan_tci_outer);
3201 desc->tx.outer_vlan_tag =
3202 rte_cpu_to_le_16(rxm->vlan_tci);
3205 if (ol_flags & PKT_TX_QINQ_PKT ||
3206 ((ol_flags & PKT_TX_VLAN_PKT) && txq->pvid_sw_shift_en)) {
3207 desc->tx.type_cs_vlan_tso_len |=
3208 rte_cpu_to_le_32(BIT(HNS3_TXD_VLAN_B));
3209 desc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci);
3212 if (ol_flags & PKT_TX_IEEE1588_TMST)
3213 desc->tx.tp_fe_sc_vld_ra_ri |=
3214 rte_cpu_to_le_16(BIT(HNS3_TXD_TSYN_B));
3218 hns3_tx_alloc_mbufs(struct rte_mempool *mb_pool, uint16_t nb_new_buf,
3219 struct rte_mbuf **alloc_mbuf)
3221 #define MAX_NON_TSO_BD_PER_PKT 18
3222 struct rte_mbuf *pkt_segs[MAX_NON_TSO_BD_PER_PKT];
3225 /* Allocate enough mbufs */
3226 if (rte_mempool_get_bulk(mb_pool, (void **)pkt_segs, nb_new_buf))
3229 for (i = 0; i < nb_new_buf - 1; i++)
3230 pkt_segs[i]->next = pkt_segs[i + 1];
3232 pkt_segs[nb_new_buf - 1]->next = NULL;
3233 pkt_segs[0]->nb_segs = nb_new_buf;
3234 *alloc_mbuf = pkt_segs[0];
3240 hns3_pktmbuf_copy_hdr(struct rte_mbuf *new_pkt, struct rte_mbuf *old_pkt)
3242 new_pkt->ol_flags = old_pkt->ol_flags;
3243 new_pkt->pkt_len = rte_pktmbuf_pkt_len(old_pkt);
3244 new_pkt->outer_l2_len = old_pkt->outer_l2_len;
3245 new_pkt->outer_l3_len = old_pkt->outer_l3_len;
3246 new_pkt->l2_len = old_pkt->l2_len;
3247 new_pkt->l3_len = old_pkt->l3_len;
3248 new_pkt->l4_len = old_pkt->l4_len;
3249 new_pkt->vlan_tci_outer = old_pkt->vlan_tci_outer;
3250 new_pkt->vlan_tci = old_pkt->vlan_tci;
3254 hns3_reassemble_tx_pkts(struct rte_mbuf *tx_pkt, struct rte_mbuf **new_pkt,
3255 uint8_t max_non_tso_bd_num)
3257 struct rte_mempool *mb_pool;
3258 struct rte_mbuf *new_mbuf;
3259 struct rte_mbuf *temp_new;
3260 struct rte_mbuf *temp;
3261 uint16_t last_buf_len;
3262 uint16_t nb_new_buf;
3272 mb_pool = tx_pkt->pool;
3273 buf_size = tx_pkt->buf_len - RTE_PKTMBUF_HEADROOM;
3274 nb_new_buf = (rte_pktmbuf_pkt_len(tx_pkt) - 1) / buf_size + 1;
3275 if (nb_new_buf > max_non_tso_bd_num)
3278 last_buf_len = rte_pktmbuf_pkt_len(tx_pkt) % buf_size;
3279 if (last_buf_len == 0)
3280 last_buf_len = buf_size;
3282 /* Allocate enough mbufs */
3283 ret = hns3_tx_alloc_mbufs(mb_pool, nb_new_buf, &new_mbuf);
3287 /* Copy the original packet content to the new mbufs */
3289 s = rte_pktmbuf_mtod(temp, char *);
3290 len_s = rte_pktmbuf_data_len(temp);
3291 temp_new = new_mbuf;
3292 while (temp != NULL && temp_new != NULL) {
3293 d = rte_pktmbuf_mtod(temp_new, char *);
3294 buf_len = temp_new->next == NULL ? last_buf_len : buf_size;
3298 len = RTE_MIN(len_s, len_d);
3302 len_d = len_d - len;
3303 len_s = len_s - len;
3309 s = rte_pktmbuf_mtod(temp, char *);
3310 len_s = rte_pktmbuf_data_len(temp);
3314 temp_new->data_len = buf_len;
3315 temp_new = temp_new->next;
3317 hns3_pktmbuf_copy_hdr(new_mbuf, tx_pkt);
3319 /* free original mbufs */
3320 rte_pktmbuf_free(tx_pkt);
3322 *new_pkt = new_mbuf;
3328 hns3_parse_outer_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec)
3330 uint32_t tmp = *ol_type_vlan_len_msec;
3331 uint64_t ol_flags = m->ol_flags;
3333 /* (outer) IP header type */
3334 if (ol_flags & PKT_TX_OUTER_IPV4) {
3335 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
3336 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M,
3337 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_CSUM);
3339 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M,
3340 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_NO_CSUM);
3341 } else if (ol_flags & PKT_TX_OUTER_IPV6) {
3342 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
3345 /* OL3 header size, defined in 4 bytes */
3346 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
3347 m->outer_l3_len >> HNS3_L3_LEN_UNIT);
3348 *ol_type_vlan_len_msec = tmp;
3352 hns3_parse_inner_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec,
3353 uint32_t *type_cs_vlan_tso_len)
3355 #define HNS3_NVGRE_HLEN 8
3356 uint32_t tmp_outer = *ol_type_vlan_len_msec;
3357 uint32_t tmp_inner = *type_cs_vlan_tso_len;
3358 uint64_t ol_flags = m->ol_flags;
3359 uint16_t inner_l2_len;
3361 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
3362 case PKT_TX_TUNNEL_VXLAN_GPE:
3363 case PKT_TX_TUNNEL_GENEVE:
3364 case PKT_TX_TUNNEL_VXLAN:
3365 /* MAC in UDP tunnelling packet, include VxLAN and GENEVE */
3366 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M,
3367 HNS3_TXD_TUNTYPE_S, HNS3_TUN_MAC_IN_UDP);
3369 * The inner l2 length of mbuf is the sum of outer l4 length,
3370 * tunneling header length and inner l2 length for a tunnel
3371 * packect. But in hns3 tx descriptor, the tunneling header
3372 * length is contained in the field of outer L4 length.
3373 * Therefore, driver need to calculate the outer L4 length and
3376 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M,
3378 (uint8_t)RTE_ETHER_VXLAN_HLEN >>
3381 inner_l2_len = m->l2_len - RTE_ETHER_VXLAN_HLEN;
3383 case PKT_TX_TUNNEL_GRE:
3384 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M,
3385 HNS3_TXD_TUNTYPE_S, HNS3_TUN_NVGRE);
3387 * For NVGRE tunnel packect, the outer L4 is empty. So only
3388 * fill the NVGRE header length to the outer L4 field.
3390 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M,
3392 (uint8_t)HNS3_NVGRE_HLEN >> HNS3_L4_LEN_UNIT);
3394 inner_l2_len = m->l2_len - HNS3_NVGRE_HLEN;
3397 /* For non UDP / GRE tunneling, drop the tunnel packet */
3401 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
3402 inner_l2_len >> HNS3_L2_LEN_UNIT);
3403 /* OL2 header size, defined in 2 bytes */
3404 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
3405 m->outer_l2_len >> HNS3_L2_LEN_UNIT);
3407 *type_cs_vlan_tso_len = tmp_inner;
3408 *ol_type_vlan_len_msec = tmp_outer;
3414 hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m,
3415 uint16_t tx_desc_id)
3417 struct hns3_desc *tx_ring = txq->tx_ring;
3418 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3419 uint64_t ol_flags = m->ol_flags;
3420 uint32_t tmp_outer = 0;
3421 uint32_t tmp_inner = 0;
3426 * The tunnel header is contained in the inner L2 header field of the
3427 * mbuf, but for hns3 descriptor, it is contained in the outer L4. So,
3428 * there is a need that switching between them. To avoid multiple
3429 * calculations, the length of the L2 header include the outer and
3430 * inner, will be filled during the parsing of tunnel packects.
3432 if (!(ol_flags & PKT_TX_TUNNEL_MASK)) {
3434 * For non tunnel type the tunnel type id is 0, so no need to
3435 * assign a value to it. Only the inner(normal) L2 header length
3438 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M,
3439 HNS3_TXD_L2LEN_S, m->l2_len >> HNS3_L2_LEN_UNIT);
3442 * If outer csum is not offload, the outer length may be filled
3443 * with 0. And the length of the outer header is added to the
3444 * inner l2_len. It would lead a cksum error. So driver has to
3445 * calculate the header length.
3447 if (unlikely(!(ol_flags &
3448 (PKT_TX_OUTER_IP_CKSUM | PKT_TX_OUTER_UDP_CKSUM)) &&
3449 m->outer_l2_len == 0)) {
3450 struct rte_net_hdr_lens hdr_len;
3451 (void)rte_net_get_ptype(m, &hdr_len,
3452 RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK);
3453 m->outer_l3_len = hdr_len.l3_len;
3454 m->outer_l2_len = hdr_len.l2_len;
3455 m->l2_len = m->l2_len - hdr_len.l2_len - hdr_len.l3_len;
3457 hns3_parse_outer_params(m, &tmp_outer);
3458 ret = hns3_parse_inner_params(m, &tmp_outer, &tmp_inner);
3463 desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp_outer);
3464 desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp_inner);
3465 tmp_ol4cs = ol_flags & PKT_TX_OUTER_UDP_CKSUM ?
3466 BIT(HNS3_TXD_OL4CS_B) : 0;
3467 desc->tx.paylen_fd_dop_ol4cs = rte_cpu_to_le_32(tmp_ol4cs);
3473 hns3_parse_l3_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len)
3475 uint64_t ol_flags = m->ol_flags;
3479 tmp = *type_cs_vlan_tso_len;
3480 if (ol_flags & PKT_TX_IPV4)
3481 l3_type = HNS3_L3T_IPV4;
3482 else if (ol_flags & PKT_TX_IPV6)
3483 l3_type = HNS3_L3T_IPV6;
3485 l3_type = HNS3_L3T_NONE;
3487 /* inner(/normal) L3 header size, defined in 4 bytes */
3488 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
3489 m->l3_len >> HNS3_L3_LEN_UNIT);
3491 tmp |= hns3_gen_field_val(HNS3_TXD_L3T_M, HNS3_TXD_L3T_S, l3_type);
3493 /* Enable L3 checksum offloads */
3494 if (ol_flags & PKT_TX_IP_CKSUM)
3495 tmp |= BIT(HNS3_TXD_L3CS_B);
3496 *type_cs_vlan_tso_len = tmp;
3500 hns3_parse_l4_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len)
3502 uint64_t ol_flags = m->ol_flags;
3504 /* Enable L4 checksum offloads */
3505 switch (ol_flags & (PKT_TX_L4_MASK | PKT_TX_TCP_SEG)) {
3506 case PKT_TX_TCP_CKSUM | PKT_TX_TCP_SEG:
3507 case PKT_TX_TCP_CKSUM:
3508 case PKT_TX_TCP_SEG:
3509 tmp = *type_cs_vlan_tso_len;
3510 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3513 case PKT_TX_UDP_CKSUM:
3514 tmp = *type_cs_vlan_tso_len;
3515 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3518 case PKT_TX_SCTP_CKSUM:
3519 tmp = *type_cs_vlan_tso_len;
3520 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3526 tmp |= BIT(HNS3_TXD_L4CS_B);
3527 tmp |= hns3_gen_field_val(HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
3528 m->l4_len >> HNS3_L4_LEN_UNIT);
3529 *type_cs_vlan_tso_len = tmp;
3533 hns3_txd_enable_checksum(struct hns3_tx_queue *txq, struct rte_mbuf *m,
3534 uint16_t tx_desc_id)
3536 struct hns3_desc *tx_ring = txq->tx_ring;
3537 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3540 hns3_parse_l3_cksum_params(m, &value);
3541 hns3_parse_l4_cksum_params(m, &value);
3543 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(value);
3547 hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num,
3548 uint32_t max_non_tso_bd_num)
3550 struct rte_mbuf *m_first = tx_pkts;
3551 struct rte_mbuf *m_last = tx_pkts;
3552 uint32_t tot_len = 0;
3557 * Hardware requires that the sum of the data length of every 8
3558 * consecutive buffers is greater than MSS in hns3 network engine.
3559 * We simplify it by ensuring pkt_headlen + the first 8 consecutive
3560 * frags greater than gso header len + mss, and the remaining 7
3561 * consecutive frags greater than MSS except the last 7 frags.
3563 if (bd_num <= max_non_tso_bd_num)
3566 for (i = 0; m_last && i < max_non_tso_bd_num - 1;
3567 i++, m_last = m_last->next)
3568 tot_len += m_last->data_len;
3573 /* ensure the first 8 frags is greater than mss + header */
3574 hdr_len = tx_pkts->l2_len + tx_pkts->l3_len + tx_pkts->l4_len;
3575 hdr_len += (tx_pkts->ol_flags & PKT_TX_TUNNEL_MASK) ?
3576 tx_pkts->outer_l2_len + tx_pkts->outer_l3_len : 0;
3577 if (tot_len + m_last->data_len < tx_pkts->tso_segsz + hdr_len)
3581 * ensure the sum of the data length of every 7 consecutive buffer
3582 * is greater than mss except the last one.
3584 for (i = 0; m_last && i < bd_num - max_non_tso_bd_num; i++) {
3585 tot_len -= m_first->data_len;
3586 tot_len += m_last->data_len;
3588 if (tot_len < tx_pkts->tso_segsz)
3591 m_first = m_first->next;
3592 m_last = m_last->next;
3599 hns3_outer_ipv4_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags,
3602 struct rte_ipv4_hdr *ipv4_hdr;
3603 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
3605 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
3606 ipv4_hdr->hdr_checksum = 0;
3607 if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) {
3608 struct rte_udp_hdr *udp_hdr;
3610 * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo
3611 * header for TSO packets
3613 if (ol_flags & PKT_TX_TCP_SEG)
3615 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3616 m->outer_l2_len + m->outer_l3_len);
3617 udp_hdr->dgram_cksum = rte_ipv4_phdr_cksum(ipv4_hdr, ol_flags);
3621 *l4_proto = ipv4_hdr->next_proto_id;
3626 hns3_outer_ipv6_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags,
3629 struct rte_ipv6_hdr *ipv6_hdr;
3630 ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *,
3632 if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) {
3633 struct rte_udp_hdr *udp_hdr;
3635 * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo
3636 * header for TSO packets
3638 if (ol_flags & PKT_TX_TCP_SEG)
3640 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3641 m->outer_l2_len + m->outer_l3_len);
3642 udp_hdr->dgram_cksum = rte_ipv6_phdr_cksum(ipv6_hdr, ol_flags);
3646 *l4_proto = ipv6_hdr->proto;
3651 hns3_outer_header_cksum_prepare(struct rte_mbuf *m)
3653 uint64_t ol_flags = m->ol_flags;
3654 uint32_t paylen, hdr_len, l4_proto;
3655 struct rte_udp_hdr *udp_hdr;
3657 if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6)))
3660 if (ol_flags & PKT_TX_OUTER_IPV4) {
3661 if (hns3_outer_ipv4_cksum_prepared(m, ol_flags, &l4_proto))
3664 if (hns3_outer_ipv6_cksum_prepared(m, ol_flags, &l4_proto))
3668 /* driver should ensure the outer udp cksum is 0 for TUNNEL TSO */
3669 if (l4_proto == IPPROTO_UDP && (ol_flags & PKT_TX_TCP_SEG)) {
3670 hdr_len = m->l2_len + m->l3_len + m->l4_len;
3671 hdr_len += m->outer_l2_len + m->outer_l3_len;
3672 paylen = m->pkt_len - hdr_len;
3673 if (paylen <= m->tso_segsz)
3675 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3678 udp_hdr->dgram_cksum = 0;
3683 hns3_check_tso_pkt_valid(struct rte_mbuf *m)
3685 uint32_t tmp_data_len_sum = 0;
3686 uint16_t nb_buf = m->nb_segs;
3687 uint32_t paylen, hdr_len;
3688 struct rte_mbuf *m_seg;
3691 if (nb_buf > HNS3_MAX_TSO_BD_PER_PKT)
3694 hdr_len = m->l2_len + m->l3_len + m->l4_len;
3695 hdr_len += (m->ol_flags & PKT_TX_TUNNEL_MASK) ?
3696 m->outer_l2_len + m->outer_l3_len : 0;
3697 if (hdr_len > HNS3_MAX_TSO_HDR_SIZE)
3700 paylen = m->pkt_len - hdr_len;
3701 if (paylen > HNS3_MAX_BD_PAYLEN)
3705 * The TSO header (include outer and inner L2, L3 and L4 header)
3706 * should be provided by three descriptors in maximum in hns3 network
3710 for (i = 0; m_seg != NULL && i < HNS3_MAX_TSO_HDR_BD_NUM && i < nb_buf;
3711 i++, m_seg = m_seg->next) {
3712 tmp_data_len_sum += m_seg->data_len;
3715 if (hdr_len > tmp_data_len_sum)
3721 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3723 hns3_vld_vlan_chk(struct hns3_tx_queue *txq, struct rte_mbuf *m)
3725 struct rte_ether_hdr *eh;
3726 struct rte_vlan_hdr *vh;
3728 if (!txq->pvid_sw_shift_en)
3732 * Due to hardware limitations, we only support two-layer VLAN hardware
3733 * offload in Tx direction based on hns3 network engine, so when PVID is
3734 * enabled, QinQ insert is no longer supported.
3735 * And when PVID is enabled, in the following two cases:
3736 * i) packets with more than two VLAN tags.
3737 * ii) packets with one VLAN tag while the hardware VLAN insert is
3739 * The packets will be regarded as abnormal packets and discarded by
3740 * hardware in Tx direction. For debugging purposes, a validation check
3741 * for these types of packets is added to the '.tx_pkt_prepare' ops
3742 * implementation function named hns3_prep_pkts to inform users that
3743 * these packets will be discarded.
3745 if (m->ol_flags & PKT_TX_QINQ_PKT)
3748 eh = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
3749 if (eh->ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
3750 if (m->ol_flags & PKT_TX_VLAN_PKT)
3753 /* Ensure the incoming packet is not a QinQ packet */
3754 vh = (struct rte_vlan_hdr *)(eh + 1);
3755 if (vh->eth_proto == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN))
3764 hns3_udp_cksum_help(struct rte_mbuf *m)
3766 uint64_t ol_flags = m->ol_flags;
3770 if (ol_flags & PKT_TX_IPV4) {
3771 struct rte_ipv4_hdr *ipv4_hdr = rte_pktmbuf_mtod_offset(m,
3772 struct rte_ipv4_hdr *, m->l2_len);
3773 l4_len = rte_be_to_cpu_16(ipv4_hdr->total_length) - m->l3_len;
3775 struct rte_ipv6_hdr *ipv6_hdr = rte_pktmbuf_mtod_offset(m,
3776 struct rte_ipv6_hdr *, m->l2_len);
3777 l4_len = rte_be_to_cpu_16(ipv6_hdr->payload_len);
3780 rte_raw_cksum_mbuf(m, m->l2_len + m->l3_len, l4_len, &cksum);
3784 * RFC 768:If the computed checksum is zero for UDP, it is transmitted
3790 return (uint16_t)cksum;
3794 hns3_validate_tunnel_cksum(struct hns3_tx_queue *tx_queue, struct rte_mbuf *m)
3796 uint64_t ol_flags = m->ol_flags;
3797 struct rte_udp_hdr *udp_hdr;
3800 if (tx_queue->udp_cksum_mode == HNS3_SPECIAL_PORT_HW_CKSUM_MODE ||
3801 ol_flags & PKT_TX_TUNNEL_MASK ||
3802 (ol_flags & PKT_TX_L4_MASK) != PKT_TX_UDP_CKSUM)
3805 * A UDP packet with the same dst_port as VXLAN\VXLAN_GPE\GENEVE will
3806 * be recognized as a tunnel packet in HW. In this case, if UDP CKSUM
3807 * offload is set and the tunnel mask has not been set, the CKSUM will
3808 * be wrong since the header length is wrong and driver should complete
3809 * the CKSUM to avoid CKSUM error.
3811 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3812 m->l2_len + m->l3_len);
3813 dst_port = rte_be_to_cpu_16(udp_hdr->dst_port);
3815 case RTE_VXLAN_DEFAULT_PORT:
3816 case RTE_VXLAN_GPE_DEFAULT_PORT:
3817 case RTE_GENEVE_DEFAULT_PORT:
3818 udp_hdr->dgram_cksum = hns3_udp_cksum_help(m);
3819 m->ol_flags = ol_flags & ~PKT_TX_L4_MASK;
3827 hns3_prep_pkt_proc(struct hns3_tx_queue *tx_queue, struct rte_mbuf *m)
3831 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3832 ret = rte_validate_tx_offload(m);
3838 ret = hns3_vld_vlan_chk(tx_queue, m);
3844 if (hns3_pkt_is_tso(m)) {
3845 if (hns3_pkt_need_linearized(m, m->nb_segs,
3846 tx_queue->max_non_tso_bd_num) ||
3847 hns3_check_tso_pkt_valid(m)) {
3852 if (tx_queue->tso_mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) {
3854 * (tso mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) means
3855 * hardware support recalculate the TCP pseudo header
3856 * checksum of packets that need TSO, so network driver
3857 * software not need to recalculate it.
3859 hns3_outer_header_cksum_prepare(m);
3864 ret = rte_net_intel_cksum_prepare(m);
3870 if (!hns3_validate_tunnel_cksum(tx_queue, m))
3873 hns3_outer_header_cksum_prepare(m);
3879 hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3885 for (i = 0; i < nb_pkts; i++) {
3887 if (hns3_prep_pkt_proc(tx_queue, m))
3895 hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
3898 struct hns3_desc *tx_ring = txq->tx_ring;
3899 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3901 /* Enable checksum offloading */
3902 if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK) {
3903 /* Fill in tunneling parameters if necessary */
3904 if (hns3_parse_tunneling_params(txq, m, tx_desc_id)) {
3905 txq->dfx_stats.unsupported_tunnel_pkt_cnt++;
3909 hns3_txd_enable_checksum(txq, m, tx_desc_id);
3911 /* clear the control bit */
3912 desc->tx.type_cs_vlan_tso_len = 0;
3913 desc->tx.ol_type_vlan_len_msec = 0;
3920 hns3_check_non_tso_pkt(uint16_t nb_buf, struct rte_mbuf **m_seg,
3921 struct rte_mbuf *tx_pkt, struct hns3_tx_queue *txq)
3923 uint8_t max_non_tso_bd_num;
3924 struct rte_mbuf *new_pkt;
3927 if (hns3_pkt_is_tso(*m_seg))
3931 * If packet length is greater than HNS3_MAX_FRAME_LEN
3932 * driver support, the packet will be ignored.
3934 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) > HNS3_MAX_FRAME_LEN)) {
3935 txq->dfx_stats.over_length_pkt_cnt++;
3939 max_non_tso_bd_num = txq->max_non_tso_bd_num;
3940 if (unlikely(nb_buf > max_non_tso_bd_num)) {
3941 txq->dfx_stats.exceed_limit_bd_pkt_cnt++;
3942 ret = hns3_reassemble_tx_pkts(tx_pkt, &new_pkt,
3943 max_non_tso_bd_num);
3945 txq->dfx_stats.exceed_limit_bd_reassem_fail++;
3955 hns3_tx_free_buffer_simple(struct hns3_tx_queue *txq)
3957 struct hns3_entry *tx_entry;
3958 struct hns3_desc *desc;
3959 uint16_t tx_next_clean;
3963 if (HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) < txq->tx_rs_thresh)
3967 * All mbufs can be released only when the VLD bits of all
3968 * descriptors in a batch are cleared.
3970 tx_next_clean = (txq->next_to_clean + txq->tx_rs_thresh - 1) %
3972 desc = &txq->tx_ring[tx_next_clean];
3973 for (i = 0; i < txq->tx_rs_thresh; i++) {
3974 if (rte_le_to_cpu_16(desc->tx.tp_fe_sc_vld_ra_ri) &
3975 BIT(HNS3_TXD_VLD_B))
3980 tx_entry = &txq->sw_ring[txq->next_to_clean];
3982 for (i = 0; i < txq->tx_rs_thresh; i++)
3983 rte_prefetch0((tx_entry + i)->mbuf);
3984 for (i = 0; i < txq->tx_rs_thresh; i++, tx_entry++) {
3985 rte_mempool_put(tx_entry->mbuf->pool, tx_entry->mbuf);
3986 tx_entry->mbuf = NULL;
3989 txq->next_to_clean = (tx_next_clean + 1) % txq->nb_tx_desc;
3990 txq->tx_bd_ready += txq->tx_rs_thresh;
3995 hns3_tx_backup_1mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
3997 tx_entry->mbuf = pkts[0];
4001 hns3_tx_backup_4mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
4003 hns3_tx_backup_1mbuf(&tx_entry[0], &pkts[0]);
4004 hns3_tx_backup_1mbuf(&tx_entry[1], &pkts[1]);
4005 hns3_tx_backup_1mbuf(&tx_entry[2], &pkts[2]);
4006 hns3_tx_backup_1mbuf(&tx_entry[3], &pkts[3]);
4010 hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
4012 #define PER_LOOP_NUM 4
4013 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
4017 for (i = 0; i < PER_LOOP_NUM; i++, txdp++, pkts++) {
4018 dma_addr = rte_mbuf_data_iova(*pkts);
4019 txdp->addr = rte_cpu_to_le_64(dma_addr);
4020 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
4021 txdp->tx.paylen_fd_dop_ol4cs = 0;
4022 txdp->tx.type_cs_vlan_tso_len = 0;
4023 txdp->tx.ol_type_vlan_len_msec = 0;
4024 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
4029 hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
4031 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
4034 dma_addr = rte_mbuf_data_iova(*pkts);
4035 txdp->addr = rte_cpu_to_le_64(dma_addr);
4036 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
4037 txdp->tx.paylen_fd_dop_ol4cs = 0;
4038 txdp->tx.type_cs_vlan_tso_len = 0;
4039 txdp->tx.ol_type_vlan_len_msec = 0;
4040 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
4044 hns3_tx_fill_hw_ring(struct hns3_tx_queue *txq,
4045 struct rte_mbuf **pkts,
4048 #define PER_LOOP_NUM 4
4049 #define PER_LOOP_MASK (PER_LOOP_NUM - 1)
4050 struct hns3_desc *txdp = &txq->tx_ring[txq->next_to_use];
4051 struct hns3_entry *tx_entry = &txq->sw_ring[txq->next_to_use];
4052 const uint32_t mainpart = (nb_pkts & ((uint32_t)~PER_LOOP_MASK));
4053 const uint32_t leftover = (nb_pkts & ((uint32_t)PER_LOOP_MASK));
4056 for (i = 0; i < mainpart; i += PER_LOOP_NUM) {
4057 hns3_tx_backup_4mbuf(tx_entry + i, pkts + i);
4058 hns3_tx_setup_4bd(txdp + i, pkts + i);
4060 /* Increment bytes counter */
4062 for (j = 0; j < PER_LOOP_NUM; j++)
4063 txq->basic_stats.bytes += pkts[i + j]->pkt_len;
4065 if (unlikely(leftover > 0)) {
4066 for (i = 0; i < leftover; i++) {
4067 hns3_tx_backup_1mbuf(tx_entry + mainpart + i,
4068 pkts + mainpart + i);
4069 hns3_tx_setup_1bd(txdp + mainpart + i,
4070 pkts + mainpart + i);
4072 /* Increment bytes counter */
4073 txq->basic_stats.bytes += pkts[mainpart + i]->pkt_len;
4079 hns3_xmit_pkts_simple(void *tx_queue,
4080 struct rte_mbuf **tx_pkts,
4083 struct hns3_tx_queue *txq = tx_queue;
4086 hns3_tx_free_buffer_simple(txq);
4088 nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts);
4089 if (unlikely(nb_pkts == 0)) {
4090 if (txq->tx_bd_ready == 0)
4091 txq->dfx_stats.queue_full_cnt++;
4095 txq->tx_bd_ready -= nb_pkts;
4096 if (txq->next_to_use + nb_pkts > txq->nb_tx_desc) {
4097 nb_tx = txq->nb_tx_desc - txq->next_to_use;
4098 hns3_tx_fill_hw_ring(txq, tx_pkts, nb_tx);
4099 txq->next_to_use = 0;
4102 hns3_tx_fill_hw_ring(txq, tx_pkts + nb_tx, nb_pkts - nb_tx);
4103 txq->next_to_use += nb_pkts - nb_tx;
4105 hns3_write_txq_tail_reg(txq, nb_pkts);
4111 hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
4113 struct hns3_tx_queue *txq = tx_queue;
4114 struct hns3_entry *tx_bak_pkt;
4115 struct hns3_desc *tx_ring;
4116 struct rte_mbuf *tx_pkt;
4117 struct rte_mbuf *m_seg;
4118 struct hns3_desc *desc;
4119 uint32_t nb_hold = 0;
4120 uint16_t tx_next_use;
4121 uint16_t tx_pkt_num;
4127 /* free useless buffer */
4128 hns3_tx_free_useless_buffer(txq);
4130 tx_next_use = txq->next_to_use;
4131 tx_bd_max = txq->nb_tx_desc;
4132 tx_pkt_num = nb_pkts;
4133 tx_ring = txq->tx_ring;
4136 tx_bak_pkt = &txq->sw_ring[tx_next_use];
4137 for (nb_tx = 0; nb_tx < tx_pkt_num; nb_tx++) {
4138 tx_pkt = *tx_pkts++;
4140 nb_buf = tx_pkt->nb_segs;
4142 if (nb_buf > txq->tx_bd_ready) {
4143 txq->dfx_stats.queue_full_cnt++;
4151 * If packet length is less than minimum packet length supported
4152 * by hardware in Tx direction, driver need to pad it to avoid
4155 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) <
4156 txq->min_tx_pkt_len)) {
4160 add_len = txq->min_tx_pkt_len -
4161 rte_pktmbuf_pkt_len(tx_pkt);
4162 appended = rte_pktmbuf_append(tx_pkt, add_len);
4163 if (appended == NULL) {
4164 txq->dfx_stats.pkt_padding_fail_cnt++;
4168 memset(appended, 0, add_len);
4173 if (hns3_check_non_tso_pkt(nb_buf, &m_seg, tx_pkt, txq))
4176 if (hns3_parse_cksum(txq, tx_next_use, m_seg))
4180 desc = &tx_ring[tx_next_use];
4183 * If the packet is divided into multiple Tx Buffer Descriptors,
4184 * only need to fill vlan, paylen and tso into the first Tx
4185 * Buffer Descriptor.
4187 hns3_fill_first_desc(txq, desc, m_seg);
4190 desc = &tx_ring[tx_next_use];
4192 * Fill valid bits, DMA address and data length for each
4193 * Tx Buffer Descriptor.
4195 hns3_fill_per_desc(desc, m_seg);
4196 tx_bak_pkt->mbuf = m_seg;
4197 m_seg = m_seg->next;
4200 if (tx_next_use >= tx_bd_max) {
4202 tx_bak_pkt = txq->sw_ring;
4206 } while (m_seg != NULL);
4208 /* Add end flag for the last Tx Buffer Descriptor */
4209 desc->tx.tp_fe_sc_vld_ra_ri |=
4210 rte_cpu_to_le_16(BIT(HNS3_TXD_FE_B));
4212 /* Increment bytes counter */
4213 txq->basic_stats.bytes += tx_pkt->pkt_len;
4215 txq->next_to_use = tx_next_use;
4216 txq->tx_bd_ready -= i;
4222 hns3_write_txq_tail_reg(txq, nb_hold);
4228 hns3_tx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
4234 hns3_xmit_pkts_vec(__rte_unused void *tx_queue,
4235 __rte_unused struct rte_mbuf **tx_pkts,
4236 __rte_unused uint16_t nb_pkts)
4242 hns3_xmit_pkts_vec_sve(void __rte_unused * tx_queue,
4243 struct rte_mbuf __rte_unused **tx_pkts,
4244 uint16_t __rte_unused nb_pkts)
4250 hns3_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
4251 struct rte_eth_burst_mode *mode)
4253 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
4254 const char *info = NULL;
4256 if (pkt_burst == hns3_xmit_pkts_simple)
4257 info = "Scalar Simple";
4258 else if (pkt_burst == hns3_xmit_pkts)
4260 else if (pkt_burst == hns3_xmit_pkts_vec)
4261 info = "Vector Neon";
4262 else if (pkt_burst == hns3_xmit_pkts_vec_sve)
4263 info = "Vector Sve";
4268 snprintf(mode->info, sizeof(mode->info), "%s", info);
4274 hns3_tx_check_simple_support(struct rte_eth_dev *dev)
4276 uint64_t offloads = dev->data->dev_conf.txmode.offloads;
4278 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4279 if (hns3_dev_ptp_supported(hw))
4282 return (offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE));
4286 hns3_get_tx_prep_needed(struct rte_eth_dev *dev)
4288 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4290 /* always perform tx_prepare when debug */
4293 #define HNS3_DEV_TX_CSKUM_TSO_OFFLOAD_MASK (\
4294 DEV_TX_OFFLOAD_IPV4_CKSUM | \
4295 DEV_TX_OFFLOAD_TCP_CKSUM | \
4296 DEV_TX_OFFLOAD_UDP_CKSUM | \
4297 DEV_TX_OFFLOAD_SCTP_CKSUM | \
4298 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
4299 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
4300 DEV_TX_OFFLOAD_TCP_TSO | \
4301 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
4302 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
4303 DEV_TX_OFFLOAD_GENEVE_TNL_TSO)
4305 uint64_t tx_offload = dev->data->dev_conf.txmode.offloads;
4306 if (tx_offload & HNS3_DEV_TX_CSKUM_TSO_OFFLOAD_MASK)
4314 hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep)
4316 struct hns3_adapter *hns = dev->data->dev_private;
4317 bool vec_allowed, sve_allowed, simple_allowed;
4318 bool vec_support, tx_prepare_needed;
4320 vec_support = hns3_tx_check_vec_support(dev) == 0;
4321 vec_allowed = vec_support && hns3_get_default_vec_support();
4322 sve_allowed = vec_support && hns3_get_sve_support();
4323 simple_allowed = hns3_tx_check_simple_support(dev);
4324 tx_prepare_needed = hns3_get_tx_prep_needed(dev);
4328 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed)
4329 return hns3_xmit_pkts_vec;
4330 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed)
4331 return hns3_xmit_pkts_vec_sve;
4332 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed)
4333 return hns3_xmit_pkts_simple;
4334 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_COMMON) {
4335 if (tx_prepare_needed)
4336 *prep = hns3_prep_pkts;
4337 return hns3_xmit_pkts;
4341 return hns3_xmit_pkts_vec;
4343 return hns3_xmit_pkts_simple;
4345 if (tx_prepare_needed)
4346 *prep = hns3_prep_pkts;
4347 return hns3_xmit_pkts;
4351 hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused,
4352 struct rte_mbuf **pkts __rte_unused,
4353 uint16_t pkts_n __rte_unused)
4359 hns3_trace_rxtx_function(struct rte_eth_dev *dev)
4361 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4362 struct rte_eth_burst_mode rx_mode;
4363 struct rte_eth_burst_mode tx_mode;
4365 memset(&rx_mode, 0, sizeof(rx_mode));
4366 memset(&tx_mode, 0, sizeof(tx_mode));
4367 (void)hns3_rx_burst_mode_get(dev, 0, &rx_mode);
4368 (void)hns3_tx_burst_mode_get(dev, 0, &tx_mode);
4370 hns3_dbg(hw, "using rx_pkt_burst: %s, tx_pkt_burst: %s.",
4371 rx_mode.info, tx_mode.info);
4374 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)
4376 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
4377 struct hns3_adapter *hns = eth_dev->data->dev_private;
4378 eth_tx_prep_t prep = NULL;
4380 if (hns->hw.adapter_state == HNS3_NIC_STARTED &&
4381 __atomic_load_n(&hns->hw.reset.resetting, __ATOMIC_RELAXED) == 0) {
4382 eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev);
4383 eth_dev->rx_descriptor_status = hns3_dev_rx_descriptor_status;
4384 eth_dev->tx_pkt_burst = hw->set_link_down ?
4385 hns3_dummy_rxtx_burst :
4386 hns3_get_tx_function(eth_dev, &prep);
4387 eth_dev->tx_pkt_prepare = prep;
4388 eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status;
4389 hns3_trace_rxtx_function(eth_dev);
4391 eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst;
4392 eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
4393 eth_dev->tx_pkt_prepare = NULL;
4398 hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
4399 struct rte_eth_rxq_info *qinfo)
4401 struct hns3_rx_queue *rxq = dev->data->rx_queues[queue_id];
4403 qinfo->mp = rxq->mb_pool;
4404 qinfo->nb_desc = rxq->nb_rx_desc;
4405 qinfo->scattered_rx = dev->data->scattered_rx;
4406 /* Report the HW Rx buffer length to user */
4407 qinfo->rx_buf_size = rxq->rx_buf_len;
4410 * If there are no available Rx buffer descriptors, incoming packets
4411 * are always dropped by hardware based on hns3 network engine.
4413 qinfo->conf.rx_drop_en = 1;
4414 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
4415 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
4416 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
4420 hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
4421 struct rte_eth_txq_info *qinfo)
4423 struct hns3_tx_queue *txq = dev->data->tx_queues[queue_id];
4425 qinfo->nb_desc = txq->nb_tx_desc;
4426 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
4427 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
4428 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
4429 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
4433 hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4435 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4436 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id];
4437 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4440 if (!hns3_dev_indep_txrx_supported(hw))
4443 rte_spinlock_lock(&hw->lock);
4444 ret = hns3_reset_queue(hw, rx_queue_id, HNS3_RING_TYPE_RX);
4446 hns3_err(hw, "fail to reset Rx queue %u, ret = %d.",
4448 rte_spinlock_unlock(&hw->lock);
4452 ret = hns3_init_rxq(hns, rx_queue_id);
4454 hns3_err(hw, "fail to init Rx queue %u, ret = %d.",
4456 rte_spinlock_unlock(&hw->lock);
4460 hns3_enable_rxq(rxq, true);
4461 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
4462 rte_spinlock_unlock(&hw->lock);
4468 hns3_reset_sw_rxq(struct hns3_rx_queue *rxq)
4470 rxq->next_to_use = 0;
4471 rxq->rx_rearm_start = 0;
4472 rxq->rx_free_hold = 0;
4473 rxq->rx_rearm_nb = 0;
4474 rxq->pkt_first_seg = NULL;
4475 rxq->pkt_last_seg = NULL;
4476 memset(&rxq->rx_ring[0], 0, rxq->nb_rx_desc * sizeof(struct hns3_desc));
4477 hns3_rxq_vec_setup(rxq);
4481 hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4483 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4484 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id];
4486 if (!hns3_dev_indep_txrx_supported(hw))
4489 rte_spinlock_lock(&hw->lock);
4490 hns3_enable_rxq(rxq, false);
4492 hns3_rx_queue_release_mbufs(rxq);
4494 hns3_reset_sw_rxq(rxq);
4495 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
4496 rte_spinlock_unlock(&hw->lock);
4502 hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4504 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4505 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id];
4508 if (!hns3_dev_indep_txrx_supported(hw))
4511 rte_spinlock_lock(&hw->lock);
4512 ret = hns3_reset_queue(hw, tx_queue_id, HNS3_RING_TYPE_TX);
4514 hns3_err(hw, "fail to reset Tx queue %u, ret = %d.",
4516 rte_spinlock_unlock(&hw->lock);
4521 hns3_enable_txq(txq, true);
4522 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
4523 rte_spinlock_unlock(&hw->lock);
4529 hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4531 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4532 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id];
4534 if (!hns3_dev_indep_txrx_supported(hw))
4537 rte_spinlock_lock(&hw->lock);
4538 hns3_enable_txq(txq, false);
4539 hns3_tx_queue_release_mbufs(txq);
4541 * All the mbufs in sw_ring are released and all the pointers in sw_ring
4542 * are set to NULL. If this queue is still called by upper layer,
4543 * residual SW status of this txq may cause these pointers in sw_ring
4544 * which have been set to NULL to be released again. To avoid it,
4548 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
4549 rte_spinlock_unlock(&hw->lock);
4555 hns3_tx_done_cleanup_full(struct hns3_tx_queue *txq, uint32_t free_cnt)
4557 uint16_t next_to_clean = txq->next_to_clean;
4558 uint16_t next_to_use = txq->next_to_use;
4559 uint16_t tx_bd_ready = txq->tx_bd_ready;
4560 struct hns3_entry *tx_pkt = &txq->sw_ring[next_to_clean];
4561 struct hns3_desc *desc = &txq->tx_ring[next_to_clean];
4564 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
4565 free_cnt = txq->nb_tx_desc;
4567 for (idx = 0; idx < free_cnt; idx++) {
4568 if (next_to_clean == next_to_use)
4571 if (desc->tx.tp_fe_sc_vld_ra_ri &
4572 rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)))
4575 if (tx_pkt->mbuf != NULL) {
4576 rte_pktmbuf_free_seg(tx_pkt->mbuf);
4577 tx_pkt->mbuf = NULL;
4584 if (next_to_clean == txq->nb_tx_desc) {
4585 tx_pkt = txq->sw_ring;
4586 desc = txq->tx_ring;
4592 txq->next_to_clean = next_to_clean;
4593 txq->tx_bd_ready = tx_bd_ready;
4600 hns3_tx_done_cleanup(void *txq, uint32_t free_cnt)
4602 struct hns3_tx_queue *q = (struct hns3_tx_queue *)txq;
4603 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
4605 if (dev->tx_pkt_burst == hns3_xmit_pkts)
4606 return hns3_tx_done_cleanup_full(q, free_cnt);
4607 else if (dev->tx_pkt_burst == hns3_dummy_rxtx_burst)
4614 hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
4616 volatile struct hns3_desc *rxdp;
4617 struct hns3_rx_queue *rxq;
4618 struct rte_eth_dev *dev;
4619 uint32_t bd_base_info;
4622 rxq = (struct hns3_rx_queue *)rx_queue;
4623 if (offset >= rxq->nb_rx_desc)
4626 desc_id = (rxq->next_to_use + offset) % rxq->nb_rx_desc;
4627 rxdp = &rxq->rx_ring[desc_id];
4628 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
4629 dev = &rte_eth_devices[rxq->port_id];
4630 if (dev->rx_pkt_burst == hns3_recv_pkts_simple ||
4631 dev->rx_pkt_burst == hns3_recv_scattered_pkts) {
4632 if (offset >= rxq->nb_rx_desc - rxq->rx_free_hold)
4633 return RTE_ETH_RX_DESC_UNAVAIL;
4634 } else if (dev->rx_pkt_burst == hns3_recv_pkts_vec ||
4635 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve) {
4636 if (offset >= rxq->nb_rx_desc - rxq->rx_rearm_nb)
4637 return RTE_ETH_RX_DESC_UNAVAIL;
4639 return RTE_ETH_RX_DESC_UNAVAIL;
4642 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
4643 return RTE_ETH_RX_DESC_AVAIL;
4645 return RTE_ETH_RX_DESC_DONE;
4649 hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
4651 volatile struct hns3_desc *txdp;
4652 struct hns3_tx_queue *txq;
4653 struct rte_eth_dev *dev;
4656 txq = (struct hns3_tx_queue *)tx_queue;
4657 if (offset >= txq->nb_tx_desc)
4660 dev = &rte_eth_devices[txq->port_id];
4661 if (dev->tx_pkt_burst != hns3_xmit_pkts_simple &&
4662 dev->tx_pkt_burst != hns3_xmit_pkts &&
4663 dev->tx_pkt_burst != hns3_xmit_pkts_vec_sve &&
4664 dev->tx_pkt_burst != hns3_xmit_pkts_vec)
4665 return RTE_ETH_TX_DESC_UNAVAIL;
4667 desc_id = (txq->next_to_use + offset) % txq->nb_tx_desc;
4668 txdp = &txq->tx_ring[desc_id];
4669 if (txdp->tx.tp_fe_sc_vld_ra_ri & rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)))
4670 return RTE_ETH_TX_DESC_FULL;
4672 return RTE_ETH_TX_DESC_DONE;
4676 hns3_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4679 * Number of BDs that have been processed by the driver
4680 * but have not been notified to the hardware.
4682 uint32_t driver_hold_bd_num;
4683 struct hns3_rx_queue *rxq;
4686 rxq = dev->data->rx_queues[rx_queue_id];
4687 fbd_num = hns3_read_dev(rxq, HNS3_RING_RX_FBDNUM_REG);
4688 if (dev->rx_pkt_burst == hns3_recv_pkts_vec ||
4689 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve)
4690 driver_hold_bd_num = rxq->rx_rearm_nb;
4692 driver_hold_bd_num = rxq->rx_free_hold;
4694 if (fbd_num <= driver_hold_bd_num)
4697 return fbd_num - driver_hold_bd_num;
4701 hns3_enable_rxd_adv_layout(struct hns3_hw *hw)
4704 * If the hardware support rxd advanced layout, then driver enable it
4707 if (hns3_dev_rxd_adv_layout_supported(hw))
4708 hns3_write_dev(hw, HNS3_RXD_ADV_LAYOUT_EN_REG, 1);
4712 hns3_stop_tx_datapath(struct rte_eth_dev *dev)
4714 dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
4715 dev->tx_pkt_prepare = NULL;
4717 /* Disable tx datapath on secondary process. */
4718 hns3_mp_req_stop_tx(dev);
4719 /* Prevent crashes when queues are still in use. */
4720 rte_delay_ms(dev->data->nb_tx_queues);
4724 hns3_start_tx_datapath(struct rte_eth_dev *dev)
4726 eth_tx_prep_t prep = NULL;
4728 dev->tx_pkt_burst = hns3_get_tx_function(dev, &prep);
4729 dev->tx_pkt_prepare = prep;
4730 hns3_mp_req_start_tx(dev);