1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #include <rte_bus_pci.h>
6 #include <rte_common.h>
7 #include <rte_cycles.h>
9 #include <rte_ethdev_driver.h>
12 #include <rte_malloc.h>
13 #if defined(RTE_ARCH_ARM64) && defined(CC_SVE_SUPPORT)
14 #include <rte_cpuflags.h>
17 #include "hns3_ethdev.h"
18 #include "hns3_rxtx.h"
19 #include "hns3_regs.h"
20 #include "hns3_logs.h"
22 #define HNS3_CFG_DESC_NUM(num) ((num) / 8 - 1)
23 #define HNS3_RX_RING_PREFETCTH_MASK 3
26 hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq)
30 /* Note: Fake rx queue will not enter here */
31 if (rxq->sw_ring == NULL)
34 if (rxq->rx_rearm_nb == 0) {
35 for (i = 0; i < rxq->nb_rx_desc; i++) {
36 if (rxq->sw_ring[i].mbuf != NULL) {
37 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
38 rxq->sw_ring[i].mbuf = NULL;
42 for (i = rxq->next_to_use;
43 i != rxq->rx_rearm_start;
44 i = (i + 1) % rxq->nb_rx_desc) {
45 if (rxq->sw_ring[i].mbuf != NULL) {
46 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
47 rxq->sw_ring[i].mbuf = NULL;
52 for (i = 0; i < rxq->bulk_mbuf_num; i++)
53 rte_pktmbuf_free_seg(rxq->bulk_mbuf[i]);
54 rxq->bulk_mbuf_num = 0;
56 if (rxq->pkt_first_seg) {
57 rte_pktmbuf_free(rxq->pkt_first_seg);
58 rxq->pkt_first_seg = NULL;
63 hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq)
67 /* Note: Fake tx queue will not enter here */
69 for (i = 0; i < txq->nb_tx_desc; i++) {
70 if (txq->sw_ring[i].mbuf) {
71 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
72 txq->sw_ring[i].mbuf = NULL;
79 hns3_rx_queue_release(void *queue)
81 struct hns3_rx_queue *rxq = queue;
83 hns3_rx_queue_release_mbufs(rxq);
85 rte_memzone_free(rxq->mz);
87 rte_free(rxq->sw_ring);
93 hns3_tx_queue_release(void *queue)
95 struct hns3_tx_queue *txq = queue;
97 hns3_tx_queue_release_mbufs(txq);
99 rte_memzone_free(txq->mz);
101 rte_free(txq->sw_ring);
109 hns3_dev_rx_queue_release(void *queue)
111 struct hns3_rx_queue *rxq = queue;
112 struct hns3_adapter *hns;
118 rte_spinlock_lock(&hns->hw.lock);
119 hns3_rx_queue_release(queue);
120 rte_spinlock_unlock(&hns->hw.lock);
124 hns3_dev_tx_queue_release(void *queue)
126 struct hns3_tx_queue *txq = queue;
127 struct hns3_adapter *hns;
133 rte_spinlock_lock(&hns->hw.lock);
134 hns3_tx_queue_release(queue);
135 rte_spinlock_unlock(&hns->hw.lock);
139 hns3_fake_rx_queue_release(struct hns3_rx_queue *queue)
141 struct hns3_rx_queue *rxq = queue;
142 struct hns3_adapter *hns;
152 if (hw->fkq_data.rx_queues[idx]) {
153 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
154 hw->fkq_data.rx_queues[idx] = NULL;
157 /* free fake rx queue arrays */
158 if (idx == (hw->fkq_data.nb_fake_rx_queues - 1)) {
159 hw->fkq_data.nb_fake_rx_queues = 0;
160 rte_free(hw->fkq_data.rx_queues);
161 hw->fkq_data.rx_queues = NULL;
166 hns3_fake_tx_queue_release(struct hns3_tx_queue *queue)
168 struct hns3_tx_queue *txq = queue;
169 struct hns3_adapter *hns;
179 if (hw->fkq_data.tx_queues[idx]) {
180 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
181 hw->fkq_data.tx_queues[idx] = NULL;
184 /* free fake tx queue arrays */
185 if (idx == (hw->fkq_data.nb_fake_tx_queues - 1)) {
186 hw->fkq_data.nb_fake_tx_queues = 0;
187 rte_free(hw->fkq_data.tx_queues);
188 hw->fkq_data.tx_queues = NULL;
193 hns3_free_rx_queues(struct rte_eth_dev *dev)
195 struct hns3_adapter *hns = dev->data->dev_private;
196 struct hns3_fake_queue_data *fkq_data;
197 struct hns3_hw *hw = &hns->hw;
201 nb_rx_q = hw->data->nb_rx_queues;
202 for (i = 0; i < nb_rx_q; i++) {
203 if (dev->data->rx_queues[i]) {
204 hns3_rx_queue_release(dev->data->rx_queues[i]);
205 dev->data->rx_queues[i] = NULL;
209 /* Free fake Rx queues */
210 fkq_data = &hw->fkq_data;
211 for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) {
212 if (fkq_data->rx_queues[i])
213 hns3_fake_rx_queue_release(fkq_data->rx_queues[i]);
218 hns3_free_tx_queues(struct rte_eth_dev *dev)
220 struct hns3_adapter *hns = dev->data->dev_private;
221 struct hns3_fake_queue_data *fkq_data;
222 struct hns3_hw *hw = &hns->hw;
226 nb_tx_q = hw->data->nb_tx_queues;
227 for (i = 0; i < nb_tx_q; i++) {
228 if (dev->data->tx_queues[i]) {
229 hns3_tx_queue_release(dev->data->tx_queues[i]);
230 dev->data->tx_queues[i] = NULL;
234 /* Free fake Tx queues */
235 fkq_data = &hw->fkq_data;
236 for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) {
237 if (fkq_data->tx_queues[i])
238 hns3_fake_tx_queue_release(fkq_data->tx_queues[i]);
243 hns3_free_all_queues(struct rte_eth_dev *dev)
245 hns3_free_rx_queues(dev);
246 hns3_free_tx_queues(dev);
250 hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq)
252 struct rte_mbuf *mbuf;
256 for (i = 0; i < rxq->nb_rx_desc; i++) {
257 mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
258 if (unlikely(mbuf == NULL)) {
259 hns3_err(hw, "Failed to allocate RXD[%u] for rx queue!",
261 hns3_rx_queue_release_mbufs(rxq);
265 rte_mbuf_refcnt_set(mbuf, 1);
267 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
269 mbuf->port = rxq->port_id;
271 rxq->sw_ring[i].mbuf = mbuf;
272 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
273 rxq->rx_ring[i].addr = dma_addr;
274 rxq->rx_ring[i].rx.bd_base_info = 0;
281 hns3_buf_size2type(uint32_t buf_size)
287 bd_size_type = HNS3_BD_SIZE_512_TYPE;
290 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
293 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
296 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
303 hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)
305 uint32_t rx_buf_len = rxq->rx_buf_len;
306 uint64_t dma_addr = rxq->rx_ring_phys_addr;
308 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);
309 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,
310 (uint32_t)((dma_addr >> 31) >> 1));
312 hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,
313 hns3_buf_size2type(rx_buf_len));
314 hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG,
315 HNS3_CFG_DESC_NUM(rxq->nb_rx_desc));
319 hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)
321 uint64_t dma_addr = txq->tx_ring_phys_addr;
323 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);
324 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,
325 (uint32_t)((dma_addr >> 31) >> 1));
327 hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,
328 HNS3_CFG_DESC_NUM(txq->nb_tx_desc));
332 hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw)
334 uint16_t nb_rx_q = hw->data->nb_rx_queues;
335 uint16_t nb_tx_q = hw->data->nb_tx_queues;
336 struct hns3_rx_queue *rxq;
337 struct hns3_tx_queue *txq;
341 pvid_en = hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE;
342 for (i = 0; i < hw->cfg_max_queues; i++) {
344 rxq = hw->data->rx_queues[i];
346 rxq->pvid_sw_discard_en = pvid_en;
349 txq = hw->data->tx_queues[i];
351 txq->pvid_sw_shift_en = pvid_en;
357 hns3_enable_all_queues(struct hns3_hw *hw, bool en)
359 uint16_t nb_rx_q = hw->data->nb_rx_queues;
360 uint16_t nb_tx_q = hw->data->nb_tx_queues;
361 struct hns3_rx_queue *rxq;
362 struct hns3_tx_queue *txq;
367 for (i = 0; i < hw->cfg_max_queues; i++) {
368 if (hns3_dev_indep_txrx_supported(hw)) {
369 rxq = i < nb_rx_q ? hw->data->rx_queues[i] : NULL;
370 txq = i < nb_tx_q ? hw->data->tx_queues[i] : NULL;
372 * After initialization, rxq and txq won't be NULL at
376 tqp_base = rxq->io_base;
377 else if (txq != NULL)
378 tqp_base = txq->io_base;
382 rxq = i < nb_rx_q ? hw->data->rx_queues[i] :
383 hw->fkq_data.rx_queues[i - nb_rx_q];
385 tqp_base = rxq->io_base;
388 * This is the master switch that used to control the enabling
389 * of a pair of Tx and Rx queues. Both the Rx and Tx point to
392 rcb_reg = hns3_read_reg(tqp_base, HNS3_RING_EN_REG);
394 rcb_reg |= BIT(HNS3_RING_EN_B);
396 rcb_reg &= ~BIT(HNS3_RING_EN_B);
397 hns3_write_reg(tqp_base, HNS3_RING_EN_REG, rcb_reg);
402 hns3_enable_txq(struct hns3_tx_queue *txq, bool en)
404 struct hns3_hw *hw = &txq->hns->hw;
407 if (hns3_dev_indep_txrx_supported(hw)) {
408 reg = hns3_read_dev(txq, HNS3_RING_TX_EN_REG);
410 reg |= BIT(HNS3_RING_EN_B);
412 reg &= ~BIT(HNS3_RING_EN_B);
413 hns3_write_dev(txq, HNS3_RING_TX_EN_REG, reg);
419 hns3_enable_rxq(struct hns3_rx_queue *rxq, bool en)
421 struct hns3_hw *hw = &rxq->hns->hw;
424 if (hns3_dev_indep_txrx_supported(hw)) {
425 reg = hns3_read_dev(rxq, HNS3_RING_RX_EN_REG);
427 reg |= BIT(HNS3_RING_EN_B);
429 reg &= ~BIT(HNS3_RING_EN_B);
430 hns3_write_dev(rxq, HNS3_RING_RX_EN_REG, reg);
436 hns3_start_all_txqs(struct rte_eth_dev *dev)
438 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
439 struct hns3_tx_queue *txq;
442 for (i = 0; i < dev->data->nb_tx_queues; i++) {
443 txq = hw->data->tx_queues[i];
445 hns3_err(hw, "Tx queue %u not available or setup.", i);
446 goto start_txqs_fail;
449 * Tx queue is enabled by default. Therefore, the Tx queues
450 * needs to be disabled when deferred_start is set. There is
451 * another master switch used to control the enabling of a pair
452 * of Tx and Rx queues. And the master switch is disabled by
455 if (txq->tx_deferred_start)
456 hns3_enable_txq(txq, false);
458 hns3_enable_txq(txq, true);
463 for (j = 0; j < i; j++) {
464 txq = hw->data->tx_queues[j];
465 hns3_enable_txq(txq, false);
471 hns3_start_all_rxqs(struct rte_eth_dev *dev)
473 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
474 struct hns3_rx_queue *rxq;
477 for (i = 0; i < dev->data->nb_rx_queues; i++) {
478 rxq = hw->data->rx_queues[i];
480 hns3_err(hw, "Rx queue %u not available or setup.", i);
481 goto start_rxqs_fail;
484 * Rx queue is enabled by default. Therefore, the Rx queues
485 * needs to be disabled when deferred_start is set. There is
486 * another master switch used to control the enabling of a pair
487 * of Tx and Rx queues. And the master switch is disabled by
490 if (rxq->rx_deferred_start)
491 hns3_enable_rxq(rxq, false);
493 hns3_enable_rxq(rxq, true);
498 for (j = 0; j < i; j++) {
499 rxq = hw->data->rx_queues[j];
500 hns3_enable_rxq(rxq, false);
506 hns3_restore_tqp_enable_state(struct hns3_hw *hw)
508 struct hns3_rx_queue *rxq;
509 struct hns3_tx_queue *txq;
512 for (i = 0; i < hw->data->nb_rx_queues; i++) {
513 rxq = hw->data->rx_queues[i];
515 hns3_enable_rxq(rxq, rxq->enabled);
518 for (i = 0; i < hw->data->nb_tx_queues; i++) {
519 txq = hw->data->tx_queues[i];
521 hns3_enable_txq(txq, txq->enabled);
526 hns3_stop_all_txqs(struct rte_eth_dev *dev)
528 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
529 struct hns3_tx_queue *txq;
532 for (i = 0; i < dev->data->nb_tx_queues; i++) {
533 txq = hw->data->tx_queues[i];
536 hns3_enable_txq(txq, false);
541 hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable)
543 struct hns3_cfg_com_tqp_queue_cmd *req;
544 struct hns3_cmd_desc desc;
547 req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data;
549 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false);
550 req->tqp_id = rte_cpu_to_le_16(queue_id);
552 hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0);
554 ret = hns3_cmd_send(hw, &desc, 1);
556 hns3_err(hw, "TQP enable fail, ret = %d", ret);
562 hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable)
564 struct hns3_reset_tqp_queue_cmd *req;
565 struct hns3_cmd_desc desc;
568 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false);
570 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
571 req->tqp_id = rte_cpu_to_le_16(queue_id);
572 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
573 ret = hns3_cmd_send(hw, &desc, 1);
575 hns3_err(hw, "send tqp reset cmd error, queue_id = %u, "
576 "ret = %d", queue_id, ret);
582 hns3_get_tqp_reset_status(struct hns3_hw *hw, uint16_t queue_id,
583 uint8_t *reset_status)
585 struct hns3_reset_tqp_queue_cmd *req;
586 struct hns3_cmd_desc desc;
589 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true);
591 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
592 req->tqp_id = rte_cpu_to_le_16(queue_id);
594 ret = hns3_cmd_send(hw, &desc, 1);
596 hns3_err(hw, "get tqp reset status error, queue_id = %u, "
597 "ret = %d.", queue_id, ret);
600 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
605 hns3pf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
607 #define HNS3_TQP_RESET_TRY_MS 200
608 uint8_t reset_status;
612 ret = hns3_tqp_enable(hw, queue_id, false);
617 * In current version VF is not supported when PF is driven by DPDK
618 * driver, all task queue pairs are mapped to PF function, so PF's queue
619 * id is equals to the global queue id in PF range.
621 ret = hns3_send_reset_tqp_cmd(hw, queue_id, true);
623 hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret);
626 end = get_timeofday_ms() + HNS3_TQP_RESET_TRY_MS;
628 /* Wait for tqp hw reset */
629 rte_delay_ms(HNS3_POLL_RESPONE_MS);
630 ret = hns3_get_tqp_reset_status(hw, queue_id, &reset_status);
636 } while (get_timeofday_ms() < end);
640 hns3_err(hw, "reset tqp timeout, queue_id = %u, ret = %d",
645 ret = hns3_send_reset_tqp_cmd(hw, queue_id, false);
647 hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret);
652 hns3_send_reset_tqp_cmd(hw, queue_id, false);
657 hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
662 /* Disable VF's queue before send queue reset msg to PF */
663 ret = hns3_tqp_enable(hw, queue_id, false);
667 memcpy(msg_data, &queue_id, sizeof(uint16_t));
669 ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
670 sizeof(msg_data), true, NULL, 0);
672 hns3_err(hw, "fail to reset tqp, queue_id = %u, ret = %d.",
678 hns3_reset_tqp(struct hns3_adapter *hns, uint16_t queue_id)
680 struct hns3_hw *hw = &hns->hw;
683 return hns3vf_reset_tqp(hw, queue_id);
685 return hns3pf_reset_tqp(hw, queue_id);
689 hns3_reset_all_tqps(struct hns3_adapter *hns)
691 struct hns3_hw *hw = &hns->hw;
694 for (i = 0; i < hw->cfg_max_queues; i++) {
695 ret = hns3_reset_tqp(hns, i);
697 hns3_err(hw, "Failed to reset No.%d queue: %d", i, ret);
705 hns3_send_reset_queue_cmd(struct hns3_hw *hw, uint16_t queue_id,
706 enum hns3_ring_type queue_type, bool enable)
708 struct hns3_reset_tqp_queue_cmd *req;
709 struct hns3_cmd_desc desc;
713 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, false);
715 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
716 req->tqp_id = rte_cpu_to_le_16(queue_id);
717 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
718 req->queue_direction = rte_cpu_to_le_16(queue_direction);
719 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
721 ret = hns3_cmd_send(hw, &desc, 1);
723 hns3_err(hw, "send queue reset cmd error, queue_id = %u, "
724 "queue_type = %s, ret = %d.", queue_id,
725 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
730 hns3_get_queue_reset_status(struct hns3_hw *hw, uint16_t queue_id,
731 enum hns3_ring_type queue_type,
732 uint8_t *reset_status)
734 struct hns3_reset_tqp_queue_cmd *req;
735 struct hns3_cmd_desc desc;
739 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, true);
741 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
742 req->tqp_id = rte_cpu_to_le_16(queue_id);
743 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
744 req->queue_direction = rte_cpu_to_le_16(queue_direction);
746 ret = hns3_cmd_send(hw, &desc, 1);
748 hns3_err(hw, "get queue reset status error, queue_id = %u "
749 "queue_type = %s, ret = %d.", queue_id,
750 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
754 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
759 hns3_reset_queue(struct hns3_hw *hw, uint16_t queue_id,
760 enum hns3_ring_type queue_type)
762 #define HNS3_QUEUE_RESET_TRY_MS 200
763 struct hns3_tx_queue *txq;
764 struct hns3_rx_queue *rxq;
765 uint32_t reset_wait_times;
766 uint32_t max_wait_times;
767 uint8_t reset_status;
770 if (queue_type == HNS3_RING_TYPE_TX) {
771 txq = hw->data->tx_queues[queue_id];
772 hns3_enable_txq(txq, false);
774 rxq = hw->data->rx_queues[queue_id];
775 hns3_enable_rxq(rxq, false);
778 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, true);
780 hns3_err(hw, "send reset queue cmd fail, ret = %d.", ret);
784 reset_wait_times = 0;
785 max_wait_times = HNS3_QUEUE_RESET_TRY_MS / HNS3_POLL_RESPONE_MS;
786 while (reset_wait_times < max_wait_times) {
787 /* Wait for queue hw reset */
788 rte_delay_ms(HNS3_POLL_RESPONE_MS);
789 ret = hns3_get_queue_reset_status(hw, queue_id,
790 queue_type, &reset_status);
792 goto queue_reset_fail;
800 hns3_err(hw, "reset queue timeout, queue_id = %u, "
801 "queue_type = %s", queue_id,
802 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx");
804 goto queue_reset_fail;
807 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
809 hns3_err(hw, "deassert queue reset fail, ret = %d.", ret);
814 hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
820 hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
821 uint8_t gl_idx, uint16_t gl_value)
823 uint32_t offset[] = {HNS3_TQP_INTR_GL0_REG,
824 HNS3_TQP_INTR_GL1_REG,
825 HNS3_TQP_INTR_GL2_REG};
826 uint32_t addr, value;
828 if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX)
831 addr = offset[gl_idx] + queue_id * HNS3_TQP_INTR_REG_SIZE;
832 if (hw->intr.gl_unit == HNS3_INTR_COALESCE_GL_UINT_1US)
833 value = gl_value | HNS3_TQP_INTR_GL_UNIT_1US;
835 value = HNS3_GL_USEC_TO_REG(gl_value);
837 hns3_write_dev(hw, addr, value);
841 hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value)
843 uint32_t addr, value;
845 if (rl_value > HNS3_TQP_INTR_RL_MAX)
848 addr = HNS3_TQP_INTR_RL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
849 value = HNS3_RL_USEC_TO_REG(rl_value);
851 value |= HNS3_TQP_INTR_RL_ENABLE_MASK;
853 hns3_write_dev(hw, addr, value);
857 hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value)
862 * int_ql_max == 0 means the hardware does not support QL,
863 * QL regs config is not permitted if QL is not supported,
866 if (hw->intr.int_ql_max == HNS3_INTR_QL_NONE)
869 addr = HNS3_TQP_INTR_TX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
870 hns3_write_dev(hw, addr, ql_value);
872 addr = HNS3_TQP_INTR_RX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
873 hns3_write_dev(hw, addr, ql_value);
877 hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en)
879 uint32_t addr, value;
881 addr = HNS3_TQP_INTR_CTRL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
884 hns3_write_dev(hw, addr, value);
888 * Enable all rx queue interrupt when in interrupt rx mode.
889 * This api was called before enable queue rx&tx (in normal start or reset
890 * recover scenes), used to fix hardware rx queue interrupt enable was clear
894 hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en)
896 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
897 uint16_t nb_rx_q = hw->data->nb_rx_queues;
900 if (dev->data->dev_conf.intr_conf.rxq == 0)
903 for (i = 0; i < nb_rx_q; i++)
904 hns3_queue_intr_enable(hw, i, en);
908 hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
910 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
911 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
912 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
914 if (dev->data->dev_conf.intr_conf.rxq == 0)
917 hns3_queue_intr_enable(hw, queue_id, true);
919 return rte_intr_ack(intr_handle);
923 hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
925 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
927 if (dev->data->dev_conf.intr_conf.rxq == 0)
930 hns3_queue_intr_enable(hw, queue_id, false);
936 hns3_init_rxq(struct hns3_adapter *hns, uint16_t idx)
938 struct hns3_hw *hw = &hns->hw;
939 struct hns3_rx_queue *rxq;
942 PMD_INIT_FUNC_TRACE();
944 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx];
945 ret = hns3_alloc_rx_queue_mbufs(hw, rxq);
947 hns3_err(hw, "fail to alloc mbuf for Rx queue %u, ret = %d.",
952 rxq->next_to_use = 0;
953 rxq->rx_rearm_start = 0;
954 rxq->rx_free_hold = 0;
955 rxq->rx_rearm_nb = 0;
956 rxq->pkt_first_seg = NULL;
957 rxq->pkt_last_seg = NULL;
958 hns3_init_rx_queue_hw(rxq);
959 hns3_rxq_vec_setup(rxq);
965 hns3_init_fake_rxq(struct hns3_adapter *hns, uint16_t idx)
967 struct hns3_hw *hw = &hns->hw;
968 struct hns3_rx_queue *rxq;
970 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx];
971 rxq->next_to_use = 0;
972 rxq->rx_free_hold = 0;
973 rxq->rx_rearm_start = 0;
974 rxq->rx_rearm_nb = 0;
975 hns3_init_rx_queue_hw(rxq);
979 hns3_init_txq(struct hns3_tx_queue *txq)
981 struct hns3_desc *desc;
986 for (i = 0; i < txq->nb_tx_desc; i++) {
987 desc->tx.tp_fe_sc_vld_ra_ri = 0;
991 txq->next_to_use = 0;
992 txq->next_to_clean = 0;
993 txq->tx_bd_ready = txq->nb_tx_desc - 1;
994 hns3_init_tx_queue_hw(txq);
998 hns3_init_tx_ring_tc(struct hns3_adapter *hns)
1000 struct hns3_hw *hw = &hns->hw;
1001 struct hns3_tx_queue *txq;
1004 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1005 struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i];
1008 if (!tc_queue->enable)
1011 for (j = 0; j < tc_queue->tqp_count; j++) {
1012 num = tc_queue->tqp_offset + j;
1013 txq = (struct hns3_tx_queue *)hw->data->tx_queues[num];
1017 hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc);
1023 hns3_init_rx_queues(struct hns3_adapter *hns)
1025 struct hns3_hw *hw = &hns->hw;
1026 struct hns3_rx_queue *rxq;
1030 /* Initialize RSS for queues */
1031 ret = hns3_config_rss(hns);
1033 hns3_err(hw, "failed to configure rss, ret = %d.", ret);
1037 for (i = 0; i < hw->data->nb_rx_queues; i++) {
1038 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i];
1040 hns3_err(hw, "Rx queue %u not available or setup.", i);
1044 if (rxq->rx_deferred_start)
1047 ret = hns3_init_rxq(hns, i);
1049 hns3_err(hw, "failed to init Rx queue %u, ret = %d.", i,
1055 for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++)
1056 hns3_init_fake_rxq(hns, i);
1061 for (j = 0; j < i; j++) {
1062 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j];
1063 hns3_rx_queue_release_mbufs(rxq);
1070 hns3_init_tx_queues(struct hns3_adapter *hns)
1072 struct hns3_hw *hw = &hns->hw;
1073 struct hns3_tx_queue *txq;
1076 for (i = 0; i < hw->data->nb_tx_queues; i++) {
1077 txq = (struct hns3_tx_queue *)hw->data->tx_queues[i];
1079 hns3_err(hw, "Tx queue %u not available or setup.", i);
1083 if (txq->tx_deferred_start)
1088 for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) {
1089 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i];
1092 hns3_init_tx_ring_tc(hns);
1099 * Note: just init and setup queues, and don't enable tqps.
1102 hns3_init_queues(struct hns3_adapter *hns, bool reset_queue)
1104 struct hns3_hw *hw = &hns->hw;
1108 ret = hns3_reset_all_tqps(hns);
1110 hns3_err(hw, "failed to reset all queues, ret = %d.",
1116 ret = hns3_init_rx_queues(hns);
1118 hns3_err(hw, "failed to init rx queues, ret = %d.", ret);
1122 ret = hns3_init_tx_queues(hns);
1124 hns3_dev_release_mbufs(hns);
1125 hns3_err(hw, "failed to init tx queues, ret = %d.", ret);
1132 hns3_start_tqps(struct hns3_hw *hw)
1134 struct hns3_tx_queue *txq;
1135 struct hns3_rx_queue *rxq;
1138 hns3_enable_all_queues(hw, true);
1140 for (i = 0; i < hw->data->nb_tx_queues; i++) {
1141 txq = hw->data->tx_queues[i];
1143 hw->data->tx_queue_state[i] =
1144 RTE_ETH_QUEUE_STATE_STARTED;
1147 for (i = 0; i < hw->data->nb_rx_queues; i++) {
1148 rxq = hw->data->rx_queues[i];
1150 hw->data->rx_queue_state[i] =
1151 RTE_ETH_QUEUE_STATE_STARTED;
1156 hns3_stop_tqps(struct hns3_hw *hw)
1160 hns3_enable_all_queues(hw, false);
1162 for (i = 0; i < hw->data->nb_tx_queues; i++)
1163 hw->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1165 for (i = 0; i < hw->data->nb_rx_queues; i++)
1166 hw->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1170 * Iterate over all Rx Queue, and call the callback() function for each Rx
1174 * The target eth dev.
1175 * @param[in] callback
1176 * The function to call for each queue.
1177 * if callback function return nonzero will stop iterate and return it's value
1179 * The arguments to provide the callback function with.
1182 * 0 on success, otherwise with errno set.
1185 hns3_rxq_iterate(struct rte_eth_dev *dev,
1186 int (*callback)(struct hns3_rx_queue *, void *), void *arg)
1191 if (dev->data->rx_queues == NULL)
1194 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1195 ret = callback(dev->data->rx_queues[i], arg);
1204 hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev,
1205 struct hns3_queue_info *q_info)
1207 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1208 const struct rte_memzone *rx_mz;
1209 struct hns3_rx_queue *rxq;
1210 unsigned int rx_desc;
1212 rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue),
1213 RTE_CACHE_LINE_SIZE, q_info->socket_id);
1215 hns3_err(hw, "Failed to allocate memory for No.%u rx ring!",
1220 /* Allocate rx ring hardware descriptors. */
1221 rxq->queue_id = q_info->idx;
1222 rxq->nb_rx_desc = q_info->nb_desc;
1225 * Allocate a litter more memory because rx vector functions
1226 * don't check boundaries each time.
1228 rx_desc = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
1229 sizeof(struct hns3_desc);
1230 rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
1231 rx_desc, HNS3_RING_BASE_ALIGN,
1233 if (rx_mz == NULL) {
1234 hns3_err(hw, "Failed to reserve DMA memory for No.%u rx ring!",
1236 hns3_rx_queue_release(rxq);
1240 rxq->rx_ring = (struct hns3_desc *)rx_mz->addr;
1241 rxq->rx_ring_phys_addr = rx_mz->iova;
1243 hns3_dbg(hw, "No.%u rx descriptors iova 0x%" PRIx64, q_info->idx,
1244 rxq->rx_ring_phys_addr);
1250 hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
1251 uint16_t nb_desc, unsigned int socket_id)
1253 struct hns3_adapter *hns = dev->data->dev_private;
1254 struct hns3_hw *hw = &hns->hw;
1255 struct hns3_queue_info q_info;
1256 struct hns3_rx_queue *rxq;
1259 if (hw->fkq_data.rx_queues[idx]) {
1260 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
1261 hw->fkq_data.rx_queues[idx] = NULL;
1265 q_info.socket_id = socket_id;
1266 q_info.nb_desc = nb_desc;
1267 q_info.type = "hns3 fake RX queue";
1268 q_info.ring_name = "rx_fake_ring";
1269 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1271 hns3_err(hw, "Failed to setup No.%u fake rx ring.", idx);
1275 /* Don't need alloc sw_ring, because upper applications don't use it */
1276 rxq->sw_ring = NULL;
1279 rxq->rx_deferred_start = false;
1280 rxq->port_id = dev->data->port_id;
1281 rxq->configured = true;
1282 nb_rx_q = dev->data->nb_rx_queues;
1283 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1284 (nb_rx_q + idx) * HNS3_TQP_REG_SIZE);
1285 rxq->rx_buf_len = HNS3_MIN_BD_BUF_SIZE;
1287 rte_spinlock_lock(&hw->lock);
1288 hw->fkq_data.rx_queues[idx] = rxq;
1289 rte_spinlock_unlock(&hw->lock);
1295 hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev,
1296 struct hns3_queue_info *q_info)
1298 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1299 const struct rte_memzone *tx_mz;
1300 struct hns3_tx_queue *txq;
1301 struct hns3_desc *desc;
1302 unsigned int tx_desc;
1305 txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue),
1306 RTE_CACHE_LINE_SIZE, q_info->socket_id);
1308 hns3_err(hw, "Failed to allocate memory for No.%u tx ring!",
1313 /* Allocate tx ring hardware descriptors. */
1314 txq->queue_id = q_info->idx;
1315 txq->nb_tx_desc = q_info->nb_desc;
1316 tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc);
1317 tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
1318 tx_desc, HNS3_RING_BASE_ALIGN,
1320 if (tx_mz == NULL) {
1321 hns3_err(hw, "Failed to reserve DMA memory for No.%u tx ring!",
1323 hns3_tx_queue_release(txq);
1327 txq->tx_ring = (struct hns3_desc *)tx_mz->addr;
1328 txq->tx_ring_phys_addr = tx_mz->iova;
1330 hns3_dbg(hw, "No.%u tx descriptors iova 0x%" PRIx64, q_info->idx,
1331 txq->tx_ring_phys_addr);
1334 desc = txq->tx_ring;
1335 for (i = 0; i < txq->nb_tx_desc; i++) {
1336 desc->tx.tp_fe_sc_vld_ra_ri = 0;
1344 hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
1345 uint16_t nb_desc, unsigned int socket_id)
1347 struct hns3_adapter *hns = dev->data->dev_private;
1348 struct hns3_hw *hw = &hns->hw;
1349 struct hns3_queue_info q_info;
1350 struct hns3_tx_queue *txq;
1353 if (hw->fkq_data.tx_queues[idx] != NULL) {
1354 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
1355 hw->fkq_data.tx_queues[idx] = NULL;
1359 q_info.socket_id = socket_id;
1360 q_info.nb_desc = nb_desc;
1361 q_info.type = "hns3 fake TX queue";
1362 q_info.ring_name = "tx_fake_ring";
1363 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
1365 hns3_err(hw, "Failed to setup No.%u fake tx ring.", idx);
1369 /* Don't need alloc sw_ring, because upper applications don't use it */
1370 txq->sw_ring = NULL;
1374 txq->tx_deferred_start = false;
1375 txq->port_id = dev->data->port_id;
1376 txq->configured = true;
1377 nb_tx_q = dev->data->nb_tx_queues;
1378 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1379 (nb_tx_q + idx) * HNS3_TQP_REG_SIZE);
1381 rte_spinlock_lock(&hw->lock);
1382 hw->fkq_data.tx_queues[idx] = txq;
1383 rte_spinlock_unlock(&hw->lock);
1389 hns3_fake_rx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1391 uint16_t old_nb_queues = hw->fkq_data.nb_fake_rx_queues;
1395 if (hw->fkq_data.rx_queues == NULL && nb_queues != 0) {
1396 /* first time configuration */
1398 size = sizeof(hw->fkq_data.rx_queues[0]) * nb_queues;
1399 hw->fkq_data.rx_queues = rte_zmalloc("fake_rx_queues", size,
1400 RTE_CACHE_LINE_SIZE);
1401 if (hw->fkq_data.rx_queues == NULL) {
1402 hw->fkq_data.nb_fake_rx_queues = 0;
1405 } else if (hw->fkq_data.rx_queues != NULL && nb_queues != 0) {
1407 rxq = hw->fkq_data.rx_queues;
1408 for (i = nb_queues; i < old_nb_queues; i++)
1409 hns3_dev_rx_queue_release(rxq[i]);
1411 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
1412 RTE_CACHE_LINE_SIZE);
1415 if (nb_queues > old_nb_queues) {
1416 uint16_t new_qs = nb_queues - old_nb_queues;
1417 memset(rxq + old_nb_queues, 0, sizeof(rxq[0]) * new_qs);
1420 hw->fkq_data.rx_queues = rxq;
1421 } else if (hw->fkq_data.rx_queues != NULL && nb_queues == 0) {
1422 rxq = hw->fkq_data.rx_queues;
1423 for (i = nb_queues; i < old_nb_queues; i++)
1424 hns3_dev_rx_queue_release(rxq[i]);
1426 rte_free(hw->fkq_data.rx_queues);
1427 hw->fkq_data.rx_queues = NULL;
1430 hw->fkq_data.nb_fake_rx_queues = nb_queues;
1436 hns3_fake_tx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1438 uint16_t old_nb_queues = hw->fkq_data.nb_fake_tx_queues;
1442 if (hw->fkq_data.tx_queues == NULL && nb_queues != 0) {
1443 /* first time configuration */
1445 size = sizeof(hw->fkq_data.tx_queues[0]) * nb_queues;
1446 hw->fkq_data.tx_queues = rte_zmalloc("fake_tx_queues", size,
1447 RTE_CACHE_LINE_SIZE);
1448 if (hw->fkq_data.tx_queues == NULL) {
1449 hw->fkq_data.nb_fake_tx_queues = 0;
1452 } else if (hw->fkq_data.tx_queues != NULL && nb_queues != 0) {
1454 txq = hw->fkq_data.tx_queues;
1455 for (i = nb_queues; i < old_nb_queues; i++)
1456 hns3_dev_tx_queue_release(txq[i]);
1457 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1458 RTE_CACHE_LINE_SIZE);
1461 if (nb_queues > old_nb_queues) {
1462 uint16_t new_qs = nb_queues - old_nb_queues;
1463 memset(txq + old_nb_queues, 0, sizeof(txq[0]) * new_qs);
1466 hw->fkq_data.tx_queues = txq;
1467 } else if (hw->fkq_data.tx_queues != NULL && nb_queues == 0) {
1468 txq = hw->fkq_data.tx_queues;
1469 for (i = nb_queues; i < old_nb_queues; i++)
1470 hns3_dev_tx_queue_release(txq[i]);
1472 rte_free(hw->fkq_data.tx_queues);
1473 hw->fkq_data.tx_queues = NULL;
1475 hw->fkq_data.nb_fake_tx_queues = nb_queues;
1481 hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
1484 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1485 uint16_t rx_need_add_nb_q;
1486 uint16_t tx_need_add_nb_q;
1491 /* Setup new number of fake RX/TX queues and reconfigure device. */
1492 rx_need_add_nb_q = hw->cfg_max_queues - nb_rx_q;
1493 tx_need_add_nb_q = hw->cfg_max_queues - nb_tx_q;
1494 ret = hns3_fake_rx_queue_config(hw, rx_need_add_nb_q);
1496 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1500 ret = hns3_fake_tx_queue_config(hw, tx_need_add_nb_q);
1502 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1503 goto cfg_fake_tx_q_fail;
1506 /* Allocate and set up fake RX queue per Ethernet port. */
1507 port_id = hw->data->port_id;
1508 for (q = 0; q < rx_need_add_nb_q; q++) {
1509 ret = hns3_fake_rx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1510 rte_eth_dev_socket_id(port_id));
1512 goto setup_fake_rx_q_fail;
1515 /* Allocate and set up fake TX queue per Ethernet port. */
1516 for (q = 0; q < tx_need_add_nb_q; q++) {
1517 ret = hns3_fake_tx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1518 rte_eth_dev_socket_id(port_id));
1520 goto setup_fake_tx_q_fail;
1525 setup_fake_tx_q_fail:
1526 setup_fake_rx_q_fail:
1527 (void)hns3_fake_tx_queue_config(hw, 0);
1529 (void)hns3_fake_rx_queue_config(hw, 0);
1535 hns3_dev_release_mbufs(struct hns3_adapter *hns)
1537 struct rte_eth_dev_data *dev_data = hns->hw.data;
1538 struct hns3_rx_queue *rxq;
1539 struct hns3_tx_queue *txq;
1542 if (dev_data->rx_queues)
1543 for (i = 0; i < dev_data->nb_rx_queues; i++) {
1544 rxq = dev_data->rx_queues[i];
1547 hns3_rx_queue_release_mbufs(rxq);
1550 if (dev_data->tx_queues)
1551 for (i = 0; i < dev_data->nb_tx_queues; i++) {
1552 txq = dev_data->tx_queues[i];
1555 hns3_tx_queue_release_mbufs(txq);
1560 hns3_rx_buf_len_calc(struct rte_mempool *mp, uint16_t *rx_buf_len)
1562 uint16_t vld_buf_size;
1563 uint16_t num_hw_specs;
1567 * hns3 network engine only support to set 4 typical specification, and
1568 * different buffer size will affect the max packet_len and the max
1569 * number of segmentation when hw gro is turned on in receive side. The
1570 * relationship between them is as follows:
1571 * rx_buf_size | max_gro_pkt_len | max_gro_nb_seg
1572 * ---------------------|-------------------|----------------
1573 * HNS3_4K_BD_BUF_SIZE | 60KB | 15
1574 * HNS3_2K_BD_BUF_SIZE | 62KB | 31
1575 * HNS3_1K_BD_BUF_SIZE | 63KB | 63
1576 * HNS3_512_BD_BUF_SIZE | 31.5KB | 63
1578 static const uint16_t hw_rx_buf_size[] = {
1579 HNS3_4K_BD_BUF_SIZE,
1580 HNS3_2K_BD_BUF_SIZE,
1581 HNS3_1K_BD_BUF_SIZE,
1582 HNS3_512_BD_BUF_SIZE
1585 vld_buf_size = (uint16_t)(rte_pktmbuf_data_room_size(mp) -
1586 RTE_PKTMBUF_HEADROOM);
1588 if (vld_buf_size < HNS3_MIN_BD_BUF_SIZE)
1591 num_hw_specs = RTE_DIM(hw_rx_buf_size);
1592 for (i = 0; i < num_hw_specs; i++) {
1593 if (vld_buf_size >= hw_rx_buf_size[i]) {
1594 *rx_buf_len = hw_rx_buf_size[i];
1602 hns3_rxq_conf_runtime_check(struct hns3_hw *hw, uint16_t buf_size,
1605 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1606 struct rte_eth_rxmode *rxmode = &hw->data->dev_conf.rxmode;
1607 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
1608 uint16_t min_vec_bds;
1611 * HNS3 hardware network engine set scattered as default. If the driver
1612 * is not work in scattered mode and the pkts greater than buf_size
1613 * but smaller than max_rx_pkt_len will be distributed to multiple BDs.
1614 * Driver cannot handle this situation.
1616 if (!hw->data->scattered_rx && rxmode->max_rx_pkt_len > buf_size) {
1617 hns3_err(hw, "max_rx_pkt_len is not allowed to be set greater "
1618 "than rx_buf_len if scattered is off.");
1622 if (pkt_burst == hns3_recv_pkts_vec) {
1623 min_vec_bds = HNS3_DEFAULT_RXQ_REARM_THRESH +
1624 HNS3_DEFAULT_RX_BURST;
1625 if (nb_desc < min_vec_bds ||
1626 nb_desc % HNS3_DEFAULT_RXQ_REARM_THRESH) {
1627 hns3_err(hw, "if Rx burst mode is vector, "
1628 "number of descriptor is required to be "
1629 "bigger than min vector bds:%u, and could be "
1630 "divided by rxq rearm thresh:%u.",
1631 min_vec_bds, HNS3_DEFAULT_RXQ_REARM_THRESH);
1639 hns3_rx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_rxconf *conf,
1640 struct rte_mempool *mp, uint16_t nb_desc,
1645 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1646 nb_desc % HNS3_ALIGN_RING_DESC) {
1647 hns3_err(hw, "Number (%u) of rx descriptors is invalid",
1652 if (conf->rx_drop_en == 0)
1653 hns3_warn(hw, "if no descriptors available, packets are always "
1654 "dropped and rx_drop_en (1) is fixed on");
1656 if (hns3_rx_buf_len_calc(mp, buf_size)) {
1657 hns3_err(hw, "rxq mbufs' data room size (%u) is not enough! "
1658 "minimal data room size (%u).",
1659 rte_pktmbuf_data_room_size(mp),
1660 HNS3_MIN_BD_BUF_SIZE + RTE_PKTMBUF_HEADROOM);
1664 if (hw->data->dev_started) {
1665 ret = hns3_rxq_conf_runtime_check(hw, *buf_size, nb_desc);
1667 hns3_err(hw, "Rx queue runtime setup fail.");
1676 hns3_get_tqp_reg_offset(uint16_t queue_id)
1678 uint32_t reg_offset;
1680 /* Need an extend offset to config queue > 1024 */
1681 if (queue_id < HNS3_MIN_EXTEND_QUEUE_ID)
1682 reg_offset = HNS3_TQP_REG_OFFSET + queue_id * HNS3_TQP_REG_SIZE;
1684 reg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_EXT_REG_OFFSET +
1685 (queue_id - HNS3_MIN_EXTEND_QUEUE_ID) *
1692 hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1693 unsigned int socket_id, const struct rte_eth_rxconf *conf,
1694 struct rte_mempool *mp)
1696 struct hns3_adapter *hns = dev->data->dev_private;
1697 struct hns3_hw *hw = &hns->hw;
1698 struct hns3_queue_info q_info;
1699 struct hns3_rx_queue *rxq;
1700 uint16_t rx_buf_size;
1704 ret = hns3_rx_queue_conf_check(hw, conf, mp, nb_desc, &rx_buf_size);
1708 if (dev->data->rx_queues[idx]) {
1709 hns3_rx_queue_release(dev->data->rx_queues[idx]);
1710 dev->data->rx_queues[idx] = NULL;
1714 q_info.socket_id = socket_id;
1715 q_info.nb_desc = nb_desc;
1716 q_info.type = "hns3 RX queue";
1717 q_info.ring_name = "rx_ring";
1719 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1722 "Failed to alloc mem and reserve DMA mem for rx ring!");
1727 rxq->ptype_tbl = &hns->ptype_tbl;
1729 rxq->rx_free_thresh = (conf->rx_free_thresh > 0) ?
1730 conf->rx_free_thresh : HNS3_DEFAULT_RX_FREE_THRESH;
1732 rxq->rx_deferred_start = conf->rx_deferred_start;
1733 if (rxq->rx_deferred_start && !hns3_dev_indep_txrx_supported(hw)) {
1734 hns3_warn(hw, "deferred start is not supported.");
1735 rxq->rx_deferred_start = false;
1738 rx_entry_len = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
1739 sizeof(struct hns3_entry);
1740 rxq->sw_ring = rte_zmalloc_socket("hns3 RX sw ring", rx_entry_len,
1741 RTE_CACHE_LINE_SIZE, socket_id);
1742 if (rxq->sw_ring == NULL) {
1743 hns3_err(hw, "Failed to allocate memory for rx sw ring!");
1744 hns3_rx_queue_release(rxq);
1748 rxq->next_to_use = 0;
1749 rxq->rx_free_hold = 0;
1750 rxq->rx_rearm_start = 0;
1751 rxq->rx_rearm_nb = 0;
1752 rxq->pkt_first_seg = NULL;
1753 rxq->pkt_last_seg = NULL;
1754 rxq->port_id = dev->data->port_id;
1756 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
1757 * the pvid_sw_discard_en in the queue struct should not be changed,
1758 * because PVID-related operations do not need to be processed by PMD
1759 * driver. For hns3 VF device, whether it needs to process PVID depends
1760 * on the configuration of PF kernel mode netdevice driver. And the
1761 * related PF configuration is delivered through the mailbox and finally
1762 * reflectd in port_base_vlan_cfg.
1764 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1765 rxq->pvid_sw_discard_en = hw->port_base_vlan_cfg.state ==
1766 HNS3_PORT_BASE_VLAN_ENABLE;
1768 rxq->pvid_sw_discard_en = false;
1769 rxq->configured = true;
1770 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1771 idx * HNS3_TQP_REG_SIZE);
1772 rxq->io_base = (void *)((char *)hw->io_base +
1773 hns3_get_tqp_reg_offset(idx));
1774 rxq->io_head_reg = (volatile void *)((char *)rxq->io_base +
1775 HNS3_RING_RX_HEAD_REG);
1776 rxq->rx_buf_len = rx_buf_size;
1778 rxq->pkt_len_errors = 0;
1779 rxq->l3_csum_errors = 0;
1780 rxq->l4_csum_errors = 0;
1781 rxq->ol3_csum_errors = 0;
1782 rxq->ol4_csum_errors = 0;
1784 /* CRC len set here is used for amending packet length */
1785 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1786 rxq->crc_len = RTE_ETHER_CRC_LEN;
1790 rxq->bulk_mbuf_num = 0;
1792 rte_spinlock_lock(&hw->lock);
1793 dev->data->rx_queues[idx] = rxq;
1794 rte_spinlock_unlock(&hw->lock);
1800 hns3_rx_scattered_reset(struct rte_eth_dev *dev)
1802 struct hns3_adapter *hns = dev->data->dev_private;
1803 struct hns3_hw *hw = &hns->hw;
1806 dev->data->scattered_rx = false;
1810 hns3_rx_scattered_calc(struct rte_eth_dev *dev)
1812 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1813 struct hns3_adapter *hns = dev->data->dev_private;
1814 struct hns3_hw *hw = &hns->hw;
1815 struct hns3_rx_queue *rxq;
1818 if (dev->data->rx_queues == NULL)
1821 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
1822 rxq = dev->data->rx_queues[queue_id];
1823 if (hw->rx_buf_len == 0)
1824 hw->rx_buf_len = rxq->rx_buf_len;
1826 hw->rx_buf_len = RTE_MIN(hw->rx_buf_len,
1830 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_SCATTER ||
1831 dev_conf->rxmode.max_rx_pkt_len > hw->rx_buf_len)
1832 dev->data->scattered_rx = true;
1836 hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1838 static const uint32_t ptypes[] = {
1840 RTE_PTYPE_L2_ETHER_VLAN,
1841 RTE_PTYPE_L2_ETHER_QINQ,
1842 RTE_PTYPE_L2_ETHER_LLDP,
1843 RTE_PTYPE_L2_ETHER_ARP,
1845 RTE_PTYPE_L3_IPV4_EXT,
1847 RTE_PTYPE_L3_IPV6_EXT,
1853 RTE_PTYPE_TUNNEL_GRE,
1854 RTE_PTYPE_INNER_L2_ETHER,
1855 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1856 RTE_PTYPE_INNER_L2_ETHER_QINQ,
1857 RTE_PTYPE_INNER_L3_IPV4,
1858 RTE_PTYPE_INNER_L3_IPV6,
1859 RTE_PTYPE_INNER_L3_IPV4_EXT,
1860 RTE_PTYPE_INNER_L3_IPV6_EXT,
1861 RTE_PTYPE_INNER_L4_UDP,
1862 RTE_PTYPE_INNER_L4_TCP,
1863 RTE_PTYPE_INNER_L4_SCTP,
1864 RTE_PTYPE_INNER_L4_ICMP,
1865 RTE_PTYPE_TUNNEL_VXLAN,
1866 RTE_PTYPE_TUNNEL_NVGRE,
1870 if (dev->rx_pkt_burst == hns3_recv_pkts ||
1871 dev->rx_pkt_burst == hns3_recv_scattered_pkts ||
1872 dev->rx_pkt_burst == hns3_recv_pkts_vec ||
1873 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve)
1880 hns3_init_non_tunnel_ptype_tbl(struct hns3_ptype_table *tbl)
1882 tbl->l2l3table[0][0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
1883 tbl->l2l3table[0][1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
1884 tbl->l2l3table[0][2] = RTE_PTYPE_L2_ETHER_ARP;
1885 tbl->l2l3table[0][3] = RTE_PTYPE_L2_ETHER;
1886 tbl->l2l3table[0][4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT;
1887 tbl->l2l3table[0][5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT;
1888 tbl->l2l3table[0][6] = RTE_PTYPE_L2_ETHER_LLDP;
1889 tbl->l2l3table[0][15] = RTE_PTYPE_L2_ETHER;
1891 tbl->l2l3table[1][0] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV4;
1892 tbl->l2l3table[1][1] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV6;
1893 tbl->l2l3table[1][2] = RTE_PTYPE_L2_ETHER_ARP;
1894 tbl->l2l3table[1][3] = RTE_PTYPE_L2_ETHER_VLAN;
1895 tbl->l2l3table[1][4] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV4_EXT;
1896 tbl->l2l3table[1][5] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV6_EXT;
1897 tbl->l2l3table[1][6] = RTE_PTYPE_L2_ETHER_LLDP;
1898 tbl->l2l3table[1][15] = RTE_PTYPE_L2_ETHER_VLAN;
1900 tbl->l2l3table[2][0] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV4;
1901 tbl->l2l3table[2][1] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV6;
1902 tbl->l2l3table[2][2] = RTE_PTYPE_L2_ETHER_ARP;
1903 tbl->l2l3table[2][3] = RTE_PTYPE_L2_ETHER_QINQ;
1904 tbl->l2l3table[2][4] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV4_EXT;
1905 tbl->l2l3table[2][5] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV6_EXT;
1906 tbl->l2l3table[2][6] = RTE_PTYPE_L2_ETHER_LLDP;
1907 tbl->l2l3table[2][15] = RTE_PTYPE_L2_ETHER_QINQ;
1909 tbl->l4table[0] = RTE_PTYPE_L4_UDP;
1910 tbl->l4table[1] = RTE_PTYPE_L4_TCP;
1911 tbl->l4table[2] = RTE_PTYPE_TUNNEL_GRE;
1912 tbl->l4table[3] = RTE_PTYPE_L4_SCTP;
1913 tbl->l4table[4] = RTE_PTYPE_L4_IGMP;
1914 tbl->l4table[5] = RTE_PTYPE_L4_ICMP;
1918 hns3_init_tunnel_ptype_tbl(struct hns3_ptype_table *tbl)
1920 tbl->inner_l2table[0] = RTE_PTYPE_INNER_L2_ETHER;
1921 tbl->inner_l2table[1] = RTE_PTYPE_INNER_L2_ETHER_VLAN;
1922 tbl->inner_l2table[2] = RTE_PTYPE_INNER_L2_ETHER_QINQ;
1924 tbl->inner_l3table[0] = RTE_PTYPE_INNER_L3_IPV4;
1925 tbl->inner_l3table[1] = RTE_PTYPE_INNER_L3_IPV6;
1926 /* There is not a ptype for inner ARP/RARP */
1927 tbl->inner_l3table[2] = RTE_PTYPE_UNKNOWN;
1928 tbl->inner_l3table[3] = RTE_PTYPE_UNKNOWN;
1929 tbl->inner_l3table[4] = RTE_PTYPE_INNER_L3_IPV4_EXT;
1930 tbl->inner_l3table[5] = RTE_PTYPE_INNER_L3_IPV6_EXT;
1932 tbl->inner_l4table[0] = RTE_PTYPE_INNER_L4_UDP;
1933 tbl->inner_l4table[1] = RTE_PTYPE_INNER_L4_TCP;
1934 /* There is not a ptype for inner GRE */
1935 tbl->inner_l4table[2] = RTE_PTYPE_UNKNOWN;
1936 tbl->inner_l4table[3] = RTE_PTYPE_INNER_L4_SCTP;
1937 /* There is not a ptype for inner IGMP */
1938 tbl->inner_l4table[4] = RTE_PTYPE_UNKNOWN;
1939 tbl->inner_l4table[5] = RTE_PTYPE_INNER_L4_ICMP;
1941 tbl->ol2table[0] = RTE_PTYPE_L2_ETHER;
1942 tbl->ol2table[1] = RTE_PTYPE_L2_ETHER_VLAN;
1943 tbl->ol2table[2] = RTE_PTYPE_L2_ETHER_QINQ;
1945 tbl->ol3table[0] = RTE_PTYPE_L3_IPV4;
1946 tbl->ol3table[1] = RTE_PTYPE_L3_IPV6;
1947 tbl->ol3table[2] = RTE_PTYPE_UNKNOWN;
1948 tbl->ol3table[3] = RTE_PTYPE_UNKNOWN;
1949 tbl->ol3table[4] = RTE_PTYPE_L3_IPV4_EXT;
1950 tbl->ol3table[5] = RTE_PTYPE_L3_IPV6_EXT;
1952 tbl->ol4table[0] = RTE_PTYPE_UNKNOWN;
1953 tbl->ol4table[1] = RTE_PTYPE_TUNNEL_VXLAN;
1954 tbl->ol4table[2] = RTE_PTYPE_TUNNEL_NVGRE;
1958 hns3_init_rx_ptype_tble(struct rte_eth_dev *dev)
1960 struct hns3_adapter *hns = dev->data->dev_private;
1961 struct hns3_ptype_table *tbl = &hns->ptype_tbl;
1963 memset(tbl, 0, sizeof(*tbl));
1965 hns3_init_non_tunnel_ptype_tbl(tbl);
1966 hns3_init_tunnel_ptype_tbl(tbl);
1970 hns3_rxd_to_vlan_tci(struct hns3_rx_queue *rxq, struct rte_mbuf *mb,
1971 uint32_t l234_info, const struct hns3_desc *rxd)
1973 #define HNS3_STRP_STATUS_NUM 0x4
1975 #define HNS3_NO_STRP_VLAN_VLD 0x0
1976 #define HNS3_INNER_STRP_VLAN_VLD 0x1
1977 #define HNS3_OUTER_STRP_VLAN_VLD 0x2
1978 uint32_t strip_status;
1979 uint32_t report_mode;
1982 * Since HW limitation, the vlan tag will always be inserted into RX
1983 * descriptor when strip the tag from packet, driver needs to determine
1984 * reporting which tag to mbuf according to the PVID configuration
1985 * and vlan striped status.
1987 static const uint32_t report_type[][HNS3_STRP_STATUS_NUM] = {
1989 HNS3_NO_STRP_VLAN_VLD,
1990 HNS3_OUTER_STRP_VLAN_VLD,
1991 HNS3_INNER_STRP_VLAN_VLD,
1992 HNS3_OUTER_STRP_VLAN_VLD
1995 HNS3_NO_STRP_VLAN_VLD,
1996 HNS3_NO_STRP_VLAN_VLD,
1997 HNS3_NO_STRP_VLAN_VLD,
1998 HNS3_INNER_STRP_VLAN_VLD
2001 strip_status = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,
2002 HNS3_RXD_STRP_TAGP_S);
2003 report_mode = report_type[rxq->pvid_sw_discard_en][strip_status];
2004 switch (report_mode) {
2005 case HNS3_NO_STRP_VLAN_VLD:
2008 case HNS3_INNER_STRP_VLAN_VLD:
2009 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2010 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.vlan_tag);
2012 case HNS3_OUTER_STRP_VLAN_VLD:
2013 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2014 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.ot_vlan_tag);
2023 recalculate_data_len(struct rte_mbuf *first_seg, struct rte_mbuf *last_seg,
2024 struct rte_mbuf *rxm, struct hns3_rx_queue *rxq,
2027 uint8_t crc_len = rxq->crc_len;
2029 if (data_len <= crc_len) {
2030 rte_pktmbuf_free_seg(rxm);
2031 first_seg->nb_segs--;
2032 last_seg->data_len = (uint16_t)(last_seg->data_len -
2033 (crc_len - data_len));
2034 last_seg->next = NULL;
2036 rxm->data_len = (uint16_t)(data_len - crc_len);
2039 static inline struct rte_mbuf *
2040 hns3_rx_alloc_buffer(struct hns3_rx_queue *rxq)
2044 if (likely(rxq->bulk_mbuf_num > 0))
2045 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
2047 ret = rte_mempool_get_bulk(rxq->mb_pool, (void **)rxq->bulk_mbuf,
2048 HNS3_BULK_ALLOC_MBUF_NUM);
2049 if (likely(ret == 0)) {
2050 rxq->bulk_mbuf_num = HNS3_BULK_ALLOC_MBUF_NUM;
2051 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
2053 return rte_mbuf_raw_alloc(rxq->mb_pool);
2057 hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2059 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
2060 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
2061 struct hns3_rx_queue *rxq; /* RX queue */
2062 struct hns3_entry *sw_ring;
2063 struct hns3_entry *rxe;
2064 struct hns3_desc rxd;
2065 struct rte_mbuf *nmb; /* pointer of the new mbuf */
2066 struct rte_mbuf *rxm;
2067 uint32_t bd_base_info;
2080 rx_ring = rxq->rx_ring;
2081 sw_ring = rxq->sw_ring;
2082 rx_id = rxq->next_to_use;
2084 while (nb_rx < nb_pkts) {
2085 rxdp = &rx_ring[rx_id];
2086 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
2087 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
2090 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2091 (1u << HNS3_RXD_VLD_B)];
2093 nmb = hns3_rx_alloc_buffer(rxq);
2094 if (unlikely(nmb == NULL)) {
2097 port_id = rxq->port_id;
2098 rte_eth_devices[port_id].data->rx_mbuf_alloc_failed++;
2103 rxe = &sw_ring[rx_id];
2105 if (unlikely(rx_id == rxq->nb_rx_desc))
2108 rte_prefetch0(sw_ring[rx_id].mbuf);
2109 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
2110 rte_prefetch0(&rx_ring[rx_id]);
2111 rte_prefetch0(&sw_ring[rx_id]);
2117 dma_addr = rte_mbuf_data_iova_default(nmb);
2118 rxdp->addr = rte_cpu_to_le_64(dma_addr);
2119 rxdp->rx.bd_base_info = 0;
2121 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2122 rxm->pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.pkt_len)) -
2124 rxm->data_len = rxm->pkt_len;
2125 rxm->port = rxq->port_id;
2126 rxm->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
2127 rxm->ol_flags = PKT_RX_RSS_HASH;
2128 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
2130 rte_le_to_cpu_16(rxd.rx.fd_id);
2131 rxm->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
2136 /* Load remained descriptor data and extract necessary fields */
2137 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
2138 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
2139 ret = hns3_handle_bdinfo(rxq, rxm, bd_base_info,
2140 l234_info, &cksum_err);
2144 rxm->packet_type = hns3_rx_calc_ptype(rxq, l234_info, ol_info);
2146 if (likely(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
2147 hns3_rx_set_cksum_flag(rxm, rxm->packet_type,
2149 hns3_rxd_to_vlan_tci(rxq, rxm, l234_info, &rxd);
2151 rx_pkts[nb_rx++] = rxm;
2154 rte_pktmbuf_free(rxm);
2157 rxq->next_to_use = rx_id;
2158 rxq->rx_free_hold += nb_rx_bd;
2159 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
2160 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
2161 rxq->rx_free_hold = 0;
2168 hns3_recv_scattered_pkts(void *rx_queue,
2169 struct rte_mbuf **rx_pkts,
2172 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
2173 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
2174 struct hns3_rx_queue *rxq; /* RX queue */
2175 struct hns3_entry *sw_ring;
2176 struct hns3_entry *rxe;
2177 struct rte_mbuf *first_seg;
2178 struct rte_mbuf *last_seg;
2179 struct hns3_desc rxd;
2180 struct rte_mbuf *nmb; /* pointer of the new mbuf */
2181 struct rte_mbuf *rxm;
2182 struct rte_eth_dev *dev;
2183 uint32_t bd_base_info;
2198 rx_id = rxq->next_to_use;
2199 rx_ring = rxq->rx_ring;
2200 sw_ring = rxq->sw_ring;
2201 first_seg = rxq->pkt_first_seg;
2202 last_seg = rxq->pkt_last_seg;
2204 while (nb_rx < nb_pkts) {
2205 rxdp = &rx_ring[rx_id];
2206 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
2207 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
2211 * The interactive process between software and hardware of
2212 * receiving a new packet in hns3 network engine:
2213 * 1. Hardware network engine firstly writes the packet content
2214 * to the memory pointed by the 'addr' field of the Rx Buffer
2215 * Descriptor, secondly fills the result of parsing the
2216 * packet include the valid field into the Rx Buffer
2217 * Descriptor in one write operation.
2218 * 2. Driver reads the Rx BD's valid field in the loop to check
2219 * whether it's valid, if valid then assign a new address to
2220 * the addr field, clear the valid field, get the other
2221 * information of the packet by parsing Rx BD's other fields,
2222 * finally write back the number of Rx BDs processed by the
2223 * driver to the HNS3_RING_RX_HEAD_REG register to inform
2225 * In the above process, the ordering is very important. We must
2226 * make sure that CPU read Rx BD's other fields only after the
2229 * There are two type of re-ordering: compiler re-ordering and
2230 * CPU re-ordering under the ARMv8 architecture.
2231 * 1. we use volatile to deal with compiler re-ordering, so you
2232 * can see that rx_ring/rxdp defined with volatile.
2233 * 2. we commonly use memory barrier to deal with CPU
2234 * re-ordering, but the cost is high.
2236 * In order to solve the high cost of using memory barrier, we
2237 * use the data dependency order under the ARMv8 architecture,
2240 * instr02: load B <- A
2241 * the instr02 will always execute after instr01.
2243 * To construct the data dependency ordering, we use the
2244 * following assignment:
2245 * rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2246 * (1u<<HNS3_RXD_VLD_B)]
2247 * Using gcc compiler under the ARMv8 architecture, the related
2248 * assembly code example as follows:
2249 * note: (1u << HNS3_RXD_VLD_B) equal 0x10
2250 * instr01: ldr w26, [x22, #28] --read bd_base_info
2251 * instr02: and w0, w26, #0x10 --calc bd_base_info & 0x10
2252 * instr03: sub w0, w0, #0x10 --calc (bd_base_info &
2254 * instr04: add x0, x22, x0, lsl #5 --calc copy source addr
2255 * instr05: ldp x2, x3, [x0]
2256 * instr06: stp x2, x3, [x29, #256] --copy BD's [0 ~ 15]B
2257 * instr07: ldp x4, x5, [x0, #16]
2258 * instr08: stp x4, x5, [x29, #272] --copy BD's [16 ~ 31]B
2259 * the instr05~08 depend on x0's value, x0 depent on w26's
2260 * value, the w26 is the bd_base_info, this form the data
2261 * dependency ordering.
2262 * note: if BD is valid, (bd_base_info & (1u<<HNS3_RXD_VLD_B)) -
2263 * (1u<<HNS3_RXD_VLD_B) will always zero, so the
2264 * assignment is correct.
2266 * So we use the data dependency ordering instead of memory
2267 * barrier to improve receive performance.
2269 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2270 (1u << HNS3_RXD_VLD_B)];
2272 nmb = hns3_rx_alloc_buffer(rxq);
2273 if (unlikely(nmb == NULL)) {
2274 dev = &rte_eth_devices[rxq->port_id];
2275 dev->data->rx_mbuf_alloc_failed++;
2280 rxe = &sw_ring[rx_id];
2282 if (unlikely(rx_id == rxq->nb_rx_desc))
2285 rte_prefetch0(sw_ring[rx_id].mbuf);
2286 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
2287 rte_prefetch0(&rx_ring[rx_id]);
2288 rte_prefetch0(&sw_ring[rx_id]);
2294 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2295 rxdp->rx.bd_base_info = 0;
2296 rxdp->addr = dma_addr;
2298 if (first_seg == NULL) {
2300 first_seg->nb_segs = 1;
2302 first_seg->nb_segs++;
2303 last_seg->next = rxm;
2306 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2307 rxm->data_len = rte_le_to_cpu_16(rxd.rx.size);
2309 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
2316 * The last buffer of the received packet. packet len from
2317 * buffer description may contains CRC len, packet len should
2318 * subtract it, same as data len.
2320 first_seg->pkt_len = rte_le_to_cpu_16(rxd.rx.pkt_len);
2323 * This is the last buffer of the received packet. If the CRC
2324 * is not stripped by the hardware:
2325 * - Subtract the CRC length from the total packet length.
2326 * - If the last buffer only contains the whole CRC or a part
2327 * of it, free the mbuf associated to the last buffer. If part
2328 * of the CRC is also contained in the previous mbuf, subtract
2329 * the length of that CRC part from the data length of the
2333 if (unlikely(rxq->crc_len > 0)) {
2334 first_seg->pkt_len -= rxq->crc_len;
2335 recalculate_data_len(first_seg, last_seg, rxm, rxq,
2339 first_seg->port = rxq->port_id;
2340 first_seg->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
2341 first_seg->ol_flags = PKT_RX_RSS_HASH;
2342 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
2343 first_seg->hash.fdir.hi =
2344 rte_le_to_cpu_16(rxd.rx.fd_id);
2345 first_seg->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
2348 gro_size = hns3_get_field(bd_base_info, HNS3_RXD_GRO_SIZE_M,
2349 HNS3_RXD_GRO_SIZE_S);
2350 if (gro_size != 0) {
2351 first_seg->ol_flags |= PKT_RX_LRO;
2352 first_seg->tso_segsz = gro_size;
2355 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
2356 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
2357 ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info,
2358 l234_info, &cksum_err);
2362 first_seg->packet_type = hns3_rx_calc_ptype(rxq,
2363 l234_info, ol_info);
2365 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B))
2366 hns3_rx_set_cksum_flag(first_seg,
2367 first_seg->packet_type,
2369 hns3_rxd_to_vlan_tci(rxq, first_seg, l234_info, &rxd);
2371 rx_pkts[nb_rx++] = first_seg;
2375 rte_pktmbuf_free(first_seg);
2379 rxq->next_to_use = rx_id;
2380 rxq->pkt_first_seg = first_seg;
2381 rxq->pkt_last_seg = last_seg;
2383 rxq->rx_free_hold += nb_rx_bd;
2384 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
2385 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
2386 rxq->rx_free_hold = 0;
2393 hns3_rxq_vec_setup(__rte_unused struct hns3_rx_queue *rxq)
2398 hns3_rx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
2404 hns3_recv_pkts_vec(__rte_unused void *tx_queue,
2405 __rte_unused struct rte_mbuf **rx_pkts,
2406 __rte_unused uint16_t nb_pkts)
2412 hns3_recv_pkts_vec_sve(__rte_unused void *tx_queue,
2413 __rte_unused struct rte_mbuf **rx_pkts,
2414 __rte_unused uint16_t nb_pkts)
2420 hns3_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2421 struct rte_eth_burst_mode *mode)
2423 static const struct {
2424 eth_rx_burst_t pkt_burst;
2427 { hns3_recv_pkts, "Scalar" },
2428 { hns3_recv_scattered_pkts, "Scalar Scattered" },
2429 { hns3_recv_pkts_vec, "Vector Neon" },
2430 { hns3_recv_pkts_vec_sve, "Vector Sve" },
2433 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2437 for (i = 0; i < RTE_DIM(burst_infos); i++) {
2438 if (pkt_burst == burst_infos[i].pkt_burst) {
2439 snprintf(mode->info, sizeof(mode->info), "%s",
2440 burst_infos[i].info);
2450 hns3_check_sve_support(void)
2452 #if defined(RTE_ARCH_ARM64) && defined(CC_SVE_SUPPORT)
2453 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE))
2459 static eth_rx_burst_t
2460 hns3_get_rx_function(struct rte_eth_dev *dev)
2462 struct hns3_adapter *hns = dev->data->dev_private;
2463 uint64_t offloads = dev->data->dev_conf.rxmode.offloads;
2465 if (hns->rx_vec_allowed && hns3_rx_check_vec_support(dev) == 0)
2466 return hns3_check_sve_support() ? hns3_recv_pkts_vec_sve :
2469 if (hns->rx_simple_allowed && !dev->data->scattered_rx &&
2470 (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0)
2471 return hns3_recv_pkts;
2473 return hns3_recv_scattered_pkts;
2477 hns3_tx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_txconf *conf,
2478 uint16_t nb_desc, uint16_t *tx_rs_thresh,
2479 uint16_t *tx_free_thresh, uint16_t idx)
2481 #define HNS3_TX_RS_FREE_THRESH_GAP 8
2482 uint16_t rs_thresh, free_thresh, fast_free_thresh;
2484 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
2485 nb_desc % HNS3_ALIGN_RING_DESC) {
2486 hns3_err(hw, "number (%u) of tx descriptors is invalid",
2491 rs_thresh = (conf->tx_rs_thresh > 0) ?
2492 conf->tx_rs_thresh : HNS3_DEFAULT_TX_RS_THRESH;
2493 free_thresh = (conf->tx_free_thresh > 0) ?
2494 conf->tx_free_thresh : HNS3_DEFAULT_TX_FREE_THRESH;
2495 if (rs_thresh + free_thresh > nb_desc || nb_desc % rs_thresh ||
2496 rs_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP ||
2497 free_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP) {
2498 hns3_err(hw, "tx_rs_thresh (%u) tx_free_thresh (%u) nb_desc "
2499 "(%u) of tx descriptors for port=%u queue=%u check "
2501 rs_thresh, free_thresh, nb_desc, hw->data->port_id,
2506 if (conf->tx_free_thresh == 0) {
2507 /* Fast free Tx memory buffer to improve cache hit rate */
2508 fast_free_thresh = nb_desc - rs_thresh;
2509 if (fast_free_thresh >=
2510 HNS3_TX_FAST_FREE_AHEAD + HNS3_DEFAULT_TX_FREE_THRESH)
2511 free_thresh = fast_free_thresh -
2512 HNS3_TX_FAST_FREE_AHEAD;
2515 *tx_rs_thresh = rs_thresh;
2516 *tx_free_thresh = free_thresh;
2521 hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
2522 unsigned int socket_id, const struct rte_eth_txconf *conf)
2524 struct hns3_adapter *hns = dev->data->dev_private;
2525 uint16_t tx_rs_thresh, tx_free_thresh;
2526 struct hns3_hw *hw = &hns->hw;
2527 struct hns3_queue_info q_info;
2528 struct hns3_tx_queue *txq;
2532 ret = hns3_tx_queue_conf_check(hw, conf, nb_desc,
2533 &tx_rs_thresh, &tx_free_thresh, idx);
2537 if (dev->data->tx_queues[idx] != NULL) {
2538 hns3_tx_queue_release(dev->data->tx_queues[idx]);
2539 dev->data->tx_queues[idx] = NULL;
2543 q_info.socket_id = socket_id;
2544 q_info.nb_desc = nb_desc;
2545 q_info.type = "hns3 TX queue";
2546 q_info.ring_name = "tx_ring";
2547 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
2550 "Failed to alloc mem and reserve DMA mem for tx ring!");
2554 txq->tx_deferred_start = conf->tx_deferred_start;
2555 if (txq->tx_deferred_start && !hns3_dev_indep_txrx_supported(hw)) {
2556 hns3_warn(hw, "deferred start is not supported.");
2557 txq->tx_deferred_start = false;
2560 tx_entry_len = sizeof(struct hns3_entry) * txq->nb_tx_desc;
2561 txq->sw_ring = rte_zmalloc_socket("hns3 TX sw ring", tx_entry_len,
2562 RTE_CACHE_LINE_SIZE, socket_id);
2563 if (txq->sw_ring == NULL) {
2564 hns3_err(hw, "Failed to allocate memory for tx sw ring!");
2565 hns3_tx_queue_release(txq);
2570 txq->next_to_use = 0;
2571 txq->next_to_clean = 0;
2572 txq->tx_bd_ready = txq->nb_tx_desc - 1;
2573 txq->tx_free_thresh = tx_free_thresh;
2574 txq->tx_rs_thresh = tx_rs_thresh;
2575 txq->free = rte_zmalloc_socket("hns3 TX mbuf free array",
2576 sizeof(struct rte_mbuf *) * txq->tx_rs_thresh,
2577 RTE_CACHE_LINE_SIZE, socket_id);
2579 hns3_err(hw, "failed to allocate tx mbuf free array!");
2580 hns3_tx_queue_release(txq);
2584 txq->port_id = dev->data->port_id;
2586 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
2587 * the pvid_sw_shift_en in the queue struct should not be changed,
2588 * because PVID-related operations do not need to be processed by PMD
2589 * driver. For hns3 VF device, whether it needs to process PVID depends
2590 * on the configuration of PF kernel mode netdev driver. And the
2591 * related PF configuration is delivered through the mailbox and finally
2592 * reflectd in port_base_vlan_cfg.
2594 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
2595 txq->pvid_sw_shift_en = hw->port_base_vlan_cfg.state ==
2596 HNS3_PORT_BASE_VLAN_ENABLE;
2598 txq->pvid_sw_shift_en = false;
2599 txq->max_non_tso_bd_num = hw->max_non_tso_bd_num;
2600 txq->configured = true;
2601 txq->io_base = (void *)((char *)hw->io_base +
2602 hns3_get_tqp_reg_offset(idx));
2603 txq->io_tail_reg = (volatile void *)((char *)txq->io_base +
2604 HNS3_RING_TX_TAIL_REG);
2605 txq->min_tx_pkt_len = hw->min_tx_pkt_len;
2606 txq->tso_mode = hw->tso_mode;
2607 txq->over_length_pkt_cnt = 0;
2608 txq->exceed_limit_bd_pkt_cnt = 0;
2609 txq->exceed_limit_bd_reassem_fail = 0;
2610 txq->unsupported_tunnel_pkt_cnt = 0;
2611 txq->queue_full_cnt = 0;
2612 txq->pkt_padding_fail_cnt = 0;
2613 rte_spinlock_lock(&hw->lock);
2614 dev->data->tx_queues[idx] = txq;
2615 rte_spinlock_unlock(&hw->lock);
2621 hns3_tx_free_useless_buffer(struct hns3_tx_queue *txq)
2623 uint16_t tx_next_clean = txq->next_to_clean;
2624 uint16_t tx_next_use = txq->next_to_use;
2625 uint16_t tx_bd_ready = txq->tx_bd_ready;
2626 uint16_t tx_bd_max = txq->nb_tx_desc;
2627 struct hns3_entry *tx_bak_pkt = &txq->sw_ring[tx_next_clean];
2628 struct hns3_desc *desc = &txq->tx_ring[tx_next_clean];
2629 struct rte_mbuf *mbuf;
2631 while ((!(desc->tx.tp_fe_sc_vld_ra_ri &
2632 rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)))) &&
2633 tx_next_use != tx_next_clean) {
2634 mbuf = tx_bak_pkt->mbuf;
2636 rte_pktmbuf_free_seg(mbuf);
2637 tx_bak_pkt->mbuf = NULL;
2645 if (tx_next_clean >= tx_bd_max) {
2647 desc = txq->tx_ring;
2648 tx_bak_pkt = txq->sw_ring;
2652 txq->next_to_clean = tx_next_clean;
2653 txq->tx_bd_ready = tx_bd_ready;
2657 hns3_config_gro(struct hns3_hw *hw, bool en)
2659 struct hns3_cfg_gro_status_cmd *req;
2660 struct hns3_cmd_desc desc;
2663 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
2664 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
2666 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
2668 ret = hns3_cmd_send(hw, &desc, 1);
2670 hns3_err(hw, "%s hardware GRO failed, ret = %d",
2671 en ? "enable" : "disable", ret);
2677 hns3_restore_gro_conf(struct hns3_hw *hw)
2683 offloads = hw->data->dev_conf.rxmode.offloads;
2684 gro_en = offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2685 ret = hns3_config_gro(hw, gro_en);
2687 hns3_err(hw, "restore hardware GRO to %s failed, ret = %d",
2688 gro_en ? "enabled" : "disabled", ret);
2694 hns3_pkt_is_tso(struct rte_mbuf *m)
2696 return (m->tso_segsz != 0 && m->ol_flags & PKT_TX_TCP_SEG);
2700 hns3_set_tso(struct hns3_desc *desc, uint32_t paylen, struct rte_mbuf *rxm)
2702 if (!hns3_pkt_is_tso(rxm))
2705 if (paylen <= rxm->tso_segsz)
2708 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(BIT(HNS3_TXD_TSO_B));
2709 desc->tx.mss = rte_cpu_to_le_16(rxm->tso_segsz);
2713 hns3_fill_per_desc(struct hns3_desc *desc, struct rte_mbuf *rxm)
2715 desc->addr = rte_mbuf_data_iova(rxm);
2716 desc->tx.send_size = rte_cpu_to_le_16(rte_pktmbuf_data_len(rxm));
2717 desc->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B));
2721 hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc,
2722 struct rte_mbuf *rxm)
2724 uint64_t ol_flags = rxm->ol_flags;
2728 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len;
2729 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
2730 rxm->outer_l2_len + rxm->outer_l3_len : 0;
2731 paylen = rxm->pkt_len - hdr_len;
2732 desc->tx.paylen = rte_cpu_to_le_32(paylen);
2733 hns3_set_tso(desc, paylen, rxm);
2736 * Currently, hardware doesn't support more than two layers VLAN offload
2737 * in Tx direction based on hns3 network engine. So when the number of
2738 * VLANs in the packets represented by rxm plus the number of VLAN
2739 * offload by hardware such as PVID etc, exceeds two, the packets will
2740 * be discarded or the original VLAN of the packets will be overwitted
2741 * by hardware. When the PF PVID is enabled by calling the API function
2742 * named rte_eth_dev_set_vlan_pvid or the VF PVID is enabled by the hns3
2743 * PF kernel ether driver, the outer VLAN tag will always be the PVID.
2744 * To avoid the VLAN of Tx descriptor is overwritten by PVID, it should
2745 * be added to the position close to the IP header when PVID is enabled.
2747 if (!txq->pvid_sw_shift_en && ol_flags & (PKT_TX_VLAN_PKT |
2749 desc->tx.ol_type_vlan_len_msec |=
2750 rte_cpu_to_le_32(BIT(HNS3_TXD_OVLAN_B));
2751 if (ol_flags & PKT_TX_QINQ_PKT)
2752 desc->tx.outer_vlan_tag =
2753 rte_cpu_to_le_16(rxm->vlan_tci_outer);
2755 desc->tx.outer_vlan_tag =
2756 rte_cpu_to_le_16(rxm->vlan_tci);
2759 if (ol_flags & PKT_TX_QINQ_PKT ||
2760 ((ol_flags & PKT_TX_VLAN_PKT) && txq->pvid_sw_shift_en)) {
2761 desc->tx.type_cs_vlan_tso_len |=
2762 rte_cpu_to_le_32(BIT(HNS3_TXD_VLAN_B));
2763 desc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci);
2768 hns3_tx_alloc_mbufs(struct rte_mempool *mb_pool, uint16_t nb_new_buf,
2769 struct rte_mbuf **alloc_mbuf)
2771 #define MAX_NON_TSO_BD_PER_PKT 18
2772 struct rte_mbuf *pkt_segs[MAX_NON_TSO_BD_PER_PKT];
2775 /* Allocate enough mbufs */
2776 if (rte_mempool_get_bulk(mb_pool, (void **)pkt_segs, nb_new_buf))
2779 for (i = 0; i < nb_new_buf - 1; i++)
2780 pkt_segs[i]->next = pkt_segs[i + 1];
2782 pkt_segs[nb_new_buf - 1]->next = NULL;
2783 pkt_segs[0]->nb_segs = nb_new_buf;
2784 *alloc_mbuf = pkt_segs[0];
2790 hns3_pktmbuf_copy_hdr(struct rte_mbuf *new_pkt, struct rte_mbuf *old_pkt)
2792 new_pkt->ol_flags = old_pkt->ol_flags;
2793 new_pkt->pkt_len = rte_pktmbuf_pkt_len(old_pkt);
2794 new_pkt->outer_l2_len = old_pkt->outer_l2_len;
2795 new_pkt->outer_l3_len = old_pkt->outer_l3_len;
2796 new_pkt->l2_len = old_pkt->l2_len;
2797 new_pkt->l3_len = old_pkt->l3_len;
2798 new_pkt->l4_len = old_pkt->l4_len;
2799 new_pkt->vlan_tci_outer = old_pkt->vlan_tci_outer;
2800 new_pkt->vlan_tci = old_pkt->vlan_tci;
2804 hns3_reassemble_tx_pkts(struct rte_mbuf *tx_pkt, struct rte_mbuf **new_pkt,
2805 uint8_t max_non_tso_bd_num)
2807 struct rte_mempool *mb_pool;
2808 struct rte_mbuf *new_mbuf;
2809 struct rte_mbuf *temp_new;
2810 struct rte_mbuf *temp;
2811 uint16_t last_buf_len;
2812 uint16_t nb_new_buf;
2822 mb_pool = tx_pkt->pool;
2823 buf_size = tx_pkt->buf_len - RTE_PKTMBUF_HEADROOM;
2824 nb_new_buf = (rte_pktmbuf_pkt_len(tx_pkt) - 1) / buf_size + 1;
2825 if (nb_new_buf > max_non_tso_bd_num)
2828 last_buf_len = rte_pktmbuf_pkt_len(tx_pkt) % buf_size;
2829 if (last_buf_len == 0)
2830 last_buf_len = buf_size;
2832 /* Allocate enough mbufs */
2833 ret = hns3_tx_alloc_mbufs(mb_pool, nb_new_buf, &new_mbuf);
2837 /* Copy the original packet content to the new mbufs */
2839 s = rte_pktmbuf_mtod(temp, char *);
2840 len_s = rte_pktmbuf_data_len(temp);
2841 temp_new = new_mbuf;
2842 while (temp != NULL && temp_new != NULL) {
2843 d = rte_pktmbuf_mtod(temp_new, char *);
2844 buf_len = temp_new->next == NULL ? last_buf_len : buf_size;
2848 len = RTE_MIN(len_s, len_d);
2852 len_d = len_d - len;
2853 len_s = len_s - len;
2859 s = rte_pktmbuf_mtod(temp, char *);
2860 len_s = rte_pktmbuf_data_len(temp);
2864 temp_new->data_len = buf_len;
2865 temp_new = temp_new->next;
2867 hns3_pktmbuf_copy_hdr(new_mbuf, tx_pkt);
2869 /* free original mbufs */
2870 rte_pktmbuf_free(tx_pkt);
2872 *new_pkt = new_mbuf;
2878 hns3_parse_outer_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec)
2880 uint32_t tmp = *ol_type_vlan_len_msec;
2881 uint64_t ol_flags = m->ol_flags;
2883 /* (outer) IP header type */
2884 if (ol_flags & PKT_TX_OUTER_IPV4) {
2885 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2886 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M,
2887 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_CSUM);
2889 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M,
2890 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_NO_CSUM);
2891 } else if (ol_flags & PKT_TX_OUTER_IPV6) {
2892 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
2895 /* OL3 header size, defined in 4 bytes */
2896 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2897 m->outer_l3_len >> HNS3_L3_LEN_UNIT);
2898 *ol_type_vlan_len_msec = tmp;
2902 hns3_parse_inner_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec,
2903 uint32_t *type_cs_vlan_tso_len)
2905 #define HNS3_NVGRE_HLEN 8
2906 uint32_t tmp_outer = *ol_type_vlan_len_msec;
2907 uint32_t tmp_inner = *type_cs_vlan_tso_len;
2908 uint64_t ol_flags = m->ol_flags;
2909 uint16_t inner_l2_len;
2911 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2912 case PKT_TX_TUNNEL_VXLAN_GPE:
2913 case PKT_TX_TUNNEL_GENEVE:
2914 case PKT_TX_TUNNEL_VXLAN:
2915 /* MAC in UDP tunnelling packet, include VxLAN and GENEVE */
2916 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M,
2917 HNS3_TXD_TUNTYPE_S, HNS3_TUN_MAC_IN_UDP);
2919 * The inner l2 length of mbuf is the sum of outer l4 length,
2920 * tunneling header length and inner l2 length for a tunnel
2921 * packect. But in hns3 tx descriptor, the tunneling header
2922 * length is contained in the field of outer L4 length.
2923 * Therefore, driver need to calculate the outer L4 length and
2926 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M,
2928 (uint8_t)RTE_ETHER_VXLAN_HLEN >>
2931 inner_l2_len = m->l2_len - RTE_ETHER_VXLAN_HLEN;
2933 case PKT_TX_TUNNEL_GRE:
2934 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M,
2935 HNS3_TXD_TUNTYPE_S, HNS3_TUN_NVGRE);
2937 * For NVGRE tunnel packect, the outer L4 is empty. So only
2938 * fill the NVGRE header length to the outer L4 field.
2940 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M,
2942 (uint8_t)HNS3_NVGRE_HLEN >> HNS3_L4_LEN_UNIT);
2944 inner_l2_len = m->l2_len - HNS3_NVGRE_HLEN;
2947 /* For non UDP / GRE tunneling, drop the tunnel packet */
2951 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2952 inner_l2_len >> HNS3_L2_LEN_UNIT);
2953 /* OL2 header size, defined in 2 bytes */
2954 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2955 m->outer_l2_len >> HNS3_L2_LEN_UNIT);
2957 *type_cs_vlan_tso_len = tmp_inner;
2958 *ol_type_vlan_len_msec = tmp_outer;
2964 hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m,
2965 uint16_t tx_desc_id)
2967 struct hns3_desc *tx_ring = txq->tx_ring;
2968 struct hns3_desc *desc = &tx_ring[tx_desc_id];
2969 uint32_t tmp_outer = 0;
2970 uint32_t tmp_inner = 0;
2974 * The tunnel header is contained in the inner L2 header field of the
2975 * mbuf, but for hns3 descriptor, it is contained in the outer L4. So,
2976 * there is a need that switching between them. To avoid multiple
2977 * calculations, the length of the L2 header include the outer and
2978 * inner, will be filled during the parsing of tunnel packects.
2980 if (!(m->ol_flags & PKT_TX_TUNNEL_MASK)) {
2982 * For non tunnel type the tunnel type id is 0, so no need to
2983 * assign a value to it. Only the inner(normal) L2 header length
2986 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M,
2987 HNS3_TXD_L2LEN_S, m->l2_len >> HNS3_L2_LEN_UNIT);
2990 * If outer csum is not offload, the outer length may be filled
2991 * with 0. And the length of the outer header is added to the
2992 * inner l2_len. It would lead a cksum error. So driver has to
2993 * calculate the header length.
2995 if (unlikely(!(m->ol_flags & PKT_TX_OUTER_IP_CKSUM) &&
2996 m->outer_l2_len == 0)) {
2997 struct rte_net_hdr_lens hdr_len;
2998 (void)rte_net_get_ptype(m, &hdr_len,
2999 RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK);
3000 m->outer_l3_len = hdr_len.l3_len;
3001 m->outer_l2_len = hdr_len.l2_len;
3002 m->l2_len = m->l2_len - hdr_len.l2_len - hdr_len.l3_len;
3004 hns3_parse_outer_params(m, &tmp_outer);
3005 ret = hns3_parse_inner_params(m, &tmp_outer, &tmp_inner);
3010 desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp_outer);
3011 desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp_inner);
3017 hns3_parse_l3_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len)
3019 uint64_t ol_flags = m->ol_flags;
3023 tmp = *type_cs_vlan_tso_len;
3024 if (ol_flags & PKT_TX_IPV4)
3025 l3_type = HNS3_L3T_IPV4;
3026 else if (ol_flags & PKT_TX_IPV6)
3027 l3_type = HNS3_L3T_IPV6;
3029 l3_type = HNS3_L3T_NONE;
3031 /* inner(/normal) L3 header size, defined in 4 bytes */
3032 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
3033 m->l3_len >> HNS3_L3_LEN_UNIT);
3035 tmp |= hns3_gen_field_val(HNS3_TXD_L3T_M, HNS3_TXD_L3T_S, l3_type);
3037 /* Enable L3 checksum offloads */
3038 if (ol_flags & PKT_TX_IP_CKSUM)
3039 tmp |= BIT(HNS3_TXD_L3CS_B);
3040 *type_cs_vlan_tso_len = tmp;
3044 hns3_parse_l4_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len)
3046 uint64_t ol_flags = m->ol_flags;
3048 /* Enable L4 checksum offloads */
3049 switch (ol_flags & (PKT_TX_L4_MASK | PKT_TX_TCP_SEG)) {
3050 case PKT_TX_TCP_CKSUM:
3051 case PKT_TX_TCP_SEG:
3052 tmp = *type_cs_vlan_tso_len;
3053 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3056 case PKT_TX_UDP_CKSUM:
3057 tmp = *type_cs_vlan_tso_len;
3058 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3061 case PKT_TX_SCTP_CKSUM:
3062 tmp = *type_cs_vlan_tso_len;
3063 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3069 tmp |= BIT(HNS3_TXD_L4CS_B);
3070 tmp |= hns3_gen_field_val(HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
3071 m->l4_len >> HNS3_L4_LEN_UNIT);
3072 *type_cs_vlan_tso_len = tmp;
3076 hns3_txd_enable_checksum(struct hns3_tx_queue *txq, struct rte_mbuf *m,
3077 uint16_t tx_desc_id)
3079 struct hns3_desc *tx_ring = txq->tx_ring;
3080 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3083 hns3_parse_l3_cksum_params(m, &value);
3084 hns3_parse_l4_cksum_params(m, &value);
3086 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(value);
3090 hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num,
3091 uint32_t max_non_tso_bd_num)
3093 struct rte_mbuf *m_first = tx_pkts;
3094 struct rte_mbuf *m_last = tx_pkts;
3095 uint32_t tot_len = 0;
3100 * Hardware requires that the sum of the data length of every 8
3101 * consecutive buffers is greater than MSS in hns3 network engine.
3102 * We simplify it by ensuring pkt_headlen + the first 8 consecutive
3103 * frags greater than gso header len + mss, and the remaining 7
3104 * consecutive frags greater than MSS except the last 7 frags.
3106 if (bd_num <= max_non_tso_bd_num)
3109 for (i = 0; m_last && i < max_non_tso_bd_num - 1;
3110 i++, m_last = m_last->next)
3111 tot_len += m_last->data_len;
3116 /* ensure the first 8 frags is greater than mss + header */
3117 hdr_len = tx_pkts->l2_len + tx_pkts->l3_len + tx_pkts->l4_len;
3118 hdr_len += (tx_pkts->ol_flags & PKT_TX_TUNNEL_MASK) ?
3119 tx_pkts->outer_l2_len + tx_pkts->outer_l3_len : 0;
3120 if (tot_len + m_last->data_len < tx_pkts->tso_segsz + hdr_len)
3124 * ensure the sum of the data length of every 7 consecutive buffer
3125 * is greater than mss except the last one.
3127 for (i = 0; m_last && i < bd_num - max_non_tso_bd_num; i++) {
3128 tot_len -= m_first->data_len;
3129 tot_len += m_last->data_len;
3131 if (tot_len < tx_pkts->tso_segsz)
3134 m_first = m_first->next;
3135 m_last = m_last->next;
3142 hns3_outer_header_cksum_prepare(struct rte_mbuf *m)
3144 uint64_t ol_flags = m->ol_flags;
3145 uint32_t paylen, hdr_len, l4_proto;
3147 if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6)))
3150 if (ol_flags & PKT_TX_OUTER_IPV4) {
3151 struct rte_ipv4_hdr *ipv4_hdr;
3152 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
3154 l4_proto = ipv4_hdr->next_proto_id;
3155 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
3156 ipv4_hdr->hdr_checksum = 0;
3158 struct rte_ipv6_hdr *ipv6_hdr;
3159 ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *,
3161 l4_proto = ipv6_hdr->proto;
3163 /* driver should ensure the outer udp cksum is 0 for TUNNEL TSO */
3164 if (l4_proto == IPPROTO_UDP && (ol_flags & PKT_TX_TCP_SEG)) {
3165 struct rte_udp_hdr *udp_hdr;
3166 hdr_len = m->l2_len + m->l3_len + m->l4_len;
3167 hdr_len += m->outer_l2_len + m->outer_l3_len;
3168 paylen = m->pkt_len - hdr_len;
3169 if (paylen <= m->tso_segsz)
3171 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3174 udp_hdr->dgram_cksum = 0;
3179 hns3_check_tso_pkt_valid(struct rte_mbuf *m)
3181 uint32_t tmp_data_len_sum = 0;
3182 uint16_t nb_buf = m->nb_segs;
3183 uint32_t paylen, hdr_len;
3184 struct rte_mbuf *m_seg;
3187 if (nb_buf > HNS3_MAX_TSO_BD_PER_PKT)
3190 hdr_len = m->l2_len + m->l3_len + m->l4_len;
3191 hdr_len += (m->ol_flags & PKT_TX_TUNNEL_MASK) ?
3192 m->outer_l2_len + m->outer_l3_len : 0;
3193 if (hdr_len > HNS3_MAX_TSO_HDR_SIZE)
3196 paylen = m->pkt_len - hdr_len;
3197 if (paylen > HNS3_MAX_BD_PAYLEN)
3201 * The TSO header (include outer and inner L2, L3 and L4 header)
3202 * should be provided by three descriptors in maximum in hns3 network
3206 for (i = 0; m_seg != NULL && i < HNS3_MAX_TSO_HDR_BD_NUM && i < nb_buf;
3207 i++, m_seg = m_seg->next) {
3208 tmp_data_len_sum += m_seg->data_len;
3211 if (hdr_len > tmp_data_len_sum)
3217 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3219 hns3_vld_vlan_chk(struct hns3_tx_queue *txq, struct rte_mbuf *m)
3221 struct rte_ether_hdr *eh;
3222 struct rte_vlan_hdr *vh;
3224 if (!txq->pvid_sw_shift_en)
3228 * Due to hardware limitations, we only support two-layer VLAN hardware
3229 * offload in Tx direction based on hns3 network engine, so when PVID is
3230 * enabled, QinQ insert is no longer supported.
3231 * And when PVID is enabled, in the following two cases:
3232 * i) packets with more than two VLAN tags.
3233 * ii) packets with one VLAN tag while the hardware VLAN insert is
3235 * The packets will be regarded as abnormal packets and discarded by
3236 * hardware in Tx direction. For debugging purposes, a validation check
3237 * for these types of packets is added to the '.tx_pkt_prepare' ops
3238 * implementation function named hns3_prep_pkts to inform users that
3239 * these packets will be discarded.
3241 if (m->ol_flags & PKT_TX_QINQ_PKT)
3244 eh = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
3245 if (eh->ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
3246 if (m->ol_flags & PKT_TX_VLAN_PKT)
3249 /* Ensure the incoming packet is not a QinQ packet */
3250 vh = (struct rte_vlan_hdr *)(eh + 1);
3251 if (vh->eth_proto == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN))
3260 hns3_prep_pkt_proc(struct hns3_tx_queue *tx_queue, struct rte_mbuf *m)
3264 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3265 ret = rte_validate_tx_offload(m);
3271 ret = hns3_vld_vlan_chk(tx_queue, m);
3277 if (hns3_pkt_is_tso(m)) {
3278 if (hns3_pkt_need_linearized(m, m->nb_segs,
3279 tx_queue->max_non_tso_bd_num) ||
3280 hns3_check_tso_pkt_valid(m)) {
3285 if (tx_queue->tso_mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) {
3287 * (tso mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) means
3288 * hardware support recalculate the TCP pseudo header
3289 * checksum of packets that need TSO, so network driver
3290 * software not need to recalculate it.
3292 hns3_outer_header_cksum_prepare(m);
3297 ret = rte_net_intel_cksum_prepare(m);
3303 hns3_outer_header_cksum_prepare(m);
3309 hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3315 for (i = 0; i < nb_pkts; i++) {
3317 if (hns3_prep_pkt_proc(tx_queue, m))
3325 hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
3328 struct hns3_desc *tx_ring = txq->tx_ring;
3329 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3331 /* Enable checksum offloading */
3332 if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK) {
3333 /* Fill in tunneling parameters if necessary */
3334 if (hns3_parse_tunneling_params(txq, m, tx_desc_id)) {
3335 txq->unsupported_tunnel_pkt_cnt++;
3339 hns3_txd_enable_checksum(txq, m, tx_desc_id);
3341 /* clear the control bit */
3342 desc->tx.type_cs_vlan_tso_len = 0;
3343 desc->tx.ol_type_vlan_len_msec = 0;
3350 hns3_check_non_tso_pkt(uint16_t nb_buf, struct rte_mbuf **m_seg,
3351 struct rte_mbuf *tx_pkt, struct hns3_tx_queue *txq)
3353 uint8_t max_non_tso_bd_num;
3354 struct rte_mbuf *new_pkt;
3357 if (hns3_pkt_is_tso(*m_seg))
3361 * If packet length is greater than HNS3_MAX_FRAME_LEN
3362 * driver support, the packet will be ignored.
3364 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) > HNS3_MAX_FRAME_LEN)) {
3365 txq->over_length_pkt_cnt++;
3369 max_non_tso_bd_num = txq->max_non_tso_bd_num;
3370 if (unlikely(nb_buf > max_non_tso_bd_num)) {
3371 txq->exceed_limit_bd_pkt_cnt++;
3372 ret = hns3_reassemble_tx_pkts(tx_pkt, &new_pkt,
3373 max_non_tso_bd_num);
3375 txq->exceed_limit_bd_reassem_fail++;
3385 hns3_tx_free_buffer_simple(struct hns3_tx_queue *txq)
3387 struct hns3_entry *tx_entry;
3388 struct hns3_desc *desc;
3389 uint16_t tx_next_clean;
3393 if (HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) < txq->tx_rs_thresh)
3397 * All mbufs can be released only when the VLD bits of all
3398 * descriptors in a batch are cleared.
3400 tx_next_clean = (txq->next_to_clean + txq->tx_rs_thresh - 1) %
3402 desc = &txq->tx_ring[tx_next_clean];
3403 for (i = 0; i < txq->tx_rs_thresh; i++) {
3404 if (rte_le_to_cpu_16(desc->tx.tp_fe_sc_vld_ra_ri) &
3405 BIT(HNS3_TXD_VLD_B))
3410 tx_entry = &txq->sw_ring[txq->next_to_clean];
3412 for (i = 0; i < txq->tx_rs_thresh; i++)
3413 rte_prefetch0((tx_entry + i)->mbuf);
3414 for (i = 0; i < txq->tx_rs_thresh; i++, tx_entry++) {
3415 rte_mempool_put(tx_entry->mbuf->pool, tx_entry->mbuf);
3416 tx_entry->mbuf = NULL;
3419 txq->next_to_clean = (tx_next_clean + 1) % txq->nb_tx_desc;
3420 txq->tx_bd_ready += txq->tx_rs_thresh;
3425 hns3_tx_backup_1mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
3427 tx_entry->mbuf = pkts[0];
3431 hns3_tx_backup_4mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
3433 hns3_tx_backup_1mbuf(&tx_entry[0], &pkts[0]);
3434 hns3_tx_backup_1mbuf(&tx_entry[1], &pkts[1]);
3435 hns3_tx_backup_1mbuf(&tx_entry[2], &pkts[2]);
3436 hns3_tx_backup_1mbuf(&tx_entry[3], &pkts[3]);
3440 hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
3442 #define PER_LOOP_NUM 4
3443 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
3447 for (i = 0; i < PER_LOOP_NUM; i++, txdp++, pkts++) {
3448 dma_addr = rte_mbuf_data_iova(*pkts);
3449 txdp->addr = rte_cpu_to_le_64(dma_addr);
3450 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
3451 txdp->tx.paylen = 0;
3452 txdp->tx.type_cs_vlan_tso_len = 0;
3453 txdp->tx.ol_type_vlan_len_msec = 0;
3454 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
3459 hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
3461 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
3464 dma_addr = rte_mbuf_data_iova(*pkts);
3465 txdp->addr = rte_cpu_to_le_64(dma_addr);
3466 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
3467 txdp->tx.paylen = 0;
3468 txdp->tx.type_cs_vlan_tso_len = 0;
3469 txdp->tx.ol_type_vlan_len_msec = 0;
3470 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
3474 hns3_tx_fill_hw_ring(struct hns3_tx_queue *txq,
3475 struct rte_mbuf **pkts,
3478 #define PER_LOOP_NUM 4
3479 #define PER_LOOP_MASK (PER_LOOP_NUM - 1)
3480 struct hns3_desc *txdp = &txq->tx_ring[txq->next_to_use];
3481 struct hns3_entry *tx_entry = &txq->sw_ring[txq->next_to_use];
3482 const uint32_t mainpart = (nb_pkts & ((uint32_t)~PER_LOOP_MASK));
3483 const uint32_t leftover = (nb_pkts & ((uint32_t)PER_LOOP_MASK));
3486 for (i = 0; i < mainpart; i += PER_LOOP_NUM) {
3487 hns3_tx_backup_4mbuf(tx_entry + i, pkts + i);
3488 hns3_tx_setup_4bd(txdp + i, pkts + i);
3490 if (unlikely(leftover > 0)) {
3491 for (i = 0; i < leftover; i++) {
3492 hns3_tx_backup_1mbuf(tx_entry + mainpart + i,
3493 pkts + mainpart + i);
3494 hns3_tx_setup_1bd(txdp + mainpart + i,
3495 pkts + mainpart + i);
3501 hns3_xmit_pkts_simple(void *tx_queue,
3502 struct rte_mbuf **tx_pkts,
3505 struct hns3_tx_queue *txq = tx_queue;
3508 hns3_tx_free_buffer_simple(txq);
3510 nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts);
3511 if (unlikely(nb_pkts == 0)) {
3512 if (txq->tx_bd_ready == 0)
3513 txq->queue_full_cnt++;
3517 txq->tx_bd_ready -= nb_pkts;
3518 if (txq->next_to_use + nb_pkts > txq->nb_tx_desc) {
3519 nb_tx = txq->nb_tx_desc - txq->next_to_use;
3520 hns3_tx_fill_hw_ring(txq, tx_pkts, nb_tx);
3521 txq->next_to_use = 0;
3524 hns3_tx_fill_hw_ring(txq, tx_pkts + nb_tx, nb_pkts - nb_tx);
3525 txq->next_to_use += nb_pkts - nb_tx;
3527 hns3_write_reg_opt(txq->io_tail_reg, nb_pkts);
3533 hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
3535 struct hns3_tx_queue *txq = tx_queue;
3536 struct hns3_entry *tx_bak_pkt;
3537 struct hns3_desc *tx_ring;
3538 struct rte_mbuf *tx_pkt;
3539 struct rte_mbuf *m_seg;
3540 struct hns3_desc *desc;
3541 uint32_t nb_hold = 0;
3542 uint16_t tx_next_use;
3543 uint16_t tx_pkt_num;
3549 /* free useless buffer */
3550 hns3_tx_free_useless_buffer(txq);
3552 tx_next_use = txq->next_to_use;
3553 tx_bd_max = txq->nb_tx_desc;
3554 tx_pkt_num = nb_pkts;
3555 tx_ring = txq->tx_ring;
3558 tx_bak_pkt = &txq->sw_ring[tx_next_use];
3559 for (nb_tx = 0; nb_tx < tx_pkt_num; nb_tx++) {
3560 tx_pkt = *tx_pkts++;
3562 nb_buf = tx_pkt->nb_segs;
3564 if (nb_buf > txq->tx_bd_ready) {
3565 txq->queue_full_cnt++;
3573 * If packet length is less than minimum packet length supported
3574 * by hardware in Tx direction, driver need to pad it to avoid
3577 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) <
3578 txq->min_tx_pkt_len)) {
3582 add_len = txq->min_tx_pkt_len -
3583 rte_pktmbuf_pkt_len(tx_pkt);
3584 appended = rte_pktmbuf_append(tx_pkt, add_len);
3585 if (appended == NULL) {
3586 txq->pkt_padding_fail_cnt++;
3590 memset(appended, 0, add_len);
3595 if (hns3_check_non_tso_pkt(nb_buf, &m_seg, tx_pkt, txq))
3598 if (hns3_parse_cksum(txq, tx_next_use, m_seg))
3602 desc = &tx_ring[tx_next_use];
3605 * If the packet is divided into multiple Tx Buffer Descriptors,
3606 * only need to fill vlan, paylen and tso into the first Tx
3607 * Buffer Descriptor.
3609 hns3_fill_first_desc(txq, desc, m_seg);
3612 desc = &tx_ring[tx_next_use];
3614 * Fill valid bits, DMA address and data length for each
3615 * Tx Buffer Descriptor.
3617 hns3_fill_per_desc(desc, m_seg);
3618 tx_bak_pkt->mbuf = m_seg;
3619 m_seg = m_seg->next;
3622 if (tx_next_use >= tx_bd_max) {
3624 tx_bak_pkt = txq->sw_ring;
3628 } while (m_seg != NULL);
3630 /* Add end flag for the last Tx Buffer Descriptor */
3631 desc->tx.tp_fe_sc_vld_ra_ri |=
3632 rte_cpu_to_le_16(BIT(HNS3_TXD_FE_B));
3635 txq->next_to_use = tx_next_use;
3636 txq->tx_bd_ready -= i;
3642 hns3_write_reg_opt(txq->io_tail_reg, nb_hold);
3648 hns3_tx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
3654 hns3_xmit_pkts_vec(__rte_unused void *tx_queue,
3655 __rte_unused struct rte_mbuf **tx_pkts,
3656 __rte_unused uint16_t nb_pkts)
3662 hns3_xmit_pkts_vec_sve(void __rte_unused * tx_queue,
3663 struct rte_mbuf __rte_unused **tx_pkts,
3664 uint16_t __rte_unused nb_pkts)
3670 hns3_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3671 struct rte_eth_burst_mode *mode)
3673 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3674 const char *info = NULL;
3676 if (pkt_burst == hns3_xmit_pkts_simple)
3677 info = "Scalar Simple";
3678 else if (pkt_burst == hns3_xmit_pkts)
3680 else if (pkt_burst == hns3_xmit_pkts_vec)
3681 info = "Vector Neon";
3682 else if (pkt_burst == hns3_xmit_pkts_vec_sve)
3683 info = "Vector Sve";
3688 snprintf(mode->info, sizeof(mode->info), "%s", info);
3693 static eth_tx_burst_t
3694 hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep)
3696 uint64_t offloads = dev->data->dev_conf.txmode.offloads;
3697 struct hns3_adapter *hns = dev->data->dev_private;
3699 if (hns->tx_vec_allowed && hns3_tx_check_vec_support(dev) == 0) {
3701 return hns3_check_sve_support() ? hns3_xmit_pkts_vec_sve :
3705 if (hns->tx_simple_allowed &&
3706 offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)) {
3708 return hns3_xmit_pkts_simple;
3711 *prep = hns3_prep_pkts;
3712 return hns3_xmit_pkts;
3716 hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused,
3717 struct rte_mbuf **pkts __rte_unused,
3718 uint16_t pkts_n __rte_unused)
3723 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)
3725 struct hns3_adapter *hns = eth_dev->data->dev_private;
3726 eth_tx_prep_t prep = NULL;
3728 if (hns->hw.adapter_state == HNS3_NIC_STARTED &&
3729 rte_atomic16_read(&hns->hw.reset.resetting) == 0) {
3730 eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev);
3731 eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep);
3732 eth_dev->tx_pkt_prepare = prep;
3734 eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst;
3735 eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
3736 eth_dev->tx_pkt_prepare = hns3_dummy_rxtx_burst;
3741 hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3742 struct rte_eth_rxq_info *qinfo)
3744 struct hns3_rx_queue *rxq = dev->data->rx_queues[queue_id];
3746 qinfo->mp = rxq->mb_pool;
3747 qinfo->nb_desc = rxq->nb_rx_desc;
3748 qinfo->scattered_rx = dev->data->scattered_rx;
3749 /* Report the HW Rx buffer length to user */
3750 qinfo->rx_buf_size = rxq->rx_buf_len;
3753 * If there are no available Rx buffer descriptors, incoming packets
3754 * are always dropped by hardware based on hns3 network engine.
3756 qinfo->conf.rx_drop_en = 1;
3757 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
3758 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3759 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3763 hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3764 struct rte_eth_txq_info *qinfo)
3766 struct hns3_tx_queue *txq = dev->data->tx_queues[queue_id];
3768 qinfo->nb_desc = txq->nb_tx_desc;
3769 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
3770 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3771 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3772 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3776 hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3778 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3779 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id];
3780 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3783 if (!hns3_dev_indep_txrx_supported(hw))
3786 ret = hns3_reset_queue(hw, rx_queue_id, HNS3_RING_TYPE_RX);
3788 hns3_err(hw, "fail to reset Rx queue %u, ret = %d.",
3793 ret = hns3_init_rxq(hns, rx_queue_id);
3795 hns3_err(hw, "fail to init Rx queue %u, ret = %d.",
3800 hns3_enable_rxq(rxq, true);
3801 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
3807 hns3_reset_sw_rxq(struct hns3_rx_queue *rxq)
3809 rxq->next_to_use = 0;
3810 rxq->rx_rearm_start = 0;
3811 rxq->rx_free_hold = 0;
3812 rxq->rx_rearm_nb = 0;
3813 rxq->pkt_first_seg = NULL;
3814 rxq->pkt_last_seg = NULL;
3815 memset(&rxq->rx_ring[0], 0, rxq->nb_rx_desc * sizeof(struct hns3_desc));
3816 hns3_rxq_vec_setup(rxq);
3820 hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3822 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3823 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id];
3825 if (!hns3_dev_indep_txrx_supported(hw))
3828 hns3_enable_rxq(rxq, false);
3830 hns3_rx_queue_release_mbufs(rxq);
3832 hns3_reset_sw_rxq(rxq);
3833 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
3839 hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3841 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3842 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id];
3845 if (!hns3_dev_indep_txrx_supported(hw))
3848 ret = hns3_reset_queue(hw, tx_queue_id, HNS3_RING_TYPE_TX);
3850 hns3_err(hw, "fail to reset Tx queue %u, ret = %d.",
3856 hns3_enable_txq(txq, true);
3857 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
3863 hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3865 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3866 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id];
3868 if (!hns3_dev_indep_txrx_supported(hw))
3871 hns3_enable_txq(txq, false);
3872 hns3_tx_queue_release_mbufs(txq);
3874 * All the mbufs in sw_ring are released and all the pointers in sw_ring
3875 * are set to NULL. If this queue is still called by upper layer,
3876 * residual SW status of this txq may cause these pointers in sw_ring
3877 * which have been set to NULL to be released again. To avoid it,
3881 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
3887 hns3_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3890 * Number of BDs that have been processed by the driver
3891 * but have not been notified to the hardware.
3893 uint32_t driver_hold_bd_num;
3894 struct hns3_rx_queue *rxq;
3897 rxq = dev->data->rx_queues[rx_queue_id];
3898 fbd_num = hns3_read_dev(rxq, HNS3_RING_RX_FBDNUM_REG);
3899 if (dev->rx_pkt_burst == hns3_recv_pkts_vec ||
3900 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve)
3901 driver_hold_bd_num = rxq->rx_rearm_nb;
3903 driver_hold_bd_num = rxq->rx_free_hold;
3905 if (fbd_num <= driver_hold_bd_num)
3908 return fbd_num - driver_hold_bd_num;