1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
11 #include <rte_bus_pci.h>
12 #include <rte_byteorder.h>
13 #include <rte_common.h>
14 #include <rte_cycles.h>
17 #include <rte_ether.h>
18 #include <rte_vxlan.h>
19 #include <rte_ethdev_driver.h>
24 #include <rte_malloc.h>
27 #include "hns3_ethdev.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_regs.h"
30 #include "hns3_logs.h"
32 #define HNS3_CFG_DESC_NUM(num) ((num) / 8 - 1)
33 #define DEFAULT_RX_FREE_THRESH 32
36 hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq)
40 /* Note: Fake rx queue will not enter here */
42 for (i = 0; i < rxq->nb_rx_desc; i++) {
43 if (rxq->sw_ring[i].mbuf) {
44 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
45 rxq->sw_ring[i].mbuf = NULL;
52 hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq)
56 /* Note: Fake rx queue will not enter here */
58 for (i = 0; i < txq->nb_tx_desc; i++) {
59 if (txq->sw_ring[i].mbuf) {
60 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
61 txq->sw_ring[i].mbuf = NULL;
68 hns3_rx_queue_release(void *queue)
70 struct hns3_rx_queue *rxq = queue;
72 hns3_rx_queue_release_mbufs(rxq);
74 rte_memzone_free(rxq->mz);
76 rte_free(rxq->sw_ring);
82 hns3_tx_queue_release(void *queue)
84 struct hns3_tx_queue *txq = queue;
86 hns3_tx_queue_release_mbufs(txq);
88 rte_memzone_free(txq->mz);
90 rte_free(txq->sw_ring);
96 hns3_dev_rx_queue_release(void *queue)
98 struct hns3_rx_queue *rxq = queue;
99 struct hns3_adapter *hns;
105 rte_spinlock_lock(&hns->hw.lock);
106 hns3_rx_queue_release(queue);
107 rte_spinlock_unlock(&hns->hw.lock);
111 hns3_dev_tx_queue_release(void *queue)
113 struct hns3_tx_queue *txq = queue;
114 struct hns3_adapter *hns;
120 rte_spinlock_lock(&hns->hw.lock);
121 hns3_tx_queue_release(queue);
122 rte_spinlock_unlock(&hns->hw.lock);
126 hns3_fake_rx_queue_release(struct hns3_rx_queue *queue)
128 struct hns3_rx_queue *rxq = queue;
129 struct hns3_adapter *hns;
139 if (hw->fkq_data.rx_queues[idx]) {
140 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
141 hw->fkq_data.rx_queues[idx] = NULL;
144 /* free fake rx queue arrays */
145 if (idx == (hw->fkq_data.nb_fake_rx_queues - 1)) {
146 hw->fkq_data.nb_fake_rx_queues = 0;
147 rte_free(hw->fkq_data.rx_queues);
148 hw->fkq_data.rx_queues = NULL;
153 hns3_fake_tx_queue_release(struct hns3_tx_queue *queue)
155 struct hns3_tx_queue *txq = queue;
156 struct hns3_adapter *hns;
166 if (hw->fkq_data.tx_queues[idx]) {
167 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
168 hw->fkq_data.tx_queues[idx] = NULL;
171 /* free fake tx queue arrays */
172 if (idx == (hw->fkq_data.nb_fake_tx_queues - 1)) {
173 hw->fkq_data.nb_fake_tx_queues = 0;
174 rte_free(hw->fkq_data.tx_queues);
175 hw->fkq_data.tx_queues = NULL;
180 hns3_free_rx_queues(struct rte_eth_dev *dev)
182 struct hns3_adapter *hns = dev->data->dev_private;
183 struct hns3_fake_queue_data *fkq_data;
184 struct hns3_hw *hw = &hns->hw;
188 nb_rx_q = hw->data->nb_rx_queues;
189 for (i = 0; i < nb_rx_q; i++) {
190 if (dev->data->rx_queues[i]) {
191 hns3_rx_queue_release(dev->data->rx_queues[i]);
192 dev->data->rx_queues[i] = NULL;
196 /* Free fake Rx queues */
197 fkq_data = &hw->fkq_data;
198 for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) {
199 if (fkq_data->rx_queues[i])
200 hns3_fake_rx_queue_release(fkq_data->rx_queues[i]);
205 hns3_free_tx_queues(struct rte_eth_dev *dev)
207 struct hns3_adapter *hns = dev->data->dev_private;
208 struct hns3_fake_queue_data *fkq_data;
209 struct hns3_hw *hw = &hns->hw;
213 nb_tx_q = hw->data->nb_tx_queues;
214 for (i = 0; i < nb_tx_q; i++) {
215 if (dev->data->tx_queues[i]) {
216 hns3_tx_queue_release(dev->data->tx_queues[i]);
217 dev->data->tx_queues[i] = NULL;
221 /* Free fake Tx queues */
222 fkq_data = &hw->fkq_data;
223 for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) {
224 if (fkq_data->tx_queues[i])
225 hns3_fake_tx_queue_release(fkq_data->tx_queues[i]);
230 hns3_free_all_queues(struct rte_eth_dev *dev)
232 hns3_free_rx_queues(dev);
233 hns3_free_tx_queues(dev);
237 hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq)
239 struct rte_mbuf *mbuf;
243 for (i = 0; i < rxq->nb_rx_desc; i++) {
244 mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
245 if (unlikely(mbuf == NULL)) {
246 hns3_err(hw, "Failed to allocate RXD[%d] for rx queue!",
248 hns3_rx_queue_release_mbufs(rxq);
252 rte_mbuf_refcnt_set(mbuf, 1);
254 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
256 mbuf->port = rxq->port_id;
258 rxq->sw_ring[i].mbuf = mbuf;
259 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
260 rxq->rx_ring[i].addr = dma_addr;
261 rxq->rx_ring[i].rx.bd_base_info = 0;
268 hns3_buf_size2type(uint32_t buf_size)
274 bd_size_type = HNS3_BD_SIZE_512_TYPE;
277 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
280 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
283 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
290 hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)
292 uint32_t rx_buf_len = rxq->rx_buf_len;
293 uint64_t dma_addr = rxq->rx_ring_phys_addr;
295 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);
296 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,
297 (uint32_t)((dma_addr >> 31) >> 1));
299 hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,
300 hns3_buf_size2type(rx_buf_len));
301 hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG,
302 HNS3_CFG_DESC_NUM(rxq->nb_rx_desc));
306 hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)
308 uint64_t dma_addr = txq->tx_ring_phys_addr;
310 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);
311 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,
312 (uint32_t)((dma_addr >> 31) >> 1));
314 hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,
315 HNS3_CFG_DESC_NUM(txq->nb_tx_desc));
319 hns3_update_all_queues_pvid_state(struct hns3_hw *hw)
321 uint16_t nb_rx_q = hw->data->nb_rx_queues;
322 uint16_t nb_tx_q = hw->data->nb_tx_queues;
323 struct hns3_rx_queue *rxq;
324 struct hns3_tx_queue *txq;
328 pvid_state = hw->port_base_vlan_cfg.state;
329 for (i = 0; i < hw->cfg_max_queues; i++) {
331 rxq = hw->data->rx_queues[i];
333 rxq->pvid_state = pvid_state;
336 txq = hw->data->tx_queues[i];
338 txq->pvid_state = pvid_state;
344 hns3_enable_all_queues(struct hns3_hw *hw, bool en)
346 uint16_t nb_rx_q = hw->data->nb_rx_queues;
347 uint16_t nb_tx_q = hw->data->nb_tx_queues;
348 struct hns3_rx_queue *rxq;
349 struct hns3_tx_queue *txq;
353 for (i = 0; i < hw->cfg_max_queues; i++) {
355 rxq = hw->data->rx_queues[i];
357 rxq = hw->fkq_data.rx_queues[i - nb_rx_q];
359 txq = hw->data->tx_queues[i];
361 txq = hw->fkq_data.tx_queues[i - nb_tx_q];
362 if (rxq == NULL || txq == NULL ||
363 (en && (rxq->rx_deferred_start || txq->tx_deferred_start)))
366 rcb_reg = hns3_read_dev(rxq, HNS3_RING_EN_REG);
368 rcb_reg |= BIT(HNS3_RING_EN_B);
370 rcb_reg &= ~BIT(HNS3_RING_EN_B);
371 hns3_write_dev(rxq, HNS3_RING_EN_REG, rcb_reg);
376 hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable)
378 struct hns3_cfg_com_tqp_queue_cmd *req;
379 struct hns3_cmd_desc desc;
382 req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data;
384 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false);
385 req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
387 hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0);
389 ret = hns3_cmd_send(hw, &desc, 1);
391 hns3_err(hw, "TQP enable fail, ret = %d", ret);
397 hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable)
399 struct hns3_reset_tqp_queue_cmd *req;
400 struct hns3_cmd_desc desc;
403 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false);
405 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
406 req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
407 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
409 ret = hns3_cmd_send(hw, &desc, 1);
411 hns3_err(hw, "Send tqp reset cmd error, ret = %d", ret);
417 hns3_get_reset_status(struct hns3_hw *hw, uint16_t queue_id)
419 struct hns3_reset_tqp_queue_cmd *req;
420 struct hns3_cmd_desc desc;
423 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true);
425 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
426 req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
428 ret = hns3_cmd_send(hw, &desc, 1);
430 hns3_err(hw, "Get reset status error, ret =%d", ret);
434 return hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
438 hns3_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
440 #define HNS3_TQP_RESET_TRY_MS 200
445 ret = hns3_tqp_enable(hw, queue_id, false);
450 * In current version VF is not supported when PF is driven by DPDK
451 * driver, all task queue pairs are mapped to PF function, so PF's queue
452 * id is equals to the global queue id in PF range.
454 ret = hns3_send_reset_tqp_cmd(hw, queue_id, true);
456 hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret);
460 end = get_timeofday_ms() + HNS3_TQP_RESET_TRY_MS;
462 /* Wait for tqp hw reset */
463 rte_delay_ms(HNS3_POLL_RESPONE_MS);
464 reset_status = hns3_get_reset_status(hw, queue_id);
469 } while (get_timeofday_ms() < end);
472 hns3_err(hw, "Reset TQP fail, ret = %d", ret);
476 ret = hns3_send_reset_tqp_cmd(hw, queue_id, false);
478 hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret);
484 hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
489 /* Disable VF's queue before send queue reset msg to PF */
490 ret = hns3_tqp_enable(hw, queue_id, false);
494 memcpy(msg_data, &queue_id, sizeof(uint16_t));
496 return hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
497 sizeof(msg_data), true, NULL, 0);
501 hns3_reset_queue(struct hns3_adapter *hns, uint16_t queue_id)
503 struct hns3_hw *hw = &hns->hw;
505 return hns3vf_reset_tqp(hw, queue_id);
507 return hns3_reset_tqp(hw, queue_id);
511 hns3_reset_all_queues(struct hns3_adapter *hns)
513 struct hns3_hw *hw = &hns->hw;
516 for (i = 0; i < hw->cfg_max_queues; i++) {
517 ret = hns3_reset_queue(hns, i);
519 hns3_err(hw, "Failed to reset No.%d queue: %d", i, ret);
527 hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
528 uint8_t gl_idx, uint16_t gl_value)
530 uint32_t offset[] = {HNS3_TQP_INTR_GL0_REG,
531 HNS3_TQP_INTR_GL1_REG,
532 HNS3_TQP_INTR_GL2_REG};
533 uint32_t addr, value;
535 if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX)
538 addr = offset[gl_idx] + queue_id * HNS3_TQP_INTR_REG_SIZE;
539 value = HNS3_GL_USEC_TO_REG(gl_value);
541 hns3_write_dev(hw, addr, value);
545 hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value)
547 uint32_t addr, value;
549 if (rl_value > HNS3_TQP_INTR_RL_MAX)
552 addr = HNS3_TQP_INTR_RL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
553 value = HNS3_RL_USEC_TO_REG(rl_value);
555 value |= HNS3_TQP_INTR_RL_ENABLE_MASK;
557 hns3_write_dev(hw, addr, value);
561 hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en)
563 uint32_t addr, value;
565 addr = HNS3_TQP_INTR_CTRL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
568 hns3_write_dev(hw, addr, value);
572 * Enable all rx queue interrupt when in interrupt rx mode.
573 * This api was called before enable queue rx&tx (in normal start or reset
574 * recover scenes), used to fix hardware rx queue interrupt enable was clear
578 hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en)
580 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
581 uint16_t nb_rx_q = hw->data->nb_rx_queues;
584 if (dev->data->dev_conf.intr_conf.rxq == 0)
587 for (i = 0; i < nb_rx_q; i++)
588 hns3_queue_intr_enable(hw, i, en);
592 hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
594 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
595 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
596 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
598 if (dev->data->dev_conf.intr_conf.rxq == 0)
601 hns3_queue_intr_enable(hw, queue_id, true);
603 return rte_intr_ack(intr_handle);
607 hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
609 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
611 if (dev->data->dev_conf.intr_conf.rxq == 0)
614 hns3_queue_intr_enable(hw, queue_id, false);
620 hns3_dev_rx_queue_start(struct hns3_adapter *hns, uint16_t idx)
622 struct hns3_hw *hw = &hns->hw;
623 struct hns3_rx_queue *rxq;
626 PMD_INIT_FUNC_TRACE();
628 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx];
629 ret = hns3_alloc_rx_queue_mbufs(hw, rxq);
631 hns3_err(hw, "Failed to alloc mbuf for No.%d rx queue: %d",
636 rxq->next_to_use = 0;
637 rxq->next_to_clean = 0;
639 hns3_init_rx_queue_hw(rxq);
645 hns3_fake_rx_queue_start(struct hns3_adapter *hns, uint16_t idx)
647 struct hns3_hw *hw = &hns->hw;
648 struct hns3_rx_queue *rxq;
650 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx];
651 rxq->next_to_use = 0;
652 rxq->next_to_clean = 0;
654 hns3_init_rx_queue_hw(rxq);
658 hns3_init_tx_queue(struct hns3_tx_queue *queue)
660 struct hns3_tx_queue *txq = queue;
661 struct hns3_desc *desc;
666 for (i = 0; i < txq->nb_tx_desc; i++) {
667 desc->tx.tp_fe_sc_vld_ra_ri = 0;
671 txq->next_to_use = 0;
672 txq->next_to_clean = 0;
673 txq->tx_bd_ready = txq->nb_tx_desc - 1;
674 hns3_init_tx_queue_hw(txq);
678 hns3_dev_tx_queue_start(struct hns3_adapter *hns, uint16_t idx)
680 struct hns3_hw *hw = &hns->hw;
681 struct hns3_tx_queue *txq;
683 txq = (struct hns3_tx_queue *)hw->data->tx_queues[idx];
684 hns3_init_tx_queue(txq);
688 hns3_fake_tx_queue_start(struct hns3_adapter *hns, uint16_t idx)
690 struct hns3_hw *hw = &hns->hw;
691 struct hns3_tx_queue *txq;
693 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[idx];
694 hns3_init_tx_queue(txq);
698 hns3_init_tx_ring_tc(struct hns3_adapter *hns)
700 struct hns3_hw *hw = &hns->hw;
701 struct hns3_tx_queue *txq;
704 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
705 struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i];
708 if (!tc_queue->enable)
711 for (j = 0; j < tc_queue->tqp_count; j++) {
712 num = tc_queue->tqp_offset + j;
713 txq = (struct hns3_tx_queue *)hw->data->tx_queues[num];
717 hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc);
723 hns3_start_rx_queues(struct hns3_adapter *hns)
725 struct hns3_hw *hw = &hns->hw;
726 struct hns3_rx_queue *rxq;
730 /* Initialize RSS for queues */
731 ret = hns3_config_rss(hns);
733 hns3_err(hw, "Failed to configure rss %d", ret);
737 for (i = 0; i < hw->data->nb_rx_queues; i++) {
738 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i];
739 if (rxq == NULL || rxq->rx_deferred_start)
741 ret = hns3_dev_rx_queue_start(hns, i);
743 hns3_err(hw, "Failed to start No.%d rx queue: %d", i,
749 for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++) {
750 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[i];
751 if (rxq == NULL || rxq->rx_deferred_start)
753 hns3_fake_rx_queue_start(hns, i);
758 for (j = 0; j < i; j++) {
759 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j];
760 hns3_rx_queue_release_mbufs(rxq);
767 hns3_start_tx_queues(struct hns3_adapter *hns)
769 struct hns3_hw *hw = &hns->hw;
770 struct hns3_tx_queue *txq;
773 for (i = 0; i < hw->data->nb_tx_queues; i++) {
774 txq = (struct hns3_tx_queue *)hw->data->tx_queues[i];
775 if (txq == NULL || txq->tx_deferred_start)
777 hns3_dev_tx_queue_start(hns, i);
780 for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) {
781 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i];
782 if (txq == NULL || txq->tx_deferred_start)
784 hns3_fake_tx_queue_start(hns, i);
787 hns3_init_tx_ring_tc(hns);
792 * Note: just init and setup queues, and don't enable queue rx&tx.
795 hns3_start_queues(struct hns3_adapter *hns, bool reset_queue)
797 struct hns3_hw *hw = &hns->hw;
801 ret = hns3_reset_all_queues(hns);
803 hns3_err(hw, "Failed to reset all queues %d", ret);
808 ret = hns3_start_rx_queues(hns);
810 hns3_err(hw, "Failed to start rx queues: %d", ret);
814 hns3_start_tx_queues(hns);
820 hns3_stop_queues(struct hns3_adapter *hns, bool reset_queue)
822 struct hns3_hw *hw = &hns->hw;
825 hns3_enable_all_queues(hw, false);
827 ret = hns3_reset_all_queues(hns);
829 hns3_err(hw, "Failed to reset all queues %d", ret);
837 hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev,
838 struct hns3_queue_info *q_info)
840 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
841 const struct rte_memzone *rx_mz;
842 struct hns3_rx_queue *rxq;
843 unsigned int rx_desc;
845 rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue),
846 RTE_CACHE_LINE_SIZE, q_info->socket_id);
848 hns3_err(hw, "Failed to allocate memory for No.%d rx ring!",
853 /* Allocate rx ring hardware descriptors. */
854 rxq->queue_id = q_info->idx;
855 rxq->nb_rx_desc = q_info->nb_desc;
856 rx_desc = rxq->nb_rx_desc * sizeof(struct hns3_desc);
857 rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
858 rx_desc, HNS3_RING_BASE_ALIGN,
861 hns3_err(hw, "Failed to reserve DMA memory for No.%d rx ring!",
863 hns3_rx_queue_release(rxq);
867 rxq->rx_ring = (struct hns3_desc *)rx_mz->addr;
868 rxq->rx_ring_phys_addr = rx_mz->iova;
870 hns3_dbg(hw, "No.%d rx descriptors iova 0x%" PRIx64, q_info->idx,
871 rxq->rx_ring_phys_addr);
877 hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
878 uint16_t nb_desc, unsigned int socket_id)
880 struct hns3_adapter *hns = dev->data->dev_private;
881 struct hns3_hw *hw = &hns->hw;
882 struct hns3_queue_info q_info;
883 struct hns3_rx_queue *rxq;
886 if (hw->fkq_data.rx_queues[idx]) {
887 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
888 hw->fkq_data.rx_queues[idx] = NULL;
892 q_info.socket_id = socket_id;
893 q_info.nb_desc = nb_desc;
894 q_info.type = "hns3 fake RX queue";
895 q_info.ring_name = "rx_fake_ring";
896 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
898 hns3_err(hw, "Failed to setup No.%d fake rx ring.", idx);
902 /* Don't need alloc sw_ring, because upper applications don't use it */
906 rxq->rx_deferred_start = false;
907 rxq->port_id = dev->data->port_id;
908 rxq->configured = true;
909 nb_rx_q = dev->data->nb_rx_queues;
910 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
911 (nb_rx_q + idx) * HNS3_TQP_REG_SIZE);
912 rxq->rx_buf_len = HNS3_MIN_BD_BUF_SIZE;
914 rte_spinlock_lock(&hw->lock);
915 hw->fkq_data.rx_queues[idx] = rxq;
916 rte_spinlock_unlock(&hw->lock);
922 hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev,
923 struct hns3_queue_info *q_info)
925 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
926 const struct rte_memzone *tx_mz;
927 struct hns3_tx_queue *txq;
928 struct hns3_desc *desc;
929 unsigned int tx_desc;
932 txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue),
933 RTE_CACHE_LINE_SIZE, q_info->socket_id);
935 hns3_err(hw, "Failed to allocate memory for No.%d tx ring!",
940 /* Allocate tx ring hardware descriptors. */
941 txq->queue_id = q_info->idx;
942 txq->nb_tx_desc = q_info->nb_desc;
943 tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc);
944 tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
945 tx_desc, HNS3_RING_BASE_ALIGN,
948 hns3_err(hw, "Failed to reserve DMA memory for No.%d tx ring!",
950 hns3_tx_queue_release(txq);
954 txq->tx_ring = (struct hns3_desc *)tx_mz->addr;
955 txq->tx_ring_phys_addr = tx_mz->iova;
957 hns3_dbg(hw, "No.%d tx descriptors iova 0x%" PRIx64, q_info->idx,
958 txq->tx_ring_phys_addr);
962 for (i = 0; i < txq->nb_tx_desc; i++) {
963 desc->tx.tp_fe_sc_vld_ra_ri = 0;
971 hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
972 uint16_t nb_desc, unsigned int socket_id)
974 struct hns3_adapter *hns = dev->data->dev_private;
975 struct hns3_hw *hw = &hns->hw;
976 struct hns3_queue_info q_info;
977 struct hns3_tx_queue *txq;
980 if (hw->fkq_data.tx_queues[idx] != NULL) {
981 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
982 hw->fkq_data.tx_queues[idx] = NULL;
986 q_info.socket_id = socket_id;
987 q_info.nb_desc = nb_desc;
988 q_info.type = "hns3 fake TX queue";
989 q_info.ring_name = "tx_fake_ring";
990 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
992 hns3_err(hw, "Failed to setup No.%d fake tx ring.", idx);
996 /* Don't need alloc sw_ring, because upper applications don't use it */
1000 txq->tx_deferred_start = false;
1001 txq->port_id = dev->data->port_id;
1002 txq->configured = true;
1003 nb_tx_q = dev->data->nb_tx_queues;
1004 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1005 (nb_tx_q + idx) * HNS3_TQP_REG_SIZE);
1007 rte_spinlock_lock(&hw->lock);
1008 hw->fkq_data.tx_queues[idx] = txq;
1009 rte_spinlock_unlock(&hw->lock);
1015 hns3_fake_rx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1017 uint16_t old_nb_queues = hw->fkq_data.nb_fake_rx_queues;
1021 if (hw->fkq_data.rx_queues == NULL && nb_queues != 0) {
1022 /* first time configuration */
1024 size = sizeof(hw->fkq_data.rx_queues[0]) * nb_queues;
1025 hw->fkq_data.rx_queues = rte_zmalloc("fake_rx_queues", size,
1026 RTE_CACHE_LINE_SIZE);
1027 if (hw->fkq_data.rx_queues == NULL) {
1028 hw->fkq_data.nb_fake_rx_queues = 0;
1031 } else if (hw->fkq_data.rx_queues != NULL && nb_queues != 0) {
1033 rxq = hw->fkq_data.rx_queues;
1034 for (i = nb_queues; i < old_nb_queues; i++)
1035 hns3_dev_rx_queue_release(rxq[i]);
1037 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
1038 RTE_CACHE_LINE_SIZE);
1041 if (nb_queues > old_nb_queues) {
1042 uint16_t new_qs = nb_queues - old_nb_queues;
1043 memset(rxq + old_nb_queues, 0, sizeof(rxq[0]) * new_qs);
1046 hw->fkq_data.rx_queues = rxq;
1047 } else if (hw->fkq_data.rx_queues != NULL && nb_queues == 0) {
1048 rxq = hw->fkq_data.rx_queues;
1049 for (i = nb_queues; i < old_nb_queues; i++)
1050 hns3_dev_rx_queue_release(rxq[i]);
1052 rte_free(hw->fkq_data.rx_queues);
1053 hw->fkq_data.rx_queues = NULL;
1056 hw->fkq_data.nb_fake_rx_queues = nb_queues;
1062 hns3_fake_tx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1064 uint16_t old_nb_queues = hw->fkq_data.nb_fake_tx_queues;
1068 if (hw->fkq_data.tx_queues == NULL && nb_queues != 0) {
1069 /* first time configuration */
1071 size = sizeof(hw->fkq_data.tx_queues[0]) * nb_queues;
1072 hw->fkq_data.tx_queues = rte_zmalloc("fake_tx_queues", size,
1073 RTE_CACHE_LINE_SIZE);
1074 if (hw->fkq_data.tx_queues == NULL) {
1075 hw->fkq_data.nb_fake_tx_queues = 0;
1078 } else if (hw->fkq_data.tx_queues != NULL && nb_queues != 0) {
1080 txq = hw->fkq_data.tx_queues;
1081 for (i = nb_queues; i < old_nb_queues; i++)
1082 hns3_dev_tx_queue_release(txq[i]);
1083 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1084 RTE_CACHE_LINE_SIZE);
1087 if (nb_queues > old_nb_queues) {
1088 uint16_t new_qs = nb_queues - old_nb_queues;
1089 memset(txq + old_nb_queues, 0, sizeof(txq[0]) * new_qs);
1092 hw->fkq_data.tx_queues = txq;
1093 } else if (hw->fkq_data.tx_queues != NULL && nb_queues == 0) {
1094 txq = hw->fkq_data.tx_queues;
1095 for (i = nb_queues; i < old_nb_queues; i++)
1096 hns3_dev_tx_queue_release(txq[i]);
1098 rte_free(hw->fkq_data.tx_queues);
1099 hw->fkq_data.tx_queues = NULL;
1101 hw->fkq_data.nb_fake_tx_queues = nb_queues;
1107 hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
1110 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1111 uint16_t rx_need_add_nb_q;
1112 uint16_t tx_need_add_nb_q;
1117 /* Setup new number of fake RX/TX queues and reconfigure device. */
1118 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
1119 rx_need_add_nb_q = hw->cfg_max_queues - nb_rx_q;
1120 tx_need_add_nb_q = hw->cfg_max_queues - nb_tx_q;
1121 ret = hns3_fake_rx_queue_config(hw, rx_need_add_nb_q);
1123 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1124 goto cfg_fake_rx_q_fail;
1127 ret = hns3_fake_tx_queue_config(hw, tx_need_add_nb_q);
1129 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1130 goto cfg_fake_tx_q_fail;
1133 /* Allocate and set up fake RX queue per Ethernet port. */
1134 port_id = hw->data->port_id;
1135 for (q = 0; q < rx_need_add_nb_q; q++) {
1136 ret = hns3_fake_rx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1137 rte_eth_dev_socket_id(port_id));
1139 goto setup_fake_rx_q_fail;
1142 /* Allocate and set up fake TX queue per Ethernet port. */
1143 for (q = 0; q < tx_need_add_nb_q; q++) {
1144 ret = hns3_fake_tx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1145 rte_eth_dev_socket_id(port_id));
1147 goto setup_fake_tx_q_fail;
1152 setup_fake_tx_q_fail:
1153 setup_fake_rx_q_fail:
1154 (void)hns3_fake_tx_queue_config(hw, 0);
1156 (void)hns3_fake_rx_queue_config(hw, 0);
1158 hw->cfg_max_queues = 0;
1164 hns3_dev_release_mbufs(struct hns3_adapter *hns)
1166 struct rte_eth_dev_data *dev_data = hns->hw.data;
1167 struct hns3_rx_queue *rxq;
1168 struct hns3_tx_queue *txq;
1171 if (dev_data->rx_queues)
1172 for (i = 0; i < dev_data->nb_rx_queues; i++) {
1173 rxq = dev_data->rx_queues[i];
1174 if (rxq == NULL || rxq->rx_deferred_start)
1176 hns3_rx_queue_release_mbufs(rxq);
1179 if (dev_data->tx_queues)
1180 for (i = 0; i < dev_data->nb_tx_queues; i++) {
1181 txq = dev_data->tx_queues[i];
1182 if (txq == NULL || txq->tx_deferred_start)
1184 hns3_tx_queue_release_mbufs(txq);
1189 hns3_rx_buf_len_calc(struct rte_mempool *mp, uint16_t *rx_buf_len)
1191 uint16_t vld_buf_size;
1192 uint16_t num_hw_specs;
1196 * hns3 network engine only support to set 4 typical specification, and
1197 * different buffer size will affect the max packet_len and the max
1198 * number of segmentation when hw gro is turned on in receive side. The
1199 * relationship between them is as follows:
1200 * rx_buf_size | max_gro_pkt_len | max_gro_nb_seg
1201 * ---------------------|-------------------|----------------
1202 * HNS3_4K_BD_BUF_SIZE | 60KB | 15
1203 * HNS3_2K_BD_BUF_SIZE | 62KB | 31
1204 * HNS3_1K_BD_BUF_SIZE | 63KB | 63
1205 * HNS3_512_BD_BUF_SIZE | 31.5KB | 63
1207 static const uint16_t hw_rx_buf_size[] = {
1208 HNS3_4K_BD_BUF_SIZE,
1209 HNS3_2K_BD_BUF_SIZE,
1210 HNS3_1K_BD_BUF_SIZE,
1211 HNS3_512_BD_BUF_SIZE
1214 vld_buf_size = (uint16_t)(rte_pktmbuf_data_room_size(mp) -
1215 RTE_PKTMBUF_HEADROOM);
1217 if (vld_buf_size < HNS3_MIN_BD_BUF_SIZE)
1220 num_hw_specs = RTE_DIM(hw_rx_buf_size);
1221 for (i = 0; i < num_hw_specs; i++) {
1222 if (vld_buf_size >= hw_rx_buf_size[i]) {
1223 *rx_buf_len = hw_rx_buf_size[i];
1231 hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1232 unsigned int socket_id, const struct rte_eth_rxconf *conf,
1233 struct rte_mempool *mp)
1235 struct hns3_adapter *hns = dev->data->dev_private;
1236 struct hns3_hw *hw = &hns->hw;
1237 struct hns3_queue_info q_info;
1238 struct hns3_rx_queue *rxq;
1239 uint16_t rx_buf_size;
1242 if (dev->data->dev_started) {
1243 hns3_err(hw, "rx_queue_setup after dev_start no supported");
1247 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1248 nb_desc % HNS3_ALIGN_RING_DESC) {
1249 hns3_err(hw, "Number (%u) of rx descriptors is invalid",
1254 if (dev->data->rx_queues[idx]) {
1255 hns3_rx_queue_release(dev->data->rx_queues[idx]);
1256 dev->data->rx_queues[idx] = NULL;
1260 q_info.socket_id = socket_id;
1261 q_info.nb_desc = nb_desc;
1262 q_info.type = "hns3 RX queue";
1263 q_info.ring_name = "rx_ring";
1265 if (hns3_rx_buf_len_calc(mp, &rx_buf_size)) {
1266 hns3_err(hw, "rxq mbufs' data room size:%u is not enough! "
1267 "minimal data room size:%u.",
1268 rte_pktmbuf_data_room_size(mp),
1269 HNS3_MIN_BD_BUF_SIZE + RTE_PKTMBUF_HEADROOM);
1273 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1276 "Failed to alloc mem and reserve DMA mem for rx ring!");
1282 if (conf->rx_free_thresh <= 0)
1283 rxq->rx_free_thresh = DEFAULT_RX_FREE_THRESH;
1285 rxq->rx_free_thresh = conf->rx_free_thresh;
1286 rxq->rx_deferred_start = conf->rx_deferred_start;
1288 rx_entry_len = sizeof(struct hns3_entry) * rxq->nb_rx_desc;
1289 rxq->sw_ring = rte_zmalloc_socket("hns3 RX sw ring", rx_entry_len,
1290 RTE_CACHE_LINE_SIZE, socket_id);
1291 if (rxq->sw_ring == NULL) {
1292 hns3_err(hw, "Failed to allocate memory for rx sw ring!");
1293 hns3_rx_queue_release(rxq);
1297 rxq->next_to_use = 0;
1298 rxq->next_to_clean = 0;
1299 rxq->nb_rx_hold = 0;
1300 rxq->pkt_first_seg = NULL;
1301 rxq->pkt_last_seg = NULL;
1302 rxq->port_id = dev->data->port_id;
1303 rxq->pvid_state = hw->port_base_vlan_cfg.state;
1304 rxq->configured = true;
1305 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1306 idx * HNS3_TQP_REG_SIZE);
1307 rxq->rx_buf_len = rx_buf_size;
1309 rxq->pkt_len_errors = 0;
1310 rxq->l3_csum_erros = 0;
1311 rxq->l4_csum_erros = 0;
1312 rxq->ol3_csum_erros = 0;
1313 rxq->ol4_csum_erros = 0;
1315 rte_spinlock_lock(&hw->lock);
1316 dev->data->rx_queues[idx] = rxq;
1317 rte_spinlock_unlock(&hw->lock);
1322 static inline uint32_t
1323 rxd_pkt_info_to_pkt_type(uint32_t pkt_info, uint32_t ol_info)
1325 #define HNS3_L2TBL_NUM 4
1326 #define HNS3_L3TBL_NUM 16
1327 #define HNS3_L4TBL_NUM 16
1328 #define HNS3_OL3TBL_NUM 16
1329 #define HNS3_OL4TBL_NUM 16
1330 uint32_t pkt_type = 0;
1331 uint32_t l2id, l3id, l4id;
1332 uint32_t ol3id, ol4id;
1334 static const uint32_t l2table[HNS3_L2TBL_NUM] = {
1336 RTE_PTYPE_L2_ETHER_QINQ,
1337 RTE_PTYPE_L2_ETHER_VLAN,
1338 RTE_PTYPE_L2_ETHER_VLAN
1341 static const uint32_t l3table[HNS3_L3TBL_NUM] = {
1344 RTE_PTYPE_L2_ETHER_ARP,
1346 RTE_PTYPE_L3_IPV4_EXT,
1347 RTE_PTYPE_L3_IPV6_EXT,
1348 RTE_PTYPE_L2_ETHER_LLDP,
1349 0, 0, 0, 0, 0, 0, 0, 0, 0
1352 static const uint32_t l4table[HNS3_L4TBL_NUM] = {
1355 RTE_PTYPE_TUNNEL_GRE,
1359 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1362 static const uint32_t inner_l2table[HNS3_L2TBL_NUM] = {
1363 RTE_PTYPE_INNER_L2_ETHER,
1364 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1365 RTE_PTYPE_INNER_L2_ETHER_QINQ,
1369 static const uint32_t inner_l3table[HNS3_L3TBL_NUM] = {
1370 RTE_PTYPE_INNER_L3_IPV4,
1371 RTE_PTYPE_INNER_L3_IPV6,
1373 RTE_PTYPE_INNER_L2_ETHER,
1374 RTE_PTYPE_INNER_L3_IPV4_EXT,
1375 RTE_PTYPE_INNER_L3_IPV6_EXT,
1376 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1379 static const uint32_t inner_l4table[HNS3_L4TBL_NUM] = {
1380 RTE_PTYPE_INNER_L4_UDP,
1381 RTE_PTYPE_INNER_L4_TCP,
1382 RTE_PTYPE_TUNNEL_GRE,
1383 RTE_PTYPE_INNER_L4_SCTP,
1385 RTE_PTYPE_INNER_L4_ICMP,
1386 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1389 static const uint32_t ol3table[HNS3_OL3TBL_NUM] = {
1393 RTE_PTYPE_L3_IPV4_EXT,
1394 RTE_PTYPE_L3_IPV6_EXT,
1395 0, 0, 0, 0, 0, 0, 0, 0, 0,
1399 static const uint32_t ol4table[HNS3_OL4TBL_NUM] = {
1401 RTE_PTYPE_TUNNEL_VXLAN,
1402 RTE_PTYPE_TUNNEL_NVGRE,
1403 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1406 l2id = hns3_get_field(pkt_info, HNS3_RXD_STRP_TAGP_M,
1407 HNS3_RXD_STRP_TAGP_S);
1408 l3id = hns3_get_field(pkt_info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
1409 l4id = hns3_get_field(pkt_info, HNS3_RXD_L4ID_M, HNS3_RXD_L4ID_S);
1410 ol3id = hns3_get_field(ol_info, HNS3_RXD_OL3ID_M, HNS3_RXD_OL3ID_S);
1411 ol4id = hns3_get_field(ol_info, HNS3_RXD_OL4ID_M, HNS3_RXD_OL4ID_S);
1413 if (ol4table[ol4id])
1414 pkt_type |= (inner_l2table[l2id] | inner_l3table[l3id] |
1415 inner_l4table[l4id] | ol3table[ol3id] |
1418 pkt_type |= (l2table[l2id] | l3table[l3id] | l4table[l4id]);
1423 hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1425 static const uint32_t ptypes[] = {
1427 RTE_PTYPE_L2_ETHER_VLAN,
1428 RTE_PTYPE_L2_ETHER_QINQ,
1429 RTE_PTYPE_L2_ETHER_LLDP,
1430 RTE_PTYPE_L2_ETHER_ARP,
1432 RTE_PTYPE_L3_IPV4_EXT,
1434 RTE_PTYPE_L3_IPV6_EXT,
1440 RTE_PTYPE_TUNNEL_GRE,
1444 if (dev->rx_pkt_burst == hns3_recv_pkts)
1451 hns3_clean_rx_buffers(struct hns3_rx_queue *rxq, int count)
1453 rxq->next_to_use += count;
1454 if (rxq->next_to_use >= rxq->nb_rx_desc)
1455 rxq->next_to_use -= rxq->nb_rx_desc;
1457 hns3_write_dev(rxq, HNS3_RING_RX_HEAD_REG, count);
1461 hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,
1462 uint32_t bd_base_info, uint32_t l234_info,
1463 uint32_t *cksum_err)
1467 if (unlikely(l234_info & BIT(HNS3_RXD_L2E_B))) {
1472 if (unlikely(rxm->pkt_len == 0 ||
1473 (l234_info & BIT(HNS3_RXD_TRUNCAT_B)))) {
1474 rxq->pkt_len_errors++;
1478 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B)) {
1479 if (unlikely(l234_info & BIT(HNS3_RXD_L3E_B))) {
1480 rxm->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1481 rxq->l3_csum_erros++;
1482 tmp |= HNS3_L3_CKSUM_ERR;
1485 if (unlikely(l234_info & BIT(HNS3_RXD_L4E_B))) {
1486 rxm->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1487 rxq->l4_csum_erros++;
1488 tmp |= HNS3_L4_CKSUM_ERR;
1491 if (unlikely(l234_info & BIT(HNS3_RXD_OL3E_B))) {
1492 rxq->ol3_csum_erros++;
1493 tmp |= HNS3_OUTER_L3_CKSUM_ERR;
1496 if (unlikely(l234_info & BIT(HNS3_RXD_OL4E_B))) {
1497 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
1498 rxq->ol4_csum_erros++;
1499 tmp |= HNS3_OUTER_L4_CKSUM_ERR;
1508 hns3_rx_set_cksum_flag(struct rte_mbuf *rxm, uint64_t packet_type,
1509 const uint32_t cksum_err)
1511 if (unlikely((packet_type & RTE_PTYPE_TUNNEL_MASK))) {
1512 if (likely(packet_type & RTE_PTYPE_INNER_L3_MASK) &&
1513 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
1514 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1515 if (likely(packet_type & RTE_PTYPE_INNER_L4_MASK) &&
1516 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
1517 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1518 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
1519 (cksum_err & HNS3_OUTER_L4_CKSUM_ERR) == 0)
1520 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
1522 if (likely(packet_type & RTE_PTYPE_L3_MASK) &&
1523 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
1524 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1525 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
1526 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
1527 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1532 hns3_rxd_to_vlan_tci(struct hns3_rx_queue *rxq, struct rte_mbuf *mb,
1533 uint32_t l234_info, const struct hns3_desc *rxd)
1535 #define HNS3_STRP_STATUS_NUM 0x4
1537 #define HNS3_NO_STRP_VLAN_VLD 0x0
1538 #define HNS3_INNER_STRP_VLAN_VLD 0x1
1539 #define HNS3_OUTER_STRP_VLAN_VLD 0x2
1540 uint32_t strip_status;
1541 uint32_t report_mode;
1544 * Since HW limitation, the vlan tag will always be inserted into RX
1545 * descriptor when strip the tag from packet, driver needs to determine
1546 * reporting which tag to mbuf according to the PVID configuration
1547 * and vlan striped status.
1549 static const uint32_t report_type[][HNS3_STRP_STATUS_NUM] = {
1551 HNS3_NO_STRP_VLAN_VLD,
1552 HNS3_OUTER_STRP_VLAN_VLD,
1553 HNS3_INNER_STRP_VLAN_VLD,
1554 HNS3_OUTER_STRP_VLAN_VLD
1557 HNS3_NO_STRP_VLAN_VLD,
1558 HNS3_NO_STRP_VLAN_VLD,
1559 HNS3_NO_STRP_VLAN_VLD,
1560 HNS3_INNER_STRP_VLAN_VLD
1563 strip_status = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,
1564 HNS3_RXD_STRP_TAGP_S);
1565 report_mode = report_type[rxq->pvid_state][strip_status];
1566 switch (report_mode) {
1567 case HNS3_NO_STRP_VLAN_VLD:
1570 case HNS3_INNER_STRP_VLAN_VLD:
1571 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1572 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.vlan_tag);
1574 case HNS3_OUTER_STRP_VLAN_VLD:
1575 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1576 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.ot_vlan_tag);
1582 hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1584 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
1585 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
1586 struct hns3_rx_queue *rxq; /* RX queue */
1587 struct hns3_entry *sw_ring;
1588 struct hns3_entry *rxe;
1589 struct rte_mbuf *first_seg;
1590 struct rte_mbuf *last_seg;
1591 struct hns3_desc rxd;
1592 struct rte_mbuf *nmb; /* pointer of the new mbuf */
1593 struct rte_mbuf *rxm;
1594 struct rte_eth_dev *dev;
1595 uint32_t bd_base_info;
1612 rx_id = rxq->next_to_clean;
1613 rx_ring = rxq->rx_ring;
1614 first_seg = rxq->pkt_first_seg;
1615 last_seg = rxq->pkt_last_seg;
1616 sw_ring = rxq->sw_ring;
1618 while (nb_rx < nb_pkts) {
1619 rxdp = &rx_ring[rx_id];
1620 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
1621 if (unlikely(!hns3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
1624 * The interactive process between software and hardware of
1625 * receiving a new packet in hns3 network engine:
1626 * 1. Hardware network engine firstly writes the packet content
1627 * to the memory pointed by the 'addr' field of the Rx Buffer
1628 * Descriptor, secondly fills the result of parsing the
1629 * packet include the valid field into the Rx Buffer
1630 * Descriptor in one write operation.
1631 * 2. Driver reads the Rx BD's valid field in the loop to check
1632 * whether it's valid, if valid then assign a new address to
1633 * the addr field, clear the valid field, get the other
1634 * information of the packet by parsing Rx BD's other fields,
1635 * finally write back the number of Rx BDs processed by the
1636 * driver to the HNS3_RING_RX_HEAD_REG register to inform
1638 * In the above process, the ordering is very important. We must
1639 * make sure that CPU read Rx BD's other fields only after the
1642 * There are two type of re-ordering: compiler re-ordering and
1643 * CPU re-ordering under the ARMv8 architecture.
1644 * 1. we use volatile to deal with compiler re-ordering, so you
1645 * can see that rx_ring/rxdp defined with volatile.
1646 * 2. we commonly use memory barrier to deal with CPU
1647 * re-ordering, but the cost is high.
1649 * In order to solve the high cost of using memory barrier, we
1650 * use the data dependency order under the ARMv8 architecture,
1653 * instr02: load B <- A
1654 * the instr02 will always execute after instr01.
1656 * To construct the data dependency ordering, we use the
1657 * following assignment:
1658 * rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
1659 * (1u<<HNS3_RXD_VLD_B)]
1660 * Using gcc compiler under the ARMv8 architecture, the related
1661 * assembly code example as follows:
1662 * note: (1u << HNS3_RXD_VLD_B) equal 0x10
1663 * instr01: ldr w26, [x22, #28] --read bd_base_info
1664 * instr02: and w0, w26, #0x10 --calc bd_base_info & 0x10
1665 * instr03: sub w0, w0, #0x10 --calc (bd_base_info &
1667 * instr04: add x0, x22, x0, lsl #5 --calc copy source addr
1668 * instr05: ldp x2, x3, [x0]
1669 * instr06: stp x2, x3, [x29, #256] --copy BD's [0 ~ 15]B
1670 * instr07: ldp x4, x5, [x0, #16]
1671 * instr08: stp x4, x5, [x29, #272] --copy BD's [16 ~ 31]B
1672 * the instr05~08 depend on x0's value, x0 depent on w26's
1673 * value, the w26 is the bd_base_info, this form the data
1674 * dependency ordering.
1675 * note: if BD is valid, (bd_base_info & (1u<<HNS3_RXD_VLD_B)) -
1676 * (1u<<HNS3_RXD_VLD_B) will always zero, so the
1677 * assignment is correct.
1679 * So we use the data dependency ordering instead of memory
1680 * barrier to improve receive performance.
1682 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
1683 (1u << HNS3_RXD_VLD_B)];
1685 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1686 if (unlikely(nmb == NULL)) {
1687 dev = &rte_eth_devices[rxq->port_id];
1688 dev->data->rx_mbuf_alloc_failed++;
1693 rxe = &sw_ring[rx_id];
1695 if (unlikely(rx_id == rxq->nb_rx_desc))
1698 rte_prefetch0(sw_ring[rx_id].mbuf);
1699 if ((rx_id & 0x3) == 0) {
1700 rte_prefetch0(&rx_ring[rx_id]);
1701 rte_prefetch0(&sw_ring[rx_id]);
1707 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1708 rxdp->rx.bd_base_info = 0;
1709 rxdp->addr = dma_addr;
1711 /* Load remained descriptor data and extract necessary fields */
1712 data_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.size));
1713 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
1714 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
1716 if (first_seg == NULL) {
1718 first_seg->nb_segs = 1;
1720 first_seg->nb_segs++;
1721 last_seg->next = rxm;
1724 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1725 rxm->data_len = data_len;
1727 if (!hns3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
1732 /* The last buffer of the received packet */
1733 pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.pkt_len));
1734 first_seg->pkt_len = pkt_len;
1735 first_seg->port = rxq->port_id;
1736 first_seg->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
1737 first_seg->ol_flags = PKT_RX_RSS_HASH;
1738 if (unlikely(hns3_get_bit(bd_base_info, HNS3_RXD_LUM_B))) {
1739 first_seg->hash.fdir.hi =
1740 rte_le_to_cpu_32(rxd.rx.fd_id);
1741 first_seg->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1745 gro_size = hns3_get_field(bd_base_info, HNS3_RXD_GRO_SIZE_M,
1746 HNS3_RXD_GRO_SIZE_S);
1747 if (gro_size != 0) {
1748 first_seg->ol_flags |= PKT_RX_LRO;
1749 first_seg->tso_segsz = gro_size;
1752 ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info,
1753 l234_info, &cksum_err);
1757 first_seg->packet_type = rxd_pkt_info_to_pkt_type(l234_info,
1760 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B))
1761 hns3_rx_set_cksum_flag(first_seg,
1762 first_seg->packet_type,
1764 hns3_rxd_to_vlan_tci(rxq, first_seg, l234_info, &rxd);
1766 rx_pkts[nb_rx++] = first_seg;
1770 rte_pktmbuf_free(first_seg);
1774 rxq->next_to_clean = rx_id;
1775 rxq->pkt_first_seg = first_seg;
1776 rxq->pkt_last_seg = last_seg;
1778 nb_rx_bd = nb_rx_bd + rxq->nb_rx_hold;
1779 if (nb_rx_bd > rxq->rx_free_thresh) {
1780 hns3_clean_rx_buffers(rxq, nb_rx_bd);
1783 rxq->nb_rx_hold = nb_rx_bd;
1789 hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1790 unsigned int socket_id, const struct rte_eth_txconf *conf)
1792 struct hns3_adapter *hns = dev->data->dev_private;
1793 struct hns3_hw *hw = &hns->hw;
1794 struct hns3_queue_info q_info;
1795 struct hns3_tx_queue *txq;
1798 if (dev->data->dev_started) {
1799 hns3_err(hw, "tx_queue_setup after dev_start no supported");
1803 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1804 nb_desc % HNS3_ALIGN_RING_DESC) {
1805 hns3_err(hw, "Number (%u) of tx descriptors is invalid",
1810 if (dev->data->tx_queues[idx] != NULL) {
1811 hns3_tx_queue_release(dev->data->tx_queues[idx]);
1812 dev->data->tx_queues[idx] = NULL;
1816 q_info.socket_id = socket_id;
1817 q_info.nb_desc = nb_desc;
1818 q_info.type = "hns3 TX queue";
1819 q_info.ring_name = "tx_ring";
1820 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
1823 "Failed to alloc mem and reserve DMA mem for tx ring!");
1827 txq->tx_deferred_start = conf->tx_deferred_start;
1828 tx_entry_len = sizeof(struct hns3_entry) * txq->nb_tx_desc;
1829 txq->sw_ring = rte_zmalloc_socket("hns3 TX sw ring", tx_entry_len,
1830 RTE_CACHE_LINE_SIZE, socket_id);
1831 if (txq->sw_ring == NULL) {
1832 hns3_err(hw, "Failed to allocate memory for tx sw ring!");
1833 hns3_tx_queue_release(txq);
1838 txq->next_to_use = 0;
1839 txq->next_to_clean = 0;
1840 txq->tx_bd_ready = txq->nb_tx_desc - 1;
1841 txq->port_id = dev->data->port_id;
1842 txq->pvid_state = hw->port_base_vlan_cfg.state;
1843 txq->configured = true;
1844 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1845 idx * HNS3_TQP_REG_SIZE);
1846 txq->over_length_pkt_cnt = 0;
1847 txq->exceed_limit_bd_pkt_cnt = 0;
1848 txq->exceed_limit_bd_reassem_fail = 0;
1849 txq->unsupported_tunnel_pkt_cnt = 0;
1850 txq->queue_full_cnt = 0;
1851 txq->pkt_padding_fail_cnt = 0;
1852 rte_spinlock_lock(&hw->lock);
1853 dev->data->tx_queues[idx] = txq;
1854 rte_spinlock_unlock(&hw->lock);
1860 hns3_queue_xmit(struct hns3_tx_queue *txq, uint32_t buf_num)
1862 hns3_write_dev(txq, HNS3_RING_TX_TAIL_REG, buf_num);
1866 hns3_tx_free_useless_buffer(struct hns3_tx_queue *txq)
1868 uint16_t tx_next_clean = txq->next_to_clean;
1869 uint16_t tx_next_use = txq->next_to_use;
1870 uint16_t tx_bd_ready = txq->tx_bd_ready;
1871 uint16_t tx_bd_max = txq->nb_tx_desc;
1872 struct hns3_entry *tx_bak_pkt = &txq->sw_ring[tx_next_clean];
1873 struct hns3_desc *desc = &txq->tx_ring[tx_next_clean];
1874 struct rte_mbuf *mbuf;
1876 while ((!hns3_get_bit(desc->tx.tp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B)) &&
1877 tx_next_use != tx_next_clean) {
1878 mbuf = tx_bak_pkt->mbuf;
1880 rte_pktmbuf_free_seg(mbuf);
1881 tx_bak_pkt->mbuf = NULL;
1889 if (tx_next_clean >= tx_bd_max) {
1891 desc = txq->tx_ring;
1892 tx_bak_pkt = txq->sw_ring;
1896 txq->next_to_clean = tx_next_clean;
1897 txq->tx_bd_ready = tx_bd_ready;
1901 hns3_tso_proc_tunnel(struct hns3_desc *desc, uint64_t ol_flags,
1902 struct rte_mbuf *rxm, uint8_t *l2_len)
1908 tun_flags = ol_flags & PKT_TX_TUNNEL_MASK;
1912 otmp = rte_le_to_cpu_32(desc->tx.ol_type_vlan_len_msec);
1913 switch (tun_flags) {
1914 case PKT_TX_TUNNEL_GENEVE:
1915 case PKT_TX_TUNNEL_VXLAN:
1916 *l2_len = rxm->l2_len - RTE_ETHER_VXLAN_HLEN;
1918 case PKT_TX_TUNNEL_GRE:
1920 * OL4 header size, defined in 4 Bytes, it contains outer
1921 * L4(GRE) length and tunneling length.
1923 ol4_len = hns3_get_field(otmp, HNS3_TXD_L4LEN_M,
1925 *l2_len = rxm->l2_len - (ol4_len << HNS3_L4_LEN_UNIT);
1928 /* For non UDP / GRE tunneling, drop the tunnel packet */
1931 hns3_set_field(otmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
1932 rxm->outer_l2_len >> HNS3_L2_LEN_UNIT);
1933 desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(otmp);
1939 hns3_config_gro(struct hns3_hw *hw, bool en)
1941 struct hns3_cfg_gro_status_cmd *req;
1942 struct hns3_cmd_desc desc;
1945 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1946 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1948 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1950 ret = hns3_cmd_send(hw, &desc, 1);
1952 hns3_err(hw, "%s hardware GRO failed, ret = %d",
1953 en ? "enable" : "disable", ret);
1959 hns3_restore_gro_conf(struct hns3_hw *hw)
1965 offloads = hw->data->dev_conf.rxmode.offloads;
1966 gro_en = offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
1967 ret = hns3_config_gro(hw, gro_en);
1969 hns3_err(hw, "restore hardware GRO to %s failed, ret = %d",
1970 gro_en ? "enabled" : "disabled", ret);
1976 hns3_pkt_is_tso(struct rte_mbuf *m)
1978 return (m->tso_segsz != 0 && m->ol_flags & PKT_TX_TCP_SEG);
1982 hns3_set_tso(struct hns3_desc *desc,
1983 uint64_t ol_flags, struct rte_mbuf *rxm)
1985 uint32_t paylen, hdr_len;
1987 uint8_t l2_len = rxm->l2_len;
1989 if (!hns3_pkt_is_tso(rxm))
1992 if (hns3_tso_proc_tunnel(desc, ol_flags, rxm, &l2_len))
1995 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len;
1996 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
1997 rxm->outer_l2_len + rxm->outer_l3_len : 0;
1998 paylen = rxm->pkt_len - hdr_len;
1999 if (paylen <= rxm->tso_segsz)
2002 tmp = rte_le_to_cpu_32(desc->tx.type_cs_vlan_tso_len);
2003 hns3_set_bit(tmp, HNS3_TXD_TSO_B, 1);
2004 hns3_set_bit(tmp, HNS3_TXD_L3CS_B, 1);
2005 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S, HNS3_L4T_TCP);
2006 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2007 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2008 sizeof(struct rte_tcp_hdr) >> HNS3_L4_LEN_UNIT);
2009 hns3_set_field(tmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2010 l2_len >> HNS3_L2_LEN_UNIT);
2011 desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp);
2012 desc->tx.mss = rte_cpu_to_le_16(rxm->tso_segsz);
2016 fill_desc(struct hns3_tx_queue *txq, uint16_t tx_desc_id, struct rte_mbuf *rxm,
2017 bool first, int offset)
2019 struct hns3_desc *tx_ring = txq->tx_ring;
2020 struct hns3_desc *desc = &tx_ring[tx_desc_id];
2021 uint8_t frag_end = rxm->next == NULL ? 1 : 0;
2022 uint64_t ol_flags = rxm->ol_flags;
2023 uint16_t size = rxm->data_len;
2029 desc->addr = rte_mbuf_data_iova(rxm) + offset;
2030 desc->tx.send_size = rte_cpu_to_le_16(size);
2031 hns3_set_bit(rrcfv, HNS3_TXD_VLD_B, 1);
2034 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len;
2035 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
2036 rxm->outer_l2_len + rxm->outer_l3_len : 0;
2037 paylen = rxm->pkt_len - hdr_len;
2038 desc->tx.paylen = rte_cpu_to_le_32(paylen);
2039 hns3_set_tso(desc, ol_flags, rxm);
2042 hns3_set_bit(rrcfv, HNS3_TXD_FE_B, frag_end);
2043 desc->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(rrcfv);
2046 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
2047 tmp = rte_le_to_cpu_32(desc->tx.type_cs_vlan_tso_len);
2048 hns3_set_bit(tmp, HNS3_TXD_VLAN_B, 1);
2049 desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp);
2050 desc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci);
2053 if (ol_flags & PKT_TX_QINQ_PKT) {
2054 tmp = rte_le_to_cpu_32(desc->tx.ol_type_vlan_len_msec);
2055 hns3_set_bit(tmp, HNS3_TXD_OVLAN_B, 1);
2056 desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp);
2057 desc->tx.outer_vlan_tag =
2058 rte_cpu_to_le_16(rxm->vlan_tci_outer);
2064 hns3_tx_alloc_mbufs(struct hns3_tx_queue *txq, struct rte_mempool *mb_pool,
2065 uint16_t nb_new_buf, struct rte_mbuf **alloc_mbuf)
2067 struct rte_mbuf *new_mbuf = NULL;
2068 struct rte_eth_dev *dev;
2069 struct rte_mbuf *temp;
2073 /* Allocate enough mbufs */
2074 for (i = 0; i < nb_new_buf; i++) {
2075 temp = rte_pktmbuf_alloc(mb_pool);
2076 if (unlikely(temp == NULL)) {
2077 dev = &rte_eth_devices[txq->port_id];
2078 hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079 hns3_err(hw, "Failed to alloc TX mbuf port_id=%d,"
2080 "queue_id=%d in reassemble tx pkts.",
2081 txq->port_id, txq->queue_id);
2082 rte_pktmbuf_free(new_mbuf);
2085 temp->next = new_mbuf;
2089 if (new_mbuf == NULL)
2092 new_mbuf->nb_segs = nb_new_buf;
2093 *alloc_mbuf = new_mbuf;
2099 hns3_reassemble_tx_pkts(void *tx_queue, struct rte_mbuf *tx_pkt,
2100 struct rte_mbuf **new_pkt)
2102 struct hns3_tx_queue *txq = tx_queue;
2103 struct rte_mempool *mb_pool;
2104 struct rte_mbuf *new_mbuf;
2105 struct rte_mbuf *temp_new;
2106 struct rte_mbuf *temp;
2107 uint16_t last_buf_len;
2108 uint16_t nb_new_buf;
2119 mb_pool = tx_pkt->pool;
2120 buf_size = tx_pkt->buf_len - RTE_PKTMBUF_HEADROOM;
2121 nb_new_buf = (tx_pkt->pkt_len - 1) / buf_size + 1;
2123 last_buf_len = tx_pkt->pkt_len % buf_size;
2124 if (last_buf_len == 0)
2125 last_buf_len = buf_size;
2127 /* Allocate enough mbufs */
2128 ret = hns3_tx_alloc_mbufs(txq, mb_pool, nb_new_buf, &new_mbuf);
2132 /* Copy the original packet content to the new mbufs */
2134 s = rte_pktmbuf_mtod(temp, char *);
2135 len_s = temp->data_len;
2136 temp_new = new_mbuf;
2137 for (i = 0; i < nb_new_buf; i++) {
2138 d = rte_pktmbuf_mtod(temp_new, char *);
2139 if (i < nb_new_buf - 1)
2142 buf_len = last_buf_len;
2146 len = RTE_MIN(len_s, len_d);
2150 len_d = len_d - len;
2151 len_s = len_s - len;
2157 s = rte_pktmbuf_mtod(temp, char *);
2158 len_s = temp->data_len;
2162 temp_new->data_len = buf_len;
2163 temp_new = temp_new->next;
2166 /* free original mbufs */
2167 rte_pktmbuf_free(tx_pkt);
2169 *new_pkt = new_mbuf;
2175 hns3_parse_outer_params(uint64_t ol_flags, uint32_t *ol_type_vlan_len_msec)
2177 uint32_t tmp = *ol_type_vlan_len_msec;
2179 /* (outer) IP header type */
2180 if (ol_flags & PKT_TX_OUTER_IPV4) {
2181 /* OL3 header size, defined in 4 bytes */
2182 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2183 sizeof(struct rte_ipv4_hdr) >> HNS3_L3_LEN_UNIT);
2184 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2185 hns3_set_field(tmp, HNS3_TXD_OL3T_M,
2186 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_CSUM);
2188 hns3_set_field(tmp, HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
2189 HNS3_OL3T_IPV4_NO_CSUM);
2190 } else if (ol_flags & PKT_TX_OUTER_IPV6) {
2191 hns3_set_field(tmp, HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
2193 /* OL3 header size, defined in 4 bytes */
2194 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2195 sizeof(struct rte_ipv6_hdr) >> HNS3_L3_LEN_UNIT);
2198 *ol_type_vlan_len_msec = tmp;
2202 hns3_parse_inner_params(uint64_t ol_flags, uint32_t *ol_type_vlan_len_msec,
2203 struct rte_net_hdr_lens *hdr_lens)
2205 uint32_t tmp = *ol_type_vlan_len_msec;
2208 /* OL2 header size, defined in 2 bytes */
2209 hns3_set_field(tmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2210 sizeof(struct rte_ether_hdr) >> HNS3_L2_LEN_UNIT);
2212 /* L4TUNT: L4 Tunneling Type */
2213 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2214 case PKT_TX_TUNNEL_GENEVE:
2215 case PKT_TX_TUNNEL_VXLAN:
2216 /* MAC in UDP tunnelling packet, include VxLAN */
2217 hns3_set_field(tmp, HNS3_TXD_TUNTYPE_M, HNS3_TXD_TUNTYPE_S,
2218 HNS3_TUN_MAC_IN_UDP);
2220 * OL4 header size, defined in 4 Bytes, it contains outer
2221 * L4(UDP) length and tunneling length.
2223 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2224 (uint8_t)RTE_ETHER_VXLAN_HLEN >>
2227 case PKT_TX_TUNNEL_GRE:
2228 hns3_set_field(tmp, HNS3_TXD_TUNTYPE_M, HNS3_TXD_TUNTYPE_S,
2231 * OL4 header size, defined in 4 Bytes, it contains outer
2232 * L4(GRE) length and tunneling length.
2234 l4_len = hdr_lens->l4_len + hdr_lens->tunnel_len;
2235 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2236 l4_len >> HNS3_L4_LEN_UNIT);
2239 /* For non UDP / GRE tunneling, drop the tunnel packet */
2243 *ol_type_vlan_len_msec = tmp;
2249 hns3_parse_tunneling_params(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
2251 struct rte_net_hdr_lens *hdr_lens)
2253 struct hns3_desc *tx_ring = txq->tx_ring;
2254 struct hns3_desc *desc = &tx_ring[tx_desc_id];
2258 hns3_parse_outer_params(ol_flags, &value);
2259 ret = hns3_parse_inner_params(ol_flags, &value, hdr_lens);
2263 desc->tx.ol_type_vlan_len_msec |= rte_cpu_to_le_32(value);
2269 hns3_parse_l3_cksum_params(uint64_t ol_flags, uint32_t *type_cs_vlan_tso_len)
2273 /* Enable L3 checksum offloads */
2274 if (ol_flags & PKT_TX_IPV4) {
2275 tmp = *type_cs_vlan_tso_len;
2276 hns3_set_field(tmp, HNS3_TXD_L3T_M, HNS3_TXD_L3T_S,
2278 /* inner(/normal) L3 header size, defined in 4 bytes */
2279 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2280 sizeof(struct rte_ipv4_hdr) >> HNS3_L3_LEN_UNIT);
2281 if (ol_flags & PKT_TX_IP_CKSUM)
2282 hns3_set_bit(tmp, HNS3_TXD_L3CS_B, 1);
2283 *type_cs_vlan_tso_len = tmp;
2284 } else if (ol_flags & PKT_TX_IPV6) {
2285 tmp = *type_cs_vlan_tso_len;
2286 /* L3T, IPv6 don't do checksum */
2287 hns3_set_field(tmp, HNS3_TXD_L3T_M, HNS3_TXD_L3T_S,
2289 /* inner(/normal) L3 header size, defined in 4 bytes */
2290 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2291 sizeof(struct rte_ipv6_hdr) >> HNS3_L3_LEN_UNIT);
2292 *type_cs_vlan_tso_len = tmp;
2297 hns3_parse_l4_cksum_params(uint64_t ol_flags, uint32_t *type_cs_vlan_tso_len)
2301 /* Enable L4 checksum offloads */
2302 switch (ol_flags & PKT_TX_L4_MASK) {
2303 case PKT_TX_TCP_CKSUM:
2304 tmp = *type_cs_vlan_tso_len;
2305 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
2307 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2308 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2309 sizeof(struct rte_tcp_hdr) >> HNS3_L4_LEN_UNIT);
2310 *type_cs_vlan_tso_len = tmp;
2312 case PKT_TX_UDP_CKSUM:
2313 tmp = *type_cs_vlan_tso_len;
2314 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
2316 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2317 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2318 sizeof(struct rte_udp_hdr) >> HNS3_L4_LEN_UNIT);
2319 *type_cs_vlan_tso_len = tmp;
2321 case PKT_TX_SCTP_CKSUM:
2322 tmp = *type_cs_vlan_tso_len;
2323 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
2325 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2326 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2327 sizeof(struct rte_sctp_hdr) >> HNS3_L4_LEN_UNIT);
2328 *type_cs_vlan_tso_len = tmp;
2336 hns3_txd_enable_checksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
2339 struct hns3_desc *tx_ring = txq->tx_ring;
2340 struct hns3_desc *desc = &tx_ring[tx_desc_id];
2343 /* inner(/normal) L2 header size, defined in 2 bytes */
2344 hns3_set_field(value, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2345 sizeof(struct rte_ether_hdr) >> HNS3_L2_LEN_UNIT);
2347 hns3_parse_l3_cksum_params(ol_flags, &value);
2348 hns3_parse_l4_cksum_params(ol_flags, &value);
2350 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(value);
2354 hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num)
2356 struct rte_mbuf *m_first = tx_pkts;
2357 struct rte_mbuf *m_last = tx_pkts;
2358 uint32_t tot_len = 0;
2363 * Hardware requires that the sum of the data length of every 8
2364 * consecutive buffers is greater than MSS in hns3 network engine.
2365 * We simplify it by ensuring pkt_headlen + the first 8 consecutive
2366 * frags greater than gso header len + mss, and the remaining 7
2367 * consecutive frags greater than MSS except the last 7 frags.
2369 if (bd_num <= HNS3_MAX_NON_TSO_BD_PER_PKT)
2372 for (i = 0; m_last && i < HNS3_MAX_NON_TSO_BD_PER_PKT - 1;
2373 i++, m_last = m_last->next)
2374 tot_len += m_last->data_len;
2379 /* ensure the first 8 frags is greater than mss + header */
2380 hdr_len = tx_pkts->l2_len + tx_pkts->l3_len + tx_pkts->l4_len;
2381 hdr_len += (tx_pkts->ol_flags & PKT_TX_TUNNEL_MASK) ?
2382 tx_pkts->outer_l2_len + tx_pkts->outer_l3_len : 0;
2383 if (tot_len + m_last->data_len < tx_pkts->tso_segsz + hdr_len)
2387 * ensure the sum of the data length of every 7 consecutive buffer
2388 * is greater than mss except the last one.
2390 for (i = 0; m_last && i < bd_num - HNS3_MAX_NON_TSO_BD_PER_PKT; i++) {
2391 tot_len -= m_first->data_len;
2392 tot_len += m_last->data_len;
2394 if (tot_len < tx_pkts->tso_segsz)
2397 m_first = m_first->next;
2398 m_last = m_last->next;
2405 hns3_outer_header_cksum_prepare(struct rte_mbuf *m)
2407 uint64_t ol_flags = m->ol_flags;
2408 struct rte_ipv4_hdr *ipv4_hdr;
2409 struct rte_udp_hdr *udp_hdr;
2410 uint32_t paylen, hdr_len;
2412 if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6)))
2415 if (ol_flags & PKT_TX_IPV4) {
2416 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2419 if (ol_flags & PKT_TX_IP_CKSUM)
2420 ipv4_hdr->hdr_checksum = 0;
2423 if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_UDP_CKSUM &&
2424 ol_flags & PKT_TX_TCP_SEG) {
2425 hdr_len = m->l2_len + m->l3_len + m->l4_len;
2426 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
2427 m->outer_l2_len + m->outer_l3_len : 0;
2428 paylen = m->pkt_len - hdr_len;
2429 if (paylen <= m->tso_segsz)
2431 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
2434 udp_hdr->dgram_cksum = 0;
2439 hns3_check_tso_pkt_valid(struct rte_mbuf *m)
2441 uint32_t tmp_data_len_sum = 0;
2442 uint16_t nb_buf = m->nb_segs;
2443 uint32_t paylen, hdr_len;
2444 struct rte_mbuf *m_seg;
2447 if (nb_buf > HNS3_MAX_TSO_BD_PER_PKT)
2450 hdr_len = m->l2_len + m->l3_len + m->l4_len;
2451 hdr_len += (m->ol_flags & PKT_TX_TUNNEL_MASK) ?
2452 m->outer_l2_len + m->outer_l3_len : 0;
2453 if (hdr_len > HNS3_MAX_TSO_HDR_SIZE)
2456 paylen = m->pkt_len - hdr_len;
2457 if (paylen > HNS3_MAX_BD_PAYLEN)
2461 * The TSO header (include outer and inner L2, L3 and L4 header)
2462 * should be provided by three descriptors in maximum in hns3 network
2466 for (i = 0; m_seg != NULL && i < HNS3_MAX_TSO_HDR_BD_NUM && i < nb_buf;
2467 i++, m_seg = m_seg->next) {
2468 tmp_data_len_sum += m_seg->data_len;
2471 if (hdr_len > tmp_data_len_sum)
2477 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2479 hns3_vld_vlan_chk(struct hns3_tx_queue *txq, struct rte_mbuf *m)
2481 struct rte_ether_hdr *eh;
2482 struct rte_vlan_hdr *vh;
2484 if (!txq->pvid_state)
2488 * Due to hardware limitations, we only support two-layer VLAN hardware
2489 * offload in Tx direction based on hns3 network engine, so when PVID is
2490 * enabled, QinQ insert is no longer supported.
2491 * And when PVID is enabled, in the following two cases:
2492 * i) packets with more than two VLAN tags.
2493 * ii) packets with one VLAN tag while the hardware VLAN insert is
2495 * The packets will be regarded as abnormal packets and discarded by
2496 * hardware in Tx direction. For debugging purposes, a validation check
2497 * for these types of packets is added to the '.tx_pkt_prepare' ops
2498 * implementation function named hns3_prep_pkts to inform users that
2499 * these packets will be discarded.
2501 if (m->ol_flags & PKT_TX_QINQ_PKT)
2504 eh = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
2505 if (eh->ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
2506 if (m->ol_flags & PKT_TX_VLAN_PKT)
2509 /* Ensure the incoming packet is not a QinQ packet */
2510 vh = (struct rte_vlan_hdr *)(eh + 1);
2511 if (vh->eth_proto == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN))
2520 hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2527 for (i = 0; i < nb_pkts; i++) {
2530 if (hns3_pkt_is_tso(m) &&
2531 (hns3_pkt_need_linearized(m, m->nb_segs) ||
2532 hns3_check_tso_pkt_valid(m))) {
2537 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2538 ret = rte_validate_tx_offload(m);
2544 if (hns3_vld_vlan_chk(tx_queue, m)) {
2549 ret = rte_net_intel_cksum_prepare(m);
2555 hns3_outer_header_cksum_prepare(m);
2562 hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
2563 const struct rte_mbuf *m, struct rte_net_hdr_lens *hdr_lens)
2565 /* Fill in tunneling parameters if necessary */
2566 if (m->ol_flags & PKT_TX_TUNNEL_MASK) {
2567 (void)rte_net_get_ptype(m, hdr_lens, RTE_PTYPE_ALL_MASK);
2568 if (hns3_parse_tunneling_params(txq, tx_desc_id, m->ol_flags,
2570 txq->unsupported_tunnel_pkt_cnt++;
2574 /* Enable checksum offloading */
2575 if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK)
2576 hns3_txd_enable_checksum(txq, tx_desc_id, m->ol_flags);
2582 hns3_check_non_tso_pkt(uint16_t nb_buf, struct rte_mbuf **m_seg,
2583 struct rte_mbuf *tx_pkt, struct hns3_tx_queue *txq)
2585 struct rte_mbuf *new_pkt;
2588 if (hns3_pkt_is_tso(*m_seg))
2592 * If packet length is greater than HNS3_MAX_FRAME_LEN
2593 * driver support, the packet will be ignored.
2595 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) > HNS3_MAX_FRAME_LEN)) {
2596 txq->over_length_pkt_cnt++;
2600 if (unlikely(nb_buf > HNS3_MAX_NON_TSO_BD_PER_PKT)) {
2601 txq->exceed_limit_bd_pkt_cnt++;
2602 ret = hns3_reassemble_tx_pkts(txq, tx_pkt, &new_pkt);
2604 txq->exceed_limit_bd_reassem_fail++;
2614 hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2616 struct rte_net_hdr_lens hdr_lens = {0};
2617 struct hns3_tx_queue *txq = tx_queue;
2618 struct hns3_entry *tx_bak_pkt;
2619 struct rte_mbuf *tx_pkt;
2620 struct rte_mbuf *m_seg;
2621 uint32_t nb_hold = 0;
2622 uint16_t tx_next_use;
2623 uint16_t tx_pkt_num;
2629 /* free useless buffer */
2630 hns3_tx_free_useless_buffer(txq);
2632 tx_next_use = txq->next_to_use;
2633 tx_bd_max = txq->nb_tx_desc;
2634 tx_pkt_num = nb_pkts;
2637 tx_bak_pkt = &txq->sw_ring[tx_next_use];
2638 for (nb_tx = 0; nb_tx < tx_pkt_num; nb_tx++) {
2639 tx_pkt = *tx_pkts++;
2641 nb_buf = tx_pkt->nb_segs;
2643 if (nb_buf > txq->tx_bd_ready) {
2644 txq->queue_full_cnt++;
2652 * If packet length is less than minimum packet size, driver
2655 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) < HNS3_MIN_PKT_SIZE)) {
2659 add_len = HNS3_MIN_PKT_SIZE -
2660 rte_pktmbuf_pkt_len(tx_pkt);
2661 appended = rte_pktmbuf_append(tx_pkt, add_len);
2662 if (appended == NULL) {
2663 txq->pkt_padding_fail_cnt++;
2667 memset(appended, 0, add_len);
2672 if (hns3_check_non_tso_pkt(nb_buf, &m_seg, tx_pkt, txq))
2675 if (hns3_parse_cksum(txq, tx_next_use, m_seg, &hdr_lens))
2680 fill_desc(txq, tx_next_use, m_seg, (i == 0), 0);
2681 tx_bak_pkt->mbuf = m_seg;
2682 m_seg = m_seg->next;
2685 if (tx_next_use >= tx_bd_max) {
2687 tx_bak_pkt = txq->sw_ring;
2691 } while (m_seg != NULL);
2694 txq->next_to_use = tx_next_use;
2695 txq->tx_bd_ready -= i;
2701 hns3_queue_xmit(txq, nb_hold);
2707 hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused,
2708 struct rte_mbuf **pkts __rte_unused,
2709 uint16_t pkts_n __rte_unused)
2714 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)
2716 struct hns3_adapter *hns = eth_dev->data->dev_private;
2718 if (hns->hw.adapter_state == HNS3_NIC_STARTED &&
2719 rte_atomic16_read(&hns->hw.reset.resetting) == 0) {
2720 eth_dev->rx_pkt_burst = hns3_recv_pkts;
2721 eth_dev->tx_pkt_burst = hns3_xmit_pkts;
2722 eth_dev->tx_pkt_prepare = hns3_prep_pkts;
2724 eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst;
2725 eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
2726 eth_dev->tx_pkt_prepare = hns3_dummy_rxtx_burst;