1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #include <rte_bus_pci.h>
6 #include <rte_common.h>
7 #include <rte_cycles.h>
9 #include <ethdev_driver.h>
12 #include <rte_malloc.h>
13 #if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE)
14 #include <rte_cpuflags.h>
17 #include "hns3_ethdev.h"
18 #include "hns3_rxtx.h"
19 #include "hns3_regs.h"
20 #include "hns3_logs.h"
22 #define HNS3_CFG_DESC_NUM(num) ((num) / 8 - 1)
23 #define HNS3_RX_RING_PREFETCTH_MASK 3
26 hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq)
30 /* Note: Fake rx queue will not enter here */
31 if (rxq->sw_ring == NULL)
34 if (rxq->rx_rearm_nb == 0) {
35 for (i = 0; i < rxq->nb_rx_desc; i++) {
36 if (rxq->sw_ring[i].mbuf != NULL) {
37 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
38 rxq->sw_ring[i].mbuf = NULL;
42 for (i = rxq->next_to_use;
43 i != rxq->rx_rearm_start;
44 i = (i + 1) % rxq->nb_rx_desc) {
45 if (rxq->sw_ring[i].mbuf != NULL) {
46 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
47 rxq->sw_ring[i].mbuf = NULL;
52 for (i = 0; i < rxq->bulk_mbuf_num; i++)
53 rte_pktmbuf_free_seg(rxq->bulk_mbuf[i]);
54 rxq->bulk_mbuf_num = 0;
56 if (rxq->pkt_first_seg) {
57 rte_pktmbuf_free(rxq->pkt_first_seg);
58 rxq->pkt_first_seg = NULL;
63 hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq)
67 /* Note: Fake tx queue will not enter here */
69 for (i = 0; i < txq->nb_tx_desc; i++) {
70 if (txq->sw_ring[i].mbuf) {
71 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
72 txq->sw_ring[i].mbuf = NULL;
79 hns3_rx_queue_release(void *queue)
81 struct hns3_rx_queue *rxq = queue;
83 hns3_rx_queue_release_mbufs(rxq);
85 rte_memzone_free(rxq->mz);
87 rte_free(rxq->sw_ring);
93 hns3_tx_queue_release(void *queue)
95 struct hns3_tx_queue *txq = queue;
97 hns3_tx_queue_release_mbufs(txq);
99 rte_memzone_free(txq->mz);
101 rte_free(txq->sw_ring);
109 hns3_dev_rx_queue_release(void *queue)
111 struct hns3_rx_queue *rxq = queue;
112 struct hns3_adapter *hns;
118 rte_spinlock_lock(&hns->hw.lock);
119 hns3_rx_queue_release(queue);
120 rte_spinlock_unlock(&hns->hw.lock);
124 hns3_dev_tx_queue_release(void *queue)
126 struct hns3_tx_queue *txq = queue;
127 struct hns3_adapter *hns;
133 rte_spinlock_lock(&hns->hw.lock);
134 hns3_tx_queue_release(queue);
135 rte_spinlock_unlock(&hns->hw.lock);
139 hns3_fake_rx_queue_release(struct hns3_rx_queue *queue)
141 struct hns3_rx_queue *rxq = queue;
142 struct hns3_adapter *hns;
152 if (hw->fkq_data.rx_queues[idx]) {
153 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
154 hw->fkq_data.rx_queues[idx] = NULL;
157 /* free fake rx queue arrays */
158 if (idx == (hw->fkq_data.nb_fake_rx_queues - 1)) {
159 hw->fkq_data.nb_fake_rx_queues = 0;
160 rte_free(hw->fkq_data.rx_queues);
161 hw->fkq_data.rx_queues = NULL;
166 hns3_fake_tx_queue_release(struct hns3_tx_queue *queue)
168 struct hns3_tx_queue *txq = queue;
169 struct hns3_adapter *hns;
179 if (hw->fkq_data.tx_queues[idx]) {
180 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
181 hw->fkq_data.tx_queues[idx] = NULL;
184 /* free fake tx queue arrays */
185 if (idx == (hw->fkq_data.nb_fake_tx_queues - 1)) {
186 hw->fkq_data.nb_fake_tx_queues = 0;
187 rte_free(hw->fkq_data.tx_queues);
188 hw->fkq_data.tx_queues = NULL;
193 hns3_free_rx_queues(struct rte_eth_dev *dev)
195 struct hns3_adapter *hns = dev->data->dev_private;
196 struct hns3_fake_queue_data *fkq_data;
197 struct hns3_hw *hw = &hns->hw;
201 nb_rx_q = hw->data->nb_rx_queues;
202 for (i = 0; i < nb_rx_q; i++) {
203 if (dev->data->rx_queues[i]) {
204 hns3_rx_queue_release(dev->data->rx_queues[i]);
205 dev->data->rx_queues[i] = NULL;
209 /* Free fake Rx queues */
210 fkq_data = &hw->fkq_data;
211 for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) {
212 if (fkq_data->rx_queues[i])
213 hns3_fake_rx_queue_release(fkq_data->rx_queues[i]);
218 hns3_free_tx_queues(struct rte_eth_dev *dev)
220 struct hns3_adapter *hns = dev->data->dev_private;
221 struct hns3_fake_queue_data *fkq_data;
222 struct hns3_hw *hw = &hns->hw;
226 nb_tx_q = hw->data->nb_tx_queues;
227 for (i = 0; i < nb_tx_q; i++) {
228 if (dev->data->tx_queues[i]) {
229 hns3_tx_queue_release(dev->data->tx_queues[i]);
230 dev->data->tx_queues[i] = NULL;
234 /* Free fake Tx queues */
235 fkq_data = &hw->fkq_data;
236 for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) {
237 if (fkq_data->tx_queues[i])
238 hns3_fake_tx_queue_release(fkq_data->tx_queues[i]);
243 hns3_free_all_queues(struct rte_eth_dev *dev)
245 hns3_free_rx_queues(dev);
246 hns3_free_tx_queues(dev);
250 hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq)
252 struct rte_mbuf *mbuf;
256 for (i = 0; i < rxq->nb_rx_desc; i++) {
257 mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
258 if (unlikely(mbuf == NULL)) {
259 hns3_err(hw, "Failed to allocate RXD[%u] for rx queue!",
261 hns3_rx_queue_release_mbufs(rxq);
265 rte_mbuf_refcnt_set(mbuf, 1);
267 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
269 mbuf->port = rxq->port_id;
271 rxq->sw_ring[i].mbuf = mbuf;
272 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
273 rxq->rx_ring[i].addr = dma_addr;
274 rxq->rx_ring[i].rx.bd_base_info = 0;
281 hns3_buf_size2type(uint32_t buf_size)
287 bd_size_type = HNS3_BD_SIZE_512_TYPE;
290 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
293 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
296 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
303 hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)
305 uint32_t rx_buf_len = rxq->rx_buf_len;
306 uint64_t dma_addr = rxq->rx_ring_phys_addr;
308 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);
309 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,
310 (uint32_t)((dma_addr >> 31) >> 1));
312 hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,
313 hns3_buf_size2type(rx_buf_len));
314 hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG,
315 HNS3_CFG_DESC_NUM(rxq->nb_rx_desc));
319 hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)
321 uint64_t dma_addr = txq->tx_ring_phys_addr;
323 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);
324 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,
325 (uint32_t)((dma_addr >> 31) >> 1));
327 hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,
328 HNS3_CFG_DESC_NUM(txq->nb_tx_desc));
332 hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw)
334 uint16_t nb_rx_q = hw->data->nb_rx_queues;
335 uint16_t nb_tx_q = hw->data->nb_tx_queues;
336 struct hns3_rx_queue *rxq;
337 struct hns3_tx_queue *txq;
341 pvid_en = hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE;
342 for (i = 0; i < hw->cfg_max_queues; i++) {
344 rxq = hw->data->rx_queues[i];
346 rxq->pvid_sw_discard_en = pvid_en;
349 txq = hw->data->tx_queues[i];
351 txq->pvid_sw_shift_en = pvid_en;
357 hns3_stop_unused_queue(void *tqp_base, enum hns3_ring_type queue_type)
362 reg_offset = queue_type == HNS3_RING_TYPE_TX ?
363 HNS3_RING_TX_EN_REG : HNS3_RING_RX_EN_REG;
364 reg = hns3_read_reg(tqp_base, reg_offset);
365 reg &= ~BIT(HNS3_RING_EN_B);
366 hns3_write_reg(tqp_base, reg_offset, reg);
370 hns3_enable_all_queues(struct hns3_hw *hw, bool en)
372 uint16_t nb_rx_q = hw->data->nb_rx_queues;
373 uint16_t nb_tx_q = hw->data->nb_tx_queues;
374 struct hns3_rx_queue *rxq;
375 struct hns3_tx_queue *txq;
380 for (i = 0; i < hw->cfg_max_queues; i++) {
381 if (hns3_dev_indep_txrx_supported(hw)) {
382 rxq = i < nb_rx_q ? hw->data->rx_queues[i] : NULL;
383 txq = i < nb_tx_q ? hw->data->tx_queues[i] : NULL;
385 tqp_base = (void *)((char *)hw->io_base +
386 hns3_get_tqp_reg_offset(i));
388 * If queue struct is not initialized, it means the
389 * related HW ring has not been initialized yet.
390 * So, these queues should be disabled before enable
391 * the tqps to avoid a HW exception since the queues
392 * are enabled by default.
395 hns3_stop_unused_queue(tqp_base,
398 hns3_stop_unused_queue(tqp_base,
401 rxq = i < nb_rx_q ? hw->data->rx_queues[i] :
402 hw->fkq_data.rx_queues[i - nb_rx_q];
404 tqp_base = rxq->io_base;
407 * This is the master switch that used to control the enabling
408 * of a pair of Tx and Rx queues. Both the Rx and Tx point to
411 rcb_reg = hns3_read_reg(tqp_base, HNS3_RING_EN_REG);
413 rcb_reg |= BIT(HNS3_RING_EN_B);
415 rcb_reg &= ~BIT(HNS3_RING_EN_B);
416 hns3_write_reg(tqp_base, HNS3_RING_EN_REG, rcb_reg);
421 hns3_enable_txq(struct hns3_tx_queue *txq, bool en)
423 struct hns3_hw *hw = &txq->hns->hw;
426 if (hns3_dev_indep_txrx_supported(hw)) {
427 reg = hns3_read_dev(txq, HNS3_RING_TX_EN_REG);
429 reg |= BIT(HNS3_RING_EN_B);
431 reg &= ~BIT(HNS3_RING_EN_B);
432 hns3_write_dev(txq, HNS3_RING_TX_EN_REG, reg);
438 hns3_enable_rxq(struct hns3_rx_queue *rxq, bool en)
440 struct hns3_hw *hw = &rxq->hns->hw;
443 if (hns3_dev_indep_txrx_supported(hw)) {
444 reg = hns3_read_dev(rxq, HNS3_RING_RX_EN_REG);
446 reg |= BIT(HNS3_RING_EN_B);
448 reg &= ~BIT(HNS3_RING_EN_B);
449 hns3_write_dev(rxq, HNS3_RING_RX_EN_REG, reg);
455 hns3_start_all_txqs(struct rte_eth_dev *dev)
457 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
458 struct hns3_tx_queue *txq;
461 for (i = 0; i < dev->data->nb_tx_queues; i++) {
462 txq = hw->data->tx_queues[i];
464 hns3_err(hw, "Tx queue %u not available or setup.", i);
465 goto start_txqs_fail;
468 * Tx queue is enabled by default. Therefore, the Tx queues
469 * needs to be disabled when deferred_start is set. There is
470 * another master switch used to control the enabling of a pair
471 * of Tx and Rx queues. And the master switch is disabled by
474 if (txq->tx_deferred_start)
475 hns3_enable_txq(txq, false);
477 hns3_enable_txq(txq, true);
482 for (j = 0; j < i; j++) {
483 txq = hw->data->tx_queues[j];
484 hns3_enable_txq(txq, false);
490 hns3_start_all_rxqs(struct rte_eth_dev *dev)
492 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
493 struct hns3_rx_queue *rxq;
496 for (i = 0; i < dev->data->nb_rx_queues; i++) {
497 rxq = hw->data->rx_queues[i];
499 hns3_err(hw, "Rx queue %u not available or setup.", i);
500 goto start_rxqs_fail;
503 * Rx queue is enabled by default. Therefore, the Rx queues
504 * needs to be disabled when deferred_start is set. There is
505 * another master switch used to control the enabling of a pair
506 * of Tx and Rx queues. And the master switch is disabled by
509 if (rxq->rx_deferred_start)
510 hns3_enable_rxq(rxq, false);
512 hns3_enable_rxq(rxq, true);
517 for (j = 0; j < i; j++) {
518 rxq = hw->data->rx_queues[j];
519 hns3_enable_rxq(rxq, false);
525 hns3_restore_tqp_enable_state(struct hns3_hw *hw)
527 struct hns3_rx_queue *rxq;
528 struct hns3_tx_queue *txq;
531 for (i = 0; i < hw->data->nb_rx_queues; i++) {
532 rxq = hw->data->rx_queues[i];
534 hns3_enable_rxq(rxq, rxq->enabled);
537 for (i = 0; i < hw->data->nb_tx_queues; i++) {
538 txq = hw->data->tx_queues[i];
540 hns3_enable_txq(txq, txq->enabled);
545 hns3_stop_all_txqs(struct rte_eth_dev *dev)
547 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
548 struct hns3_tx_queue *txq;
551 for (i = 0; i < dev->data->nb_tx_queues; i++) {
552 txq = hw->data->tx_queues[i];
555 hns3_enable_txq(txq, false);
560 hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable)
562 struct hns3_cfg_com_tqp_queue_cmd *req;
563 struct hns3_cmd_desc desc;
566 req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data;
568 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false);
569 req->tqp_id = rte_cpu_to_le_16(queue_id);
571 hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0);
573 ret = hns3_cmd_send(hw, &desc, 1);
575 hns3_err(hw, "TQP enable fail, ret = %d", ret);
581 hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable)
583 struct hns3_reset_tqp_queue_cmd *req;
584 struct hns3_cmd_desc desc;
587 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false);
589 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
590 req->tqp_id = rte_cpu_to_le_16(queue_id);
591 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
592 ret = hns3_cmd_send(hw, &desc, 1);
594 hns3_err(hw, "send tqp reset cmd error, queue_id = %u, "
595 "ret = %d", queue_id, ret);
601 hns3_get_tqp_reset_status(struct hns3_hw *hw, uint16_t queue_id,
602 uint8_t *reset_status)
604 struct hns3_reset_tqp_queue_cmd *req;
605 struct hns3_cmd_desc desc;
608 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true);
610 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
611 req->tqp_id = rte_cpu_to_le_16(queue_id);
613 ret = hns3_cmd_send(hw, &desc, 1);
615 hns3_err(hw, "get tqp reset status error, queue_id = %u, "
616 "ret = %d.", queue_id, ret);
619 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
624 hns3pf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
626 #define HNS3_TQP_RESET_TRY_MS 200
627 uint8_t reset_status;
631 ret = hns3_tqp_enable(hw, queue_id, false);
636 * In current version VF is not supported when PF is driven by DPDK
637 * driver, all task queue pairs are mapped to PF function, so PF's queue
638 * id is equals to the global queue id in PF range.
640 ret = hns3_send_reset_tqp_cmd(hw, queue_id, true);
642 hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret);
645 end = get_timeofday_ms() + HNS3_TQP_RESET_TRY_MS;
647 /* Wait for tqp hw reset */
648 rte_delay_ms(HNS3_POLL_RESPONE_MS);
649 ret = hns3_get_tqp_reset_status(hw, queue_id, &reset_status);
655 } while (get_timeofday_ms() < end);
659 hns3_err(hw, "reset tqp timeout, queue_id = %u, ret = %d",
664 ret = hns3_send_reset_tqp_cmd(hw, queue_id, false);
666 hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret);
671 hns3_send_reset_tqp_cmd(hw, queue_id, false);
676 hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
681 /* Disable VF's queue before send queue reset msg to PF */
682 ret = hns3_tqp_enable(hw, queue_id, false);
686 memcpy(msg_data, &queue_id, sizeof(uint16_t));
688 ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
689 sizeof(msg_data), true, NULL, 0);
691 hns3_err(hw, "fail to reset tqp, queue_id = %u, ret = %d.",
697 hns3_reset_tqp(struct hns3_adapter *hns, uint16_t queue_id)
699 struct hns3_hw *hw = &hns->hw;
702 return hns3vf_reset_tqp(hw, queue_id);
704 return hns3pf_reset_tqp(hw, queue_id);
708 hns3_reset_all_tqps(struct hns3_adapter *hns)
710 struct hns3_hw *hw = &hns->hw;
713 for (i = 0; i < hw->cfg_max_queues; i++) {
714 ret = hns3_reset_tqp(hns, i);
716 hns3_err(hw, "Failed to reset No.%d queue: %d", i, ret);
724 hns3_send_reset_queue_cmd(struct hns3_hw *hw, uint16_t queue_id,
725 enum hns3_ring_type queue_type, bool enable)
727 struct hns3_reset_tqp_queue_cmd *req;
728 struct hns3_cmd_desc desc;
732 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, false);
734 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
735 req->tqp_id = rte_cpu_to_le_16(queue_id);
736 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
737 req->queue_direction = rte_cpu_to_le_16(queue_direction);
738 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
740 ret = hns3_cmd_send(hw, &desc, 1);
742 hns3_err(hw, "send queue reset cmd error, queue_id = %u, "
743 "queue_type = %s, ret = %d.", queue_id,
744 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
749 hns3_get_queue_reset_status(struct hns3_hw *hw, uint16_t queue_id,
750 enum hns3_ring_type queue_type,
751 uint8_t *reset_status)
753 struct hns3_reset_tqp_queue_cmd *req;
754 struct hns3_cmd_desc desc;
758 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, true);
760 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
761 req->tqp_id = rte_cpu_to_le_16(queue_id);
762 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
763 req->queue_direction = rte_cpu_to_le_16(queue_direction);
765 ret = hns3_cmd_send(hw, &desc, 1);
767 hns3_err(hw, "get queue reset status error, queue_id = %u "
768 "queue_type = %s, ret = %d.", queue_id,
769 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
773 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
778 hns3_reset_queue(struct hns3_hw *hw, uint16_t queue_id,
779 enum hns3_ring_type queue_type)
781 #define HNS3_QUEUE_RESET_TRY_MS 200
782 struct hns3_tx_queue *txq;
783 struct hns3_rx_queue *rxq;
784 uint32_t reset_wait_times;
785 uint32_t max_wait_times;
786 uint8_t reset_status;
789 if (queue_type == HNS3_RING_TYPE_TX) {
790 txq = hw->data->tx_queues[queue_id];
791 hns3_enable_txq(txq, false);
793 rxq = hw->data->rx_queues[queue_id];
794 hns3_enable_rxq(rxq, false);
797 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, true);
799 hns3_err(hw, "send reset queue cmd fail, ret = %d.", ret);
803 reset_wait_times = 0;
804 max_wait_times = HNS3_QUEUE_RESET_TRY_MS / HNS3_POLL_RESPONE_MS;
805 while (reset_wait_times < max_wait_times) {
806 /* Wait for queue hw reset */
807 rte_delay_ms(HNS3_POLL_RESPONE_MS);
808 ret = hns3_get_queue_reset_status(hw, queue_id,
809 queue_type, &reset_status);
811 goto queue_reset_fail;
819 hns3_err(hw, "reset queue timeout, queue_id = %u, "
820 "queue_type = %s", queue_id,
821 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx");
823 goto queue_reset_fail;
826 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
828 hns3_err(hw, "deassert queue reset fail, ret = %d.", ret);
833 hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
839 hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
840 uint8_t gl_idx, uint16_t gl_value)
842 uint32_t offset[] = {HNS3_TQP_INTR_GL0_REG,
843 HNS3_TQP_INTR_GL1_REG,
844 HNS3_TQP_INTR_GL2_REG};
845 uint32_t addr, value;
847 if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX)
850 addr = offset[gl_idx] + queue_id * HNS3_TQP_INTR_REG_SIZE;
851 if (hw->intr.gl_unit == HNS3_INTR_COALESCE_GL_UINT_1US)
852 value = gl_value | HNS3_TQP_INTR_GL_UNIT_1US;
854 value = HNS3_GL_USEC_TO_REG(gl_value);
856 hns3_write_dev(hw, addr, value);
860 hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value)
862 uint32_t addr, value;
864 if (rl_value > HNS3_TQP_INTR_RL_MAX)
867 addr = HNS3_TQP_INTR_RL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
868 value = HNS3_RL_USEC_TO_REG(rl_value);
870 value |= HNS3_TQP_INTR_RL_ENABLE_MASK;
872 hns3_write_dev(hw, addr, value);
876 hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value)
881 * int_ql_max == 0 means the hardware does not support QL,
882 * QL regs config is not permitted if QL is not supported,
885 if (hw->intr.int_ql_max == HNS3_INTR_QL_NONE)
888 addr = HNS3_TQP_INTR_TX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
889 hns3_write_dev(hw, addr, ql_value);
891 addr = HNS3_TQP_INTR_RX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
892 hns3_write_dev(hw, addr, ql_value);
896 hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en)
898 uint32_t addr, value;
900 addr = HNS3_TQP_INTR_CTRL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
903 hns3_write_dev(hw, addr, value);
907 * Enable all rx queue interrupt when in interrupt rx mode.
908 * This api was called before enable queue rx&tx (in normal start or reset
909 * recover scenes), used to fix hardware rx queue interrupt enable was clear
913 hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en)
915 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
916 uint16_t nb_rx_q = hw->data->nb_rx_queues;
919 if (dev->data->dev_conf.intr_conf.rxq == 0)
922 for (i = 0; i < nb_rx_q; i++)
923 hns3_queue_intr_enable(hw, i, en);
927 hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
929 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
930 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
931 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
933 if (dev->data->dev_conf.intr_conf.rxq == 0)
936 hns3_queue_intr_enable(hw, queue_id, true);
938 return rte_intr_ack(intr_handle);
942 hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
944 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
946 if (dev->data->dev_conf.intr_conf.rxq == 0)
949 hns3_queue_intr_enable(hw, queue_id, false);
955 hns3_init_rxq(struct hns3_adapter *hns, uint16_t idx)
957 struct hns3_hw *hw = &hns->hw;
958 struct hns3_rx_queue *rxq;
961 PMD_INIT_FUNC_TRACE();
963 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx];
964 ret = hns3_alloc_rx_queue_mbufs(hw, rxq);
966 hns3_err(hw, "fail to alloc mbuf for Rx queue %u, ret = %d.",
971 rxq->next_to_use = 0;
972 rxq->rx_rearm_start = 0;
973 rxq->rx_free_hold = 0;
974 rxq->rx_rearm_nb = 0;
975 rxq->pkt_first_seg = NULL;
976 rxq->pkt_last_seg = NULL;
977 hns3_init_rx_queue_hw(rxq);
978 hns3_rxq_vec_setup(rxq);
984 hns3_init_fake_rxq(struct hns3_adapter *hns, uint16_t idx)
986 struct hns3_hw *hw = &hns->hw;
987 struct hns3_rx_queue *rxq;
989 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx];
990 rxq->next_to_use = 0;
991 rxq->rx_free_hold = 0;
992 rxq->rx_rearm_start = 0;
993 rxq->rx_rearm_nb = 0;
994 hns3_init_rx_queue_hw(rxq);
998 hns3_init_txq(struct hns3_tx_queue *txq)
1000 struct hns3_desc *desc;
1004 desc = txq->tx_ring;
1005 for (i = 0; i < txq->nb_tx_desc; i++) {
1006 desc->tx.tp_fe_sc_vld_ra_ri = 0;
1010 txq->next_to_use = 0;
1011 txq->next_to_clean = 0;
1012 txq->tx_bd_ready = txq->nb_tx_desc - 1;
1013 hns3_init_tx_queue_hw(txq);
1017 hns3_init_tx_ring_tc(struct hns3_adapter *hns)
1019 struct hns3_hw *hw = &hns->hw;
1020 struct hns3_tx_queue *txq;
1023 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1024 struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i];
1027 if (!tc_queue->enable)
1030 for (j = 0; j < tc_queue->tqp_count; j++) {
1031 num = tc_queue->tqp_offset + j;
1032 txq = (struct hns3_tx_queue *)hw->data->tx_queues[num];
1036 hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc);
1042 hns3_init_rx_queues(struct hns3_adapter *hns)
1044 struct hns3_hw *hw = &hns->hw;
1045 struct hns3_rx_queue *rxq;
1049 /* Initialize RSS for queues */
1050 ret = hns3_config_rss(hns);
1052 hns3_err(hw, "failed to configure rss, ret = %d.", ret);
1056 for (i = 0; i < hw->data->nb_rx_queues; i++) {
1057 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i];
1059 hns3_err(hw, "Rx queue %u not available or setup.", i);
1063 if (rxq->rx_deferred_start)
1066 ret = hns3_init_rxq(hns, i);
1068 hns3_err(hw, "failed to init Rx queue %u, ret = %d.", i,
1074 for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++)
1075 hns3_init_fake_rxq(hns, i);
1080 for (j = 0; j < i; j++) {
1081 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j];
1082 hns3_rx_queue_release_mbufs(rxq);
1089 hns3_init_tx_queues(struct hns3_adapter *hns)
1091 struct hns3_hw *hw = &hns->hw;
1092 struct hns3_tx_queue *txq;
1095 for (i = 0; i < hw->data->nb_tx_queues; i++) {
1096 txq = (struct hns3_tx_queue *)hw->data->tx_queues[i];
1098 hns3_err(hw, "Tx queue %u not available or setup.", i);
1102 if (txq->tx_deferred_start)
1107 for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) {
1108 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i];
1111 hns3_init_tx_ring_tc(hns);
1118 * Note: just init and setup queues, and don't enable tqps.
1121 hns3_init_queues(struct hns3_adapter *hns, bool reset_queue)
1123 struct hns3_hw *hw = &hns->hw;
1127 ret = hns3_reset_all_tqps(hns);
1129 hns3_err(hw, "failed to reset all queues, ret = %d.",
1135 ret = hns3_init_rx_queues(hns);
1137 hns3_err(hw, "failed to init rx queues, ret = %d.", ret);
1141 ret = hns3_init_tx_queues(hns);
1143 hns3_dev_release_mbufs(hns);
1144 hns3_err(hw, "failed to init tx queues, ret = %d.", ret);
1151 hns3_start_tqps(struct hns3_hw *hw)
1153 struct hns3_tx_queue *txq;
1154 struct hns3_rx_queue *rxq;
1157 hns3_enable_all_queues(hw, true);
1159 for (i = 0; i < hw->data->nb_tx_queues; i++) {
1160 txq = hw->data->tx_queues[i];
1162 hw->data->tx_queue_state[i] =
1163 RTE_ETH_QUEUE_STATE_STARTED;
1166 for (i = 0; i < hw->data->nb_rx_queues; i++) {
1167 rxq = hw->data->rx_queues[i];
1169 hw->data->rx_queue_state[i] =
1170 RTE_ETH_QUEUE_STATE_STARTED;
1175 hns3_stop_tqps(struct hns3_hw *hw)
1179 hns3_enable_all_queues(hw, false);
1181 for (i = 0; i < hw->data->nb_tx_queues; i++)
1182 hw->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1184 for (i = 0; i < hw->data->nb_rx_queues; i++)
1185 hw->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1189 * Iterate over all Rx Queue, and call the callback() function for each Rx
1193 * The target eth dev.
1194 * @param[in] callback
1195 * The function to call for each queue.
1196 * if callback function return nonzero will stop iterate and return it's value
1198 * The arguments to provide the callback function with.
1201 * 0 on success, otherwise with errno set.
1204 hns3_rxq_iterate(struct rte_eth_dev *dev,
1205 int (*callback)(struct hns3_rx_queue *, void *), void *arg)
1210 if (dev->data->rx_queues == NULL)
1213 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1214 ret = callback(dev->data->rx_queues[i], arg);
1223 hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev,
1224 struct hns3_queue_info *q_info)
1226 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1227 const struct rte_memzone *rx_mz;
1228 struct hns3_rx_queue *rxq;
1229 unsigned int rx_desc;
1231 rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue),
1232 RTE_CACHE_LINE_SIZE, q_info->socket_id);
1234 hns3_err(hw, "Failed to allocate memory for No.%u rx ring!",
1239 /* Allocate rx ring hardware descriptors. */
1240 rxq->queue_id = q_info->idx;
1241 rxq->nb_rx_desc = q_info->nb_desc;
1244 * Allocate a litter more memory because rx vector functions
1245 * don't check boundaries each time.
1247 rx_desc = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
1248 sizeof(struct hns3_desc);
1249 rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
1250 rx_desc, HNS3_RING_BASE_ALIGN,
1252 if (rx_mz == NULL) {
1253 hns3_err(hw, "Failed to reserve DMA memory for No.%u rx ring!",
1255 hns3_rx_queue_release(rxq);
1259 rxq->rx_ring = (struct hns3_desc *)rx_mz->addr;
1260 rxq->rx_ring_phys_addr = rx_mz->iova;
1262 hns3_dbg(hw, "No.%u rx descriptors iova 0x%" PRIx64, q_info->idx,
1263 rxq->rx_ring_phys_addr);
1269 hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
1270 uint16_t nb_desc, unsigned int socket_id)
1272 struct hns3_adapter *hns = dev->data->dev_private;
1273 struct hns3_hw *hw = &hns->hw;
1274 struct hns3_queue_info q_info;
1275 struct hns3_rx_queue *rxq;
1278 if (hw->fkq_data.rx_queues[idx]) {
1279 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
1280 hw->fkq_data.rx_queues[idx] = NULL;
1284 q_info.socket_id = socket_id;
1285 q_info.nb_desc = nb_desc;
1286 q_info.type = "hns3 fake RX queue";
1287 q_info.ring_name = "rx_fake_ring";
1288 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1290 hns3_err(hw, "Failed to setup No.%u fake rx ring.", idx);
1294 /* Don't need alloc sw_ring, because upper applications don't use it */
1295 rxq->sw_ring = NULL;
1298 rxq->rx_deferred_start = false;
1299 rxq->port_id = dev->data->port_id;
1300 rxq->configured = true;
1301 nb_rx_q = dev->data->nb_rx_queues;
1302 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1303 (nb_rx_q + idx) * HNS3_TQP_REG_SIZE);
1304 rxq->rx_buf_len = HNS3_MIN_BD_BUF_SIZE;
1306 rte_spinlock_lock(&hw->lock);
1307 hw->fkq_data.rx_queues[idx] = rxq;
1308 rte_spinlock_unlock(&hw->lock);
1314 hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev,
1315 struct hns3_queue_info *q_info)
1317 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1318 const struct rte_memzone *tx_mz;
1319 struct hns3_tx_queue *txq;
1320 struct hns3_desc *desc;
1321 unsigned int tx_desc;
1324 txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue),
1325 RTE_CACHE_LINE_SIZE, q_info->socket_id);
1327 hns3_err(hw, "Failed to allocate memory for No.%u tx ring!",
1332 /* Allocate tx ring hardware descriptors. */
1333 txq->queue_id = q_info->idx;
1334 txq->nb_tx_desc = q_info->nb_desc;
1335 tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc);
1336 tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
1337 tx_desc, HNS3_RING_BASE_ALIGN,
1339 if (tx_mz == NULL) {
1340 hns3_err(hw, "Failed to reserve DMA memory for No.%u tx ring!",
1342 hns3_tx_queue_release(txq);
1346 txq->tx_ring = (struct hns3_desc *)tx_mz->addr;
1347 txq->tx_ring_phys_addr = tx_mz->iova;
1349 hns3_dbg(hw, "No.%u tx descriptors iova 0x%" PRIx64, q_info->idx,
1350 txq->tx_ring_phys_addr);
1353 desc = txq->tx_ring;
1354 for (i = 0; i < txq->nb_tx_desc; i++) {
1355 desc->tx.tp_fe_sc_vld_ra_ri = 0;
1363 hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
1364 uint16_t nb_desc, unsigned int socket_id)
1366 struct hns3_adapter *hns = dev->data->dev_private;
1367 struct hns3_hw *hw = &hns->hw;
1368 struct hns3_queue_info q_info;
1369 struct hns3_tx_queue *txq;
1372 if (hw->fkq_data.tx_queues[idx] != NULL) {
1373 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
1374 hw->fkq_data.tx_queues[idx] = NULL;
1378 q_info.socket_id = socket_id;
1379 q_info.nb_desc = nb_desc;
1380 q_info.type = "hns3 fake TX queue";
1381 q_info.ring_name = "tx_fake_ring";
1382 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
1384 hns3_err(hw, "Failed to setup No.%u fake tx ring.", idx);
1388 /* Don't need alloc sw_ring, because upper applications don't use it */
1389 txq->sw_ring = NULL;
1393 txq->tx_deferred_start = false;
1394 txq->port_id = dev->data->port_id;
1395 txq->configured = true;
1396 nb_tx_q = dev->data->nb_tx_queues;
1397 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1398 (nb_tx_q + idx) * HNS3_TQP_REG_SIZE);
1400 rte_spinlock_lock(&hw->lock);
1401 hw->fkq_data.tx_queues[idx] = txq;
1402 rte_spinlock_unlock(&hw->lock);
1408 hns3_fake_rx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1410 uint16_t old_nb_queues = hw->fkq_data.nb_fake_rx_queues;
1414 if (hw->fkq_data.rx_queues == NULL && nb_queues != 0) {
1415 /* first time configuration */
1417 size = sizeof(hw->fkq_data.rx_queues[0]) * nb_queues;
1418 hw->fkq_data.rx_queues = rte_zmalloc("fake_rx_queues", size,
1419 RTE_CACHE_LINE_SIZE);
1420 if (hw->fkq_data.rx_queues == NULL) {
1421 hw->fkq_data.nb_fake_rx_queues = 0;
1424 } else if (hw->fkq_data.rx_queues != NULL && nb_queues != 0) {
1426 rxq = hw->fkq_data.rx_queues;
1427 for (i = nb_queues; i < old_nb_queues; i++)
1428 hns3_dev_rx_queue_release(rxq[i]);
1430 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
1431 RTE_CACHE_LINE_SIZE);
1434 if (nb_queues > old_nb_queues) {
1435 uint16_t new_qs = nb_queues - old_nb_queues;
1436 memset(rxq + old_nb_queues, 0, sizeof(rxq[0]) * new_qs);
1439 hw->fkq_data.rx_queues = rxq;
1440 } else if (hw->fkq_data.rx_queues != NULL && nb_queues == 0) {
1441 rxq = hw->fkq_data.rx_queues;
1442 for (i = nb_queues; i < old_nb_queues; i++)
1443 hns3_dev_rx_queue_release(rxq[i]);
1445 rte_free(hw->fkq_data.rx_queues);
1446 hw->fkq_data.rx_queues = NULL;
1449 hw->fkq_data.nb_fake_rx_queues = nb_queues;
1455 hns3_fake_tx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1457 uint16_t old_nb_queues = hw->fkq_data.nb_fake_tx_queues;
1461 if (hw->fkq_data.tx_queues == NULL && nb_queues != 0) {
1462 /* first time configuration */
1464 size = sizeof(hw->fkq_data.tx_queues[0]) * nb_queues;
1465 hw->fkq_data.tx_queues = rte_zmalloc("fake_tx_queues", size,
1466 RTE_CACHE_LINE_SIZE);
1467 if (hw->fkq_data.tx_queues == NULL) {
1468 hw->fkq_data.nb_fake_tx_queues = 0;
1471 } else if (hw->fkq_data.tx_queues != NULL && nb_queues != 0) {
1473 txq = hw->fkq_data.tx_queues;
1474 for (i = nb_queues; i < old_nb_queues; i++)
1475 hns3_dev_tx_queue_release(txq[i]);
1476 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1477 RTE_CACHE_LINE_SIZE);
1480 if (nb_queues > old_nb_queues) {
1481 uint16_t new_qs = nb_queues - old_nb_queues;
1482 memset(txq + old_nb_queues, 0, sizeof(txq[0]) * new_qs);
1485 hw->fkq_data.tx_queues = txq;
1486 } else if (hw->fkq_data.tx_queues != NULL && nb_queues == 0) {
1487 txq = hw->fkq_data.tx_queues;
1488 for (i = nb_queues; i < old_nb_queues; i++)
1489 hns3_dev_tx_queue_release(txq[i]);
1491 rte_free(hw->fkq_data.tx_queues);
1492 hw->fkq_data.tx_queues = NULL;
1494 hw->fkq_data.nb_fake_tx_queues = nb_queues;
1500 hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
1503 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1504 uint16_t rx_need_add_nb_q;
1505 uint16_t tx_need_add_nb_q;
1510 /* Setup new number of fake RX/TX queues and reconfigure device. */
1511 rx_need_add_nb_q = hw->cfg_max_queues - nb_rx_q;
1512 tx_need_add_nb_q = hw->cfg_max_queues - nb_tx_q;
1513 ret = hns3_fake_rx_queue_config(hw, rx_need_add_nb_q);
1515 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1519 ret = hns3_fake_tx_queue_config(hw, tx_need_add_nb_q);
1521 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1522 goto cfg_fake_tx_q_fail;
1525 /* Allocate and set up fake RX queue per Ethernet port. */
1526 port_id = hw->data->port_id;
1527 for (q = 0; q < rx_need_add_nb_q; q++) {
1528 ret = hns3_fake_rx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1529 rte_eth_dev_socket_id(port_id));
1531 goto setup_fake_rx_q_fail;
1534 /* Allocate and set up fake TX queue per Ethernet port. */
1535 for (q = 0; q < tx_need_add_nb_q; q++) {
1536 ret = hns3_fake_tx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1537 rte_eth_dev_socket_id(port_id));
1539 goto setup_fake_tx_q_fail;
1544 setup_fake_tx_q_fail:
1545 setup_fake_rx_q_fail:
1546 (void)hns3_fake_tx_queue_config(hw, 0);
1548 (void)hns3_fake_rx_queue_config(hw, 0);
1554 hns3_dev_release_mbufs(struct hns3_adapter *hns)
1556 struct rte_eth_dev_data *dev_data = hns->hw.data;
1557 struct hns3_rx_queue *rxq;
1558 struct hns3_tx_queue *txq;
1561 if (dev_data->rx_queues)
1562 for (i = 0; i < dev_data->nb_rx_queues; i++) {
1563 rxq = dev_data->rx_queues[i];
1566 hns3_rx_queue_release_mbufs(rxq);
1569 if (dev_data->tx_queues)
1570 for (i = 0; i < dev_data->nb_tx_queues; i++) {
1571 txq = dev_data->tx_queues[i];
1574 hns3_tx_queue_release_mbufs(txq);
1579 hns3_rx_buf_len_calc(struct rte_mempool *mp, uint16_t *rx_buf_len)
1581 uint16_t vld_buf_size;
1582 uint16_t num_hw_specs;
1586 * hns3 network engine only support to set 4 typical specification, and
1587 * different buffer size will affect the max packet_len and the max
1588 * number of segmentation when hw gro is turned on in receive side. The
1589 * relationship between them is as follows:
1590 * rx_buf_size | max_gro_pkt_len | max_gro_nb_seg
1591 * ---------------------|-------------------|----------------
1592 * HNS3_4K_BD_BUF_SIZE | 60KB | 15
1593 * HNS3_2K_BD_BUF_SIZE | 62KB | 31
1594 * HNS3_1K_BD_BUF_SIZE | 63KB | 63
1595 * HNS3_512_BD_BUF_SIZE | 31.5KB | 63
1597 static const uint16_t hw_rx_buf_size[] = {
1598 HNS3_4K_BD_BUF_SIZE,
1599 HNS3_2K_BD_BUF_SIZE,
1600 HNS3_1K_BD_BUF_SIZE,
1601 HNS3_512_BD_BUF_SIZE
1604 vld_buf_size = (uint16_t)(rte_pktmbuf_data_room_size(mp) -
1605 RTE_PKTMBUF_HEADROOM);
1606 if (vld_buf_size < HNS3_MIN_BD_BUF_SIZE)
1609 num_hw_specs = RTE_DIM(hw_rx_buf_size);
1610 for (i = 0; i < num_hw_specs; i++) {
1611 if (vld_buf_size >= hw_rx_buf_size[i]) {
1612 *rx_buf_len = hw_rx_buf_size[i];
1620 hns3_rxq_conf_runtime_check(struct hns3_hw *hw, uint16_t buf_size,
1623 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1624 struct rte_eth_rxmode *rxmode = &hw->data->dev_conf.rxmode;
1625 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
1626 uint16_t min_vec_bds;
1629 * HNS3 hardware network engine set scattered as default. If the driver
1630 * is not work in scattered mode and the pkts greater than buf_size
1631 * but smaller than max_rx_pkt_len will be distributed to multiple BDs.
1632 * Driver cannot handle this situation.
1634 if (!hw->data->scattered_rx && rxmode->max_rx_pkt_len > buf_size) {
1635 hns3_err(hw, "max_rx_pkt_len is not allowed to be set greater "
1636 "than rx_buf_len if scattered is off.");
1640 if (pkt_burst == hns3_recv_pkts_vec) {
1641 min_vec_bds = HNS3_DEFAULT_RXQ_REARM_THRESH +
1642 HNS3_DEFAULT_RX_BURST;
1643 if (nb_desc < min_vec_bds ||
1644 nb_desc % HNS3_DEFAULT_RXQ_REARM_THRESH) {
1645 hns3_err(hw, "if Rx burst mode is vector, "
1646 "number of descriptor is required to be "
1647 "bigger than min vector bds:%u, and could be "
1648 "divided by rxq rearm thresh:%u.",
1649 min_vec_bds, HNS3_DEFAULT_RXQ_REARM_THRESH);
1657 hns3_rx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_rxconf *conf,
1658 struct rte_mempool *mp, uint16_t nb_desc,
1663 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1664 nb_desc % HNS3_ALIGN_RING_DESC) {
1665 hns3_err(hw, "Number (%u) of rx descriptors is invalid",
1670 if (conf->rx_drop_en == 0)
1671 hns3_warn(hw, "if no descriptors available, packets are always "
1672 "dropped and rx_drop_en (1) is fixed on");
1674 if (hns3_rx_buf_len_calc(mp, buf_size)) {
1675 hns3_err(hw, "rxq mbufs' data room size (%u) is not enough! "
1676 "minimal data room size (%u).",
1677 rte_pktmbuf_data_room_size(mp),
1678 HNS3_MIN_BD_BUF_SIZE + RTE_PKTMBUF_HEADROOM);
1682 if (hw->data->dev_started) {
1683 ret = hns3_rxq_conf_runtime_check(hw, *buf_size, nb_desc);
1685 hns3_err(hw, "Rx queue runtime setup fail.");
1694 hns3_get_tqp_reg_offset(uint16_t queue_id)
1696 uint32_t reg_offset;
1698 /* Need an extend offset to config queue > 1024 */
1699 if (queue_id < HNS3_MIN_EXTEND_QUEUE_ID)
1700 reg_offset = HNS3_TQP_REG_OFFSET + queue_id * HNS3_TQP_REG_SIZE;
1702 reg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_EXT_REG_OFFSET +
1703 (queue_id - HNS3_MIN_EXTEND_QUEUE_ID) *
1710 hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1711 unsigned int socket_id, const struct rte_eth_rxconf *conf,
1712 struct rte_mempool *mp)
1714 struct hns3_adapter *hns = dev->data->dev_private;
1715 struct hns3_hw *hw = &hns->hw;
1716 struct hns3_queue_info q_info;
1717 struct hns3_rx_queue *rxq;
1718 uint16_t rx_buf_size;
1722 ret = hns3_rx_queue_conf_check(hw, conf, mp, nb_desc, &rx_buf_size);
1726 if (dev->data->rx_queues[idx]) {
1727 hns3_rx_queue_release(dev->data->rx_queues[idx]);
1728 dev->data->rx_queues[idx] = NULL;
1732 q_info.socket_id = socket_id;
1733 q_info.nb_desc = nb_desc;
1734 q_info.type = "hns3 RX queue";
1735 q_info.ring_name = "rx_ring";
1737 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1740 "Failed to alloc mem and reserve DMA mem for rx ring!");
1745 rxq->ptype_tbl = &hns->ptype_tbl;
1747 rxq->rx_free_thresh = (conf->rx_free_thresh > 0) ?
1748 conf->rx_free_thresh : HNS3_DEFAULT_RX_FREE_THRESH;
1750 rxq->rx_deferred_start = conf->rx_deferred_start;
1751 if (rxq->rx_deferred_start && !hns3_dev_indep_txrx_supported(hw)) {
1752 hns3_warn(hw, "deferred start is not supported.");
1753 rxq->rx_deferred_start = false;
1756 rx_entry_len = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
1757 sizeof(struct hns3_entry);
1758 rxq->sw_ring = rte_zmalloc_socket("hns3 RX sw ring", rx_entry_len,
1759 RTE_CACHE_LINE_SIZE, socket_id);
1760 if (rxq->sw_ring == NULL) {
1761 hns3_err(hw, "Failed to allocate memory for rx sw ring!");
1762 hns3_rx_queue_release(rxq);
1766 rxq->next_to_use = 0;
1767 rxq->rx_free_hold = 0;
1768 rxq->rx_rearm_start = 0;
1769 rxq->rx_rearm_nb = 0;
1770 rxq->pkt_first_seg = NULL;
1771 rxq->pkt_last_seg = NULL;
1772 rxq->port_id = dev->data->port_id;
1774 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
1775 * the pvid_sw_discard_en in the queue struct should not be changed,
1776 * because PVID-related operations do not need to be processed by PMD
1777 * driver. For hns3 VF device, whether it needs to process PVID depends
1778 * on the configuration of PF kernel mode netdevice driver. And the
1779 * related PF configuration is delivered through the mailbox and finally
1780 * reflectd in port_base_vlan_cfg.
1782 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1783 rxq->pvid_sw_discard_en = hw->port_base_vlan_cfg.state ==
1784 HNS3_PORT_BASE_VLAN_ENABLE;
1786 rxq->pvid_sw_discard_en = false;
1787 rxq->configured = true;
1788 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1789 idx * HNS3_TQP_REG_SIZE);
1790 rxq->io_base = (void *)((char *)hw->io_base +
1791 hns3_get_tqp_reg_offset(idx));
1792 rxq->io_head_reg = (volatile void *)((char *)rxq->io_base +
1793 HNS3_RING_RX_HEAD_REG);
1794 rxq->rx_buf_len = rx_buf_size;
1795 memset(&rxq->basic_stats, 0, sizeof(struct hns3_rx_basic_stats));
1796 memset(&rxq->err_stats, 0, sizeof(struct hns3_rx_bd_errors_stats));
1797 memset(&rxq->dfx_stats, 0, sizeof(struct hns3_rx_dfx_stats));
1799 /* CRC len set here is used for amending packet length */
1800 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1801 rxq->crc_len = RTE_ETHER_CRC_LEN;
1805 rxq->bulk_mbuf_num = 0;
1807 rte_spinlock_lock(&hw->lock);
1808 dev->data->rx_queues[idx] = rxq;
1809 rte_spinlock_unlock(&hw->lock);
1815 hns3_rx_scattered_reset(struct rte_eth_dev *dev)
1817 struct hns3_adapter *hns = dev->data->dev_private;
1818 struct hns3_hw *hw = &hns->hw;
1821 dev->data->scattered_rx = false;
1825 hns3_rx_scattered_calc(struct rte_eth_dev *dev)
1827 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1828 struct hns3_adapter *hns = dev->data->dev_private;
1829 struct hns3_hw *hw = &hns->hw;
1830 struct hns3_rx_queue *rxq;
1833 if (dev->data->rx_queues == NULL)
1836 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
1837 rxq = dev->data->rx_queues[queue_id];
1838 if (hw->rx_buf_len == 0)
1839 hw->rx_buf_len = rxq->rx_buf_len;
1841 hw->rx_buf_len = RTE_MIN(hw->rx_buf_len,
1845 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_SCATTER ||
1846 dev_conf->rxmode.max_rx_pkt_len > hw->rx_buf_len)
1847 dev->data->scattered_rx = true;
1851 hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1853 static const uint32_t ptypes[] = {
1855 RTE_PTYPE_L2_ETHER_VLAN,
1856 RTE_PTYPE_L2_ETHER_QINQ,
1857 RTE_PTYPE_L2_ETHER_LLDP,
1858 RTE_PTYPE_L2_ETHER_ARP,
1860 RTE_PTYPE_L3_IPV4_EXT,
1862 RTE_PTYPE_L3_IPV6_EXT,
1868 RTE_PTYPE_TUNNEL_GRE,
1869 RTE_PTYPE_INNER_L2_ETHER,
1870 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1871 RTE_PTYPE_INNER_L2_ETHER_QINQ,
1872 RTE_PTYPE_INNER_L3_IPV4,
1873 RTE_PTYPE_INNER_L3_IPV6,
1874 RTE_PTYPE_INNER_L3_IPV4_EXT,
1875 RTE_PTYPE_INNER_L3_IPV6_EXT,
1876 RTE_PTYPE_INNER_L4_UDP,
1877 RTE_PTYPE_INNER_L4_TCP,
1878 RTE_PTYPE_INNER_L4_SCTP,
1879 RTE_PTYPE_INNER_L4_ICMP,
1880 RTE_PTYPE_TUNNEL_VXLAN,
1881 RTE_PTYPE_TUNNEL_NVGRE,
1885 if (dev->rx_pkt_burst == hns3_recv_pkts ||
1886 dev->rx_pkt_burst == hns3_recv_scattered_pkts ||
1887 dev->rx_pkt_burst == hns3_recv_pkts_vec ||
1888 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve)
1895 hns3_init_non_tunnel_ptype_tbl(struct hns3_ptype_table *tbl)
1897 tbl->l2l3table[0][0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
1898 tbl->l2l3table[0][1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
1899 tbl->l2l3table[0][2] = RTE_PTYPE_L2_ETHER_ARP;
1900 tbl->l2l3table[0][3] = RTE_PTYPE_L2_ETHER;
1901 tbl->l2l3table[0][4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT;
1902 tbl->l2l3table[0][5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT;
1903 tbl->l2l3table[0][6] = RTE_PTYPE_L2_ETHER_LLDP;
1904 tbl->l2l3table[0][15] = RTE_PTYPE_L2_ETHER;
1906 tbl->l2l3table[1][0] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV4;
1907 tbl->l2l3table[1][1] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV6;
1908 tbl->l2l3table[1][2] = RTE_PTYPE_L2_ETHER_ARP;
1909 tbl->l2l3table[1][3] = RTE_PTYPE_L2_ETHER_VLAN;
1910 tbl->l2l3table[1][4] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV4_EXT;
1911 tbl->l2l3table[1][5] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV6_EXT;
1912 tbl->l2l3table[1][6] = RTE_PTYPE_L2_ETHER_LLDP;
1913 tbl->l2l3table[1][15] = RTE_PTYPE_L2_ETHER_VLAN;
1915 tbl->l2l3table[2][0] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV4;
1916 tbl->l2l3table[2][1] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV6;
1917 tbl->l2l3table[2][2] = RTE_PTYPE_L2_ETHER_ARP;
1918 tbl->l2l3table[2][3] = RTE_PTYPE_L2_ETHER_QINQ;
1919 tbl->l2l3table[2][4] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV4_EXT;
1920 tbl->l2l3table[2][5] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV6_EXT;
1921 tbl->l2l3table[2][6] = RTE_PTYPE_L2_ETHER_LLDP;
1922 tbl->l2l3table[2][15] = RTE_PTYPE_L2_ETHER_QINQ;
1924 tbl->l4table[0] = RTE_PTYPE_L4_UDP;
1925 tbl->l4table[1] = RTE_PTYPE_L4_TCP;
1926 tbl->l4table[2] = RTE_PTYPE_TUNNEL_GRE;
1927 tbl->l4table[3] = RTE_PTYPE_L4_SCTP;
1928 tbl->l4table[4] = RTE_PTYPE_L4_IGMP;
1929 tbl->l4table[5] = RTE_PTYPE_L4_ICMP;
1933 hns3_init_tunnel_ptype_tbl(struct hns3_ptype_table *tbl)
1935 tbl->inner_l2table[0] = RTE_PTYPE_INNER_L2_ETHER;
1936 tbl->inner_l2table[1] = RTE_PTYPE_INNER_L2_ETHER_VLAN;
1937 tbl->inner_l2table[2] = RTE_PTYPE_INNER_L2_ETHER_QINQ;
1939 tbl->inner_l3table[0] = RTE_PTYPE_INNER_L3_IPV4;
1940 tbl->inner_l3table[1] = RTE_PTYPE_INNER_L3_IPV6;
1941 /* There is not a ptype for inner ARP/RARP */
1942 tbl->inner_l3table[2] = RTE_PTYPE_UNKNOWN;
1943 tbl->inner_l3table[3] = RTE_PTYPE_UNKNOWN;
1944 tbl->inner_l3table[4] = RTE_PTYPE_INNER_L3_IPV4_EXT;
1945 tbl->inner_l3table[5] = RTE_PTYPE_INNER_L3_IPV6_EXT;
1947 tbl->inner_l4table[0] = RTE_PTYPE_INNER_L4_UDP;
1948 tbl->inner_l4table[1] = RTE_PTYPE_INNER_L4_TCP;
1949 /* There is not a ptype for inner GRE */
1950 tbl->inner_l4table[2] = RTE_PTYPE_UNKNOWN;
1951 tbl->inner_l4table[3] = RTE_PTYPE_INNER_L4_SCTP;
1952 /* There is not a ptype for inner IGMP */
1953 tbl->inner_l4table[4] = RTE_PTYPE_UNKNOWN;
1954 tbl->inner_l4table[5] = RTE_PTYPE_INNER_L4_ICMP;
1956 tbl->ol2table[0] = RTE_PTYPE_L2_ETHER;
1957 tbl->ol2table[1] = RTE_PTYPE_L2_ETHER_VLAN;
1958 tbl->ol2table[2] = RTE_PTYPE_L2_ETHER_QINQ;
1960 tbl->ol3table[0] = RTE_PTYPE_L3_IPV4;
1961 tbl->ol3table[1] = RTE_PTYPE_L3_IPV6;
1962 tbl->ol3table[2] = RTE_PTYPE_UNKNOWN;
1963 tbl->ol3table[3] = RTE_PTYPE_UNKNOWN;
1964 tbl->ol3table[4] = RTE_PTYPE_L3_IPV4_EXT;
1965 tbl->ol3table[5] = RTE_PTYPE_L3_IPV6_EXT;
1967 tbl->ol4table[0] = RTE_PTYPE_UNKNOWN;
1968 tbl->ol4table[1] = RTE_PTYPE_TUNNEL_VXLAN;
1969 tbl->ol4table[2] = RTE_PTYPE_TUNNEL_NVGRE;
1973 hns3_init_rx_ptype_tble(struct rte_eth_dev *dev)
1975 struct hns3_adapter *hns = dev->data->dev_private;
1976 struct hns3_ptype_table *tbl = &hns->ptype_tbl;
1978 memset(tbl, 0, sizeof(*tbl));
1980 hns3_init_non_tunnel_ptype_tbl(tbl);
1981 hns3_init_tunnel_ptype_tbl(tbl);
1985 hns3_rxd_to_vlan_tci(struct hns3_rx_queue *rxq, struct rte_mbuf *mb,
1986 uint32_t l234_info, const struct hns3_desc *rxd)
1988 #define HNS3_STRP_STATUS_NUM 0x4
1990 #define HNS3_NO_STRP_VLAN_VLD 0x0
1991 #define HNS3_INNER_STRP_VLAN_VLD 0x1
1992 #define HNS3_OUTER_STRP_VLAN_VLD 0x2
1993 uint32_t strip_status;
1994 uint32_t report_mode;
1997 * Since HW limitation, the vlan tag will always be inserted into RX
1998 * descriptor when strip the tag from packet, driver needs to determine
1999 * reporting which tag to mbuf according to the PVID configuration
2000 * and vlan striped status.
2002 static const uint32_t report_type[][HNS3_STRP_STATUS_NUM] = {
2004 HNS3_NO_STRP_VLAN_VLD,
2005 HNS3_OUTER_STRP_VLAN_VLD,
2006 HNS3_INNER_STRP_VLAN_VLD,
2007 HNS3_OUTER_STRP_VLAN_VLD
2010 HNS3_NO_STRP_VLAN_VLD,
2011 HNS3_NO_STRP_VLAN_VLD,
2012 HNS3_NO_STRP_VLAN_VLD,
2013 HNS3_INNER_STRP_VLAN_VLD
2016 strip_status = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,
2017 HNS3_RXD_STRP_TAGP_S);
2018 report_mode = report_type[rxq->pvid_sw_discard_en][strip_status];
2019 switch (report_mode) {
2020 case HNS3_NO_STRP_VLAN_VLD:
2023 case HNS3_INNER_STRP_VLAN_VLD:
2024 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2025 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.vlan_tag);
2027 case HNS3_OUTER_STRP_VLAN_VLD:
2028 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2029 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.ot_vlan_tag);
2038 recalculate_data_len(struct rte_mbuf *first_seg, struct rte_mbuf *last_seg,
2039 struct rte_mbuf *rxm, struct hns3_rx_queue *rxq,
2042 uint8_t crc_len = rxq->crc_len;
2044 if (data_len <= crc_len) {
2045 rte_pktmbuf_free_seg(rxm);
2046 first_seg->nb_segs--;
2047 last_seg->data_len = (uint16_t)(last_seg->data_len -
2048 (crc_len - data_len));
2049 last_seg->next = NULL;
2051 rxm->data_len = (uint16_t)(data_len - crc_len);
2054 static inline struct rte_mbuf *
2055 hns3_rx_alloc_buffer(struct hns3_rx_queue *rxq)
2059 if (likely(rxq->bulk_mbuf_num > 0))
2060 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
2062 ret = rte_mempool_get_bulk(rxq->mb_pool, (void **)rxq->bulk_mbuf,
2063 HNS3_BULK_ALLOC_MBUF_NUM);
2064 if (likely(ret == 0)) {
2065 rxq->bulk_mbuf_num = HNS3_BULK_ALLOC_MBUF_NUM;
2066 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
2068 return rte_mbuf_raw_alloc(rxq->mb_pool);
2072 hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2074 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
2075 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
2076 struct hns3_rx_queue *rxq; /* RX queue */
2077 struct hns3_entry *sw_ring;
2078 struct hns3_entry *rxe;
2079 struct hns3_desc rxd;
2080 struct rte_mbuf *nmb; /* pointer of the new mbuf */
2081 struct rte_mbuf *rxm;
2082 uint32_t bd_base_info;
2095 rx_ring = rxq->rx_ring;
2096 sw_ring = rxq->sw_ring;
2097 rx_id = rxq->next_to_use;
2099 while (nb_rx < nb_pkts) {
2100 rxdp = &rx_ring[rx_id];
2101 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
2102 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
2105 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2106 (1u << HNS3_RXD_VLD_B)];
2108 nmb = hns3_rx_alloc_buffer(rxq);
2109 if (unlikely(nmb == NULL)) {
2112 port_id = rxq->port_id;
2113 rte_eth_devices[port_id].data->rx_mbuf_alloc_failed++;
2118 rxe = &sw_ring[rx_id];
2120 if (unlikely(rx_id == rxq->nb_rx_desc))
2123 rte_prefetch0(sw_ring[rx_id].mbuf);
2124 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
2125 rte_prefetch0(&rx_ring[rx_id]);
2126 rte_prefetch0(&sw_ring[rx_id]);
2132 dma_addr = rte_mbuf_data_iova_default(nmb);
2133 rxdp->addr = rte_cpu_to_le_64(dma_addr);
2134 rxdp->rx.bd_base_info = 0;
2136 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2137 rxm->pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.pkt_len)) -
2139 rxm->data_len = rxm->pkt_len;
2140 rxm->port = rxq->port_id;
2141 rxm->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
2142 rxm->ol_flags = PKT_RX_RSS_HASH;
2143 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
2145 rte_le_to_cpu_16(rxd.rx.fd_id);
2146 rxm->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
2151 /* Load remained descriptor data and extract necessary fields */
2152 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
2153 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
2154 ret = hns3_handle_bdinfo(rxq, rxm, bd_base_info,
2155 l234_info, &cksum_err);
2159 rxm->packet_type = hns3_rx_calc_ptype(rxq, l234_info, ol_info);
2161 if (likely(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
2162 hns3_rx_set_cksum_flag(rxm, rxm->packet_type,
2164 hns3_rxd_to_vlan_tci(rxq, rxm, l234_info, &rxd);
2166 rx_pkts[nb_rx++] = rxm;
2169 rte_pktmbuf_free(rxm);
2172 rxq->next_to_use = rx_id;
2173 rxq->rx_free_hold += nb_rx_bd;
2174 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
2175 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
2176 rxq->rx_free_hold = 0;
2183 hns3_recv_scattered_pkts(void *rx_queue,
2184 struct rte_mbuf **rx_pkts,
2187 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
2188 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
2189 struct hns3_rx_queue *rxq; /* RX queue */
2190 struct hns3_entry *sw_ring;
2191 struct hns3_entry *rxe;
2192 struct rte_mbuf *first_seg;
2193 struct rte_mbuf *last_seg;
2194 struct hns3_desc rxd;
2195 struct rte_mbuf *nmb; /* pointer of the new mbuf */
2196 struct rte_mbuf *rxm;
2197 struct rte_eth_dev *dev;
2198 uint32_t bd_base_info;
2213 rx_id = rxq->next_to_use;
2214 rx_ring = rxq->rx_ring;
2215 sw_ring = rxq->sw_ring;
2216 first_seg = rxq->pkt_first_seg;
2217 last_seg = rxq->pkt_last_seg;
2219 while (nb_rx < nb_pkts) {
2220 rxdp = &rx_ring[rx_id];
2221 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
2222 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
2226 * The interactive process between software and hardware of
2227 * receiving a new packet in hns3 network engine:
2228 * 1. Hardware network engine firstly writes the packet content
2229 * to the memory pointed by the 'addr' field of the Rx Buffer
2230 * Descriptor, secondly fills the result of parsing the
2231 * packet include the valid field into the Rx Buffer
2232 * Descriptor in one write operation.
2233 * 2. Driver reads the Rx BD's valid field in the loop to check
2234 * whether it's valid, if valid then assign a new address to
2235 * the addr field, clear the valid field, get the other
2236 * information of the packet by parsing Rx BD's other fields,
2237 * finally write back the number of Rx BDs processed by the
2238 * driver to the HNS3_RING_RX_HEAD_REG register to inform
2240 * In the above process, the ordering is very important. We must
2241 * make sure that CPU read Rx BD's other fields only after the
2244 * There are two type of re-ordering: compiler re-ordering and
2245 * CPU re-ordering under the ARMv8 architecture.
2246 * 1. we use volatile to deal with compiler re-ordering, so you
2247 * can see that rx_ring/rxdp defined with volatile.
2248 * 2. we commonly use memory barrier to deal with CPU
2249 * re-ordering, but the cost is high.
2251 * In order to solve the high cost of using memory barrier, we
2252 * use the data dependency order under the ARMv8 architecture,
2255 * instr02: load B <- A
2256 * the instr02 will always execute after instr01.
2258 * To construct the data dependency ordering, we use the
2259 * following assignment:
2260 * rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2261 * (1u<<HNS3_RXD_VLD_B)]
2262 * Using gcc compiler under the ARMv8 architecture, the related
2263 * assembly code example as follows:
2264 * note: (1u << HNS3_RXD_VLD_B) equal 0x10
2265 * instr01: ldr w26, [x22, #28] --read bd_base_info
2266 * instr02: and w0, w26, #0x10 --calc bd_base_info & 0x10
2267 * instr03: sub w0, w0, #0x10 --calc (bd_base_info &
2269 * instr04: add x0, x22, x0, lsl #5 --calc copy source addr
2270 * instr05: ldp x2, x3, [x0]
2271 * instr06: stp x2, x3, [x29, #256] --copy BD's [0 ~ 15]B
2272 * instr07: ldp x4, x5, [x0, #16]
2273 * instr08: stp x4, x5, [x29, #272] --copy BD's [16 ~ 31]B
2274 * the instr05~08 depend on x0's value, x0 depent on w26's
2275 * value, the w26 is the bd_base_info, this form the data
2276 * dependency ordering.
2277 * note: if BD is valid, (bd_base_info & (1u<<HNS3_RXD_VLD_B)) -
2278 * (1u<<HNS3_RXD_VLD_B) will always zero, so the
2279 * assignment is correct.
2281 * So we use the data dependency ordering instead of memory
2282 * barrier to improve receive performance.
2284 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2285 (1u << HNS3_RXD_VLD_B)];
2287 nmb = hns3_rx_alloc_buffer(rxq);
2288 if (unlikely(nmb == NULL)) {
2289 dev = &rte_eth_devices[rxq->port_id];
2290 dev->data->rx_mbuf_alloc_failed++;
2295 rxe = &sw_ring[rx_id];
2297 if (unlikely(rx_id == rxq->nb_rx_desc))
2300 rte_prefetch0(sw_ring[rx_id].mbuf);
2301 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
2302 rte_prefetch0(&rx_ring[rx_id]);
2303 rte_prefetch0(&sw_ring[rx_id]);
2309 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2310 rxdp->rx.bd_base_info = 0;
2311 rxdp->addr = dma_addr;
2313 if (first_seg == NULL) {
2315 first_seg->nb_segs = 1;
2317 first_seg->nb_segs++;
2318 last_seg->next = rxm;
2321 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2322 rxm->data_len = rte_le_to_cpu_16(rxd.rx.size);
2324 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
2331 * The last buffer of the received packet. packet len from
2332 * buffer description may contains CRC len, packet len should
2333 * subtract it, same as data len.
2335 first_seg->pkt_len = rte_le_to_cpu_16(rxd.rx.pkt_len);
2338 * This is the last buffer of the received packet. If the CRC
2339 * is not stripped by the hardware:
2340 * - Subtract the CRC length from the total packet length.
2341 * - If the last buffer only contains the whole CRC or a part
2342 * of it, free the mbuf associated to the last buffer. If part
2343 * of the CRC is also contained in the previous mbuf, subtract
2344 * the length of that CRC part from the data length of the
2348 if (unlikely(rxq->crc_len > 0)) {
2349 first_seg->pkt_len -= rxq->crc_len;
2350 recalculate_data_len(first_seg, last_seg, rxm, rxq,
2354 first_seg->port = rxq->port_id;
2355 first_seg->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
2356 first_seg->ol_flags = PKT_RX_RSS_HASH;
2357 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
2358 first_seg->hash.fdir.hi =
2359 rte_le_to_cpu_16(rxd.rx.fd_id);
2360 first_seg->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
2363 gro_size = hns3_get_field(bd_base_info, HNS3_RXD_GRO_SIZE_M,
2364 HNS3_RXD_GRO_SIZE_S);
2365 if (gro_size != 0) {
2366 first_seg->ol_flags |= PKT_RX_LRO;
2367 first_seg->tso_segsz = gro_size;
2370 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
2371 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
2372 ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info,
2373 l234_info, &cksum_err);
2377 first_seg->packet_type = hns3_rx_calc_ptype(rxq,
2378 l234_info, ol_info);
2380 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B))
2381 hns3_rx_set_cksum_flag(first_seg,
2382 first_seg->packet_type,
2384 hns3_rxd_to_vlan_tci(rxq, first_seg, l234_info, &rxd);
2386 rx_pkts[nb_rx++] = first_seg;
2390 rte_pktmbuf_free(first_seg);
2394 rxq->next_to_use = rx_id;
2395 rxq->pkt_first_seg = first_seg;
2396 rxq->pkt_last_seg = last_seg;
2398 rxq->rx_free_hold += nb_rx_bd;
2399 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
2400 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
2401 rxq->rx_free_hold = 0;
2408 hns3_rxq_vec_setup(__rte_unused struct hns3_rx_queue *rxq)
2413 hns3_rx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
2419 hns3_recv_pkts_vec(__rte_unused void *tx_queue,
2420 __rte_unused struct rte_mbuf **rx_pkts,
2421 __rte_unused uint16_t nb_pkts)
2427 hns3_recv_pkts_vec_sve(__rte_unused void *tx_queue,
2428 __rte_unused struct rte_mbuf **rx_pkts,
2429 __rte_unused uint16_t nb_pkts)
2435 hns3_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2436 struct rte_eth_burst_mode *mode)
2438 static const struct {
2439 eth_rx_burst_t pkt_burst;
2442 { hns3_recv_pkts, "Scalar" },
2443 { hns3_recv_scattered_pkts, "Scalar Scattered" },
2444 { hns3_recv_pkts_vec, "Vector Neon" },
2445 { hns3_recv_pkts_vec_sve, "Vector Sve" },
2448 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2452 for (i = 0; i < RTE_DIM(burst_infos); i++) {
2453 if (pkt_burst == burst_infos[i].pkt_burst) {
2454 snprintf(mode->info, sizeof(mode->info), "%s",
2455 burst_infos[i].info);
2465 hns3_check_sve_support(void)
2467 #if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE)
2468 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE))
2474 static eth_rx_burst_t
2475 hns3_get_rx_function(struct rte_eth_dev *dev)
2477 struct hns3_adapter *hns = dev->data->dev_private;
2478 uint64_t offloads = dev->data->dev_conf.rxmode.offloads;
2480 if (hns->rx_vec_allowed && hns3_rx_check_vec_support(dev) == 0)
2481 return hns3_check_sve_support() ? hns3_recv_pkts_vec_sve :
2484 if (hns->rx_simple_allowed && !dev->data->scattered_rx &&
2485 (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0)
2486 return hns3_recv_pkts;
2488 return hns3_recv_scattered_pkts;
2492 hns3_tx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_txconf *conf,
2493 uint16_t nb_desc, uint16_t *tx_rs_thresh,
2494 uint16_t *tx_free_thresh, uint16_t idx)
2496 #define HNS3_TX_RS_FREE_THRESH_GAP 8
2497 uint16_t rs_thresh, free_thresh, fast_free_thresh;
2499 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
2500 nb_desc % HNS3_ALIGN_RING_DESC) {
2501 hns3_err(hw, "number (%u) of tx descriptors is invalid",
2506 rs_thresh = (conf->tx_rs_thresh > 0) ?
2507 conf->tx_rs_thresh : HNS3_DEFAULT_TX_RS_THRESH;
2508 free_thresh = (conf->tx_free_thresh > 0) ?
2509 conf->tx_free_thresh : HNS3_DEFAULT_TX_FREE_THRESH;
2510 if (rs_thresh + free_thresh > nb_desc || nb_desc % rs_thresh ||
2511 rs_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP ||
2512 free_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP) {
2513 hns3_err(hw, "tx_rs_thresh (%u) tx_free_thresh (%u) nb_desc "
2514 "(%u) of tx descriptors for port=%u queue=%u check "
2516 rs_thresh, free_thresh, nb_desc, hw->data->port_id,
2521 if (conf->tx_free_thresh == 0) {
2522 /* Fast free Tx memory buffer to improve cache hit rate */
2523 fast_free_thresh = nb_desc - rs_thresh;
2524 if (fast_free_thresh >=
2525 HNS3_TX_FAST_FREE_AHEAD + HNS3_DEFAULT_TX_FREE_THRESH)
2526 free_thresh = fast_free_thresh -
2527 HNS3_TX_FAST_FREE_AHEAD;
2530 *tx_rs_thresh = rs_thresh;
2531 *tx_free_thresh = free_thresh;
2536 hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
2537 unsigned int socket_id, const struct rte_eth_txconf *conf)
2539 struct hns3_adapter *hns = dev->data->dev_private;
2540 uint16_t tx_rs_thresh, tx_free_thresh;
2541 struct hns3_hw *hw = &hns->hw;
2542 struct hns3_queue_info q_info;
2543 struct hns3_tx_queue *txq;
2547 ret = hns3_tx_queue_conf_check(hw, conf, nb_desc,
2548 &tx_rs_thresh, &tx_free_thresh, idx);
2552 if (dev->data->tx_queues[idx] != NULL) {
2553 hns3_tx_queue_release(dev->data->tx_queues[idx]);
2554 dev->data->tx_queues[idx] = NULL;
2558 q_info.socket_id = socket_id;
2559 q_info.nb_desc = nb_desc;
2560 q_info.type = "hns3 TX queue";
2561 q_info.ring_name = "tx_ring";
2562 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
2565 "Failed to alloc mem and reserve DMA mem for tx ring!");
2569 txq->tx_deferred_start = conf->tx_deferred_start;
2570 if (txq->tx_deferred_start && !hns3_dev_indep_txrx_supported(hw)) {
2571 hns3_warn(hw, "deferred start is not supported.");
2572 txq->tx_deferred_start = false;
2575 tx_entry_len = sizeof(struct hns3_entry) * txq->nb_tx_desc;
2576 txq->sw_ring = rte_zmalloc_socket("hns3 TX sw ring", tx_entry_len,
2577 RTE_CACHE_LINE_SIZE, socket_id);
2578 if (txq->sw_ring == NULL) {
2579 hns3_err(hw, "Failed to allocate memory for tx sw ring!");
2580 hns3_tx_queue_release(txq);
2585 txq->next_to_use = 0;
2586 txq->next_to_clean = 0;
2587 txq->tx_bd_ready = txq->nb_tx_desc - 1;
2588 txq->tx_free_thresh = tx_free_thresh;
2589 txq->tx_rs_thresh = tx_rs_thresh;
2590 txq->free = rte_zmalloc_socket("hns3 TX mbuf free array",
2591 sizeof(struct rte_mbuf *) * txq->tx_rs_thresh,
2592 RTE_CACHE_LINE_SIZE, socket_id);
2594 hns3_err(hw, "failed to allocate tx mbuf free array!");
2595 hns3_tx_queue_release(txq);
2599 txq->port_id = dev->data->port_id;
2601 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
2602 * the pvid_sw_shift_en in the queue struct should not be changed,
2603 * because PVID-related operations do not need to be processed by PMD
2604 * driver. For hns3 VF device, whether it needs to process PVID depends
2605 * on the configuration of PF kernel mode netdev driver. And the
2606 * related PF configuration is delivered through the mailbox and finally
2607 * reflectd in port_base_vlan_cfg.
2609 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
2610 txq->pvid_sw_shift_en = hw->port_base_vlan_cfg.state ==
2611 HNS3_PORT_BASE_VLAN_ENABLE;
2613 txq->pvid_sw_shift_en = false;
2614 txq->max_non_tso_bd_num = hw->max_non_tso_bd_num;
2615 txq->configured = true;
2616 txq->io_base = (void *)((char *)hw->io_base +
2617 hns3_get_tqp_reg_offset(idx));
2618 txq->io_tail_reg = (volatile void *)((char *)txq->io_base +
2619 HNS3_RING_TX_TAIL_REG);
2620 txq->min_tx_pkt_len = hw->min_tx_pkt_len;
2621 txq->tso_mode = hw->tso_mode;
2622 memset(&txq->basic_stats, 0, sizeof(struct hns3_tx_basic_stats));
2623 memset(&txq->dfx_stats, 0, sizeof(struct hns3_tx_dfx_stats));
2625 rte_spinlock_lock(&hw->lock);
2626 dev->data->tx_queues[idx] = txq;
2627 rte_spinlock_unlock(&hw->lock);
2633 hns3_tx_free_useless_buffer(struct hns3_tx_queue *txq)
2635 uint16_t tx_next_clean = txq->next_to_clean;
2636 uint16_t tx_next_use = txq->next_to_use;
2637 uint16_t tx_bd_ready = txq->tx_bd_ready;
2638 uint16_t tx_bd_max = txq->nb_tx_desc;
2639 struct hns3_entry *tx_bak_pkt = &txq->sw_ring[tx_next_clean];
2640 struct hns3_desc *desc = &txq->tx_ring[tx_next_clean];
2641 struct rte_mbuf *mbuf;
2643 while ((!(desc->tx.tp_fe_sc_vld_ra_ri &
2644 rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)))) &&
2645 tx_next_use != tx_next_clean) {
2646 mbuf = tx_bak_pkt->mbuf;
2648 rte_pktmbuf_free_seg(mbuf);
2649 tx_bak_pkt->mbuf = NULL;
2657 if (tx_next_clean >= tx_bd_max) {
2659 desc = txq->tx_ring;
2660 tx_bak_pkt = txq->sw_ring;
2664 txq->next_to_clean = tx_next_clean;
2665 txq->tx_bd_ready = tx_bd_ready;
2669 hns3_config_gro(struct hns3_hw *hw, bool en)
2671 struct hns3_cfg_gro_status_cmd *req;
2672 struct hns3_cmd_desc desc;
2675 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
2676 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
2678 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
2680 ret = hns3_cmd_send(hw, &desc, 1);
2682 hns3_err(hw, "%s hardware GRO failed, ret = %d",
2683 en ? "enable" : "disable", ret);
2689 hns3_restore_gro_conf(struct hns3_hw *hw)
2695 offloads = hw->data->dev_conf.rxmode.offloads;
2696 gro_en = offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2697 ret = hns3_config_gro(hw, gro_en);
2699 hns3_err(hw, "restore hardware GRO to %s failed, ret = %d",
2700 gro_en ? "enabled" : "disabled", ret);
2706 hns3_pkt_is_tso(struct rte_mbuf *m)
2708 return (m->tso_segsz != 0 && m->ol_flags & PKT_TX_TCP_SEG);
2712 hns3_set_tso(struct hns3_desc *desc, uint32_t paylen, struct rte_mbuf *rxm)
2714 if (!hns3_pkt_is_tso(rxm))
2717 if (paylen <= rxm->tso_segsz)
2720 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(BIT(HNS3_TXD_TSO_B));
2721 desc->tx.mss = rte_cpu_to_le_16(rxm->tso_segsz);
2725 hns3_fill_per_desc(struct hns3_desc *desc, struct rte_mbuf *rxm)
2727 desc->addr = rte_mbuf_data_iova(rxm);
2728 desc->tx.send_size = rte_cpu_to_le_16(rte_pktmbuf_data_len(rxm));
2729 desc->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B));
2733 hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc,
2734 struct rte_mbuf *rxm)
2736 uint64_t ol_flags = rxm->ol_flags;
2740 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len;
2741 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
2742 rxm->outer_l2_len + rxm->outer_l3_len : 0;
2743 paylen = rxm->pkt_len - hdr_len;
2744 desc->tx.paylen = rte_cpu_to_le_32(paylen);
2745 hns3_set_tso(desc, paylen, rxm);
2748 * Currently, hardware doesn't support more than two layers VLAN offload
2749 * in Tx direction based on hns3 network engine. So when the number of
2750 * VLANs in the packets represented by rxm plus the number of VLAN
2751 * offload by hardware such as PVID etc, exceeds two, the packets will
2752 * be discarded or the original VLAN of the packets will be overwitted
2753 * by hardware. When the PF PVID is enabled by calling the API function
2754 * named rte_eth_dev_set_vlan_pvid or the VF PVID is enabled by the hns3
2755 * PF kernel ether driver, the outer VLAN tag will always be the PVID.
2756 * To avoid the VLAN of Tx descriptor is overwritten by PVID, it should
2757 * be added to the position close to the IP header when PVID is enabled.
2759 if (!txq->pvid_sw_shift_en && ol_flags & (PKT_TX_VLAN_PKT |
2761 desc->tx.ol_type_vlan_len_msec |=
2762 rte_cpu_to_le_32(BIT(HNS3_TXD_OVLAN_B));
2763 if (ol_flags & PKT_TX_QINQ_PKT)
2764 desc->tx.outer_vlan_tag =
2765 rte_cpu_to_le_16(rxm->vlan_tci_outer);
2767 desc->tx.outer_vlan_tag =
2768 rte_cpu_to_le_16(rxm->vlan_tci);
2771 if (ol_flags & PKT_TX_QINQ_PKT ||
2772 ((ol_flags & PKT_TX_VLAN_PKT) && txq->pvid_sw_shift_en)) {
2773 desc->tx.type_cs_vlan_tso_len |=
2774 rte_cpu_to_le_32(BIT(HNS3_TXD_VLAN_B));
2775 desc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci);
2780 hns3_tx_alloc_mbufs(struct rte_mempool *mb_pool, uint16_t nb_new_buf,
2781 struct rte_mbuf **alloc_mbuf)
2783 #define MAX_NON_TSO_BD_PER_PKT 18
2784 struct rte_mbuf *pkt_segs[MAX_NON_TSO_BD_PER_PKT];
2787 /* Allocate enough mbufs */
2788 if (rte_mempool_get_bulk(mb_pool, (void **)pkt_segs, nb_new_buf))
2791 for (i = 0; i < nb_new_buf - 1; i++)
2792 pkt_segs[i]->next = pkt_segs[i + 1];
2794 pkt_segs[nb_new_buf - 1]->next = NULL;
2795 pkt_segs[0]->nb_segs = nb_new_buf;
2796 *alloc_mbuf = pkt_segs[0];
2802 hns3_pktmbuf_copy_hdr(struct rte_mbuf *new_pkt, struct rte_mbuf *old_pkt)
2804 new_pkt->ol_flags = old_pkt->ol_flags;
2805 new_pkt->pkt_len = rte_pktmbuf_pkt_len(old_pkt);
2806 new_pkt->outer_l2_len = old_pkt->outer_l2_len;
2807 new_pkt->outer_l3_len = old_pkt->outer_l3_len;
2808 new_pkt->l2_len = old_pkt->l2_len;
2809 new_pkt->l3_len = old_pkt->l3_len;
2810 new_pkt->l4_len = old_pkt->l4_len;
2811 new_pkt->vlan_tci_outer = old_pkt->vlan_tci_outer;
2812 new_pkt->vlan_tci = old_pkt->vlan_tci;
2816 hns3_reassemble_tx_pkts(struct rte_mbuf *tx_pkt, struct rte_mbuf **new_pkt,
2817 uint8_t max_non_tso_bd_num)
2819 struct rte_mempool *mb_pool;
2820 struct rte_mbuf *new_mbuf;
2821 struct rte_mbuf *temp_new;
2822 struct rte_mbuf *temp;
2823 uint16_t last_buf_len;
2824 uint16_t nb_new_buf;
2834 mb_pool = tx_pkt->pool;
2835 buf_size = tx_pkt->buf_len - RTE_PKTMBUF_HEADROOM;
2836 nb_new_buf = (rte_pktmbuf_pkt_len(tx_pkt) - 1) / buf_size + 1;
2837 if (nb_new_buf > max_non_tso_bd_num)
2840 last_buf_len = rte_pktmbuf_pkt_len(tx_pkt) % buf_size;
2841 if (last_buf_len == 0)
2842 last_buf_len = buf_size;
2844 /* Allocate enough mbufs */
2845 ret = hns3_tx_alloc_mbufs(mb_pool, nb_new_buf, &new_mbuf);
2849 /* Copy the original packet content to the new mbufs */
2851 s = rte_pktmbuf_mtod(temp, char *);
2852 len_s = rte_pktmbuf_data_len(temp);
2853 temp_new = new_mbuf;
2854 while (temp != NULL && temp_new != NULL) {
2855 d = rte_pktmbuf_mtod(temp_new, char *);
2856 buf_len = temp_new->next == NULL ? last_buf_len : buf_size;
2860 len = RTE_MIN(len_s, len_d);
2864 len_d = len_d - len;
2865 len_s = len_s - len;
2871 s = rte_pktmbuf_mtod(temp, char *);
2872 len_s = rte_pktmbuf_data_len(temp);
2876 temp_new->data_len = buf_len;
2877 temp_new = temp_new->next;
2879 hns3_pktmbuf_copy_hdr(new_mbuf, tx_pkt);
2881 /* free original mbufs */
2882 rte_pktmbuf_free(tx_pkt);
2884 *new_pkt = new_mbuf;
2890 hns3_parse_outer_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec)
2892 uint32_t tmp = *ol_type_vlan_len_msec;
2893 uint64_t ol_flags = m->ol_flags;
2895 /* (outer) IP header type */
2896 if (ol_flags & PKT_TX_OUTER_IPV4) {
2897 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2898 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M,
2899 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_CSUM);
2901 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M,
2902 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_NO_CSUM);
2903 } else if (ol_flags & PKT_TX_OUTER_IPV6) {
2904 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
2907 /* OL3 header size, defined in 4 bytes */
2908 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2909 m->outer_l3_len >> HNS3_L3_LEN_UNIT);
2910 *ol_type_vlan_len_msec = tmp;
2914 hns3_parse_inner_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec,
2915 uint32_t *type_cs_vlan_tso_len)
2917 #define HNS3_NVGRE_HLEN 8
2918 uint32_t tmp_outer = *ol_type_vlan_len_msec;
2919 uint32_t tmp_inner = *type_cs_vlan_tso_len;
2920 uint64_t ol_flags = m->ol_flags;
2921 uint16_t inner_l2_len;
2923 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2924 case PKT_TX_TUNNEL_VXLAN_GPE:
2925 case PKT_TX_TUNNEL_GENEVE:
2926 case PKT_TX_TUNNEL_VXLAN:
2927 /* MAC in UDP tunnelling packet, include VxLAN and GENEVE */
2928 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M,
2929 HNS3_TXD_TUNTYPE_S, HNS3_TUN_MAC_IN_UDP);
2931 * The inner l2 length of mbuf is the sum of outer l4 length,
2932 * tunneling header length and inner l2 length for a tunnel
2933 * packect. But in hns3 tx descriptor, the tunneling header
2934 * length is contained in the field of outer L4 length.
2935 * Therefore, driver need to calculate the outer L4 length and
2938 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M,
2940 (uint8_t)RTE_ETHER_VXLAN_HLEN >>
2943 inner_l2_len = m->l2_len - RTE_ETHER_VXLAN_HLEN;
2945 case PKT_TX_TUNNEL_GRE:
2946 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M,
2947 HNS3_TXD_TUNTYPE_S, HNS3_TUN_NVGRE);
2949 * For NVGRE tunnel packect, the outer L4 is empty. So only
2950 * fill the NVGRE header length to the outer L4 field.
2952 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M,
2954 (uint8_t)HNS3_NVGRE_HLEN >> HNS3_L4_LEN_UNIT);
2956 inner_l2_len = m->l2_len - HNS3_NVGRE_HLEN;
2959 /* For non UDP / GRE tunneling, drop the tunnel packet */
2963 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2964 inner_l2_len >> HNS3_L2_LEN_UNIT);
2965 /* OL2 header size, defined in 2 bytes */
2966 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2967 m->outer_l2_len >> HNS3_L2_LEN_UNIT);
2969 *type_cs_vlan_tso_len = tmp_inner;
2970 *ol_type_vlan_len_msec = tmp_outer;
2976 hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m,
2977 uint16_t tx_desc_id)
2979 struct hns3_desc *tx_ring = txq->tx_ring;
2980 struct hns3_desc *desc = &tx_ring[tx_desc_id];
2981 uint32_t tmp_outer = 0;
2982 uint32_t tmp_inner = 0;
2986 * The tunnel header is contained in the inner L2 header field of the
2987 * mbuf, but for hns3 descriptor, it is contained in the outer L4. So,
2988 * there is a need that switching between them. To avoid multiple
2989 * calculations, the length of the L2 header include the outer and
2990 * inner, will be filled during the parsing of tunnel packects.
2992 if (!(m->ol_flags & PKT_TX_TUNNEL_MASK)) {
2994 * For non tunnel type the tunnel type id is 0, so no need to
2995 * assign a value to it. Only the inner(normal) L2 header length
2998 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M,
2999 HNS3_TXD_L2LEN_S, m->l2_len >> HNS3_L2_LEN_UNIT);
3002 * If outer csum is not offload, the outer length may be filled
3003 * with 0. And the length of the outer header is added to the
3004 * inner l2_len. It would lead a cksum error. So driver has to
3005 * calculate the header length.
3007 if (unlikely(!(m->ol_flags & PKT_TX_OUTER_IP_CKSUM) &&
3008 m->outer_l2_len == 0)) {
3009 struct rte_net_hdr_lens hdr_len;
3010 (void)rte_net_get_ptype(m, &hdr_len,
3011 RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK);
3012 m->outer_l3_len = hdr_len.l3_len;
3013 m->outer_l2_len = hdr_len.l2_len;
3014 m->l2_len = m->l2_len - hdr_len.l2_len - hdr_len.l3_len;
3016 hns3_parse_outer_params(m, &tmp_outer);
3017 ret = hns3_parse_inner_params(m, &tmp_outer, &tmp_inner);
3022 desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp_outer);
3023 desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp_inner);
3029 hns3_parse_l3_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len)
3031 uint64_t ol_flags = m->ol_flags;
3035 tmp = *type_cs_vlan_tso_len;
3036 if (ol_flags & PKT_TX_IPV4)
3037 l3_type = HNS3_L3T_IPV4;
3038 else if (ol_flags & PKT_TX_IPV6)
3039 l3_type = HNS3_L3T_IPV6;
3041 l3_type = HNS3_L3T_NONE;
3043 /* inner(/normal) L3 header size, defined in 4 bytes */
3044 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
3045 m->l3_len >> HNS3_L3_LEN_UNIT);
3047 tmp |= hns3_gen_field_val(HNS3_TXD_L3T_M, HNS3_TXD_L3T_S, l3_type);
3049 /* Enable L3 checksum offloads */
3050 if (ol_flags & PKT_TX_IP_CKSUM)
3051 tmp |= BIT(HNS3_TXD_L3CS_B);
3052 *type_cs_vlan_tso_len = tmp;
3056 hns3_parse_l4_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len)
3058 uint64_t ol_flags = m->ol_flags;
3060 /* Enable L4 checksum offloads */
3061 switch (ol_flags & (PKT_TX_L4_MASK | PKT_TX_TCP_SEG)) {
3062 case PKT_TX_TCP_CKSUM:
3063 case PKT_TX_TCP_SEG:
3064 tmp = *type_cs_vlan_tso_len;
3065 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3068 case PKT_TX_UDP_CKSUM:
3069 tmp = *type_cs_vlan_tso_len;
3070 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3073 case PKT_TX_SCTP_CKSUM:
3074 tmp = *type_cs_vlan_tso_len;
3075 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3081 tmp |= BIT(HNS3_TXD_L4CS_B);
3082 tmp |= hns3_gen_field_val(HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
3083 m->l4_len >> HNS3_L4_LEN_UNIT);
3084 *type_cs_vlan_tso_len = tmp;
3088 hns3_txd_enable_checksum(struct hns3_tx_queue *txq, struct rte_mbuf *m,
3089 uint16_t tx_desc_id)
3091 struct hns3_desc *tx_ring = txq->tx_ring;
3092 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3095 hns3_parse_l3_cksum_params(m, &value);
3096 hns3_parse_l4_cksum_params(m, &value);
3098 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(value);
3102 hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num,
3103 uint32_t max_non_tso_bd_num)
3105 struct rte_mbuf *m_first = tx_pkts;
3106 struct rte_mbuf *m_last = tx_pkts;
3107 uint32_t tot_len = 0;
3112 * Hardware requires that the sum of the data length of every 8
3113 * consecutive buffers is greater than MSS in hns3 network engine.
3114 * We simplify it by ensuring pkt_headlen + the first 8 consecutive
3115 * frags greater than gso header len + mss, and the remaining 7
3116 * consecutive frags greater than MSS except the last 7 frags.
3118 if (bd_num <= max_non_tso_bd_num)
3121 for (i = 0; m_last && i < max_non_tso_bd_num - 1;
3122 i++, m_last = m_last->next)
3123 tot_len += m_last->data_len;
3128 /* ensure the first 8 frags is greater than mss + header */
3129 hdr_len = tx_pkts->l2_len + tx_pkts->l3_len + tx_pkts->l4_len;
3130 hdr_len += (tx_pkts->ol_flags & PKT_TX_TUNNEL_MASK) ?
3131 tx_pkts->outer_l2_len + tx_pkts->outer_l3_len : 0;
3132 if (tot_len + m_last->data_len < tx_pkts->tso_segsz + hdr_len)
3136 * ensure the sum of the data length of every 7 consecutive buffer
3137 * is greater than mss except the last one.
3139 for (i = 0; m_last && i < bd_num - max_non_tso_bd_num; i++) {
3140 tot_len -= m_first->data_len;
3141 tot_len += m_last->data_len;
3143 if (tot_len < tx_pkts->tso_segsz)
3146 m_first = m_first->next;
3147 m_last = m_last->next;
3154 hns3_outer_header_cksum_prepare(struct rte_mbuf *m)
3156 uint64_t ol_flags = m->ol_flags;
3157 uint32_t paylen, hdr_len, l4_proto;
3159 if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6)))
3162 if (ol_flags & PKT_TX_OUTER_IPV4) {
3163 struct rte_ipv4_hdr *ipv4_hdr;
3164 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
3166 l4_proto = ipv4_hdr->next_proto_id;
3167 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
3168 ipv4_hdr->hdr_checksum = 0;
3170 struct rte_ipv6_hdr *ipv6_hdr;
3171 ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *,
3173 l4_proto = ipv6_hdr->proto;
3175 /* driver should ensure the outer udp cksum is 0 for TUNNEL TSO */
3176 if (l4_proto == IPPROTO_UDP && (ol_flags & PKT_TX_TCP_SEG)) {
3177 struct rte_udp_hdr *udp_hdr;
3178 hdr_len = m->l2_len + m->l3_len + m->l4_len;
3179 hdr_len += m->outer_l2_len + m->outer_l3_len;
3180 paylen = m->pkt_len - hdr_len;
3181 if (paylen <= m->tso_segsz)
3183 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3186 udp_hdr->dgram_cksum = 0;
3191 hns3_check_tso_pkt_valid(struct rte_mbuf *m)
3193 uint32_t tmp_data_len_sum = 0;
3194 uint16_t nb_buf = m->nb_segs;
3195 uint32_t paylen, hdr_len;
3196 struct rte_mbuf *m_seg;
3199 if (nb_buf > HNS3_MAX_TSO_BD_PER_PKT)
3202 hdr_len = m->l2_len + m->l3_len + m->l4_len;
3203 hdr_len += (m->ol_flags & PKT_TX_TUNNEL_MASK) ?
3204 m->outer_l2_len + m->outer_l3_len : 0;
3205 if (hdr_len > HNS3_MAX_TSO_HDR_SIZE)
3208 paylen = m->pkt_len - hdr_len;
3209 if (paylen > HNS3_MAX_BD_PAYLEN)
3213 * The TSO header (include outer and inner L2, L3 and L4 header)
3214 * should be provided by three descriptors in maximum in hns3 network
3218 for (i = 0; m_seg != NULL && i < HNS3_MAX_TSO_HDR_BD_NUM && i < nb_buf;
3219 i++, m_seg = m_seg->next) {
3220 tmp_data_len_sum += m_seg->data_len;
3223 if (hdr_len > tmp_data_len_sum)
3229 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3231 hns3_vld_vlan_chk(struct hns3_tx_queue *txq, struct rte_mbuf *m)
3233 struct rte_ether_hdr *eh;
3234 struct rte_vlan_hdr *vh;
3236 if (!txq->pvid_sw_shift_en)
3240 * Due to hardware limitations, we only support two-layer VLAN hardware
3241 * offload in Tx direction based on hns3 network engine, so when PVID is
3242 * enabled, QinQ insert is no longer supported.
3243 * And when PVID is enabled, in the following two cases:
3244 * i) packets with more than two VLAN tags.
3245 * ii) packets with one VLAN tag while the hardware VLAN insert is
3247 * The packets will be regarded as abnormal packets and discarded by
3248 * hardware in Tx direction. For debugging purposes, a validation check
3249 * for these types of packets is added to the '.tx_pkt_prepare' ops
3250 * implementation function named hns3_prep_pkts to inform users that
3251 * these packets will be discarded.
3253 if (m->ol_flags & PKT_TX_QINQ_PKT)
3256 eh = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
3257 if (eh->ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
3258 if (m->ol_flags & PKT_TX_VLAN_PKT)
3261 /* Ensure the incoming packet is not a QinQ packet */
3262 vh = (struct rte_vlan_hdr *)(eh + 1);
3263 if (vh->eth_proto == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN))
3272 hns3_prep_pkt_proc(struct hns3_tx_queue *tx_queue, struct rte_mbuf *m)
3276 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3277 ret = rte_validate_tx_offload(m);
3283 ret = hns3_vld_vlan_chk(tx_queue, m);
3289 if (hns3_pkt_is_tso(m)) {
3290 if (hns3_pkt_need_linearized(m, m->nb_segs,
3291 tx_queue->max_non_tso_bd_num) ||
3292 hns3_check_tso_pkt_valid(m)) {
3297 if (tx_queue->tso_mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) {
3299 * (tso mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) means
3300 * hardware support recalculate the TCP pseudo header
3301 * checksum of packets that need TSO, so network driver
3302 * software not need to recalculate it.
3304 hns3_outer_header_cksum_prepare(m);
3309 ret = rte_net_intel_cksum_prepare(m);
3315 hns3_outer_header_cksum_prepare(m);
3321 hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3327 for (i = 0; i < nb_pkts; i++) {
3329 if (hns3_prep_pkt_proc(tx_queue, m))
3337 hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
3340 struct hns3_desc *tx_ring = txq->tx_ring;
3341 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3343 /* Enable checksum offloading */
3344 if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK) {
3345 /* Fill in tunneling parameters if necessary */
3346 if (hns3_parse_tunneling_params(txq, m, tx_desc_id)) {
3347 txq->dfx_stats.unsupported_tunnel_pkt_cnt++;
3351 hns3_txd_enable_checksum(txq, m, tx_desc_id);
3353 /* clear the control bit */
3354 desc->tx.type_cs_vlan_tso_len = 0;
3355 desc->tx.ol_type_vlan_len_msec = 0;
3362 hns3_check_non_tso_pkt(uint16_t nb_buf, struct rte_mbuf **m_seg,
3363 struct rte_mbuf *tx_pkt, struct hns3_tx_queue *txq)
3365 uint8_t max_non_tso_bd_num;
3366 struct rte_mbuf *new_pkt;
3369 if (hns3_pkt_is_tso(*m_seg))
3373 * If packet length is greater than HNS3_MAX_FRAME_LEN
3374 * driver support, the packet will be ignored.
3376 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) > HNS3_MAX_FRAME_LEN)) {
3377 txq->dfx_stats.over_length_pkt_cnt++;
3381 max_non_tso_bd_num = txq->max_non_tso_bd_num;
3382 if (unlikely(nb_buf > max_non_tso_bd_num)) {
3383 txq->dfx_stats.exceed_limit_bd_pkt_cnt++;
3384 ret = hns3_reassemble_tx_pkts(tx_pkt, &new_pkt,
3385 max_non_tso_bd_num);
3387 txq->dfx_stats.exceed_limit_bd_reassem_fail++;
3397 hns3_tx_free_buffer_simple(struct hns3_tx_queue *txq)
3399 struct hns3_entry *tx_entry;
3400 struct hns3_desc *desc;
3401 uint16_t tx_next_clean;
3405 if (HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) < txq->tx_rs_thresh)
3409 * All mbufs can be released only when the VLD bits of all
3410 * descriptors in a batch are cleared.
3412 tx_next_clean = (txq->next_to_clean + txq->tx_rs_thresh - 1) %
3414 desc = &txq->tx_ring[tx_next_clean];
3415 for (i = 0; i < txq->tx_rs_thresh; i++) {
3416 if (rte_le_to_cpu_16(desc->tx.tp_fe_sc_vld_ra_ri) &
3417 BIT(HNS3_TXD_VLD_B))
3422 tx_entry = &txq->sw_ring[txq->next_to_clean];
3424 for (i = 0; i < txq->tx_rs_thresh; i++)
3425 rte_prefetch0((tx_entry + i)->mbuf);
3426 for (i = 0; i < txq->tx_rs_thresh; i++, tx_entry++) {
3427 rte_mempool_put(tx_entry->mbuf->pool, tx_entry->mbuf);
3428 tx_entry->mbuf = NULL;
3431 txq->next_to_clean = (tx_next_clean + 1) % txq->nb_tx_desc;
3432 txq->tx_bd_ready += txq->tx_rs_thresh;
3437 hns3_tx_backup_1mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
3439 tx_entry->mbuf = pkts[0];
3443 hns3_tx_backup_4mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
3445 hns3_tx_backup_1mbuf(&tx_entry[0], &pkts[0]);
3446 hns3_tx_backup_1mbuf(&tx_entry[1], &pkts[1]);
3447 hns3_tx_backup_1mbuf(&tx_entry[2], &pkts[2]);
3448 hns3_tx_backup_1mbuf(&tx_entry[3], &pkts[3]);
3452 hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
3454 #define PER_LOOP_NUM 4
3455 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
3459 for (i = 0; i < PER_LOOP_NUM; i++, txdp++, pkts++) {
3460 dma_addr = rte_mbuf_data_iova(*pkts);
3461 txdp->addr = rte_cpu_to_le_64(dma_addr);
3462 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
3463 txdp->tx.paylen = 0;
3464 txdp->tx.type_cs_vlan_tso_len = 0;
3465 txdp->tx.ol_type_vlan_len_msec = 0;
3466 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
3471 hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
3473 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
3476 dma_addr = rte_mbuf_data_iova(*pkts);
3477 txdp->addr = rte_cpu_to_le_64(dma_addr);
3478 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
3479 txdp->tx.paylen = 0;
3480 txdp->tx.type_cs_vlan_tso_len = 0;
3481 txdp->tx.ol_type_vlan_len_msec = 0;
3482 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
3486 hns3_tx_fill_hw_ring(struct hns3_tx_queue *txq,
3487 struct rte_mbuf **pkts,
3490 #define PER_LOOP_NUM 4
3491 #define PER_LOOP_MASK (PER_LOOP_NUM - 1)
3492 struct hns3_desc *txdp = &txq->tx_ring[txq->next_to_use];
3493 struct hns3_entry *tx_entry = &txq->sw_ring[txq->next_to_use];
3494 const uint32_t mainpart = (nb_pkts & ((uint32_t)~PER_LOOP_MASK));
3495 const uint32_t leftover = (nb_pkts & ((uint32_t)PER_LOOP_MASK));
3498 for (i = 0; i < mainpart; i += PER_LOOP_NUM) {
3499 hns3_tx_backup_4mbuf(tx_entry + i, pkts + i);
3500 hns3_tx_setup_4bd(txdp + i, pkts + i);
3502 if (unlikely(leftover > 0)) {
3503 for (i = 0; i < leftover; i++) {
3504 hns3_tx_backup_1mbuf(tx_entry + mainpart + i,
3505 pkts + mainpart + i);
3506 hns3_tx_setup_1bd(txdp + mainpart + i,
3507 pkts + mainpart + i);
3513 hns3_xmit_pkts_simple(void *tx_queue,
3514 struct rte_mbuf **tx_pkts,
3517 struct hns3_tx_queue *txq = tx_queue;
3520 hns3_tx_free_buffer_simple(txq);
3522 nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts);
3523 if (unlikely(nb_pkts == 0)) {
3524 if (txq->tx_bd_ready == 0)
3525 txq->dfx_stats.queue_full_cnt++;
3529 txq->tx_bd_ready -= nb_pkts;
3530 if (txq->next_to_use + nb_pkts > txq->nb_tx_desc) {
3531 nb_tx = txq->nb_tx_desc - txq->next_to_use;
3532 hns3_tx_fill_hw_ring(txq, tx_pkts, nb_tx);
3533 txq->next_to_use = 0;
3536 hns3_tx_fill_hw_ring(txq, tx_pkts + nb_tx, nb_pkts - nb_tx);
3537 txq->next_to_use += nb_pkts - nb_tx;
3539 hns3_write_reg_opt(txq->io_tail_reg, nb_pkts);
3545 hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
3547 struct hns3_tx_queue *txq = tx_queue;
3548 struct hns3_entry *tx_bak_pkt;
3549 struct hns3_desc *tx_ring;
3550 struct rte_mbuf *tx_pkt;
3551 struct rte_mbuf *m_seg;
3552 struct hns3_desc *desc;
3553 uint32_t nb_hold = 0;
3554 uint16_t tx_next_use;
3555 uint16_t tx_pkt_num;
3561 /* free useless buffer */
3562 hns3_tx_free_useless_buffer(txq);
3564 tx_next_use = txq->next_to_use;
3565 tx_bd_max = txq->nb_tx_desc;
3566 tx_pkt_num = nb_pkts;
3567 tx_ring = txq->tx_ring;
3570 tx_bak_pkt = &txq->sw_ring[tx_next_use];
3571 for (nb_tx = 0; nb_tx < tx_pkt_num; nb_tx++) {
3572 tx_pkt = *tx_pkts++;
3574 nb_buf = tx_pkt->nb_segs;
3576 if (nb_buf > txq->tx_bd_ready) {
3577 txq->dfx_stats.queue_full_cnt++;
3585 * If packet length is less than minimum packet length supported
3586 * by hardware in Tx direction, driver need to pad it to avoid
3589 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) <
3590 txq->min_tx_pkt_len)) {
3594 add_len = txq->min_tx_pkt_len -
3595 rte_pktmbuf_pkt_len(tx_pkt);
3596 appended = rte_pktmbuf_append(tx_pkt, add_len);
3597 if (appended == NULL) {
3598 txq->dfx_stats.pkt_padding_fail_cnt++;
3602 memset(appended, 0, add_len);
3607 if (hns3_check_non_tso_pkt(nb_buf, &m_seg, tx_pkt, txq))
3610 if (hns3_parse_cksum(txq, tx_next_use, m_seg))
3614 desc = &tx_ring[tx_next_use];
3617 * If the packet is divided into multiple Tx Buffer Descriptors,
3618 * only need to fill vlan, paylen and tso into the first Tx
3619 * Buffer Descriptor.
3621 hns3_fill_first_desc(txq, desc, m_seg);
3624 desc = &tx_ring[tx_next_use];
3626 * Fill valid bits, DMA address and data length for each
3627 * Tx Buffer Descriptor.
3629 hns3_fill_per_desc(desc, m_seg);
3630 tx_bak_pkt->mbuf = m_seg;
3631 m_seg = m_seg->next;
3634 if (tx_next_use >= tx_bd_max) {
3636 tx_bak_pkt = txq->sw_ring;
3640 } while (m_seg != NULL);
3642 /* Add end flag for the last Tx Buffer Descriptor */
3643 desc->tx.tp_fe_sc_vld_ra_ri |=
3644 rte_cpu_to_le_16(BIT(HNS3_TXD_FE_B));
3647 txq->next_to_use = tx_next_use;
3648 txq->tx_bd_ready -= i;
3654 hns3_write_reg_opt(txq->io_tail_reg, nb_hold);
3660 hns3_tx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
3666 hns3_xmit_pkts_vec(__rte_unused void *tx_queue,
3667 __rte_unused struct rte_mbuf **tx_pkts,
3668 __rte_unused uint16_t nb_pkts)
3674 hns3_xmit_pkts_vec_sve(void __rte_unused * tx_queue,
3675 struct rte_mbuf __rte_unused **tx_pkts,
3676 uint16_t __rte_unused nb_pkts)
3682 hns3_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3683 struct rte_eth_burst_mode *mode)
3685 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3686 const char *info = NULL;
3688 if (pkt_burst == hns3_xmit_pkts_simple)
3689 info = "Scalar Simple";
3690 else if (pkt_burst == hns3_xmit_pkts)
3692 else if (pkt_burst == hns3_xmit_pkts_vec)
3693 info = "Vector Neon";
3694 else if (pkt_burst == hns3_xmit_pkts_vec_sve)
3695 info = "Vector Sve";
3700 snprintf(mode->info, sizeof(mode->info), "%s", info);
3705 static eth_tx_burst_t
3706 hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep)
3708 uint64_t offloads = dev->data->dev_conf.txmode.offloads;
3709 struct hns3_adapter *hns = dev->data->dev_private;
3711 if (hns->tx_vec_allowed && hns3_tx_check_vec_support(dev) == 0) {
3713 return hns3_check_sve_support() ? hns3_xmit_pkts_vec_sve :
3717 if (hns->tx_simple_allowed &&
3718 offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)) {
3720 return hns3_xmit_pkts_simple;
3723 *prep = hns3_prep_pkts;
3724 return hns3_xmit_pkts;
3728 hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused,
3729 struct rte_mbuf **pkts __rte_unused,
3730 uint16_t pkts_n __rte_unused)
3735 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)
3737 struct hns3_adapter *hns = eth_dev->data->dev_private;
3738 eth_tx_prep_t prep = NULL;
3740 if (hns->hw.adapter_state == HNS3_NIC_STARTED &&
3741 __atomic_load_n(&hns->hw.reset.resetting, __ATOMIC_RELAXED) == 0) {
3742 eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev);
3743 eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep);
3744 eth_dev->tx_pkt_prepare = prep;
3746 eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst;
3747 eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
3748 eth_dev->tx_pkt_prepare = hns3_dummy_rxtx_burst;
3753 hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3754 struct rte_eth_rxq_info *qinfo)
3756 struct hns3_rx_queue *rxq = dev->data->rx_queues[queue_id];
3758 qinfo->mp = rxq->mb_pool;
3759 qinfo->nb_desc = rxq->nb_rx_desc;
3760 qinfo->scattered_rx = dev->data->scattered_rx;
3761 /* Report the HW Rx buffer length to user */
3762 qinfo->rx_buf_size = rxq->rx_buf_len;
3765 * If there are no available Rx buffer descriptors, incoming packets
3766 * are always dropped by hardware based on hns3 network engine.
3768 qinfo->conf.rx_drop_en = 1;
3769 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
3770 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3771 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3775 hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3776 struct rte_eth_txq_info *qinfo)
3778 struct hns3_tx_queue *txq = dev->data->tx_queues[queue_id];
3780 qinfo->nb_desc = txq->nb_tx_desc;
3781 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
3782 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3783 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3784 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3788 hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3790 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3791 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id];
3792 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3795 if (!hns3_dev_indep_txrx_supported(hw))
3798 ret = hns3_reset_queue(hw, rx_queue_id, HNS3_RING_TYPE_RX);
3800 hns3_err(hw, "fail to reset Rx queue %u, ret = %d.",
3805 ret = hns3_init_rxq(hns, rx_queue_id);
3807 hns3_err(hw, "fail to init Rx queue %u, ret = %d.",
3812 hns3_enable_rxq(rxq, true);
3813 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
3819 hns3_reset_sw_rxq(struct hns3_rx_queue *rxq)
3821 rxq->next_to_use = 0;
3822 rxq->rx_rearm_start = 0;
3823 rxq->rx_free_hold = 0;
3824 rxq->rx_rearm_nb = 0;
3825 rxq->pkt_first_seg = NULL;
3826 rxq->pkt_last_seg = NULL;
3827 memset(&rxq->rx_ring[0], 0, rxq->nb_rx_desc * sizeof(struct hns3_desc));
3828 hns3_rxq_vec_setup(rxq);
3832 hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3834 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3835 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id];
3837 if (!hns3_dev_indep_txrx_supported(hw))
3840 hns3_enable_rxq(rxq, false);
3842 hns3_rx_queue_release_mbufs(rxq);
3844 hns3_reset_sw_rxq(rxq);
3845 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
3851 hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3853 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3854 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id];
3857 if (!hns3_dev_indep_txrx_supported(hw))
3860 ret = hns3_reset_queue(hw, tx_queue_id, HNS3_RING_TYPE_TX);
3862 hns3_err(hw, "fail to reset Tx queue %u, ret = %d.",
3868 hns3_enable_txq(txq, true);
3869 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
3875 hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3877 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3878 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id];
3880 if (!hns3_dev_indep_txrx_supported(hw))
3883 hns3_enable_txq(txq, false);
3884 hns3_tx_queue_release_mbufs(txq);
3886 * All the mbufs in sw_ring are released and all the pointers in sw_ring
3887 * are set to NULL. If this queue is still called by upper layer,
3888 * residual SW status of this txq may cause these pointers in sw_ring
3889 * which have been set to NULL to be released again. To avoid it,
3893 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
3899 hns3_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3902 * Number of BDs that have been processed by the driver
3903 * but have not been notified to the hardware.
3905 uint32_t driver_hold_bd_num;
3906 struct hns3_rx_queue *rxq;
3909 rxq = dev->data->rx_queues[rx_queue_id];
3910 fbd_num = hns3_read_dev(rxq, HNS3_RING_RX_FBDNUM_REG);
3911 if (dev->rx_pkt_burst == hns3_recv_pkts_vec ||
3912 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve)
3913 driver_hold_bd_num = rxq->rx_rearm_nb;
3915 driver_hold_bd_num = rxq->rx_free_hold;
3917 if (fbd_num <= driver_hold_bd_num)
3920 return fbd_num - driver_hold_bd_num;