1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
11 #include <rte_bus_pci.h>
12 #include <rte_byteorder.h>
13 #include <rte_common.h>
14 #include <rte_cycles.h>
17 #include <rte_ether.h>
18 #include <rte_vxlan.h>
19 #include <rte_ethdev_driver.h>
24 #include <rte_malloc.h>
27 #include "hns3_ethdev.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_regs.h"
30 #include "hns3_logs.h"
32 #define HNS3_CFG_DESC_NUM(num) ((num) / 8 - 1)
33 #define HNS3_RX_RING_PREFETCTH_MASK 3
36 hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq)
40 /* Note: Fake rx queue will not enter here */
41 if (rxq->sw_ring == NULL)
44 if (rxq->rx_rearm_nb == 0) {
45 for (i = 0; i < rxq->nb_rx_desc; i++) {
46 if (rxq->sw_ring[i].mbuf != NULL) {
47 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
48 rxq->sw_ring[i].mbuf = NULL;
52 for (i = rxq->next_to_use;
53 i != rxq->rx_rearm_start;
54 i = (i + 1) % rxq->nb_rx_desc) {
55 if (rxq->sw_ring[i].mbuf != NULL) {
56 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
57 rxq->sw_ring[i].mbuf = NULL;
62 for (i = 0; i < rxq->bulk_mbuf_num; i++)
63 rte_pktmbuf_free_seg(rxq->bulk_mbuf[i]);
64 rxq->bulk_mbuf_num = 0;
66 if (rxq->pkt_first_seg) {
67 rte_pktmbuf_free(rxq->pkt_first_seg);
68 rxq->pkt_first_seg = NULL;
73 hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq)
77 /* Note: Fake rx queue will not enter here */
79 for (i = 0; i < txq->nb_tx_desc; i++) {
80 if (txq->sw_ring[i].mbuf) {
81 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
82 txq->sw_ring[i].mbuf = NULL;
89 hns3_rx_queue_release(void *queue)
91 struct hns3_rx_queue *rxq = queue;
93 hns3_rx_queue_release_mbufs(rxq);
95 rte_memzone_free(rxq->mz);
97 rte_free(rxq->sw_ring);
103 hns3_tx_queue_release(void *queue)
105 struct hns3_tx_queue *txq = queue;
107 hns3_tx_queue_release_mbufs(txq);
109 rte_memzone_free(txq->mz);
111 rte_free(txq->sw_ring);
119 hns3_dev_rx_queue_release(void *queue)
121 struct hns3_rx_queue *rxq = queue;
122 struct hns3_adapter *hns;
128 rte_spinlock_lock(&hns->hw.lock);
129 hns3_rx_queue_release(queue);
130 rte_spinlock_unlock(&hns->hw.lock);
134 hns3_dev_tx_queue_release(void *queue)
136 struct hns3_tx_queue *txq = queue;
137 struct hns3_adapter *hns;
143 rte_spinlock_lock(&hns->hw.lock);
144 hns3_tx_queue_release(queue);
145 rte_spinlock_unlock(&hns->hw.lock);
149 hns3_fake_rx_queue_release(struct hns3_rx_queue *queue)
151 struct hns3_rx_queue *rxq = queue;
152 struct hns3_adapter *hns;
162 if (hw->fkq_data.rx_queues[idx]) {
163 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
164 hw->fkq_data.rx_queues[idx] = NULL;
167 /* free fake rx queue arrays */
168 if (idx == (hw->fkq_data.nb_fake_rx_queues - 1)) {
169 hw->fkq_data.nb_fake_rx_queues = 0;
170 rte_free(hw->fkq_data.rx_queues);
171 hw->fkq_data.rx_queues = NULL;
176 hns3_fake_tx_queue_release(struct hns3_tx_queue *queue)
178 struct hns3_tx_queue *txq = queue;
179 struct hns3_adapter *hns;
189 if (hw->fkq_data.tx_queues[idx]) {
190 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
191 hw->fkq_data.tx_queues[idx] = NULL;
194 /* free fake tx queue arrays */
195 if (idx == (hw->fkq_data.nb_fake_tx_queues - 1)) {
196 hw->fkq_data.nb_fake_tx_queues = 0;
197 rte_free(hw->fkq_data.tx_queues);
198 hw->fkq_data.tx_queues = NULL;
203 hns3_free_rx_queues(struct rte_eth_dev *dev)
205 struct hns3_adapter *hns = dev->data->dev_private;
206 struct hns3_fake_queue_data *fkq_data;
207 struct hns3_hw *hw = &hns->hw;
211 nb_rx_q = hw->data->nb_rx_queues;
212 for (i = 0; i < nb_rx_q; i++) {
213 if (dev->data->rx_queues[i]) {
214 hns3_rx_queue_release(dev->data->rx_queues[i]);
215 dev->data->rx_queues[i] = NULL;
219 /* Free fake Rx queues */
220 fkq_data = &hw->fkq_data;
221 for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) {
222 if (fkq_data->rx_queues[i])
223 hns3_fake_rx_queue_release(fkq_data->rx_queues[i]);
228 hns3_free_tx_queues(struct rte_eth_dev *dev)
230 struct hns3_adapter *hns = dev->data->dev_private;
231 struct hns3_fake_queue_data *fkq_data;
232 struct hns3_hw *hw = &hns->hw;
236 nb_tx_q = hw->data->nb_tx_queues;
237 for (i = 0; i < nb_tx_q; i++) {
238 if (dev->data->tx_queues[i]) {
239 hns3_tx_queue_release(dev->data->tx_queues[i]);
240 dev->data->tx_queues[i] = NULL;
244 /* Free fake Tx queues */
245 fkq_data = &hw->fkq_data;
246 for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) {
247 if (fkq_data->tx_queues[i])
248 hns3_fake_tx_queue_release(fkq_data->tx_queues[i]);
253 hns3_free_all_queues(struct rte_eth_dev *dev)
255 hns3_free_rx_queues(dev);
256 hns3_free_tx_queues(dev);
260 hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq)
262 struct rte_mbuf *mbuf;
266 for (i = 0; i < rxq->nb_rx_desc; i++) {
267 mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
268 if (unlikely(mbuf == NULL)) {
269 hns3_err(hw, "Failed to allocate RXD[%d] for rx queue!",
271 hns3_rx_queue_release_mbufs(rxq);
275 rte_mbuf_refcnt_set(mbuf, 1);
277 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
279 mbuf->port = rxq->port_id;
281 rxq->sw_ring[i].mbuf = mbuf;
282 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
283 rxq->rx_ring[i].addr = dma_addr;
284 rxq->rx_ring[i].rx.bd_base_info = 0;
291 hns3_buf_size2type(uint32_t buf_size)
297 bd_size_type = HNS3_BD_SIZE_512_TYPE;
300 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
303 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
306 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
313 hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)
315 uint32_t rx_buf_len = rxq->rx_buf_len;
316 uint64_t dma_addr = rxq->rx_ring_phys_addr;
318 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);
319 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,
320 (uint32_t)((dma_addr >> 31) >> 1));
322 hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,
323 hns3_buf_size2type(rx_buf_len));
324 hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG,
325 HNS3_CFG_DESC_NUM(rxq->nb_rx_desc));
329 hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)
331 uint64_t dma_addr = txq->tx_ring_phys_addr;
333 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);
334 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,
335 (uint32_t)((dma_addr >> 31) >> 1));
337 hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,
338 HNS3_CFG_DESC_NUM(txq->nb_tx_desc));
342 hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw)
344 uint16_t nb_rx_q = hw->data->nb_rx_queues;
345 uint16_t nb_tx_q = hw->data->nb_tx_queues;
346 struct hns3_rx_queue *rxq;
347 struct hns3_tx_queue *txq;
351 pvid_en = hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE;
352 for (i = 0; i < hw->cfg_max_queues; i++) {
354 rxq = hw->data->rx_queues[i];
356 rxq->pvid_sw_discard_en = pvid_en;
359 txq = hw->data->tx_queues[i];
361 txq->pvid_sw_shift_en = pvid_en;
367 hns3_enable_all_queues(struct hns3_hw *hw, bool en)
369 uint16_t nb_rx_q = hw->data->nb_rx_queues;
370 uint16_t nb_tx_q = hw->data->nb_tx_queues;
371 struct hns3_rx_queue *rxq;
372 struct hns3_tx_queue *txq;
376 for (i = 0; i < hw->cfg_max_queues; i++) {
378 rxq = hw->data->rx_queues[i];
380 rxq = hw->fkq_data.rx_queues[i - nb_rx_q];
382 txq = hw->data->tx_queues[i];
384 txq = hw->fkq_data.tx_queues[i - nb_tx_q];
385 if (rxq == NULL || txq == NULL ||
386 (en && (rxq->rx_deferred_start || txq->tx_deferred_start)))
389 rcb_reg = hns3_read_dev(rxq, HNS3_RING_EN_REG);
391 rcb_reg |= BIT(HNS3_RING_EN_B);
393 rcb_reg &= ~BIT(HNS3_RING_EN_B);
394 hns3_write_dev(rxq, HNS3_RING_EN_REG, rcb_reg);
399 hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable)
401 struct hns3_cfg_com_tqp_queue_cmd *req;
402 struct hns3_cmd_desc desc;
405 req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data;
407 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false);
408 req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
410 hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0);
412 ret = hns3_cmd_send(hw, &desc, 1);
414 hns3_err(hw, "TQP enable fail, ret = %d", ret);
420 hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable)
422 struct hns3_reset_tqp_queue_cmd *req;
423 struct hns3_cmd_desc desc;
426 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false);
428 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
429 req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
430 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
432 ret = hns3_cmd_send(hw, &desc, 1);
434 hns3_err(hw, "Send tqp reset cmd error, ret = %d", ret);
440 hns3_get_reset_status(struct hns3_hw *hw, uint16_t queue_id)
442 struct hns3_reset_tqp_queue_cmd *req;
443 struct hns3_cmd_desc desc;
446 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true);
448 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
449 req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
451 ret = hns3_cmd_send(hw, &desc, 1);
453 hns3_err(hw, "Get reset status error, ret =%d", ret);
457 return hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
461 hns3_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
463 #define HNS3_TQP_RESET_TRY_MS 200
468 ret = hns3_tqp_enable(hw, queue_id, false);
473 * In current version VF is not supported when PF is driven by DPDK
474 * driver, all task queue pairs are mapped to PF function, so PF's queue
475 * id is equals to the global queue id in PF range.
477 ret = hns3_send_reset_tqp_cmd(hw, queue_id, true);
479 hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret);
483 end = get_timeofday_ms() + HNS3_TQP_RESET_TRY_MS;
485 /* Wait for tqp hw reset */
486 rte_delay_ms(HNS3_POLL_RESPONE_MS);
487 reset_status = hns3_get_reset_status(hw, queue_id);
492 } while (get_timeofday_ms() < end);
495 hns3_err(hw, "Reset TQP fail, ret = %d", ret);
499 ret = hns3_send_reset_tqp_cmd(hw, queue_id, false);
501 hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret);
507 hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
512 /* Disable VF's queue before send queue reset msg to PF */
513 ret = hns3_tqp_enable(hw, queue_id, false);
517 memcpy(msg_data, &queue_id, sizeof(uint16_t));
519 return hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
520 sizeof(msg_data), true, NULL, 0);
524 hns3_reset_queue(struct hns3_adapter *hns, uint16_t queue_id)
526 struct hns3_hw *hw = &hns->hw;
528 return hns3vf_reset_tqp(hw, queue_id);
530 return hns3_reset_tqp(hw, queue_id);
534 hns3_reset_all_queues(struct hns3_adapter *hns)
536 struct hns3_hw *hw = &hns->hw;
539 for (i = 0; i < hw->cfg_max_queues; i++) {
540 ret = hns3_reset_queue(hns, i);
542 hns3_err(hw, "Failed to reset No.%d queue: %d", i, ret);
550 hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
551 uint8_t gl_idx, uint16_t gl_value)
553 uint32_t offset[] = {HNS3_TQP_INTR_GL0_REG,
554 HNS3_TQP_INTR_GL1_REG,
555 HNS3_TQP_INTR_GL2_REG};
556 uint32_t addr, value;
558 if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX)
561 addr = offset[gl_idx] + queue_id * HNS3_TQP_INTR_REG_SIZE;
562 if (hw->intr.gl_unit == HNS3_INTR_COALESCE_GL_UINT_1US)
563 value = gl_value | HNS3_TQP_INTR_GL_UNIT_1US;
565 value = HNS3_GL_USEC_TO_REG(gl_value);
567 hns3_write_dev(hw, addr, value);
571 hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value)
573 uint32_t addr, value;
575 if (rl_value > HNS3_TQP_INTR_RL_MAX)
578 addr = HNS3_TQP_INTR_RL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
579 value = HNS3_RL_USEC_TO_REG(rl_value);
581 value |= HNS3_TQP_INTR_RL_ENABLE_MASK;
583 hns3_write_dev(hw, addr, value);
587 hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value)
591 if (hw->intr.coalesce_mode == HNS3_INTR_COALESCE_NON_QL)
594 addr = HNS3_TQP_INTR_TX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
595 hns3_write_dev(hw, addr, ql_value);
597 addr = HNS3_TQP_INTR_RX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
598 hns3_write_dev(hw, addr, ql_value);
602 hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en)
604 uint32_t addr, value;
606 addr = HNS3_TQP_INTR_CTRL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
609 hns3_write_dev(hw, addr, value);
613 * Enable all rx queue interrupt when in interrupt rx mode.
614 * This api was called before enable queue rx&tx (in normal start or reset
615 * recover scenes), used to fix hardware rx queue interrupt enable was clear
619 hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en)
621 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
622 uint16_t nb_rx_q = hw->data->nb_rx_queues;
625 if (dev->data->dev_conf.intr_conf.rxq == 0)
628 for (i = 0; i < nb_rx_q; i++)
629 hns3_queue_intr_enable(hw, i, en);
633 hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
635 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
636 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
637 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
639 if (dev->data->dev_conf.intr_conf.rxq == 0)
642 hns3_queue_intr_enable(hw, queue_id, true);
644 return rte_intr_ack(intr_handle);
648 hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
650 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
652 if (dev->data->dev_conf.intr_conf.rxq == 0)
655 hns3_queue_intr_enable(hw, queue_id, false);
661 hns3_dev_rx_queue_start(struct hns3_adapter *hns, uint16_t idx)
663 struct hns3_hw *hw = &hns->hw;
664 struct hns3_rx_queue *rxq;
667 PMD_INIT_FUNC_TRACE();
669 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx];
670 ret = hns3_alloc_rx_queue_mbufs(hw, rxq);
672 hns3_err(hw, "Failed to alloc mbuf for No.%d rx queue: %d",
677 rxq->next_to_use = 0;
678 rxq->rx_rearm_start = 0;
679 rxq->rx_free_hold = 0;
680 rxq->rx_rearm_nb = 0;
681 rxq->pkt_first_seg = NULL;
682 rxq->pkt_last_seg = NULL;
683 hns3_init_rx_queue_hw(rxq);
684 hns3_rxq_vec_setup(rxq);
690 hns3_fake_rx_queue_start(struct hns3_adapter *hns, uint16_t idx)
692 struct hns3_hw *hw = &hns->hw;
693 struct hns3_rx_queue *rxq;
695 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx];
696 rxq->next_to_use = 0;
697 rxq->rx_free_hold = 0;
698 rxq->rx_rearm_start = 0;
699 rxq->rx_rearm_nb = 0;
700 hns3_init_rx_queue_hw(rxq);
704 hns3_init_tx_queue(struct hns3_tx_queue *queue)
706 struct hns3_tx_queue *txq = queue;
707 struct hns3_desc *desc;
712 for (i = 0; i < txq->nb_tx_desc; i++) {
713 desc->tx.tp_fe_sc_vld_ra_ri = 0;
717 txq->next_to_use = 0;
718 txq->next_to_clean = 0;
719 txq->tx_bd_ready = txq->nb_tx_desc - 1;
720 hns3_init_tx_queue_hw(txq);
724 hns3_dev_tx_queue_start(struct hns3_adapter *hns, uint16_t idx)
726 struct hns3_hw *hw = &hns->hw;
727 struct hns3_tx_queue *txq;
729 txq = (struct hns3_tx_queue *)hw->data->tx_queues[idx];
730 hns3_init_tx_queue(txq);
734 hns3_fake_tx_queue_start(struct hns3_adapter *hns, uint16_t idx)
736 struct hns3_hw *hw = &hns->hw;
737 struct hns3_tx_queue *txq;
739 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[idx];
740 hns3_init_tx_queue(txq);
744 hns3_init_tx_ring_tc(struct hns3_adapter *hns)
746 struct hns3_hw *hw = &hns->hw;
747 struct hns3_tx_queue *txq;
750 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
751 struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i];
754 if (!tc_queue->enable)
757 for (j = 0; j < tc_queue->tqp_count; j++) {
758 num = tc_queue->tqp_offset + j;
759 txq = (struct hns3_tx_queue *)hw->data->tx_queues[num];
763 hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc);
769 hns3_start_rx_queues(struct hns3_adapter *hns)
771 struct hns3_hw *hw = &hns->hw;
772 struct hns3_rx_queue *rxq;
776 /* Initialize RSS for queues */
777 ret = hns3_config_rss(hns);
779 hns3_err(hw, "Failed to configure rss %d", ret);
783 for (i = 0; i < hw->data->nb_rx_queues; i++) {
784 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i];
785 if (rxq == NULL || rxq->rx_deferred_start)
787 ret = hns3_dev_rx_queue_start(hns, i);
789 hns3_err(hw, "Failed to start No.%d rx queue: %d", i,
795 for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++) {
796 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[i];
797 if (rxq == NULL || rxq->rx_deferred_start)
799 hns3_fake_rx_queue_start(hns, i);
804 for (j = 0; j < i; j++) {
805 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j];
806 hns3_rx_queue_release_mbufs(rxq);
813 hns3_start_tx_queues(struct hns3_adapter *hns)
815 struct hns3_hw *hw = &hns->hw;
816 struct hns3_tx_queue *txq;
819 for (i = 0; i < hw->data->nb_tx_queues; i++) {
820 txq = (struct hns3_tx_queue *)hw->data->tx_queues[i];
821 if (txq == NULL || txq->tx_deferred_start)
823 hns3_dev_tx_queue_start(hns, i);
826 for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) {
827 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i];
828 if (txq == NULL || txq->tx_deferred_start)
830 hns3_fake_tx_queue_start(hns, i);
833 hns3_init_tx_ring_tc(hns);
838 * Note: just init and setup queues, and don't enable queue rx&tx.
841 hns3_start_queues(struct hns3_adapter *hns, bool reset_queue)
843 struct hns3_hw *hw = &hns->hw;
847 ret = hns3_reset_all_queues(hns);
849 hns3_err(hw, "Failed to reset all queues %d", ret);
854 ret = hns3_start_rx_queues(hns);
856 hns3_err(hw, "Failed to start rx queues: %d", ret);
860 hns3_start_tx_queues(hns);
866 hns3_stop_queues(struct hns3_adapter *hns, bool reset_queue)
868 struct hns3_hw *hw = &hns->hw;
871 hns3_enable_all_queues(hw, false);
873 ret = hns3_reset_all_queues(hns);
875 hns3_err(hw, "Failed to reset all queues %d", ret);
883 * Iterate over all Rx Queue, and call the callback() function for each Rx
887 * The target eth dev.
888 * @param[in] callback
889 * The function to call for each queue.
890 * if callback function return nonzero will stop iterate and return it's value
892 * The arguments to provide the callback function with.
895 * 0 on success, otherwise with errno set.
898 hns3_rxq_iterate(struct rte_eth_dev *dev,
899 int (*callback)(struct hns3_rx_queue *, void *), void *arg)
904 if (dev->data->rx_queues == NULL)
907 for (i = 0; i < dev->data->nb_rx_queues; i++) {
908 ret = callback(dev->data->rx_queues[i], arg);
917 hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev,
918 struct hns3_queue_info *q_info)
920 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
921 const struct rte_memzone *rx_mz;
922 struct hns3_rx_queue *rxq;
923 unsigned int rx_desc;
925 rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue),
926 RTE_CACHE_LINE_SIZE, q_info->socket_id);
928 hns3_err(hw, "Failed to allocate memory for No.%d rx ring!",
933 /* Allocate rx ring hardware descriptors. */
934 rxq->queue_id = q_info->idx;
935 rxq->nb_rx_desc = q_info->nb_desc;
938 * Allocate a litter more memory because rx vector functions
939 * don't check boundaries each time.
941 rx_desc = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
942 sizeof(struct hns3_desc);
943 rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
944 rx_desc, HNS3_RING_BASE_ALIGN,
947 hns3_err(hw, "Failed to reserve DMA memory for No.%d rx ring!",
949 hns3_rx_queue_release(rxq);
953 rxq->rx_ring = (struct hns3_desc *)rx_mz->addr;
954 rxq->rx_ring_phys_addr = rx_mz->iova;
956 hns3_dbg(hw, "No.%d rx descriptors iova 0x%" PRIx64, q_info->idx,
957 rxq->rx_ring_phys_addr);
963 hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
964 uint16_t nb_desc, unsigned int socket_id)
966 struct hns3_adapter *hns = dev->data->dev_private;
967 struct hns3_hw *hw = &hns->hw;
968 struct hns3_queue_info q_info;
969 struct hns3_rx_queue *rxq;
972 if (hw->fkq_data.rx_queues[idx]) {
973 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
974 hw->fkq_data.rx_queues[idx] = NULL;
978 q_info.socket_id = socket_id;
979 q_info.nb_desc = nb_desc;
980 q_info.type = "hns3 fake RX queue";
981 q_info.ring_name = "rx_fake_ring";
982 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
984 hns3_err(hw, "Failed to setup No.%d fake rx ring.", idx);
988 /* Don't need alloc sw_ring, because upper applications don't use it */
992 rxq->rx_deferred_start = false;
993 rxq->port_id = dev->data->port_id;
994 rxq->configured = true;
995 nb_rx_q = dev->data->nb_rx_queues;
996 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
997 (nb_rx_q + idx) * HNS3_TQP_REG_SIZE);
998 rxq->rx_buf_len = HNS3_MIN_BD_BUF_SIZE;
1000 rte_spinlock_lock(&hw->lock);
1001 hw->fkq_data.rx_queues[idx] = rxq;
1002 rte_spinlock_unlock(&hw->lock);
1008 hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev,
1009 struct hns3_queue_info *q_info)
1011 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1012 const struct rte_memzone *tx_mz;
1013 struct hns3_tx_queue *txq;
1014 struct hns3_desc *desc;
1015 unsigned int tx_desc;
1018 txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue),
1019 RTE_CACHE_LINE_SIZE, q_info->socket_id);
1021 hns3_err(hw, "Failed to allocate memory for No.%d tx ring!",
1026 /* Allocate tx ring hardware descriptors. */
1027 txq->queue_id = q_info->idx;
1028 txq->nb_tx_desc = q_info->nb_desc;
1029 tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc);
1030 tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
1031 tx_desc, HNS3_RING_BASE_ALIGN,
1033 if (tx_mz == NULL) {
1034 hns3_err(hw, "Failed to reserve DMA memory for No.%d tx ring!",
1036 hns3_tx_queue_release(txq);
1040 txq->tx_ring = (struct hns3_desc *)tx_mz->addr;
1041 txq->tx_ring_phys_addr = tx_mz->iova;
1043 hns3_dbg(hw, "No.%d tx descriptors iova 0x%" PRIx64, q_info->idx,
1044 txq->tx_ring_phys_addr);
1047 desc = txq->tx_ring;
1048 for (i = 0; i < txq->nb_tx_desc; i++) {
1049 desc->tx.tp_fe_sc_vld_ra_ri = 0;
1057 hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
1058 uint16_t nb_desc, unsigned int socket_id)
1060 struct hns3_adapter *hns = dev->data->dev_private;
1061 struct hns3_hw *hw = &hns->hw;
1062 struct hns3_queue_info q_info;
1063 struct hns3_tx_queue *txq;
1066 if (hw->fkq_data.tx_queues[idx] != NULL) {
1067 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
1068 hw->fkq_data.tx_queues[idx] = NULL;
1072 q_info.socket_id = socket_id;
1073 q_info.nb_desc = nb_desc;
1074 q_info.type = "hns3 fake TX queue";
1075 q_info.ring_name = "tx_fake_ring";
1076 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
1078 hns3_err(hw, "Failed to setup No.%d fake tx ring.", idx);
1082 /* Don't need alloc sw_ring, because upper applications don't use it */
1083 txq->sw_ring = NULL;
1087 txq->tx_deferred_start = false;
1088 txq->port_id = dev->data->port_id;
1089 txq->configured = true;
1090 nb_tx_q = dev->data->nb_tx_queues;
1091 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1092 (nb_tx_q + idx) * HNS3_TQP_REG_SIZE);
1094 rte_spinlock_lock(&hw->lock);
1095 hw->fkq_data.tx_queues[idx] = txq;
1096 rte_spinlock_unlock(&hw->lock);
1102 hns3_fake_rx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1104 uint16_t old_nb_queues = hw->fkq_data.nb_fake_rx_queues;
1108 if (hw->fkq_data.rx_queues == NULL && nb_queues != 0) {
1109 /* first time configuration */
1111 size = sizeof(hw->fkq_data.rx_queues[0]) * nb_queues;
1112 hw->fkq_data.rx_queues = rte_zmalloc("fake_rx_queues", size,
1113 RTE_CACHE_LINE_SIZE);
1114 if (hw->fkq_data.rx_queues == NULL) {
1115 hw->fkq_data.nb_fake_rx_queues = 0;
1118 } else if (hw->fkq_data.rx_queues != NULL && nb_queues != 0) {
1120 rxq = hw->fkq_data.rx_queues;
1121 for (i = nb_queues; i < old_nb_queues; i++)
1122 hns3_dev_rx_queue_release(rxq[i]);
1124 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
1125 RTE_CACHE_LINE_SIZE);
1128 if (nb_queues > old_nb_queues) {
1129 uint16_t new_qs = nb_queues - old_nb_queues;
1130 memset(rxq + old_nb_queues, 0, sizeof(rxq[0]) * new_qs);
1133 hw->fkq_data.rx_queues = rxq;
1134 } else if (hw->fkq_data.rx_queues != NULL && nb_queues == 0) {
1135 rxq = hw->fkq_data.rx_queues;
1136 for (i = nb_queues; i < old_nb_queues; i++)
1137 hns3_dev_rx_queue_release(rxq[i]);
1139 rte_free(hw->fkq_data.rx_queues);
1140 hw->fkq_data.rx_queues = NULL;
1143 hw->fkq_data.nb_fake_rx_queues = nb_queues;
1149 hns3_fake_tx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1151 uint16_t old_nb_queues = hw->fkq_data.nb_fake_tx_queues;
1155 if (hw->fkq_data.tx_queues == NULL && nb_queues != 0) {
1156 /* first time configuration */
1158 size = sizeof(hw->fkq_data.tx_queues[0]) * nb_queues;
1159 hw->fkq_data.tx_queues = rte_zmalloc("fake_tx_queues", size,
1160 RTE_CACHE_LINE_SIZE);
1161 if (hw->fkq_data.tx_queues == NULL) {
1162 hw->fkq_data.nb_fake_tx_queues = 0;
1165 } else if (hw->fkq_data.tx_queues != NULL && nb_queues != 0) {
1167 txq = hw->fkq_data.tx_queues;
1168 for (i = nb_queues; i < old_nb_queues; i++)
1169 hns3_dev_tx_queue_release(txq[i]);
1170 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1171 RTE_CACHE_LINE_SIZE);
1174 if (nb_queues > old_nb_queues) {
1175 uint16_t new_qs = nb_queues - old_nb_queues;
1176 memset(txq + old_nb_queues, 0, sizeof(txq[0]) * new_qs);
1179 hw->fkq_data.tx_queues = txq;
1180 } else if (hw->fkq_data.tx_queues != NULL && nb_queues == 0) {
1181 txq = hw->fkq_data.tx_queues;
1182 for (i = nb_queues; i < old_nb_queues; i++)
1183 hns3_dev_tx_queue_release(txq[i]);
1185 rte_free(hw->fkq_data.tx_queues);
1186 hw->fkq_data.tx_queues = NULL;
1188 hw->fkq_data.nb_fake_tx_queues = nb_queues;
1194 hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
1197 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1198 uint16_t rx_need_add_nb_q;
1199 uint16_t tx_need_add_nb_q;
1204 /* Setup new number of fake RX/TX queues and reconfigure device. */
1205 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
1206 rx_need_add_nb_q = hw->cfg_max_queues - nb_rx_q;
1207 tx_need_add_nb_q = hw->cfg_max_queues - nb_tx_q;
1208 ret = hns3_fake_rx_queue_config(hw, rx_need_add_nb_q);
1210 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1211 goto cfg_fake_rx_q_fail;
1214 ret = hns3_fake_tx_queue_config(hw, tx_need_add_nb_q);
1216 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1217 goto cfg_fake_tx_q_fail;
1220 /* Allocate and set up fake RX queue per Ethernet port. */
1221 port_id = hw->data->port_id;
1222 for (q = 0; q < rx_need_add_nb_q; q++) {
1223 ret = hns3_fake_rx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1224 rte_eth_dev_socket_id(port_id));
1226 goto setup_fake_rx_q_fail;
1229 /* Allocate and set up fake TX queue per Ethernet port. */
1230 for (q = 0; q < tx_need_add_nb_q; q++) {
1231 ret = hns3_fake_tx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1232 rte_eth_dev_socket_id(port_id));
1234 goto setup_fake_tx_q_fail;
1239 setup_fake_tx_q_fail:
1240 setup_fake_rx_q_fail:
1241 (void)hns3_fake_tx_queue_config(hw, 0);
1243 (void)hns3_fake_rx_queue_config(hw, 0);
1245 hw->cfg_max_queues = 0;
1251 hns3_dev_release_mbufs(struct hns3_adapter *hns)
1253 struct rte_eth_dev_data *dev_data = hns->hw.data;
1254 struct hns3_rx_queue *rxq;
1255 struct hns3_tx_queue *txq;
1258 if (dev_data->rx_queues)
1259 for (i = 0; i < dev_data->nb_rx_queues; i++) {
1260 rxq = dev_data->rx_queues[i];
1261 if (rxq == NULL || rxq->rx_deferred_start)
1263 hns3_rx_queue_release_mbufs(rxq);
1266 if (dev_data->tx_queues)
1267 for (i = 0; i < dev_data->nb_tx_queues; i++) {
1268 txq = dev_data->tx_queues[i];
1269 if (txq == NULL || txq->tx_deferred_start)
1271 hns3_tx_queue_release_mbufs(txq);
1276 hns3_rx_buf_len_calc(struct rte_mempool *mp, uint16_t *rx_buf_len)
1278 uint16_t vld_buf_size;
1279 uint16_t num_hw_specs;
1283 * hns3 network engine only support to set 4 typical specification, and
1284 * different buffer size will affect the max packet_len and the max
1285 * number of segmentation when hw gro is turned on in receive side. The
1286 * relationship between them is as follows:
1287 * rx_buf_size | max_gro_pkt_len | max_gro_nb_seg
1288 * ---------------------|-------------------|----------------
1289 * HNS3_4K_BD_BUF_SIZE | 60KB | 15
1290 * HNS3_2K_BD_BUF_SIZE | 62KB | 31
1291 * HNS3_1K_BD_BUF_SIZE | 63KB | 63
1292 * HNS3_512_BD_BUF_SIZE | 31.5KB | 63
1294 static const uint16_t hw_rx_buf_size[] = {
1295 HNS3_4K_BD_BUF_SIZE,
1296 HNS3_2K_BD_BUF_SIZE,
1297 HNS3_1K_BD_BUF_SIZE,
1298 HNS3_512_BD_BUF_SIZE
1301 vld_buf_size = (uint16_t)(rte_pktmbuf_data_room_size(mp) -
1302 RTE_PKTMBUF_HEADROOM);
1304 if (vld_buf_size < HNS3_MIN_BD_BUF_SIZE)
1307 num_hw_specs = RTE_DIM(hw_rx_buf_size);
1308 for (i = 0; i < num_hw_specs; i++) {
1309 if (vld_buf_size >= hw_rx_buf_size[i]) {
1310 *rx_buf_len = hw_rx_buf_size[i];
1318 hns3_rx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_rxconf *conf,
1319 struct rte_mempool *mp, uint16_t nb_desc,
1322 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1323 nb_desc % HNS3_ALIGN_RING_DESC) {
1324 hns3_err(hw, "Number (%u) of rx descriptors is invalid",
1329 if (conf->rx_drop_en == 0)
1330 hns3_warn(hw, "if no descriptors available, packets are always "
1331 "dropped and rx_drop_en (1) is fixed on");
1333 if (hns3_rx_buf_len_calc(mp, buf_size)) {
1334 hns3_err(hw, "rxq mbufs' data room size (%u) is not enough! "
1335 "minimal data room size (%u).",
1336 rte_pktmbuf_data_room_size(mp),
1337 HNS3_MIN_BD_BUF_SIZE + RTE_PKTMBUF_HEADROOM);
1345 hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1346 unsigned int socket_id, const struct rte_eth_rxconf *conf,
1347 struct rte_mempool *mp)
1349 struct hns3_adapter *hns = dev->data->dev_private;
1350 struct hns3_hw *hw = &hns->hw;
1351 struct hns3_queue_info q_info;
1352 struct hns3_rx_queue *rxq;
1353 uint16_t rx_buf_size;
1357 if (dev->data->dev_started) {
1358 hns3_err(hw, "rx_queue_setup after dev_start no supported");
1362 ret = hns3_rx_queue_conf_check(hw, conf, mp, nb_desc, &rx_buf_size);
1366 if (dev->data->rx_queues[idx]) {
1367 hns3_rx_queue_release(dev->data->rx_queues[idx]);
1368 dev->data->rx_queues[idx] = NULL;
1372 q_info.socket_id = socket_id;
1373 q_info.nb_desc = nb_desc;
1374 q_info.type = "hns3 RX queue";
1375 q_info.ring_name = "rx_ring";
1377 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1380 "Failed to alloc mem and reserve DMA mem for rx ring!");
1385 rxq->ptype_tbl = &hns->ptype_tbl;
1387 rxq->rx_free_thresh = (conf->rx_free_thresh > 0) ?
1388 conf->rx_free_thresh : HNS3_DEFAULT_RX_FREE_THRESH;
1389 rxq->rx_deferred_start = conf->rx_deferred_start;
1391 rx_entry_len = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
1392 sizeof(struct hns3_entry);
1393 rxq->sw_ring = rte_zmalloc_socket("hns3 RX sw ring", rx_entry_len,
1394 RTE_CACHE_LINE_SIZE, socket_id);
1395 if (rxq->sw_ring == NULL) {
1396 hns3_err(hw, "Failed to allocate memory for rx sw ring!");
1397 hns3_rx_queue_release(rxq);
1401 rxq->next_to_use = 0;
1402 rxq->rx_free_hold = 0;
1403 rxq->rx_rearm_start = 0;
1404 rxq->rx_rearm_nb = 0;
1405 rxq->pkt_first_seg = NULL;
1406 rxq->pkt_last_seg = NULL;
1407 rxq->port_id = dev->data->port_id;
1409 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
1410 * the pvid_sw_discard_en in the queue struct should not be changed,
1411 * because PVID-related operations do not need to be processed by PMD
1412 * driver. For hns3 VF device, whether it needs to process PVID depends
1413 * on the configuration of PF kernel mode netdevice driver. And the
1414 * related PF configuration is delivered through the mailbox and finally
1415 * reflectd in port_base_vlan_cfg.
1417 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1418 rxq->pvid_sw_discard_en = hw->port_base_vlan_cfg.state ==
1419 HNS3_PORT_BASE_VLAN_ENABLE;
1421 rxq->pvid_sw_discard_en = false;
1422 rxq->configured = true;
1423 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1424 idx * HNS3_TQP_REG_SIZE);
1425 rxq->io_head_reg = (volatile void *)((char *)rxq->io_base +
1426 HNS3_RING_RX_HEAD_REG);
1427 rxq->rx_buf_len = rx_buf_size;
1429 rxq->pkt_len_errors = 0;
1430 rxq->l3_csum_errors = 0;
1431 rxq->l4_csum_errors = 0;
1432 rxq->ol3_csum_errors = 0;
1433 rxq->ol4_csum_errors = 0;
1435 /* CRC len set here is used for amending packet length */
1436 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1437 rxq->crc_len = RTE_ETHER_CRC_LEN;
1441 rxq->bulk_mbuf_num = 0;
1443 rte_spinlock_lock(&hw->lock);
1444 dev->data->rx_queues[idx] = rxq;
1445 rte_spinlock_unlock(&hw->lock);
1451 hns3_rx_scattered_reset(struct rte_eth_dev *dev)
1453 struct hns3_adapter *hns = dev->data->dev_private;
1454 struct hns3_hw *hw = &hns->hw;
1457 dev->data->scattered_rx = false;
1461 hns3_rx_scattered_calc(struct rte_eth_dev *dev)
1463 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1464 struct hns3_adapter *hns = dev->data->dev_private;
1465 struct hns3_hw *hw = &hns->hw;
1466 struct hns3_rx_queue *rxq;
1469 if (dev->data->rx_queues == NULL)
1472 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
1473 rxq = dev->data->rx_queues[queue_id];
1474 if (hw->rx_buf_len == 0)
1475 hw->rx_buf_len = rxq->rx_buf_len;
1477 hw->rx_buf_len = RTE_MIN(hw->rx_buf_len,
1481 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_SCATTER ||
1482 dev_conf->rxmode.max_rx_pkt_len > hw->rx_buf_len)
1483 dev->data->scattered_rx = true;
1487 hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1489 static const uint32_t ptypes[] = {
1491 RTE_PTYPE_L2_ETHER_VLAN,
1492 RTE_PTYPE_L2_ETHER_QINQ,
1493 RTE_PTYPE_L2_ETHER_LLDP,
1494 RTE_PTYPE_L2_ETHER_ARP,
1496 RTE_PTYPE_L3_IPV4_EXT,
1498 RTE_PTYPE_L3_IPV6_EXT,
1504 RTE_PTYPE_TUNNEL_GRE,
1508 if (dev->rx_pkt_burst == hns3_recv_pkts ||
1509 dev->rx_pkt_burst == hns3_recv_scattered_pkts ||
1510 dev->rx_pkt_burst == hns3_recv_pkts_vec)
1517 hns3_init_rx_ptype_tble(struct rte_eth_dev *dev)
1519 struct hns3_adapter *hns = dev->data->dev_private;
1520 struct hns3_ptype_table *tbl = &hns->ptype_tbl;
1522 memset(tbl, 0, sizeof(*tbl));
1524 tbl->l2table[0] = RTE_PTYPE_L2_ETHER;
1525 tbl->l2table[1] = RTE_PTYPE_L2_ETHER_QINQ;
1526 tbl->l2table[2] = RTE_PTYPE_L2_ETHER_VLAN;
1527 tbl->l2table[3] = RTE_PTYPE_L2_ETHER_VLAN;
1529 tbl->l3table[0] = RTE_PTYPE_L3_IPV4;
1530 tbl->l3table[1] = RTE_PTYPE_L3_IPV6;
1531 tbl->l3table[2] = RTE_PTYPE_L2_ETHER_ARP;
1532 tbl->l3table[3] = RTE_PTYPE_L2_ETHER;
1533 tbl->l3table[4] = RTE_PTYPE_L3_IPV4_EXT;
1534 tbl->l3table[5] = RTE_PTYPE_L3_IPV6_EXT;
1535 tbl->l3table[6] = RTE_PTYPE_L2_ETHER_LLDP;
1537 tbl->l4table[0] = RTE_PTYPE_L4_UDP;
1538 tbl->l4table[1] = RTE_PTYPE_L4_TCP;
1539 tbl->l4table[2] = RTE_PTYPE_TUNNEL_GRE;
1540 tbl->l4table[3] = RTE_PTYPE_L4_SCTP;
1541 tbl->l4table[4] = RTE_PTYPE_L4_IGMP;
1542 tbl->l4table[5] = RTE_PTYPE_L4_ICMP;
1544 tbl->inner_l2table[0] = RTE_PTYPE_INNER_L2_ETHER;
1545 tbl->inner_l2table[1] = RTE_PTYPE_INNER_L2_ETHER_VLAN;
1546 tbl->inner_l2table[2] = RTE_PTYPE_INNER_L2_ETHER_QINQ;
1548 tbl->inner_l3table[0] = RTE_PTYPE_INNER_L3_IPV4;
1549 tbl->inner_l3table[1] = RTE_PTYPE_INNER_L3_IPV6;
1550 tbl->inner_l3table[2] = 0;
1551 tbl->inner_l3table[3] = RTE_PTYPE_INNER_L2_ETHER;
1552 tbl->inner_l3table[4] = RTE_PTYPE_INNER_L3_IPV4_EXT;
1553 tbl->inner_l3table[5] = RTE_PTYPE_INNER_L3_IPV6_EXT;
1555 tbl->inner_l4table[0] = RTE_PTYPE_INNER_L4_UDP;
1556 tbl->inner_l4table[1] = RTE_PTYPE_INNER_L4_TCP;
1557 tbl->inner_l4table[2] = RTE_PTYPE_TUNNEL_GRE;
1558 tbl->inner_l4table[3] = RTE_PTYPE_INNER_L4_SCTP;
1559 tbl->inner_l4table[4] = RTE_PTYPE_L4_IGMP;
1560 tbl->inner_l4table[5] = RTE_PTYPE_INNER_L4_ICMP;
1562 tbl->ol3table[0] = RTE_PTYPE_L3_IPV4;
1563 tbl->ol3table[1] = RTE_PTYPE_L3_IPV6;
1564 tbl->ol3table[2] = 0;
1565 tbl->ol3table[3] = 0;
1566 tbl->ol3table[4] = RTE_PTYPE_L3_IPV4_EXT;
1567 tbl->ol3table[5] = RTE_PTYPE_L3_IPV6_EXT;
1569 tbl->ol4table[0] = 0;
1570 tbl->ol4table[1] = RTE_PTYPE_TUNNEL_VXLAN;
1571 tbl->ol4table[2] = RTE_PTYPE_TUNNEL_NVGRE;
1575 hns3_rxd_to_vlan_tci(struct hns3_rx_queue *rxq, struct rte_mbuf *mb,
1576 uint32_t l234_info, const struct hns3_desc *rxd)
1578 #define HNS3_STRP_STATUS_NUM 0x4
1580 #define HNS3_NO_STRP_VLAN_VLD 0x0
1581 #define HNS3_INNER_STRP_VLAN_VLD 0x1
1582 #define HNS3_OUTER_STRP_VLAN_VLD 0x2
1583 uint32_t strip_status;
1584 uint32_t report_mode;
1587 * Since HW limitation, the vlan tag will always be inserted into RX
1588 * descriptor when strip the tag from packet, driver needs to determine
1589 * reporting which tag to mbuf according to the PVID configuration
1590 * and vlan striped status.
1592 static const uint32_t report_type[][HNS3_STRP_STATUS_NUM] = {
1594 HNS3_NO_STRP_VLAN_VLD,
1595 HNS3_OUTER_STRP_VLAN_VLD,
1596 HNS3_INNER_STRP_VLAN_VLD,
1597 HNS3_OUTER_STRP_VLAN_VLD
1600 HNS3_NO_STRP_VLAN_VLD,
1601 HNS3_NO_STRP_VLAN_VLD,
1602 HNS3_NO_STRP_VLAN_VLD,
1603 HNS3_INNER_STRP_VLAN_VLD
1606 strip_status = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,
1607 HNS3_RXD_STRP_TAGP_S);
1608 report_mode = report_type[rxq->pvid_sw_discard_en][strip_status];
1609 switch (report_mode) {
1610 case HNS3_NO_STRP_VLAN_VLD:
1613 case HNS3_INNER_STRP_VLAN_VLD:
1614 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1615 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.vlan_tag);
1617 case HNS3_OUTER_STRP_VLAN_VLD:
1618 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1619 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.ot_vlan_tag);
1625 recalculate_data_len(struct rte_mbuf *first_seg, struct rte_mbuf *last_seg,
1626 struct rte_mbuf *rxm, struct hns3_rx_queue *rxq,
1629 uint8_t crc_len = rxq->crc_len;
1631 if (data_len <= crc_len) {
1632 rte_pktmbuf_free_seg(rxm);
1633 first_seg->nb_segs--;
1634 last_seg->data_len = (uint16_t)(last_seg->data_len -
1635 (crc_len - data_len));
1636 last_seg->next = NULL;
1638 rxm->data_len = (uint16_t)(data_len - crc_len);
1641 static inline struct rte_mbuf *
1642 hns3_rx_alloc_buffer(struct hns3_rx_queue *rxq)
1646 if (likely(rxq->bulk_mbuf_num > 0))
1647 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
1649 ret = rte_mempool_get_bulk(rxq->mb_pool, (void **)rxq->bulk_mbuf,
1650 HNS3_BULK_ALLOC_MBUF_NUM);
1651 if (likely(ret == 0)) {
1652 rxq->bulk_mbuf_num = HNS3_BULK_ALLOC_MBUF_NUM;
1653 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
1655 return rte_mbuf_raw_alloc(rxq->mb_pool);
1659 hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1661 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
1662 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
1663 struct hns3_rx_queue *rxq; /* RX queue */
1664 struct hns3_entry *sw_ring;
1665 struct hns3_entry *rxe;
1666 struct hns3_desc rxd;
1667 struct rte_mbuf *nmb; /* pointer of the new mbuf */
1668 struct rte_mbuf *rxm;
1669 uint32_t bd_base_info;
1682 rx_ring = rxq->rx_ring;
1683 sw_ring = rxq->sw_ring;
1684 rx_id = rxq->next_to_use;
1686 while (nb_rx < nb_pkts) {
1687 rxdp = &rx_ring[rx_id];
1688 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
1689 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
1692 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
1693 (1u << HNS3_RXD_VLD_B)];
1695 nmb = hns3_rx_alloc_buffer(rxq);
1696 if (unlikely(nmb == NULL)) {
1699 port_id = rxq->port_id;
1700 rte_eth_devices[port_id].data->rx_mbuf_alloc_failed++;
1705 rxe = &sw_ring[rx_id];
1707 if (unlikely(rx_id == rxq->nb_rx_desc))
1710 rte_prefetch0(sw_ring[rx_id].mbuf);
1711 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
1712 rte_prefetch0(&rx_ring[rx_id]);
1713 rte_prefetch0(&sw_ring[rx_id]);
1719 dma_addr = rte_mbuf_data_iova_default(nmb);
1720 rxdp->addr = rte_cpu_to_le_64(dma_addr);
1721 rxdp->rx.bd_base_info = 0;
1723 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1724 rxm->pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.pkt_len)) -
1726 rxm->data_len = rxm->pkt_len;
1727 rxm->port = rxq->port_id;
1728 rxm->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
1729 rxm->ol_flags = PKT_RX_RSS_HASH;
1730 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
1732 rte_le_to_cpu_16(rxd.rx.fd_id);
1733 rxm->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1738 /* Load remained descriptor data and extract necessary fields */
1739 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
1740 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
1741 ret = hns3_handle_bdinfo(rxq, rxm, bd_base_info,
1742 l234_info, &cksum_err);
1746 rxm->packet_type = hns3_rx_calc_ptype(rxq, l234_info, ol_info);
1748 if (likely(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
1749 hns3_rx_set_cksum_flag(rxm, rxm->packet_type,
1751 hns3_rxd_to_vlan_tci(rxq, rxm, l234_info, &rxd);
1753 rx_pkts[nb_rx++] = rxm;
1756 rte_pktmbuf_free(rxm);
1759 rxq->next_to_use = rx_id;
1760 rxq->rx_free_hold += nb_rx_bd;
1761 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
1762 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
1763 rxq->rx_free_hold = 0;
1770 hns3_recv_scattered_pkts(void *rx_queue,
1771 struct rte_mbuf **rx_pkts,
1774 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
1775 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
1776 struct hns3_rx_queue *rxq; /* RX queue */
1777 struct hns3_entry *sw_ring;
1778 struct hns3_entry *rxe;
1779 struct rte_mbuf *first_seg;
1780 struct rte_mbuf *last_seg;
1781 struct hns3_desc rxd;
1782 struct rte_mbuf *nmb; /* pointer of the new mbuf */
1783 struct rte_mbuf *rxm;
1784 struct rte_eth_dev *dev;
1785 uint32_t bd_base_info;
1800 rx_id = rxq->next_to_use;
1801 rx_ring = rxq->rx_ring;
1802 sw_ring = rxq->sw_ring;
1803 first_seg = rxq->pkt_first_seg;
1804 last_seg = rxq->pkt_last_seg;
1806 while (nb_rx < nb_pkts) {
1807 rxdp = &rx_ring[rx_id];
1808 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
1809 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
1813 * The interactive process between software and hardware of
1814 * receiving a new packet in hns3 network engine:
1815 * 1. Hardware network engine firstly writes the packet content
1816 * to the memory pointed by the 'addr' field of the Rx Buffer
1817 * Descriptor, secondly fills the result of parsing the
1818 * packet include the valid field into the Rx Buffer
1819 * Descriptor in one write operation.
1820 * 2. Driver reads the Rx BD's valid field in the loop to check
1821 * whether it's valid, if valid then assign a new address to
1822 * the addr field, clear the valid field, get the other
1823 * information of the packet by parsing Rx BD's other fields,
1824 * finally write back the number of Rx BDs processed by the
1825 * driver to the HNS3_RING_RX_HEAD_REG register to inform
1827 * In the above process, the ordering is very important. We must
1828 * make sure that CPU read Rx BD's other fields only after the
1831 * There are two type of re-ordering: compiler re-ordering and
1832 * CPU re-ordering under the ARMv8 architecture.
1833 * 1. we use volatile to deal with compiler re-ordering, so you
1834 * can see that rx_ring/rxdp defined with volatile.
1835 * 2. we commonly use memory barrier to deal with CPU
1836 * re-ordering, but the cost is high.
1838 * In order to solve the high cost of using memory barrier, we
1839 * use the data dependency order under the ARMv8 architecture,
1842 * instr02: load B <- A
1843 * the instr02 will always execute after instr01.
1845 * To construct the data dependency ordering, we use the
1846 * following assignment:
1847 * rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
1848 * (1u<<HNS3_RXD_VLD_B)]
1849 * Using gcc compiler under the ARMv8 architecture, the related
1850 * assembly code example as follows:
1851 * note: (1u << HNS3_RXD_VLD_B) equal 0x10
1852 * instr01: ldr w26, [x22, #28] --read bd_base_info
1853 * instr02: and w0, w26, #0x10 --calc bd_base_info & 0x10
1854 * instr03: sub w0, w0, #0x10 --calc (bd_base_info &
1856 * instr04: add x0, x22, x0, lsl #5 --calc copy source addr
1857 * instr05: ldp x2, x3, [x0]
1858 * instr06: stp x2, x3, [x29, #256] --copy BD's [0 ~ 15]B
1859 * instr07: ldp x4, x5, [x0, #16]
1860 * instr08: stp x4, x5, [x29, #272] --copy BD's [16 ~ 31]B
1861 * the instr05~08 depend on x0's value, x0 depent on w26's
1862 * value, the w26 is the bd_base_info, this form the data
1863 * dependency ordering.
1864 * note: if BD is valid, (bd_base_info & (1u<<HNS3_RXD_VLD_B)) -
1865 * (1u<<HNS3_RXD_VLD_B) will always zero, so the
1866 * assignment is correct.
1868 * So we use the data dependency ordering instead of memory
1869 * barrier to improve receive performance.
1871 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
1872 (1u << HNS3_RXD_VLD_B)];
1874 nmb = hns3_rx_alloc_buffer(rxq);
1875 if (unlikely(nmb == NULL)) {
1876 dev = &rte_eth_devices[rxq->port_id];
1877 dev->data->rx_mbuf_alloc_failed++;
1882 rxe = &sw_ring[rx_id];
1884 if (unlikely(rx_id == rxq->nb_rx_desc))
1887 rte_prefetch0(sw_ring[rx_id].mbuf);
1888 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
1889 rte_prefetch0(&rx_ring[rx_id]);
1890 rte_prefetch0(&sw_ring[rx_id]);
1896 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1897 rxdp->rx.bd_base_info = 0;
1898 rxdp->addr = dma_addr;
1900 if (first_seg == NULL) {
1902 first_seg->nb_segs = 1;
1904 first_seg->nb_segs++;
1905 last_seg->next = rxm;
1908 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1909 rxm->data_len = rte_le_to_cpu_16(rxd.rx.size);
1911 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
1918 * The last buffer of the received packet. packet len from
1919 * buffer description may contains CRC len, packet len should
1920 * subtract it, same as data len.
1922 first_seg->pkt_len = rte_le_to_cpu_16(rxd.rx.pkt_len);
1925 * This is the last buffer of the received packet. If the CRC
1926 * is not stripped by the hardware:
1927 * - Subtract the CRC length from the total packet length.
1928 * - If the last buffer only contains the whole CRC or a part
1929 * of it, free the mbuf associated to the last buffer. If part
1930 * of the CRC is also contained in the previous mbuf, subtract
1931 * the length of that CRC part from the data length of the
1935 if (unlikely(rxq->crc_len > 0)) {
1936 first_seg->pkt_len -= rxq->crc_len;
1937 recalculate_data_len(first_seg, last_seg, rxm, rxq,
1941 first_seg->port = rxq->port_id;
1942 first_seg->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
1943 first_seg->ol_flags = PKT_RX_RSS_HASH;
1944 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
1945 first_seg->hash.fdir.hi =
1946 rte_le_to_cpu_16(rxd.rx.fd_id);
1947 first_seg->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1950 gro_size = hns3_get_field(bd_base_info, HNS3_RXD_GRO_SIZE_M,
1951 HNS3_RXD_GRO_SIZE_S);
1952 if (gro_size != 0) {
1953 first_seg->ol_flags |= PKT_RX_LRO;
1954 first_seg->tso_segsz = gro_size;
1957 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
1958 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
1959 ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info,
1960 l234_info, &cksum_err);
1964 first_seg->packet_type = hns3_rx_calc_ptype(rxq,
1965 l234_info, ol_info);
1967 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B))
1968 hns3_rx_set_cksum_flag(first_seg,
1969 first_seg->packet_type,
1971 hns3_rxd_to_vlan_tci(rxq, first_seg, l234_info, &rxd);
1973 rx_pkts[nb_rx++] = first_seg;
1977 rte_pktmbuf_free(first_seg);
1981 rxq->next_to_use = rx_id;
1982 rxq->pkt_first_seg = first_seg;
1983 rxq->pkt_last_seg = last_seg;
1985 rxq->rx_free_hold += nb_rx_bd;
1986 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
1987 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
1988 rxq->rx_free_hold = 0;
1995 hns3_rxq_vec_setup(__rte_unused struct hns3_rx_queue *rxq)
2000 hns3_rx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
2006 hns3_recv_pkts_vec(__rte_unused void *tx_queue,
2007 __rte_unused struct rte_mbuf **tx_pkts,
2008 __rte_unused uint16_t nb_pkts)
2014 hns3_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2015 struct rte_eth_burst_mode *mode)
2017 static const struct {
2018 eth_rx_burst_t pkt_burst;
2021 { hns3_recv_pkts, "Scalar" },
2022 { hns3_recv_scattered_pkts, "Scalar Scattered" },
2023 { hns3_recv_pkts_vec, "Vector Neon" },
2026 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2030 for (i = 0; i < RTE_DIM(burst_infos); i++) {
2031 if (pkt_burst == burst_infos[i].pkt_burst) {
2032 snprintf(mode->info, sizeof(mode->info), "%s",
2033 burst_infos[i].info);
2042 static eth_rx_burst_t
2043 hns3_get_rx_function(struct rte_eth_dev *dev)
2045 struct hns3_adapter *hns = dev->data->dev_private;
2046 uint64_t offloads = dev->data->dev_conf.rxmode.offloads;
2048 if (hns->rx_vec_allowed && hns3_rx_check_vec_support(dev) == 0)
2049 return hns3_recv_pkts_vec;
2051 if (hns->rx_simple_allowed && !dev->data->scattered_rx &&
2052 (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0)
2053 return hns3_recv_pkts;
2055 return hns3_recv_scattered_pkts;
2059 hns3_tx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_txconf *conf,
2060 uint16_t nb_desc, uint16_t *tx_rs_thresh,
2061 uint16_t *tx_free_thresh, uint16_t idx)
2063 #define HNS3_TX_RS_FREE_THRESH_GAP 8
2064 uint16_t rs_thresh, free_thresh, fast_free_thresh;
2066 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
2067 nb_desc % HNS3_ALIGN_RING_DESC) {
2068 hns3_err(hw, "number (%u) of tx descriptors is invalid",
2073 rs_thresh = (conf->tx_rs_thresh > 0) ?
2074 conf->tx_rs_thresh : HNS3_DEFAULT_TX_RS_THRESH;
2075 free_thresh = (conf->tx_free_thresh > 0) ?
2076 conf->tx_free_thresh : HNS3_DEFAULT_TX_FREE_THRESH;
2077 if (rs_thresh + free_thresh > nb_desc || nb_desc % rs_thresh ||
2078 rs_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP ||
2079 free_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP) {
2080 hns3_err(hw, "tx_rs_thresh (%d) tx_free_thresh (%d) nb_desc "
2081 "(%d) of tx descriptors for port=%d queue=%d check "
2083 rs_thresh, free_thresh, nb_desc, hw->data->port_id,
2088 if (conf->tx_free_thresh == 0) {
2089 /* Fast free Tx memory buffer to improve cache hit rate */
2090 fast_free_thresh = nb_desc - rs_thresh;
2091 if (fast_free_thresh >=
2092 HNS3_TX_FAST_FREE_AHEAD + HNS3_DEFAULT_TX_FREE_THRESH)
2093 free_thresh = fast_free_thresh -
2094 HNS3_TX_FAST_FREE_AHEAD;
2097 *tx_rs_thresh = rs_thresh;
2098 *tx_free_thresh = free_thresh;
2103 hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
2104 unsigned int socket_id, const struct rte_eth_txconf *conf)
2106 struct hns3_adapter *hns = dev->data->dev_private;
2107 uint16_t tx_rs_thresh, tx_free_thresh;
2108 struct hns3_hw *hw = &hns->hw;
2109 struct hns3_queue_info q_info;
2110 struct hns3_tx_queue *txq;
2114 if (dev->data->dev_started) {
2115 hns3_err(hw, "tx_queue_setup after dev_start no supported");
2119 ret = hns3_tx_queue_conf_check(hw, conf, nb_desc,
2120 &tx_rs_thresh, &tx_free_thresh, idx);
2124 if (dev->data->tx_queues[idx] != NULL) {
2125 hns3_tx_queue_release(dev->data->tx_queues[idx]);
2126 dev->data->tx_queues[idx] = NULL;
2130 q_info.socket_id = socket_id;
2131 q_info.nb_desc = nb_desc;
2132 q_info.type = "hns3 TX queue";
2133 q_info.ring_name = "tx_ring";
2134 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
2137 "Failed to alloc mem and reserve DMA mem for tx ring!");
2141 txq->tx_deferred_start = conf->tx_deferred_start;
2142 tx_entry_len = sizeof(struct hns3_entry) * txq->nb_tx_desc;
2143 txq->sw_ring = rte_zmalloc_socket("hns3 TX sw ring", tx_entry_len,
2144 RTE_CACHE_LINE_SIZE, socket_id);
2145 if (txq->sw_ring == NULL) {
2146 hns3_err(hw, "Failed to allocate memory for tx sw ring!");
2147 hns3_tx_queue_release(txq);
2152 txq->next_to_use = 0;
2153 txq->next_to_clean = 0;
2154 txq->tx_bd_ready = txq->nb_tx_desc - 1;
2155 txq->tx_free_thresh = tx_free_thresh;
2156 txq->tx_rs_thresh = tx_rs_thresh;
2157 txq->free = rte_zmalloc_socket("hns3 TX mbuf free array",
2158 sizeof(struct rte_mbuf *) * txq->tx_rs_thresh,
2159 RTE_CACHE_LINE_SIZE, socket_id);
2161 hns3_err(hw, "failed to allocate tx mbuf free array!");
2162 hns3_tx_queue_release(txq);
2166 txq->port_id = dev->data->port_id;
2168 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
2169 * the pvid_sw_shift_en in the queue struct should not be changed,
2170 * because PVID-related operations do not need to be processed by PMD
2171 * driver. For hns3 VF device, whether it needs to process PVID depends
2172 * on the configuration of PF kernel mode netdev driver. And the
2173 * related PF configuration is delivered through the mailbox and finally
2174 * reflectd in port_base_vlan_cfg.
2176 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
2177 txq->pvid_sw_shift_en = hw->port_base_vlan_cfg.state ==
2178 HNS3_PORT_BASE_VLAN_ENABLE;
2180 txq->pvid_sw_shift_en = false;
2181 txq->configured = true;
2182 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
2183 idx * HNS3_TQP_REG_SIZE);
2184 txq->io_tail_reg = (volatile void *)((char *)txq->io_base +
2185 HNS3_RING_TX_TAIL_REG);
2186 txq->min_tx_pkt_len = hw->min_tx_pkt_len;
2187 txq->over_length_pkt_cnt = 0;
2188 txq->exceed_limit_bd_pkt_cnt = 0;
2189 txq->exceed_limit_bd_reassem_fail = 0;
2190 txq->unsupported_tunnel_pkt_cnt = 0;
2191 txq->queue_full_cnt = 0;
2192 txq->pkt_padding_fail_cnt = 0;
2193 rte_spinlock_lock(&hw->lock);
2194 dev->data->tx_queues[idx] = txq;
2195 rte_spinlock_unlock(&hw->lock);
2201 hns3_tx_free_useless_buffer(struct hns3_tx_queue *txq)
2203 uint16_t tx_next_clean = txq->next_to_clean;
2204 uint16_t tx_next_use = txq->next_to_use;
2205 uint16_t tx_bd_ready = txq->tx_bd_ready;
2206 uint16_t tx_bd_max = txq->nb_tx_desc;
2207 struct hns3_entry *tx_bak_pkt = &txq->sw_ring[tx_next_clean];
2208 struct hns3_desc *desc = &txq->tx_ring[tx_next_clean];
2209 struct rte_mbuf *mbuf;
2211 while ((!(desc->tx.tp_fe_sc_vld_ra_ri &
2212 rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)))) &&
2213 tx_next_use != tx_next_clean) {
2214 mbuf = tx_bak_pkt->mbuf;
2216 rte_pktmbuf_free_seg(mbuf);
2217 tx_bak_pkt->mbuf = NULL;
2225 if (tx_next_clean >= tx_bd_max) {
2227 desc = txq->tx_ring;
2228 tx_bak_pkt = txq->sw_ring;
2232 txq->next_to_clean = tx_next_clean;
2233 txq->tx_bd_ready = tx_bd_ready;
2237 hns3_tso_proc_tunnel(struct hns3_desc *desc, uint64_t ol_flags,
2238 struct rte_mbuf *rxm, uint8_t *l2_len)
2244 tun_flags = ol_flags & PKT_TX_TUNNEL_MASK;
2248 otmp = rte_le_to_cpu_32(desc->tx.ol_type_vlan_len_msec);
2249 switch (tun_flags) {
2250 case PKT_TX_TUNNEL_GENEVE:
2251 case PKT_TX_TUNNEL_VXLAN:
2252 *l2_len = rxm->l2_len - RTE_ETHER_VXLAN_HLEN;
2254 case PKT_TX_TUNNEL_GRE:
2256 * OL4 header size, defined in 4 Bytes, it contains outer
2257 * L4(GRE) length and tunneling length.
2259 ol4_len = hns3_get_field(otmp, HNS3_TXD_L4LEN_M,
2261 *l2_len = rxm->l2_len - (ol4_len << HNS3_L4_LEN_UNIT);
2264 /* For non UDP / GRE tunneling, drop the tunnel packet */
2267 hns3_set_field(otmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2268 rxm->outer_l2_len >> HNS3_L2_LEN_UNIT);
2269 desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(otmp);
2275 hns3_config_gro(struct hns3_hw *hw, bool en)
2277 struct hns3_cfg_gro_status_cmd *req;
2278 struct hns3_cmd_desc desc;
2281 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
2282 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
2284 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
2286 ret = hns3_cmd_send(hw, &desc, 1);
2288 hns3_err(hw, "%s hardware GRO failed, ret = %d",
2289 en ? "enable" : "disable", ret);
2295 hns3_restore_gro_conf(struct hns3_hw *hw)
2301 offloads = hw->data->dev_conf.rxmode.offloads;
2302 gro_en = offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2303 ret = hns3_config_gro(hw, gro_en);
2305 hns3_err(hw, "restore hardware GRO to %s failed, ret = %d",
2306 gro_en ? "enabled" : "disabled", ret);
2312 hns3_pkt_is_tso(struct rte_mbuf *m)
2314 return (m->tso_segsz != 0 && m->ol_flags & PKT_TX_TCP_SEG);
2318 hns3_set_tso(struct hns3_desc *desc, uint64_t ol_flags,
2319 uint32_t paylen, struct rte_mbuf *rxm)
2321 uint8_t l2_len = rxm->l2_len;
2324 if (!hns3_pkt_is_tso(rxm))
2327 if (hns3_tso_proc_tunnel(desc, ol_flags, rxm, &l2_len))
2330 if (paylen <= rxm->tso_segsz)
2333 tmp = rte_le_to_cpu_32(desc->tx.type_cs_vlan_tso_len);
2334 hns3_set_bit(tmp, HNS3_TXD_TSO_B, 1);
2335 hns3_set_bit(tmp, HNS3_TXD_L3CS_B, 1);
2336 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S, HNS3_L4T_TCP);
2337 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2338 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2339 sizeof(struct rte_tcp_hdr) >> HNS3_L4_LEN_UNIT);
2340 hns3_set_field(tmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2341 l2_len >> HNS3_L2_LEN_UNIT);
2342 desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp);
2343 desc->tx.mss = rte_cpu_to_le_16(rxm->tso_segsz);
2347 hns3_fill_per_desc(struct hns3_desc *desc, struct rte_mbuf *rxm)
2349 desc->addr = rte_mbuf_data_iova(rxm);
2350 desc->tx.send_size = rte_cpu_to_le_16(rte_pktmbuf_data_len(rxm));
2351 desc->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B));
2355 hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc,
2356 struct rte_mbuf *rxm)
2358 uint64_t ol_flags = rxm->ol_flags;
2362 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len;
2363 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
2364 rxm->outer_l2_len + rxm->outer_l3_len : 0;
2365 paylen = rxm->pkt_len - hdr_len;
2366 desc->tx.paylen = rte_cpu_to_le_32(paylen);
2367 hns3_set_tso(desc, ol_flags, paylen, rxm);
2370 * Currently, hardware doesn't support more than two layers VLAN offload
2371 * in Tx direction based on hns3 network engine. So when the number of
2372 * VLANs in the packets represented by rxm plus the number of VLAN
2373 * offload by hardware such as PVID etc, exceeds two, the packets will
2374 * be discarded or the original VLAN of the packets will be overwitted
2375 * by hardware. When the PF PVID is enabled by calling the API function
2376 * named rte_eth_dev_set_vlan_pvid or the VF PVID is enabled by the hns3
2377 * PF kernel ether driver, the outer VLAN tag will always be the PVID.
2378 * To avoid the VLAN of Tx descriptor is overwritten by PVID, it should
2379 * be added to the position close to the IP header when PVID is enabled.
2381 if (!txq->pvid_sw_shift_en && ol_flags & (PKT_TX_VLAN_PKT |
2383 desc->tx.ol_type_vlan_len_msec |=
2384 rte_cpu_to_le_32(BIT(HNS3_TXD_OVLAN_B));
2385 if (ol_flags & PKT_TX_QINQ_PKT)
2386 desc->tx.outer_vlan_tag =
2387 rte_cpu_to_le_16(rxm->vlan_tci_outer);
2389 desc->tx.outer_vlan_tag =
2390 rte_cpu_to_le_16(rxm->vlan_tci);
2393 if (ol_flags & PKT_TX_QINQ_PKT ||
2394 ((ol_flags & PKT_TX_VLAN_PKT) && txq->pvid_sw_shift_en)) {
2395 desc->tx.type_cs_vlan_tso_len |=
2396 rte_cpu_to_le_32(BIT(HNS3_TXD_VLAN_B));
2397 desc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci);
2402 hns3_tx_alloc_mbufs(struct rte_mempool *mb_pool, uint16_t nb_new_buf,
2403 struct rte_mbuf **alloc_mbuf)
2405 #define MAX_NON_TSO_BD_PER_PKT 18
2406 struct rte_mbuf *pkt_segs[MAX_NON_TSO_BD_PER_PKT];
2409 /* Allocate enough mbufs */
2410 if (rte_mempool_get_bulk(mb_pool, (void **)pkt_segs, nb_new_buf))
2413 for (i = 0; i < nb_new_buf - 1; i++)
2414 pkt_segs[i]->next = pkt_segs[i + 1];
2416 pkt_segs[nb_new_buf - 1]->next = NULL;
2417 pkt_segs[0]->nb_segs = nb_new_buf;
2418 *alloc_mbuf = pkt_segs[0];
2424 hns3_pktmbuf_copy_hdr(struct rte_mbuf *new_pkt, struct rte_mbuf *old_pkt)
2426 new_pkt->ol_flags = old_pkt->ol_flags;
2427 new_pkt->pkt_len = rte_pktmbuf_pkt_len(old_pkt);
2428 new_pkt->outer_l2_len = old_pkt->outer_l2_len;
2429 new_pkt->outer_l3_len = old_pkt->outer_l3_len;
2430 new_pkt->l2_len = old_pkt->l2_len;
2431 new_pkt->l3_len = old_pkt->l3_len;
2432 new_pkt->l4_len = old_pkt->l4_len;
2433 new_pkt->vlan_tci_outer = old_pkt->vlan_tci_outer;
2434 new_pkt->vlan_tci = old_pkt->vlan_tci;
2438 hns3_reassemble_tx_pkts(struct rte_mbuf *tx_pkt, struct rte_mbuf **new_pkt)
2440 struct rte_mempool *mb_pool;
2441 struct rte_mbuf *new_mbuf;
2442 struct rte_mbuf *temp_new;
2443 struct rte_mbuf *temp;
2444 uint16_t last_buf_len;
2445 uint16_t nb_new_buf;
2455 mb_pool = tx_pkt->pool;
2456 buf_size = tx_pkt->buf_len - RTE_PKTMBUF_HEADROOM;
2457 nb_new_buf = (rte_pktmbuf_pkt_len(tx_pkt) - 1) / buf_size + 1;
2458 if (nb_new_buf > HNS3_MAX_NON_TSO_BD_PER_PKT)
2461 last_buf_len = rte_pktmbuf_pkt_len(tx_pkt) % buf_size;
2462 if (last_buf_len == 0)
2463 last_buf_len = buf_size;
2465 /* Allocate enough mbufs */
2466 ret = hns3_tx_alloc_mbufs(mb_pool, nb_new_buf, &new_mbuf);
2470 /* Copy the original packet content to the new mbufs */
2472 s = rte_pktmbuf_mtod(temp, char *);
2473 len_s = rte_pktmbuf_data_len(temp);
2474 temp_new = new_mbuf;
2475 while (temp != NULL && temp_new != NULL) {
2476 d = rte_pktmbuf_mtod(temp_new, char *);
2477 buf_len = temp_new->next == NULL ? last_buf_len : buf_size;
2481 len = RTE_MIN(len_s, len_d);
2485 len_d = len_d - len;
2486 len_s = len_s - len;
2492 s = rte_pktmbuf_mtod(temp, char *);
2493 len_s = rte_pktmbuf_data_len(temp);
2497 temp_new->data_len = buf_len;
2498 temp_new = temp_new->next;
2500 hns3_pktmbuf_copy_hdr(new_mbuf, tx_pkt);
2502 /* free original mbufs */
2503 rte_pktmbuf_free(tx_pkt);
2505 *new_pkt = new_mbuf;
2511 hns3_parse_outer_params(uint64_t ol_flags, uint32_t *ol_type_vlan_len_msec)
2513 uint32_t tmp = *ol_type_vlan_len_msec;
2515 /* (outer) IP header type */
2516 if (ol_flags & PKT_TX_OUTER_IPV4) {
2517 /* OL3 header size, defined in 4 bytes */
2518 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2519 sizeof(struct rte_ipv4_hdr) >> HNS3_L3_LEN_UNIT);
2520 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2521 hns3_set_field(tmp, HNS3_TXD_OL3T_M,
2522 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_CSUM);
2524 hns3_set_field(tmp, HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
2525 HNS3_OL3T_IPV4_NO_CSUM);
2526 } else if (ol_flags & PKT_TX_OUTER_IPV6) {
2527 hns3_set_field(tmp, HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
2529 /* OL3 header size, defined in 4 bytes */
2530 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2531 sizeof(struct rte_ipv6_hdr) >> HNS3_L3_LEN_UNIT);
2534 *ol_type_vlan_len_msec = tmp;
2538 hns3_parse_inner_params(uint64_t ol_flags, uint32_t *ol_type_vlan_len_msec,
2539 struct rte_net_hdr_lens *hdr_lens)
2541 uint32_t tmp = *ol_type_vlan_len_msec;
2544 /* OL2 header size, defined in 2 bytes */
2545 hns3_set_field(tmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2546 sizeof(struct rte_ether_hdr) >> HNS3_L2_LEN_UNIT);
2548 /* L4TUNT: L4 Tunneling Type */
2549 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2550 case PKT_TX_TUNNEL_GENEVE:
2551 case PKT_TX_TUNNEL_VXLAN:
2552 /* MAC in UDP tunnelling packet, include VxLAN */
2553 hns3_set_field(tmp, HNS3_TXD_TUNTYPE_M, HNS3_TXD_TUNTYPE_S,
2554 HNS3_TUN_MAC_IN_UDP);
2556 * OL4 header size, defined in 4 Bytes, it contains outer
2557 * L4(UDP) length and tunneling length.
2559 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2560 (uint8_t)RTE_ETHER_VXLAN_HLEN >>
2563 case PKT_TX_TUNNEL_GRE:
2564 hns3_set_field(tmp, HNS3_TXD_TUNTYPE_M, HNS3_TXD_TUNTYPE_S,
2567 * OL4 header size, defined in 4 Bytes, it contains outer
2568 * L4(GRE) length and tunneling length.
2570 l4_len = hdr_lens->l4_len + hdr_lens->tunnel_len;
2571 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2572 l4_len >> HNS3_L4_LEN_UNIT);
2575 /* For non UDP / GRE tunneling, drop the tunnel packet */
2579 *ol_type_vlan_len_msec = tmp;
2585 hns3_parse_tunneling_params(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
2587 struct rte_net_hdr_lens *hdr_lens)
2589 struct hns3_desc *tx_ring = txq->tx_ring;
2590 struct hns3_desc *desc = &tx_ring[tx_desc_id];
2594 hns3_parse_outer_params(ol_flags, &value);
2595 ret = hns3_parse_inner_params(ol_flags, &value, hdr_lens);
2599 desc->tx.ol_type_vlan_len_msec |= rte_cpu_to_le_32(value);
2605 hns3_parse_l3_cksum_params(uint64_t ol_flags, uint32_t *type_cs_vlan_tso_len)
2609 /* Enable L3 checksum offloads */
2610 if (ol_flags & PKT_TX_IPV4) {
2611 tmp = *type_cs_vlan_tso_len;
2612 hns3_set_field(tmp, HNS3_TXD_L3T_M, HNS3_TXD_L3T_S,
2614 /* inner(/normal) L3 header size, defined in 4 bytes */
2615 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2616 sizeof(struct rte_ipv4_hdr) >> HNS3_L3_LEN_UNIT);
2617 if (ol_flags & PKT_TX_IP_CKSUM)
2618 hns3_set_bit(tmp, HNS3_TXD_L3CS_B, 1);
2619 *type_cs_vlan_tso_len = tmp;
2620 } else if (ol_flags & PKT_TX_IPV6) {
2621 tmp = *type_cs_vlan_tso_len;
2622 /* L3T, IPv6 don't do checksum */
2623 hns3_set_field(tmp, HNS3_TXD_L3T_M, HNS3_TXD_L3T_S,
2625 /* inner(/normal) L3 header size, defined in 4 bytes */
2626 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2627 sizeof(struct rte_ipv6_hdr) >> HNS3_L3_LEN_UNIT);
2628 *type_cs_vlan_tso_len = tmp;
2633 hns3_parse_l4_cksum_params(uint64_t ol_flags, uint32_t *type_cs_vlan_tso_len)
2637 /* Enable L4 checksum offloads */
2638 switch (ol_flags & PKT_TX_L4_MASK) {
2639 case PKT_TX_TCP_CKSUM:
2640 tmp = *type_cs_vlan_tso_len;
2641 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
2643 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2644 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2645 sizeof(struct rte_tcp_hdr) >> HNS3_L4_LEN_UNIT);
2646 *type_cs_vlan_tso_len = tmp;
2648 case PKT_TX_UDP_CKSUM:
2649 tmp = *type_cs_vlan_tso_len;
2650 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
2652 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2653 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2654 sizeof(struct rte_udp_hdr) >> HNS3_L4_LEN_UNIT);
2655 *type_cs_vlan_tso_len = tmp;
2657 case PKT_TX_SCTP_CKSUM:
2658 tmp = *type_cs_vlan_tso_len;
2659 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
2661 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2662 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2663 sizeof(struct rte_sctp_hdr) >> HNS3_L4_LEN_UNIT);
2664 *type_cs_vlan_tso_len = tmp;
2672 hns3_txd_enable_checksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
2675 struct hns3_desc *tx_ring = txq->tx_ring;
2676 struct hns3_desc *desc = &tx_ring[tx_desc_id];
2679 /* inner(/normal) L2 header size, defined in 2 bytes */
2680 hns3_set_field(value, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2681 sizeof(struct rte_ether_hdr) >> HNS3_L2_LEN_UNIT);
2683 hns3_parse_l3_cksum_params(ol_flags, &value);
2684 hns3_parse_l4_cksum_params(ol_flags, &value);
2686 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(value);
2690 hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num)
2692 struct rte_mbuf *m_first = tx_pkts;
2693 struct rte_mbuf *m_last = tx_pkts;
2694 uint32_t tot_len = 0;
2699 * Hardware requires that the sum of the data length of every 8
2700 * consecutive buffers is greater than MSS in hns3 network engine.
2701 * We simplify it by ensuring pkt_headlen + the first 8 consecutive
2702 * frags greater than gso header len + mss, and the remaining 7
2703 * consecutive frags greater than MSS except the last 7 frags.
2705 if (bd_num <= HNS3_MAX_NON_TSO_BD_PER_PKT)
2708 for (i = 0; m_last && i < HNS3_MAX_NON_TSO_BD_PER_PKT - 1;
2709 i++, m_last = m_last->next)
2710 tot_len += m_last->data_len;
2715 /* ensure the first 8 frags is greater than mss + header */
2716 hdr_len = tx_pkts->l2_len + tx_pkts->l3_len + tx_pkts->l4_len;
2717 hdr_len += (tx_pkts->ol_flags & PKT_TX_TUNNEL_MASK) ?
2718 tx_pkts->outer_l2_len + tx_pkts->outer_l3_len : 0;
2719 if (tot_len + m_last->data_len < tx_pkts->tso_segsz + hdr_len)
2723 * ensure the sum of the data length of every 7 consecutive buffer
2724 * is greater than mss except the last one.
2726 for (i = 0; m_last && i < bd_num - HNS3_MAX_NON_TSO_BD_PER_PKT; i++) {
2727 tot_len -= m_first->data_len;
2728 tot_len += m_last->data_len;
2730 if (tot_len < tx_pkts->tso_segsz)
2733 m_first = m_first->next;
2734 m_last = m_last->next;
2741 hns3_outer_header_cksum_prepare(struct rte_mbuf *m)
2743 uint64_t ol_flags = m->ol_flags;
2744 struct rte_ipv4_hdr *ipv4_hdr;
2745 struct rte_udp_hdr *udp_hdr;
2746 uint32_t paylen, hdr_len;
2748 if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6)))
2751 if (ol_flags & PKT_TX_IPV4) {
2752 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2755 if (ol_flags & PKT_TX_IP_CKSUM)
2756 ipv4_hdr->hdr_checksum = 0;
2759 if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_UDP_CKSUM &&
2760 ol_flags & PKT_TX_TCP_SEG) {
2761 hdr_len = m->l2_len + m->l3_len + m->l4_len;
2762 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
2763 m->outer_l2_len + m->outer_l3_len : 0;
2764 paylen = m->pkt_len - hdr_len;
2765 if (paylen <= m->tso_segsz)
2767 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
2770 udp_hdr->dgram_cksum = 0;
2775 hns3_check_tso_pkt_valid(struct rte_mbuf *m)
2777 uint32_t tmp_data_len_sum = 0;
2778 uint16_t nb_buf = m->nb_segs;
2779 uint32_t paylen, hdr_len;
2780 struct rte_mbuf *m_seg;
2783 if (nb_buf > HNS3_MAX_TSO_BD_PER_PKT)
2786 hdr_len = m->l2_len + m->l3_len + m->l4_len;
2787 hdr_len += (m->ol_flags & PKT_TX_TUNNEL_MASK) ?
2788 m->outer_l2_len + m->outer_l3_len : 0;
2789 if (hdr_len > HNS3_MAX_TSO_HDR_SIZE)
2792 paylen = m->pkt_len - hdr_len;
2793 if (paylen > HNS3_MAX_BD_PAYLEN)
2797 * The TSO header (include outer and inner L2, L3 and L4 header)
2798 * should be provided by three descriptors in maximum in hns3 network
2802 for (i = 0; m_seg != NULL && i < HNS3_MAX_TSO_HDR_BD_NUM && i < nb_buf;
2803 i++, m_seg = m_seg->next) {
2804 tmp_data_len_sum += m_seg->data_len;
2807 if (hdr_len > tmp_data_len_sum)
2813 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2815 hns3_vld_vlan_chk(struct hns3_tx_queue *txq, struct rte_mbuf *m)
2817 struct rte_ether_hdr *eh;
2818 struct rte_vlan_hdr *vh;
2820 if (!txq->pvid_sw_shift_en)
2824 * Due to hardware limitations, we only support two-layer VLAN hardware
2825 * offload in Tx direction based on hns3 network engine, so when PVID is
2826 * enabled, QinQ insert is no longer supported.
2827 * And when PVID is enabled, in the following two cases:
2828 * i) packets with more than two VLAN tags.
2829 * ii) packets with one VLAN tag while the hardware VLAN insert is
2831 * The packets will be regarded as abnormal packets and discarded by
2832 * hardware in Tx direction. For debugging purposes, a validation check
2833 * for these types of packets is added to the '.tx_pkt_prepare' ops
2834 * implementation function named hns3_prep_pkts to inform users that
2835 * these packets will be discarded.
2837 if (m->ol_flags & PKT_TX_QINQ_PKT)
2840 eh = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
2841 if (eh->ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
2842 if (m->ol_flags & PKT_TX_VLAN_PKT)
2845 /* Ensure the incoming packet is not a QinQ packet */
2846 vh = (struct rte_vlan_hdr *)(eh + 1);
2847 if (vh->eth_proto == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN))
2856 hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2863 for (i = 0; i < nb_pkts; i++) {
2866 if (hns3_pkt_is_tso(m) &&
2867 (hns3_pkt_need_linearized(m, m->nb_segs) ||
2868 hns3_check_tso_pkt_valid(m))) {
2873 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2874 ret = rte_validate_tx_offload(m);
2880 if (hns3_vld_vlan_chk(tx_queue, m)) {
2885 ret = rte_net_intel_cksum_prepare(m);
2891 hns3_outer_header_cksum_prepare(m);
2898 hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
2899 const struct rte_mbuf *m, struct rte_net_hdr_lens *hdr_lens)
2901 /* Fill in tunneling parameters if necessary */
2902 if (m->ol_flags & PKT_TX_TUNNEL_MASK) {
2903 (void)rte_net_get_ptype(m, hdr_lens, RTE_PTYPE_ALL_MASK);
2904 if (hns3_parse_tunneling_params(txq, tx_desc_id, m->ol_flags,
2906 txq->unsupported_tunnel_pkt_cnt++;
2910 /* Enable checksum offloading */
2911 if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK)
2912 hns3_txd_enable_checksum(txq, tx_desc_id, m->ol_flags);
2918 hns3_check_non_tso_pkt(uint16_t nb_buf, struct rte_mbuf **m_seg,
2919 struct rte_mbuf *tx_pkt, struct hns3_tx_queue *txq)
2921 struct rte_mbuf *new_pkt;
2924 if (hns3_pkt_is_tso(*m_seg))
2928 * If packet length is greater than HNS3_MAX_FRAME_LEN
2929 * driver support, the packet will be ignored.
2931 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) > HNS3_MAX_FRAME_LEN)) {
2932 txq->over_length_pkt_cnt++;
2936 if (unlikely(nb_buf > HNS3_MAX_NON_TSO_BD_PER_PKT)) {
2937 txq->exceed_limit_bd_pkt_cnt++;
2938 ret = hns3_reassemble_tx_pkts(tx_pkt, &new_pkt);
2940 txq->exceed_limit_bd_reassem_fail++;
2950 hns3_tx_free_buffer_simple(struct hns3_tx_queue *txq)
2952 struct hns3_entry *tx_entry;
2953 struct hns3_desc *desc;
2954 uint16_t tx_next_clean;
2958 if (HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) < txq->tx_rs_thresh)
2962 * All mbufs can be released only when the VLD bits of all
2963 * descriptors in a batch are cleared.
2965 tx_next_clean = (txq->next_to_clean + txq->tx_rs_thresh - 1) %
2967 desc = &txq->tx_ring[tx_next_clean];
2968 for (i = 0; i < txq->tx_rs_thresh; i++) {
2969 if (rte_le_to_cpu_16(desc->tx.tp_fe_sc_vld_ra_ri) &
2970 BIT(HNS3_TXD_VLD_B))
2975 tx_entry = &txq->sw_ring[txq->next_to_clean];
2977 for (i = 0; i < txq->tx_rs_thresh; i++)
2978 rte_prefetch0((tx_entry + i)->mbuf);
2979 for (i = 0; i < txq->tx_rs_thresh; i++, tx_entry++) {
2980 rte_mempool_put(tx_entry->mbuf->pool, tx_entry->mbuf);
2981 tx_entry->mbuf = NULL;
2984 txq->next_to_clean = (tx_next_clean + 1) % txq->nb_tx_desc;
2985 txq->tx_bd_ready += txq->tx_rs_thresh;
2990 hns3_tx_backup_1mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
2992 tx_entry->mbuf = pkts[0];
2996 hns3_tx_backup_4mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
2998 hns3_tx_backup_1mbuf(&tx_entry[0], &pkts[0]);
2999 hns3_tx_backup_1mbuf(&tx_entry[1], &pkts[1]);
3000 hns3_tx_backup_1mbuf(&tx_entry[2], &pkts[2]);
3001 hns3_tx_backup_1mbuf(&tx_entry[3], &pkts[3]);
3005 hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
3007 #define PER_LOOP_NUM 4
3008 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
3012 for (i = 0; i < PER_LOOP_NUM; i++, txdp++, pkts++) {
3013 dma_addr = rte_mbuf_data_iova(*pkts);
3014 txdp->addr = rte_cpu_to_le_64(dma_addr);
3015 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
3016 txdp->tx.paylen = 0;
3017 txdp->tx.type_cs_vlan_tso_len = 0;
3018 txdp->tx.ol_type_vlan_len_msec = 0;
3019 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
3024 hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
3026 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
3029 dma_addr = rte_mbuf_data_iova(*pkts);
3030 txdp->addr = rte_cpu_to_le_64(dma_addr);
3031 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
3032 txdp->tx.paylen = 0;
3033 txdp->tx.type_cs_vlan_tso_len = 0;
3034 txdp->tx.ol_type_vlan_len_msec = 0;
3035 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
3039 hns3_tx_fill_hw_ring(struct hns3_tx_queue *txq,
3040 struct rte_mbuf **pkts,
3043 #define PER_LOOP_NUM 4
3044 #define PER_LOOP_MASK (PER_LOOP_NUM - 1)
3045 struct hns3_desc *txdp = &txq->tx_ring[txq->next_to_use];
3046 struct hns3_entry *tx_entry = &txq->sw_ring[txq->next_to_use];
3047 const uint32_t mainpart = (nb_pkts & ((uint32_t)~PER_LOOP_MASK));
3048 const uint32_t leftover = (nb_pkts & ((uint32_t)PER_LOOP_MASK));
3051 for (i = 0; i < mainpart; i += PER_LOOP_NUM) {
3052 hns3_tx_backup_4mbuf(tx_entry + i, pkts + i);
3053 hns3_tx_setup_4bd(txdp + i, pkts + i);
3055 if (unlikely(leftover > 0)) {
3056 for (i = 0; i < leftover; i++) {
3057 hns3_tx_backup_1mbuf(tx_entry + mainpart + i,
3058 pkts + mainpart + i);
3059 hns3_tx_setup_1bd(txdp + mainpart + i,
3060 pkts + mainpart + i);
3066 hns3_xmit_pkts_simple(void *tx_queue,
3067 struct rte_mbuf **tx_pkts,
3070 struct hns3_tx_queue *txq = tx_queue;
3073 hns3_tx_free_buffer_simple(txq);
3075 nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts);
3076 if (unlikely(nb_pkts == 0)) {
3077 if (txq->tx_bd_ready == 0)
3078 txq->queue_full_cnt++;
3082 txq->tx_bd_ready -= nb_pkts;
3083 if (txq->next_to_use + nb_pkts > txq->nb_tx_desc) {
3084 nb_tx = txq->nb_tx_desc - txq->next_to_use;
3085 hns3_tx_fill_hw_ring(txq, tx_pkts, nb_tx);
3086 txq->next_to_use = 0;
3089 hns3_tx_fill_hw_ring(txq, tx_pkts + nb_tx, nb_pkts - nb_tx);
3090 txq->next_to_use += nb_pkts - nb_tx;
3092 hns3_write_reg_opt(txq->io_tail_reg, nb_pkts);
3098 hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
3100 struct rte_net_hdr_lens hdr_lens = {0};
3101 struct hns3_tx_queue *txq = tx_queue;
3102 struct hns3_entry *tx_bak_pkt;
3103 struct hns3_desc *tx_ring;
3104 struct rte_mbuf *tx_pkt;
3105 struct rte_mbuf *m_seg;
3106 struct hns3_desc *desc;
3107 uint32_t nb_hold = 0;
3108 uint16_t tx_next_use;
3109 uint16_t tx_pkt_num;
3115 /* free useless buffer */
3116 hns3_tx_free_useless_buffer(txq);
3118 tx_next_use = txq->next_to_use;
3119 tx_bd_max = txq->nb_tx_desc;
3120 tx_pkt_num = nb_pkts;
3121 tx_ring = txq->tx_ring;
3124 tx_bak_pkt = &txq->sw_ring[tx_next_use];
3125 for (nb_tx = 0; nb_tx < tx_pkt_num; nb_tx++) {
3126 tx_pkt = *tx_pkts++;
3128 nb_buf = tx_pkt->nb_segs;
3130 if (nb_buf > txq->tx_bd_ready) {
3131 txq->queue_full_cnt++;
3139 * If packet length is less than minimum packet length supported
3140 * by hardware in Tx direction, driver need to pad it to avoid
3143 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) <
3144 txq->min_tx_pkt_len)) {
3148 add_len = txq->min_tx_pkt_len -
3149 rte_pktmbuf_pkt_len(tx_pkt);
3150 appended = rte_pktmbuf_append(tx_pkt, add_len);
3151 if (appended == NULL) {
3152 txq->pkt_padding_fail_cnt++;
3156 memset(appended, 0, add_len);
3161 if (hns3_check_non_tso_pkt(nb_buf, &m_seg, tx_pkt, txq))
3164 if (hns3_parse_cksum(txq, tx_next_use, m_seg, &hdr_lens))
3168 desc = &tx_ring[tx_next_use];
3171 * If the packet is divided into multiple Tx Buffer Descriptors,
3172 * only need to fill vlan, paylen and tso into the first Tx
3173 * Buffer Descriptor.
3175 hns3_fill_first_desc(txq, desc, m_seg);
3178 desc = &tx_ring[tx_next_use];
3180 * Fill valid bits, DMA address and data length for each
3181 * Tx Buffer Descriptor.
3183 hns3_fill_per_desc(desc, m_seg);
3184 tx_bak_pkt->mbuf = m_seg;
3185 m_seg = m_seg->next;
3188 if (tx_next_use >= tx_bd_max) {
3190 tx_bak_pkt = txq->sw_ring;
3194 } while (m_seg != NULL);
3196 /* Add end flag for the last Tx Buffer Descriptor */
3197 desc->tx.tp_fe_sc_vld_ra_ri |=
3198 rte_cpu_to_le_16(BIT(HNS3_TXD_FE_B));
3201 txq->next_to_use = tx_next_use;
3202 txq->tx_bd_ready -= i;
3208 hns3_write_reg_opt(txq->io_tail_reg, nb_hold);
3214 hns3_tx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
3220 hns3_xmit_pkts_vec(__rte_unused void *tx_queue,
3221 __rte_unused struct rte_mbuf **tx_pkts,
3222 __rte_unused uint16_t nb_pkts)
3228 hns3_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3229 struct rte_eth_burst_mode *mode)
3231 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3232 const char *info = NULL;
3234 if (pkt_burst == hns3_xmit_pkts_simple)
3235 info = "Scalar Simple";
3236 else if (pkt_burst == hns3_xmit_pkts)
3238 else if (pkt_burst == hns3_xmit_pkts_vec)
3239 info = "Vector Neon";
3244 snprintf(mode->info, sizeof(mode->info), "%s", info);
3249 static eth_tx_burst_t
3250 hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep)
3252 uint64_t offloads = dev->data->dev_conf.txmode.offloads;
3253 struct hns3_adapter *hns = dev->data->dev_private;
3255 if (hns->tx_vec_allowed && hns3_tx_check_vec_support(dev) == 0) {
3257 return hns3_xmit_pkts_vec;
3260 if (hns->tx_simple_allowed &&
3261 offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)) {
3263 return hns3_xmit_pkts_simple;
3266 *prep = hns3_prep_pkts;
3267 return hns3_xmit_pkts;
3271 hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused,
3272 struct rte_mbuf **pkts __rte_unused,
3273 uint16_t pkts_n __rte_unused)
3278 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)
3280 struct hns3_adapter *hns = eth_dev->data->dev_private;
3281 eth_tx_prep_t prep = NULL;
3283 if (hns->hw.adapter_state == HNS3_NIC_STARTED &&
3284 rte_atomic16_read(&hns->hw.reset.resetting) == 0) {
3285 eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev);
3286 eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep);
3287 eth_dev->tx_pkt_prepare = prep;
3289 eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst;
3290 eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
3291 eth_dev->tx_pkt_prepare = hns3_dummy_rxtx_burst;
3296 hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3297 struct rte_eth_rxq_info *qinfo)
3299 struct hns3_rx_queue *rxq = dev->data->rx_queues[queue_id];
3301 qinfo->mp = rxq->mb_pool;
3302 qinfo->nb_desc = rxq->nb_rx_desc;
3303 qinfo->scattered_rx = dev->data->scattered_rx;
3304 /* Report the HW Rx buffer length to user */
3305 qinfo->rx_buf_size = rxq->rx_buf_len;
3308 * If there are no available Rx buffer descriptors, incoming packets
3309 * are always dropped by hardware based on hns3 network engine.
3311 qinfo->conf.rx_drop_en = 1;
3312 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
3313 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3314 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3318 hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3319 struct rte_eth_txq_info *qinfo)
3321 struct hns3_tx_queue *txq = dev->data->tx_queues[queue_id];
3323 qinfo->nb_desc = txq->nb_tx_desc;
3324 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
3325 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3326 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3327 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;