1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
11 #include <rte_bus_pci.h>
12 #include <rte_byteorder.h>
13 #include <rte_common.h>
14 #include <rte_cycles.h>
17 #include <rte_ether.h>
18 #include <rte_vxlan.h>
19 #include <rte_ethdev_driver.h>
24 #include <rte_malloc.h>
26 #if defined(RTE_ARCH_ARM64) && defined(CC_SVE_SUPPORT)
27 #include <rte_cpuflags.h>
30 #include "hns3_ethdev.h"
31 #include "hns3_rxtx.h"
32 #include "hns3_regs.h"
33 #include "hns3_logs.h"
35 #define HNS3_CFG_DESC_NUM(num) ((num) / 8 - 1)
36 #define HNS3_RX_RING_PREFETCTH_MASK 3
39 hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq)
43 /* Note: Fake rx queue will not enter here */
44 if (rxq->sw_ring == NULL)
47 if (rxq->rx_rearm_nb == 0) {
48 for (i = 0; i < rxq->nb_rx_desc; i++) {
49 if (rxq->sw_ring[i].mbuf != NULL) {
50 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
51 rxq->sw_ring[i].mbuf = NULL;
55 for (i = rxq->next_to_use;
56 i != rxq->rx_rearm_start;
57 i = (i + 1) % rxq->nb_rx_desc) {
58 if (rxq->sw_ring[i].mbuf != NULL) {
59 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
60 rxq->sw_ring[i].mbuf = NULL;
65 for (i = 0; i < rxq->bulk_mbuf_num; i++)
66 rte_pktmbuf_free_seg(rxq->bulk_mbuf[i]);
67 rxq->bulk_mbuf_num = 0;
69 if (rxq->pkt_first_seg) {
70 rte_pktmbuf_free(rxq->pkt_first_seg);
71 rxq->pkt_first_seg = NULL;
76 hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq)
80 /* Note: Fake tx queue will not enter here */
82 for (i = 0; i < txq->nb_tx_desc; i++) {
83 if (txq->sw_ring[i].mbuf) {
84 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
85 txq->sw_ring[i].mbuf = NULL;
92 hns3_rx_queue_release(void *queue)
94 struct hns3_rx_queue *rxq = queue;
96 hns3_rx_queue_release_mbufs(rxq);
98 rte_memzone_free(rxq->mz);
100 rte_free(rxq->sw_ring);
106 hns3_tx_queue_release(void *queue)
108 struct hns3_tx_queue *txq = queue;
110 hns3_tx_queue_release_mbufs(txq);
112 rte_memzone_free(txq->mz);
114 rte_free(txq->sw_ring);
122 hns3_dev_rx_queue_release(void *queue)
124 struct hns3_rx_queue *rxq = queue;
125 struct hns3_adapter *hns;
131 rte_spinlock_lock(&hns->hw.lock);
132 hns3_rx_queue_release(queue);
133 rte_spinlock_unlock(&hns->hw.lock);
137 hns3_dev_tx_queue_release(void *queue)
139 struct hns3_tx_queue *txq = queue;
140 struct hns3_adapter *hns;
146 rte_spinlock_lock(&hns->hw.lock);
147 hns3_tx_queue_release(queue);
148 rte_spinlock_unlock(&hns->hw.lock);
152 hns3_fake_rx_queue_release(struct hns3_rx_queue *queue)
154 struct hns3_rx_queue *rxq = queue;
155 struct hns3_adapter *hns;
165 if (hw->fkq_data.rx_queues[idx]) {
166 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
167 hw->fkq_data.rx_queues[idx] = NULL;
170 /* free fake rx queue arrays */
171 if (idx == (hw->fkq_data.nb_fake_rx_queues - 1)) {
172 hw->fkq_data.nb_fake_rx_queues = 0;
173 rte_free(hw->fkq_data.rx_queues);
174 hw->fkq_data.rx_queues = NULL;
179 hns3_fake_tx_queue_release(struct hns3_tx_queue *queue)
181 struct hns3_tx_queue *txq = queue;
182 struct hns3_adapter *hns;
192 if (hw->fkq_data.tx_queues[idx]) {
193 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
194 hw->fkq_data.tx_queues[idx] = NULL;
197 /* free fake tx queue arrays */
198 if (idx == (hw->fkq_data.nb_fake_tx_queues - 1)) {
199 hw->fkq_data.nb_fake_tx_queues = 0;
200 rte_free(hw->fkq_data.tx_queues);
201 hw->fkq_data.tx_queues = NULL;
206 hns3_free_rx_queues(struct rte_eth_dev *dev)
208 struct hns3_adapter *hns = dev->data->dev_private;
209 struct hns3_fake_queue_data *fkq_data;
210 struct hns3_hw *hw = &hns->hw;
214 nb_rx_q = hw->data->nb_rx_queues;
215 for (i = 0; i < nb_rx_q; i++) {
216 if (dev->data->rx_queues[i]) {
217 hns3_rx_queue_release(dev->data->rx_queues[i]);
218 dev->data->rx_queues[i] = NULL;
222 /* Free fake Rx queues */
223 fkq_data = &hw->fkq_data;
224 for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) {
225 if (fkq_data->rx_queues[i])
226 hns3_fake_rx_queue_release(fkq_data->rx_queues[i]);
231 hns3_free_tx_queues(struct rte_eth_dev *dev)
233 struct hns3_adapter *hns = dev->data->dev_private;
234 struct hns3_fake_queue_data *fkq_data;
235 struct hns3_hw *hw = &hns->hw;
239 nb_tx_q = hw->data->nb_tx_queues;
240 for (i = 0; i < nb_tx_q; i++) {
241 if (dev->data->tx_queues[i]) {
242 hns3_tx_queue_release(dev->data->tx_queues[i]);
243 dev->data->tx_queues[i] = NULL;
247 /* Free fake Tx queues */
248 fkq_data = &hw->fkq_data;
249 for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) {
250 if (fkq_data->tx_queues[i])
251 hns3_fake_tx_queue_release(fkq_data->tx_queues[i]);
256 hns3_free_all_queues(struct rte_eth_dev *dev)
258 hns3_free_rx_queues(dev);
259 hns3_free_tx_queues(dev);
263 hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq)
265 struct rte_mbuf *mbuf;
269 for (i = 0; i < rxq->nb_rx_desc; i++) {
270 mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
271 if (unlikely(mbuf == NULL)) {
272 hns3_err(hw, "Failed to allocate RXD[%d] for rx queue!",
274 hns3_rx_queue_release_mbufs(rxq);
278 rte_mbuf_refcnt_set(mbuf, 1);
280 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
282 mbuf->port = rxq->port_id;
284 rxq->sw_ring[i].mbuf = mbuf;
285 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
286 rxq->rx_ring[i].addr = dma_addr;
287 rxq->rx_ring[i].rx.bd_base_info = 0;
294 hns3_buf_size2type(uint32_t buf_size)
300 bd_size_type = HNS3_BD_SIZE_512_TYPE;
303 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
306 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
309 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
316 hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)
318 uint32_t rx_buf_len = rxq->rx_buf_len;
319 uint64_t dma_addr = rxq->rx_ring_phys_addr;
321 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);
322 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,
323 (uint32_t)((dma_addr >> 31) >> 1));
325 hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,
326 hns3_buf_size2type(rx_buf_len));
327 hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG,
328 HNS3_CFG_DESC_NUM(rxq->nb_rx_desc));
332 hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)
334 uint64_t dma_addr = txq->tx_ring_phys_addr;
336 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);
337 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,
338 (uint32_t)((dma_addr >> 31) >> 1));
340 hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,
341 HNS3_CFG_DESC_NUM(txq->nb_tx_desc));
345 hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw)
347 uint16_t nb_rx_q = hw->data->nb_rx_queues;
348 uint16_t nb_tx_q = hw->data->nb_tx_queues;
349 struct hns3_rx_queue *rxq;
350 struct hns3_tx_queue *txq;
354 pvid_en = hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE;
355 for (i = 0; i < hw->cfg_max_queues; i++) {
357 rxq = hw->data->rx_queues[i];
359 rxq->pvid_sw_discard_en = pvid_en;
362 txq = hw->data->tx_queues[i];
364 txq->pvid_sw_shift_en = pvid_en;
370 hns3_enable_all_queues(struct hns3_hw *hw, bool en)
372 uint16_t nb_rx_q = hw->data->nb_rx_queues;
373 uint16_t nb_tx_q = hw->data->nb_tx_queues;
374 struct hns3_rx_queue *rxq;
375 struct hns3_tx_queue *txq;
380 for (i = 0; i < hw->cfg_max_queues; i++) {
381 if (hns3_dev_indep_txrx_supported(hw)) {
382 rxq = i < nb_rx_q ? hw->data->rx_queues[i] : NULL;
383 txq = i < nb_tx_q ? hw->data->tx_queues[i] : NULL;
385 * After initialization, rxq and txq won't be NULL at
389 tqp_base = rxq->io_base;
390 else if (txq != NULL)
391 tqp_base = txq->io_base;
395 rxq = i < nb_rx_q ? hw->data->rx_queues[i] :
396 hw->fkq_data.rx_queues[i - nb_rx_q];
398 tqp_base = rxq->io_base;
401 * This is the master switch that used to control the enabling
402 * of a pair of Tx and Rx queues. Both the Rx and Tx point to
405 rcb_reg = hns3_read_reg(tqp_base, HNS3_RING_EN_REG);
407 rcb_reg |= BIT(HNS3_RING_EN_B);
409 rcb_reg &= ~BIT(HNS3_RING_EN_B);
410 hns3_write_reg(tqp_base, HNS3_RING_EN_REG, rcb_reg);
415 hns3_enable_txq(struct hns3_tx_queue *txq, bool en)
417 struct hns3_hw *hw = &txq->hns->hw;
420 if (hns3_dev_indep_txrx_supported(hw)) {
421 reg = hns3_read_dev(txq, HNS3_RING_TX_EN_REG);
423 reg |= BIT(HNS3_RING_EN_B);
425 reg &= ~BIT(HNS3_RING_EN_B);
426 hns3_write_dev(txq, HNS3_RING_TX_EN_REG, reg);
432 hns3_enable_rxq(struct hns3_rx_queue *rxq, bool en)
434 struct hns3_hw *hw = &rxq->hns->hw;
437 if (hns3_dev_indep_txrx_supported(hw)) {
438 reg = hns3_read_dev(rxq, HNS3_RING_RX_EN_REG);
440 reg |= BIT(HNS3_RING_EN_B);
442 reg &= ~BIT(HNS3_RING_EN_B);
443 hns3_write_dev(rxq, HNS3_RING_RX_EN_REG, reg);
449 hns3_start_all_txqs(struct rte_eth_dev *dev)
451 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
452 struct hns3_tx_queue *txq;
455 for (i = 0; i < dev->data->nb_tx_queues; i++) {
456 txq = hw->data->tx_queues[i];
458 hns3_err(hw, "Tx queue %u not available or setup.", i);
459 goto start_txqs_fail;
462 * Tx queue is enabled by default. Therefore, the Tx queues
463 * needs to be disabled when deferred_start is set. There is
464 * another master switch used to control the enabling of a pair
465 * of Tx and Rx queues. And the master switch is disabled by
468 if (txq->tx_deferred_start)
469 hns3_enable_txq(txq, false);
471 hns3_enable_txq(txq, true);
476 for (j = 0; j < i; j++) {
477 txq = hw->data->tx_queues[j];
478 hns3_enable_txq(txq, false);
484 hns3_start_all_rxqs(struct rte_eth_dev *dev)
486 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
487 struct hns3_rx_queue *rxq;
490 for (i = 0; i < dev->data->nb_rx_queues; i++) {
491 rxq = hw->data->rx_queues[i];
493 hns3_err(hw, "Rx queue %u not available or setup.", i);
494 goto start_rxqs_fail;
497 * Rx queue is enabled by default. Therefore, the Rx queues
498 * needs to be disabled when deferred_start is set. There is
499 * another master switch used to control the enabling of a pair
500 * of Tx and Rx queues. And the master switch is disabled by
503 if (rxq->rx_deferred_start)
504 hns3_enable_rxq(rxq, false);
506 hns3_enable_rxq(rxq, true);
511 for (j = 0; j < i; j++) {
512 rxq = hw->data->rx_queues[j];
513 hns3_enable_rxq(rxq, false);
519 hns3_stop_all_txqs(struct rte_eth_dev *dev)
521 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
522 struct hns3_tx_queue *txq;
525 for (i = 0; i < dev->data->nb_tx_queues; i++) {
526 txq = hw->data->tx_queues[i];
529 hns3_enable_txq(txq, false);
534 hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable)
536 struct hns3_cfg_com_tqp_queue_cmd *req;
537 struct hns3_cmd_desc desc;
540 req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data;
542 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false);
543 req->tqp_id = rte_cpu_to_le_16(queue_id);
545 hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0);
547 ret = hns3_cmd_send(hw, &desc, 1);
549 hns3_err(hw, "TQP enable fail, ret = %d", ret);
555 hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable)
557 struct hns3_reset_tqp_queue_cmd *req;
558 struct hns3_cmd_desc desc;
561 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false);
563 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
564 req->tqp_id = rte_cpu_to_le_16(queue_id);
565 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
566 ret = hns3_cmd_send(hw, &desc, 1);
568 hns3_err(hw, "send tqp reset cmd error, queue_id = %u, "
569 "ret = %d", queue_id, ret);
575 hns3_get_tqp_reset_status(struct hns3_hw *hw, uint16_t queue_id,
576 uint8_t *reset_status)
578 struct hns3_reset_tqp_queue_cmd *req;
579 struct hns3_cmd_desc desc;
582 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true);
584 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
585 req->tqp_id = rte_cpu_to_le_16(queue_id);
587 ret = hns3_cmd_send(hw, &desc, 1);
589 hns3_err(hw, "get tqp reset status error, queue_id = %u, "
590 "ret = %d.", queue_id, ret);
593 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
598 hns3pf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
600 #define HNS3_TQP_RESET_TRY_MS 200
601 uint8_t reset_status;
605 ret = hns3_tqp_enable(hw, queue_id, false);
610 * In current version VF is not supported when PF is driven by DPDK
611 * driver, all task queue pairs are mapped to PF function, so PF's queue
612 * id is equals to the global queue id in PF range.
614 ret = hns3_send_reset_tqp_cmd(hw, queue_id, true);
616 hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret);
619 end = get_timeofday_ms() + HNS3_TQP_RESET_TRY_MS;
621 /* Wait for tqp hw reset */
622 rte_delay_ms(HNS3_POLL_RESPONE_MS);
623 ret = hns3_get_tqp_reset_status(hw, queue_id, &reset_status);
629 } while (get_timeofday_ms() < end);
633 hns3_err(hw, "reset tqp timeout, queue_id = %u, ret = %d",
638 ret = hns3_send_reset_tqp_cmd(hw, queue_id, false);
640 hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret);
645 hns3_send_reset_tqp_cmd(hw, queue_id, false);
650 hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
655 /* Disable VF's queue before send queue reset msg to PF */
656 ret = hns3_tqp_enable(hw, queue_id, false);
660 memcpy(msg_data, &queue_id, sizeof(uint16_t));
662 ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
663 sizeof(msg_data), true, NULL, 0);
665 hns3_err(hw, "fail to reset tqp, queue_id = %u, ret = %d.",
671 hns3_reset_tqp(struct hns3_adapter *hns, uint16_t queue_id)
673 struct hns3_hw *hw = &hns->hw;
676 return hns3vf_reset_tqp(hw, queue_id);
678 return hns3pf_reset_tqp(hw, queue_id);
682 hns3_reset_all_tqps(struct hns3_adapter *hns)
684 struct hns3_hw *hw = &hns->hw;
687 for (i = 0; i < hw->cfg_max_queues; i++) {
688 ret = hns3_reset_tqp(hns, i);
690 hns3_err(hw, "Failed to reset No.%d queue: %d", i, ret);
698 hns3_send_reset_queue_cmd(struct hns3_hw *hw, uint16_t queue_id,
699 enum hns3_ring_type queue_type, bool enable)
701 struct hns3_reset_tqp_queue_cmd *req;
702 struct hns3_cmd_desc desc;
706 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, false);
708 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
709 req->tqp_id = rte_cpu_to_le_16(queue_id);
710 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
711 req->queue_direction = rte_cpu_to_le_16(queue_direction);
712 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
714 ret = hns3_cmd_send(hw, &desc, 1);
716 hns3_err(hw, "send queue reset cmd error, queue_id = %u, "
717 "queue_type = %s, ret = %d.", queue_id,
718 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
723 hns3_get_queue_reset_status(struct hns3_hw *hw, uint16_t queue_id,
724 enum hns3_ring_type queue_type,
725 uint8_t *reset_status)
727 struct hns3_reset_tqp_queue_cmd *req;
728 struct hns3_cmd_desc desc;
732 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, true);
734 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
735 req->tqp_id = rte_cpu_to_le_16(queue_id);
736 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
737 req->queue_direction = rte_cpu_to_le_16(queue_direction);
739 ret = hns3_cmd_send(hw, &desc, 1);
741 hns3_err(hw, "get queue reset status error, queue_id = %u "
742 "queue_type = %s, ret = %d.", queue_id,
743 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
747 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
752 hns3_reset_queue(struct hns3_hw *hw, uint16_t queue_id,
753 enum hns3_ring_type queue_type)
755 #define HNS3_QUEUE_RESET_TRY_MS 200
756 struct hns3_tx_queue *txq;
757 struct hns3_rx_queue *rxq;
758 uint32_t reset_wait_times;
759 uint32_t max_wait_times;
760 uint8_t reset_status;
763 if (queue_type == HNS3_RING_TYPE_TX) {
764 txq = hw->data->tx_queues[queue_id];
765 hns3_enable_txq(txq, false);
767 rxq = hw->data->rx_queues[queue_id];
768 hns3_enable_rxq(rxq, false);
771 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, true);
773 hns3_err(hw, "send reset queue cmd fail, ret = %d.", ret);
777 reset_wait_times = 0;
778 max_wait_times = HNS3_QUEUE_RESET_TRY_MS / HNS3_POLL_RESPONE_MS;
779 while (reset_wait_times < max_wait_times) {
780 /* Wait for queue hw reset */
781 rte_delay_ms(HNS3_POLL_RESPONE_MS);
782 ret = hns3_get_queue_reset_status(hw, queue_id,
783 queue_type, &reset_status);
785 goto queue_reset_fail;
793 hns3_err(hw, "reset queue timeout, queue_id = %u, "
794 "queue_type = %s", queue_id,
795 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx");
797 goto queue_reset_fail;
800 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
802 hns3_err(hw, "deassert queue reset fail, ret = %d.", ret);
807 hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
813 hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
814 uint8_t gl_idx, uint16_t gl_value)
816 uint32_t offset[] = {HNS3_TQP_INTR_GL0_REG,
817 HNS3_TQP_INTR_GL1_REG,
818 HNS3_TQP_INTR_GL2_REG};
819 uint32_t addr, value;
821 if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX)
824 addr = offset[gl_idx] + queue_id * HNS3_TQP_INTR_REG_SIZE;
825 if (hw->intr.gl_unit == HNS3_INTR_COALESCE_GL_UINT_1US)
826 value = gl_value | HNS3_TQP_INTR_GL_UNIT_1US;
828 value = HNS3_GL_USEC_TO_REG(gl_value);
830 hns3_write_dev(hw, addr, value);
834 hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value)
836 uint32_t addr, value;
838 if (rl_value > HNS3_TQP_INTR_RL_MAX)
841 addr = HNS3_TQP_INTR_RL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
842 value = HNS3_RL_USEC_TO_REG(rl_value);
844 value |= HNS3_TQP_INTR_RL_ENABLE_MASK;
846 hns3_write_dev(hw, addr, value);
850 hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value)
854 if (hw->intr.coalesce_mode == HNS3_INTR_COALESCE_NON_QL)
857 addr = HNS3_TQP_INTR_TX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
858 hns3_write_dev(hw, addr, ql_value);
860 addr = HNS3_TQP_INTR_RX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
861 hns3_write_dev(hw, addr, ql_value);
865 hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en)
867 uint32_t addr, value;
869 addr = HNS3_TQP_INTR_CTRL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
872 hns3_write_dev(hw, addr, value);
876 * Enable all rx queue interrupt when in interrupt rx mode.
877 * This api was called before enable queue rx&tx (in normal start or reset
878 * recover scenes), used to fix hardware rx queue interrupt enable was clear
882 hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en)
884 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
885 uint16_t nb_rx_q = hw->data->nb_rx_queues;
888 if (dev->data->dev_conf.intr_conf.rxq == 0)
891 for (i = 0; i < nb_rx_q; i++)
892 hns3_queue_intr_enable(hw, i, en);
896 hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
898 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
899 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
900 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
902 if (dev->data->dev_conf.intr_conf.rxq == 0)
905 hns3_queue_intr_enable(hw, queue_id, true);
907 return rte_intr_ack(intr_handle);
911 hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
913 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
915 if (dev->data->dev_conf.intr_conf.rxq == 0)
918 hns3_queue_intr_enable(hw, queue_id, false);
924 hns3_init_rxq(struct hns3_adapter *hns, uint16_t idx)
926 struct hns3_hw *hw = &hns->hw;
927 struct hns3_rx_queue *rxq;
930 PMD_INIT_FUNC_TRACE();
932 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx];
933 ret = hns3_alloc_rx_queue_mbufs(hw, rxq);
935 hns3_err(hw, "fail to alloc mbuf for Rx queue %u, ret = %d.",
940 rxq->next_to_use = 0;
941 rxq->rx_rearm_start = 0;
942 rxq->rx_free_hold = 0;
943 rxq->rx_rearm_nb = 0;
944 rxq->pkt_first_seg = NULL;
945 rxq->pkt_last_seg = NULL;
946 hns3_init_rx_queue_hw(rxq);
947 hns3_rxq_vec_setup(rxq);
953 hns3_init_fake_rxq(struct hns3_adapter *hns, uint16_t idx)
955 struct hns3_hw *hw = &hns->hw;
956 struct hns3_rx_queue *rxq;
958 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx];
959 rxq->next_to_use = 0;
960 rxq->rx_free_hold = 0;
961 rxq->rx_rearm_start = 0;
962 rxq->rx_rearm_nb = 0;
963 hns3_init_rx_queue_hw(rxq);
967 hns3_init_txq(struct hns3_tx_queue *txq)
969 struct hns3_desc *desc;
974 for (i = 0; i < txq->nb_tx_desc; i++) {
975 desc->tx.tp_fe_sc_vld_ra_ri = 0;
979 txq->next_to_use = 0;
980 txq->next_to_clean = 0;
981 txq->tx_bd_ready = txq->nb_tx_desc - 1;
982 hns3_init_tx_queue_hw(txq);
986 hns3_init_tx_ring_tc(struct hns3_adapter *hns)
988 struct hns3_hw *hw = &hns->hw;
989 struct hns3_tx_queue *txq;
992 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
993 struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i];
996 if (!tc_queue->enable)
999 for (j = 0; j < tc_queue->tqp_count; j++) {
1000 num = tc_queue->tqp_offset + j;
1001 txq = (struct hns3_tx_queue *)hw->data->tx_queues[num];
1005 hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc);
1011 hns3_init_rx_queues(struct hns3_adapter *hns)
1013 struct hns3_hw *hw = &hns->hw;
1014 struct hns3_rx_queue *rxq;
1018 /* Initialize RSS for queues */
1019 ret = hns3_config_rss(hns);
1021 hns3_err(hw, "failed to configure rss, ret = %d.", ret);
1025 for (i = 0; i < hw->data->nb_rx_queues; i++) {
1026 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i];
1028 hns3_err(hw, "Rx queue %u not available or setup.", i);
1032 if (rxq->rx_deferred_start)
1035 ret = hns3_init_rxq(hns, i);
1037 hns3_err(hw, "failed to init Rx queue %u, ret = %d.", i,
1043 for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++)
1044 hns3_init_fake_rxq(hns, i);
1049 for (j = 0; j < i; j++) {
1050 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j];
1051 hns3_rx_queue_release_mbufs(rxq);
1058 hns3_init_tx_queues(struct hns3_adapter *hns)
1060 struct hns3_hw *hw = &hns->hw;
1061 struct hns3_tx_queue *txq;
1064 for (i = 0; i < hw->data->nb_tx_queues; i++) {
1065 txq = (struct hns3_tx_queue *)hw->data->tx_queues[i];
1067 hns3_err(hw, "Tx queue %u not available or setup.", i);
1071 if (txq->tx_deferred_start)
1076 for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) {
1077 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i];
1080 hns3_init_tx_ring_tc(hns);
1087 * Note: just init and setup queues, and don't enable tqps.
1090 hns3_init_queues(struct hns3_adapter *hns, bool reset_queue)
1092 struct hns3_hw *hw = &hns->hw;
1096 ret = hns3_reset_all_tqps(hns);
1098 hns3_err(hw, "failed to reset all queues, ret = %d.",
1104 ret = hns3_init_rx_queues(hns);
1106 hns3_err(hw, "failed to init rx queues, ret = %d.", ret);
1110 ret = hns3_init_tx_queues(hns);
1112 hns3_dev_release_mbufs(hns);
1113 hns3_err(hw, "failed to init tx queues, ret = %d.", ret);
1120 hns3_start_tqps(struct hns3_hw *hw)
1122 struct hns3_tx_queue *txq;
1123 struct hns3_rx_queue *rxq;
1126 hns3_enable_all_queues(hw, true);
1128 for (i = 0; i < hw->data->nb_tx_queues; i++) {
1129 txq = hw->data->tx_queues[i];
1131 hw->data->tx_queue_state[i] =
1132 RTE_ETH_QUEUE_STATE_STARTED;
1135 for (i = 0; i < hw->data->nb_rx_queues; i++) {
1136 rxq = hw->data->rx_queues[i];
1138 hw->data->rx_queue_state[i] =
1139 RTE_ETH_QUEUE_STATE_STARTED;
1144 hns3_stop_tqps(struct hns3_hw *hw)
1148 hns3_enable_all_queues(hw, false);
1150 for (i = 0; i < hw->data->nb_tx_queues; i++)
1151 hw->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1153 for (i = 0; i < hw->data->nb_rx_queues; i++)
1154 hw->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1158 * Iterate over all Rx Queue, and call the callback() function for each Rx
1162 * The target eth dev.
1163 * @param[in] callback
1164 * The function to call for each queue.
1165 * if callback function return nonzero will stop iterate and return it's value
1167 * The arguments to provide the callback function with.
1170 * 0 on success, otherwise with errno set.
1173 hns3_rxq_iterate(struct rte_eth_dev *dev,
1174 int (*callback)(struct hns3_rx_queue *, void *), void *arg)
1179 if (dev->data->rx_queues == NULL)
1182 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1183 ret = callback(dev->data->rx_queues[i], arg);
1192 hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev,
1193 struct hns3_queue_info *q_info)
1195 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1196 const struct rte_memzone *rx_mz;
1197 struct hns3_rx_queue *rxq;
1198 unsigned int rx_desc;
1200 rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue),
1201 RTE_CACHE_LINE_SIZE, q_info->socket_id);
1203 hns3_err(hw, "Failed to allocate memory for No.%d rx ring!",
1208 /* Allocate rx ring hardware descriptors. */
1209 rxq->queue_id = q_info->idx;
1210 rxq->nb_rx_desc = q_info->nb_desc;
1213 * Allocate a litter more memory because rx vector functions
1214 * don't check boundaries each time.
1216 rx_desc = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
1217 sizeof(struct hns3_desc);
1218 rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
1219 rx_desc, HNS3_RING_BASE_ALIGN,
1221 if (rx_mz == NULL) {
1222 hns3_err(hw, "Failed to reserve DMA memory for No.%d rx ring!",
1224 hns3_rx_queue_release(rxq);
1228 rxq->rx_ring = (struct hns3_desc *)rx_mz->addr;
1229 rxq->rx_ring_phys_addr = rx_mz->iova;
1231 hns3_dbg(hw, "No.%d rx descriptors iova 0x%" PRIx64, q_info->idx,
1232 rxq->rx_ring_phys_addr);
1238 hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
1239 uint16_t nb_desc, unsigned int socket_id)
1241 struct hns3_adapter *hns = dev->data->dev_private;
1242 struct hns3_hw *hw = &hns->hw;
1243 struct hns3_queue_info q_info;
1244 struct hns3_rx_queue *rxq;
1247 if (hw->fkq_data.rx_queues[idx]) {
1248 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
1249 hw->fkq_data.rx_queues[idx] = NULL;
1253 q_info.socket_id = socket_id;
1254 q_info.nb_desc = nb_desc;
1255 q_info.type = "hns3 fake RX queue";
1256 q_info.ring_name = "rx_fake_ring";
1257 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1259 hns3_err(hw, "Failed to setup No.%d fake rx ring.", idx);
1263 /* Don't need alloc sw_ring, because upper applications don't use it */
1264 rxq->sw_ring = NULL;
1267 rxq->rx_deferred_start = false;
1268 rxq->port_id = dev->data->port_id;
1269 rxq->configured = true;
1270 nb_rx_q = dev->data->nb_rx_queues;
1271 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1272 (nb_rx_q + idx) * HNS3_TQP_REG_SIZE);
1273 rxq->rx_buf_len = HNS3_MIN_BD_BUF_SIZE;
1275 rte_spinlock_lock(&hw->lock);
1276 hw->fkq_data.rx_queues[idx] = rxq;
1277 rte_spinlock_unlock(&hw->lock);
1283 hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev,
1284 struct hns3_queue_info *q_info)
1286 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1287 const struct rte_memzone *tx_mz;
1288 struct hns3_tx_queue *txq;
1289 struct hns3_desc *desc;
1290 unsigned int tx_desc;
1293 txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue),
1294 RTE_CACHE_LINE_SIZE, q_info->socket_id);
1296 hns3_err(hw, "Failed to allocate memory for No.%d tx ring!",
1301 /* Allocate tx ring hardware descriptors. */
1302 txq->queue_id = q_info->idx;
1303 txq->nb_tx_desc = q_info->nb_desc;
1304 tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc);
1305 tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
1306 tx_desc, HNS3_RING_BASE_ALIGN,
1308 if (tx_mz == NULL) {
1309 hns3_err(hw, "Failed to reserve DMA memory for No.%d tx ring!",
1311 hns3_tx_queue_release(txq);
1315 txq->tx_ring = (struct hns3_desc *)tx_mz->addr;
1316 txq->tx_ring_phys_addr = tx_mz->iova;
1318 hns3_dbg(hw, "No.%d tx descriptors iova 0x%" PRIx64, q_info->idx,
1319 txq->tx_ring_phys_addr);
1322 desc = txq->tx_ring;
1323 for (i = 0; i < txq->nb_tx_desc; i++) {
1324 desc->tx.tp_fe_sc_vld_ra_ri = 0;
1332 hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
1333 uint16_t nb_desc, unsigned int socket_id)
1335 struct hns3_adapter *hns = dev->data->dev_private;
1336 struct hns3_hw *hw = &hns->hw;
1337 struct hns3_queue_info q_info;
1338 struct hns3_tx_queue *txq;
1341 if (hw->fkq_data.tx_queues[idx] != NULL) {
1342 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
1343 hw->fkq_data.tx_queues[idx] = NULL;
1347 q_info.socket_id = socket_id;
1348 q_info.nb_desc = nb_desc;
1349 q_info.type = "hns3 fake TX queue";
1350 q_info.ring_name = "tx_fake_ring";
1351 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
1353 hns3_err(hw, "Failed to setup No.%d fake tx ring.", idx);
1357 /* Don't need alloc sw_ring, because upper applications don't use it */
1358 txq->sw_ring = NULL;
1362 txq->tx_deferred_start = false;
1363 txq->port_id = dev->data->port_id;
1364 txq->configured = true;
1365 nb_tx_q = dev->data->nb_tx_queues;
1366 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1367 (nb_tx_q + idx) * HNS3_TQP_REG_SIZE);
1369 rte_spinlock_lock(&hw->lock);
1370 hw->fkq_data.tx_queues[idx] = txq;
1371 rte_spinlock_unlock(&hw->lock);
1377 hns3_fake_rx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1379 uint16_t old_nb_queues = hw->fkq_data.nb_fake_rx_queues;
1383 if (hw->fkq_data.rx_queues == NULL && nb_queues != 0) {
1384 /* first time configuration */
1386 size = sizeof(hw->fkq_data.rx_queues[0]) * nb_queues;
1387 hw->fkq_data.rx_queues = rte_zmalloc("fake_rx_queues", size,
1388 RTE_CACHE_LINE_SIZE);
1389 if (hw->fkq_data.rx_queues == NULL) {
1390 hw->fkq_data.nb_fake_rx_queues = 0;
1393 } else if (hw->fkq_data.rx_queues != NULL && nb_queues != 0) {
1395 rxq = hw->fkq_data.rx_queues;
1396 for (i = nb_queues; i < old_nb_queues; i++)
1397 hns3_dev_rx_queue_release(rxq[i]);
1399 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
1400 RTE_CACHE_LINE_SIZE);
1403 if (nb_queues > old_nb_queues) {
1404 uint16_t new_qs = nb_queues - old_nb_queues;
1405 memset(rxq + old_nb_queues, 0, sizeof(rxq[0]) * new_qs);
1408 hw->fkq_data.rx_queues = rxq;
1409 } else if (hw->fkq_data.rx_queues != NULL && nb_queues == 0) {
1410 rxq = hw->fkq_data.rx_queues;
1411 for (i = nb_queues; i < old_nb_queues; i++)
1412 hns3_dev_rx_queue_release(rxq[i]);
1414 rte_free(hw->fkq_data.rx_queues);
1415 hw->fkq_data.rx_queues = NULL;
1418 hw->fkq_data.nb_fake_rx_queues = nb_queues;
1424 hns3_fake_tx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1426 uint16_t old_nb_queues = hw->fkq_data.nb_fake_tx_queues;
1430 if (hw->fkq_data.tx_queues == NULL && nb_queues != 0) {
1431 /* first time configuration */
1433 size = sizeof(hw->fkq_data.tx_queues[0]) * nb_queues;
1434 hw->fkq_data.tx_queues = rte_zmalloc("fake_tx_queues", size,
1435 RTE_CACHE_LINE_SIZE);
1436 if (hw->fkq_data.tx_queues == NULL) {
1437 hw->fkq_data.nb_fake_tx_queues = 0;
1440 } else if (hw->fkq_data.tx_queues != NULL && nb_queues != 0) {
1442 txq = hw->fkq_data.tx_queues;
1443 for (i = nb_queues; i < old_nb_queues; i++)
1444 hns3_dev_tx_queue_release(txq[i]);
1445 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1446 RTE_CACHE_LINE_SIZE);
1449 if (nb_queues > old_nb_queues) {
1450 uint16_t new_qs = nb_queues - old_nb_queues;
1451 memset(txq + old_nb_queues, 0, sizeof(txq[0]) * new_qs);
1454 hw->fkq_data.tx_queues = txq;
1455 } else if (hw->fkq_data.tx_queues != NULL && nb_queues == 0) {
1456 txq = hw->fkq_data.tx_queues;
1457 for (i = nb_queues; i < old_nb_queues; i++)
1458 hns3_dev_tx_queue_release(txq[i]);
1460 rte_free(hw->fkq_data.tx_queues);
1461 hw->fkq_data.tx_queues = NULL;
1463 hw->fkq_data.nb_fake_tx_queues = nb_queues;
1469 hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
1472 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1473 uint16_t rx_need_add_nb_q;
1474 uint16_t tx_need_add_nb_q;
1479 /* Setup new number of fake RX/TX queues and reconfigure device. */
1480 rx_need_add_nb_q = hw->cfg_max_queues - nb_rx_q;
1481 tx_need_add_nb_q = hw->cfg_max_queues - nb_tx_q;
1482 ret = hns3_fake_rx_queue_config(hw, rx_need_add_nb_q);
1484 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1488 ret = hns3_fake_tx_queue_config(hw, tx_need_add_nb_q);
1490 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1491 goto cfg_fake_tx_q_fail;
1494 /* Allocate and set up fake RX queue per Ethernet port. */
1495 port_id = hw->data->port_id;
1496 for (q = 0; q < rx_need_add_nb_q; q++) {
1497 ret = hns3_fake_rx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1498 rte_eth_dev_socket_id(port_id));
1500 goto setup_fake_rx_q_fail;
1503 /* Allocate and set up fake TX queue per Ethernet port. */
1504 for (q = 0; q < tx_need_add_nb_q; q++) {
1505 ret = hns3_fake_tx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1506 rte_eth_dev_socket_id(port_id));
1508 goto setup_fake_tx_q_fail;
1513 setup_fake_tx_q_fail:
1514 setup_fake_rx_q_fail:
1515 (void)hns3_fake_tx_queue_config(hw, 0);
1517 (void)hns3_fake_rx_queue_config(hw, 0);
1523 hns3_dev_release_mbufs(struct hns3_adapter *hns)
1525 struct rte_eth_dev_data *dev_data = hns->hw.data;
1526 struct hns3_rx_queue *rxq;
1527 struct hns3_tx_queue *txq;
1530 if (dev_data->rx_queues)
1531 for (i = 0; i < dev_data->nb_rx_queues; i++) {
1532 rxq = dev_data->rx_queues[i];
1535 hns3_rx_queue_release_mbufs(rxq);
1538 if (dev_data->tx_queues)
1539 for (i = 0; i < dev_data->nb_tx_queues; i++) {
1540 txq = dev_data->tx_queues[i];
1543 hns3_tx_queue_release_mbufs(txq);
1548 hns3_rx_buf_len_calc(struct rte_mempool *mp, uint16_t *rx_buf_len)
1550 uint16_t vld_buf_size;
1551 uint16_t num_hw_specs;
1555 * hns3 network engine only support to set 4 typical specification, and
1556 * different buffer size will affect the max packet_len and the max
1557 * number of segmentation when hw gro is turned on in receive side. The
1558 * relationship between them is as follows:
1559 * rx_buf_size | max_gro_pkt_len | max_gro_nb_seg
1560 * ---------------------|-------------------|----------------
1561 * HNS3_4K_BD_BUF_SIZE | 60KB | 15
1562 * HNS3_2K_BD_BUF_SIZE | 62KB | 31
1563 * HNS3_1K_BD_BUF_SIZE | 63KB | 63
1564 * HNS3_512_BD_BUF_SIZE | 31.5KB | 63
1566 static const uint16_t hw_rx_buf_size[] = {
1567 HNS3_4K_BD_BUF_SIZE,
1568 HNS3_2K_BD_BUF_SIZE,
1569 HNS3_1K_BD_BUF_SIZE,
1570 HNS3_512_BD_BUF_SIZE
1573 vld_buf_size = (uint16_t)(rte_pktmbuf_data_room_size(mp) -
1574 RTE_PKTMBUF_HEADROOM);
1576 if (vld_buf_size < HNS3_MIN_BD_BUF_SIZE)
1579 num_hw_specs = RTE_DIM(hw_rx_buf_size);
1580 for (i = 0; i < num_hw_specs; i++) {
1581 if (vld_buf_size >= hw_rx_buf_size[i]) {
1582 *rx_buf_len = hw_rx_buf_size[i];
1590 hns3_rxq_conf_runtime_check(struct hns3_hw *hw, uint16_t buf_size,
1593 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1594 struct rte_eth_rxmode *rxmode = &hw->data->dev_conf.rxmode;
1595 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
1596 uint16_t min_vec_bds;
1599 * HNS3 hardware network engine set scattered as default. If the driver
1600 * is not work in scattered mode and the pkts greater than buf_size
1601 * but smaller than max_rx_pkt_len will be distributed to multiple BDs.
1602 * Driver cannot handle this situation.
1604 if (!hw->data->scattered_rx && rxmode->max_rx_pkt_len > buf_size) {
1605 hns3_err(hw, "max_rx_pkt_len is not allowed to be set greater "
1606 "than rx_buf_len if scattered is off.");
1610 if (pkt_burst == hns3_recv_pkts_vec) {
1611 min_vec_bds = HNS3_DEFAULT_RXQ_REARM_THRESH +
1612 HNS3_DEFAULT_RX_BURST;
1613 if (nb_desc < min_vec_bds ||
1614 nb_desc % HNS3_DEFAULT_RXQ_REARM_THRESH) {
1615 hns3_err(hw, "if Rx burst mode is vector, "
1616 "number of descriptor is required to be "
1617 "bigger than min vector bds:%u, and could be "
1618 "divided by rxq rearm thresh:%u.",
1619 min_vec_bds, HNS3_DEFAULT_RXQ_REARM_THRESH);
1627 hns3_rx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_rxconf *conf,
1628 struct rte_mempool *mp, uint16_t nb_desc,
1633 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1634 nb_desc % HNS3_ALIGN_RING_DESC) {
1635 hns3_err(hw, "Number (%u) of rx descriptors is invalid",
1640 if (conf->rx_drop_en == 0)
1641 hns3_warn(hw, "if no descriptors available, packets are always "
1642 "dropped and rx_drop_en (1) is fixed on");
1644 if (hns3_rx_buf_len_calc(mp, buf_size)) {
1645 hns3_err(hw, "rxq mbufs' data room size (%u) is not enough! "
1646 "minimal data room size (%u).",
1647 rte_pktmbuf_data_room_size(mp),
1648 HNS3_MIN_BD_BUF_SIZE + RTE_PKTMBUF_HEADROOM);
1652 if (hw->data->dev_started) {
1653 ret = hns3_rxq_conf_runtime_check(hw, *buf_size, nb_desc);
1655 hns3_err(hw, "Rx queue runtime setup fail.");
1664 hns3_get_tqp_reg_offset(uint16_t queue_id)
1666 uint32_t reg_offset;
1668 /* Need an extend offset to config queue > 1024 */
1669 if (queue_id < HNS3_MIN_EXTEND_QUEUE_ID)
1670 reg_offset = HNS3_TQP_REG_OFFSET + queue_id * HNS3_TQP_REG_SIZE;
1672 reg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_EXT_REG_OFFSET +
1673 (queue_id - HNS3_MIN_EXTEND_QUEUE_ID) *
1680 hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1681 unsigned int socket_id, const struct rte_eth_rxconf *conf,
1682 struct rte_mempool *mp)
1684 struct hns3_adapter *hns = dev->data->dev_private;
1685 struct hns3_hw *hw = &hns->hw;
1686 struct hns3_queue_info q_info;
1687 struct hns3_rx_queue *rxq;
1688 uint16_t rx_buf_size;
1692 ret = hns3_rx_queue_conf_check(hw, conf, mp, nb_desc, &rx_buf_size);
1696 if (dev->data->rx_queues[idx]) {
1697 hns3_rx_queue_release(dev->data->rx_queues[idx]);
1698 dev->data->rx_queues[idx] = NULL;
1702 q_info.socket_id = socket_id;
1703 q_info.nb_desc = nb_desc;
1704 q_info.type = "hns3 RX queue";
1705 q_info.ring_name = "rx_ring";
1707 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1710 "Failed to alloc mem and reserve DMA mem for rx ring!");
1715 rxq->ptype_tbl = &hns->ptype_tbl;
1717 rxq->rx_free_thresh = (conf->rx_free_thresh > 0) ?
1718 conf->rx_free_thresh : HNS3_DEFAULT_RX_FREE_THRESH;
1720 rxq->rx_deferred_start = conf->rx_deferred_start;
1721 if (rxq->rx_deferred_start && !hns3_dev_indep_txrx_supported(hw)) {
1722 hns3_warn(hw, "deferred start is not supported.");
1723 rxq->rx_deferred_start = false;
1726 rx_entry_len = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
1727 sizeof(struct hns3_entry);
1728 rxq->sw_ring = rte_zmalloc_socket("hns3 RX sw ring", rx_entry_len,
1729 RTE_CACHE_LINE_SIZE, socket_id);
1730 if (rxq->sw_ring == NULL) {
1731 hns3_err(hw, "Failed to allocate memory for rx sw ring!");
1732 hns3_rx_queue_release(rxq);
1736 rxq->next_to_use = 0;
1737 rxq->rx_free_hold = 0;
1738 rxq->rx_rearm_start = 0;
1739 rxq->rx_rearm_nb = 0;
1740 rxq->pkt_first_seg = NULL;
1741 rxq->pkt_last_seg = NULL;
1742 rxq->port_id = dev->data->port_id;
1744 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
1745 * the pvid_sw_discard_en in the queue struct should not be changed,
1746 * because PVID-related operations do not need to be processed by PMD
1747 * driver. For hns3 VF device, whether it needs to process PVID depends
1748 * on the configuration of PF kernel mode netdevice driver. And the
1749 * related PF configuration is delivered through the mailbox and finally
1750 * reflectd in port_base_vlan_cfg.
1752 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1753 rxq->pvid_sw_discard_en = hw->port_base_vlan_cfg.state ==
1754 HNS3_PORT_BASE_VLAN_ENABLE;
1756 rxq->pvid_sw_discard_en = false;
1757 rxq->configured = true;
1758 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1759 idx * HNS3_TQP_REG_SIZE);
1760 rxq->io_base = (void *)((char *)hw->io_base +
1761 hns3_get_tqp_reg_offset(idx));
1762 rxq->io_head_reg = (volatile void *)((char *)rxq->io_base +
1763 HNS3_RING_RX_HEAD_REG);
1764 rxq->rx_buf_len = rx_buf_size;
1766 rxq->pkt_len_errors = 0;
1767 rxq->l3_csum_errors = 0;
1768 rxq->l4_csum_errors = 0;
1769 rxq->ol3_csum_errors = 0;
1770 rxq->ol4_csum_errors = 0;
1772 /* CRC len set here is used for amending packet length */
1773 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1774 rxq->crc_len = RTE_ETHER_CRC_LEN;
1778 rxq->bulk_mbuf_num = 0;
1780 rte_spinlock_lock(&hw->lock);
1781 dev->data->rx_queues[idx] = rxq;
1782 rte_spinlock_unlock(&hw->lock);
1788 hns3_rx_scattered_reset(struct rte_eth_dev *dev)
1790 struct hns3_adapter *hns = dev->data->dev_private;
1791 struct hns3_hw *hw = &hns->hw;
1794 dev->data->scattered_rx = false;
1798 hns3_rx_scattered_calc(struct rte_eth_dev *dev)
1800 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1801 struct hns3_adapter *hns = dev->data->dev_private;
1802 struct hns3_hw *hw = &hns->hw;
1803 struct hns3_rx_queue *rxq;
1806 if (dev->data->rx_queues == NULL)
1809 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
1810 rxq = dev->data->rx_queues[queue_id];
1811 if (hw->rx_buf_len == 0)
1812 hw->rx_buf_len = rxq->rx_buf_len;
1814 hw->rx_buf_len = RTE_MIN(hw->rx_buf_len,
1818 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_SCATTER ||
1819 dev_conf->rxmode.max_rx_pkt_len > hw->rx_buf_len)
1820 dev->data->scattered_rx = true;
1824 hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1826 static const uint32_t ptypes[] = {
1828 RTE_PTYPE_L2_ETHER_VLAN,
1829 RTE_PTYPE_L2_ETHER_QINQ,
1830 RTE_PTYPE_L2_ETHER_LLDP,
1831 RTE_PTYPE_L2_ETHER_ARP,
1833 RTE_PTYPE_L3_IPV4_EXT,
1835 RTE_PTYPE_L3_IPV6_EXT,
1841 RTE_PTYPE_TUNNEL_GRE,
1845 if (dev->rx_pkt_burst == hns3_recv_pkts ||
1846 dev->rx_pkt_burst == hns3_recv_scattered_pkts ||
1847 dev->rx_pkt_burst == hns3_recv_pkts_vec ||
1848 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve)
1855 hns3_init_rx_ptype_tble(struct rte_eth_dev *dev)
1857 struct hns3_adapter *hns = dev->data->dev_private;
1858 struct hns3_ptype_table *tbl = &hns->ptype_tbl;
1860 memset(tbl, 0, sizeof(*tbl));
1862 tbl->l2table[0] = RTE_PTYPE_L2_ETHER;
1863 tbl->l2table[1] = RTE_PTYPE_L2_ETHER_QINQ;
1864 tbl->l2table[2] = RTE_PTYPE_L2_ETHER_VLAN;
1865 tbl->l2table[3] = RTE_PTYPE_L2_ETHER_VLAN;
1867 tbl->l3table[0] = RTE_PTYPE_L3_IPV4;
1868 tbl->l3table[1] = RTE_PTYPE_L3_IPV6;
1869 tbl->l3table[2] = RTE_PTYPE_L2_ETHER_ARP;
1870 tbl->l3table[3] = RTE_PTYPE_L2_ETHER;
1871 tbl->l3table[4] = RTE_PTYPE_L3_IPV4_EXT;
1872 tbl->l3table[5] = RTE_PTYPE_L3_IPV6_EXT;
1873 tbl->l3table[6] = RTE_PTYPE_L2_ETHER_LLDP;
1875 tbl->l4table[0] = RTE_PTYPE_L4_UDP;
1876 tbl->l4table[1] = RTE_PTYPE_L4_TCP;
1877 tbl->l4table[2] = RTE_PTYPE_TUNNEL_GRE;
1878 tbl->l4table[3] = RTE_PTYPE_L4_SCTP;
1879 tbl->l4table[4] = RTE_PTYPE_L4_IGMP;
1880 tbl->l4table[5] = RTE_PTYPE_L4_ICMP;
1882 tbl->inner_l2table[0] = RTE_PTYPE_INNER_L2_ETHER;
1883 tbl->inner_l2table[1] = RTE_PTYPE_INNER_L2_ETHER_VLAN;
1884 tbl->inner_l2table[2] = RTE_PTYPE_INNER_L2_ETHER_QINQ;
1886 tbl->inner_l3table[0] = RTE_PTYPE_INNER_L3_IPV4;
1887 tbl->inner_l3table[1] = RTE_PTYPE_INNER_L3_IPV6;
1888 tbl->inner_l3table[2] = 0;
1889 tbl->inner_l3table[3] = RTE_PTYPE_INNER_L2_ETHER;
1890 tbl->inner_l3table[4] = RTE_PTYPE_INNER_L3_IPV4_EXT;
1891 tbl->inner_l3table[5] = RTE_PTYPE_INNER_L3_IPV6_EXT;
1893 tbl->inner_l4table[0] = RTE_PTYPE_INNER_L4_UDP;
1894 tbl->inner_l4table[1] = RTE_PTYPE_INNER_L4_TCP;
1895 tbl->inner_l4table[2] = RTE_PTYPE_TUNNEL_GRE;
1896 tbl->inner_l4table[3] = RTE_PTYPE_INNER_L4_SCTP;
1897 tbl->inner_l4table[4] = RTE_PTYPE_L4_IGMP;
1898 tbl->inner_l4table[5] = RTE_PTYPE_INNER_L4_ICMP;
1900 tbl->ol3table[0] = RTE_PTYPE_L3_IPV4;
1901 tbl->ol3table[1] = RTE_PTYPE_L3_IPV6;
1902 tbl->ol3table[2] = 0;
1903 tbl->ol3table[3] = 0;
1904 tbl->ol3table[4] = RTE_PTYPE_L3_IPV4_EXT;
1905 tbl->ol3table[5] = RTE_PTYPE_L3_IPV6_EXT;
1907 tbl->ol4table[0] = 0;
1908 tbl->ol4table[1] = RTE_PTYPE_TUNNEL_VXLAN;
1909 tbl->ol4table[2] = RTE_PTYPE_TUNNEL_NVGRE;
1913 hns3_rxd_to_vlan_tci(struct hns3_rx_queue *rxq, struct rte_mbuf *mb,
1914 uint32_t l234_info, const struct hns3_desc *rxd)
1916 #define HNS3_STRP_STATUS_NUM 0x4
1918 #define HNS3_NO_STRP_VLAN_VLD 0x0
1919 #define HNS3_INNER_STRP_VLAN_VLD 0x1
1920 #define HNS3_OUTER_STRP_VLAN_VLD 0x2
1921 uint32_t strip_status;
1922 uint32_t report_mode;
1925 * Since HW limitation, the vlan tag will always be inserted into RX
1926 * descriptor when strip the tag from packet, driver needs to determine
1927 * reporting which tag to mbuf according to the PVID configuration
1928 * and vlan striped status.
1930 static const uint32_t report_type[][HNS3_STRP_STATUS_NUM] = {
1932 HNS3_NO_STRP_VLAN_VLD,
1933 HNS3_OUTER_STRP_VLAN_VLD,
1934 HNS3_INNER_STRP_VLAN_VLD,
1935 HNS3_OUTER_STRP_VLAN_VLD
1938 HNS3_NO_STRP_VLAN_VLD,
1939 HNS3_NO_STRP_VLAN_VLD,
1940 HNS3_NO_STRP_VLAN_VLD,
1941 HNS3_INNER_STRP_VLAN_VLD
1944 strip_status = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,
1945 HNS3_RXD_STRP_TAGP_S);
1946 report_mode = report_type[rxq->pvid_sw_discard_en][strip_status];
1947 switch (report_mode) {
1948 case HNS3_NO_STRP_VLAN_VLD:
1951 case HNS3_INNER_STRP_VLAN_VLD:
1952 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1953 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.vlan_tag);
1955 case HNS3_OUTER_STRP_VLAN_VLD:
1956 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1957 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.ot_vlan_tag);
1966 recalculate_data_len(struct rte_mbuf *first_seg, struct rte_mbuf *last_seg,
1967 struct rte_mbuf *rxm, struct hns3_rx_queue *rxq,
1970 uint8_t crc_len = rxq->crc_len;
1972 if (data_len <= crc_len) {
1973 rte_pktmbuf_free_seg(rxm);
1974 first_seg->nb_segs--;
1975 last_seg->data_len = (uint16_t)(last_seg->data_len -
1976 (crc_len - data_len));
1977 last_seg->next = NULL;
1979 rxm->data_len = (uint16_t)(data_len - crc_len);
1982 static inline struct rte_mbuf *
1983 hns3_rx_alloc_buffer(struct hns3_rx_queue *rxq)
1987 if (likely(rxq->bulk_mbuf_num > 0))
1988 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
1990 ret = rte_mempool_get_bulk(rxq->mb_pool, (void **)rxq->bulk_mbuf,
1991 HNS3_BULK_ALLOC_MBUF_NUM);
1992 if (likely(ret == 0)) {
1993 rxq->bulk_mbuf_num = HNS3_BULK_ALLOC_MBUF_NUM;
1994 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
1996 return rte_mbuf_raw_alloc(rxq->mb_pool);
2000 hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2002 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
2003 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
2004 struct hns3_rx_queue *rxq; /* RX queue */
2005 struct hns3_entry *sw_ring;
2006 struct hns3_entry *rxe;
2007 struct hns3_desc rxd;
2008 struct rte_mbuf *nmb; /* pointer of the new mbuf */
2009 struct rte_mbuf *rxm;
2010 uint32_t bd_base_info;
2023 rx_ring = rxq->rx_ring;
2024 sw_ring = rxq->sw_ring;
2025 rx_id = rxq->next_to_use;
2027 while (nb_rx < nb_pkts) {
2028 rxdp = &rx_ring[rx_id];
2029 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
2030 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
2033 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2034 (1u << HNS3_RXD_VLD_B)];
2036 nmb = hns3_rx_alloc_buffer(rxq);
2037 if (unlikely(nmb == NULL)) {
2040 port_id = rxq->port_id;
2041 rte_eth_devices[port_id].data->rx_mbuf_alloc_failed++;
2046 rxe = &sw_ring[rx_id];
2048 if (unlikely(rx_id == rxq->nb_rx_desc))
2051 rte_prefetch0(sw_ring[rx_id].mbuf);
2052 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
2053 rte_prefetch0(&rx_ring[rx_id]);
2054 rte_prefetch0(&sw_ring[rx_id]);
2060 dma_addr = rte_mbuf_data_iova_default(nmb);
2061 rxdp->addr = rte_cpu_to_le_64(dma_addr);
2062 rxdp->rx.bd_base_info = 0;
2064 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2065 rxm->pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.pkt_len)) -
2067 rxm->data_len = rxm->pkt_len;
2068 rxm->port = rxq->port_id;
2069 rxm->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
2070 rxm->ol_flags = PKT_RX_RSS_HASH;
2071 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
2073 rte_le_to_cpu_16(rxd.rx.fd_id);
2074 rxm->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
2079 /* Load remained descriptor data and extract necessary fields */
2080 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
2081 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
2082 ret = hns3_handle_bdinfo(rxq, rxm, bd_base_info,
2083 l234_info, &cksum_err);
2087 rxm->packet_type = hns3_rx_calc_ptype(rxq, l234_info, ol_info);
2089 if (likely(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
2090 hns3_rx_set_cksum_flag(rxm, rxm->packet_type,
2092 hns3_rxd_to_vlan_tci(rxq, rxm, l234_info, &rxd);
2094 rx_pkts[nb_rx++] = rxm;
2097 rte_pktmbuf_free(rxm);
2100 rxq->next_to_use = rx_id;
2101 rxq->rx_free_hold += nb_rx_bd;
2102 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
2103 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
2104 rxq->rx_free_hold = 0;
2111 hns3_recv_scattered_pkts(void *rx_queue,
2112 struct rte_mbuf **rx_pkts,
2115 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
2116 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
2117 struct hns3_rx_queue *rxq; /* RX queue */
2118 struct hns3_entry *sw_ring;
2119 struct hns3_entry *rxe;
2120 struct rte_mbuf *first_seg;
2121 struct rte_mbuf *last_seg;
2122 struct hns3_desc rxd;
2123 struct rte_mbuf *nmb; /* pointer of the new mbuf */
2124 struct rte_mbuf *rxm;
2125 struct rte_eth_dev *dev;
2126 uint32_t bd_base_info;
2141 rx_id = rxq->next_to_use;
2142 rx_ring = rxq->rx_ring;
2143 sw_ring = rxq->sw_ring;
2144 first_seg = rxq->pkt_first_seg;
2145 last_seg = rxq->pkt_last_seg;
2147 while (nb_rx < nb_pkts) {
2148 rxdp = &rx_ring[rx_id];
2149 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
2150 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
2154 * The interactive process between software and hardware of
2155 * receiving a new packet in hns3 network engine:
2156 * 1. Hardware network engine firstly writes the packet content
2157 * to the memory pointed by the 'addr' field of the Rx Buffer
2158 * Descriptor, secondly fills the result of parsing the
2159 * packet include the valid field into the Rx Buffer
2160 * Descriptor in one write operation.
2161 * 2. Driver reads the Rx BD's valid field in the loop to check
2162 * whether it's valid, if valid then assign a new address to
2163 * the addr field, clear the valid field, get the other
2164 * information of the packet by parsing Rx BD's other fields,
2165 * finally write back the number of Rx BDs processed by the
2166 * driver to the HNS3_RING_RX_HEAD_REG register to inform
2168 * In the above process, the ordering is very important. We must
2169 * make sure that CPU read Rx BD's other fields only after the
2172 * There are two type of re-ordering: compiler re-ordering and
2173 * CPU re-ordering under the ARMv8 architecture.
2174 * 1. we use volatile to deal with compiler re-ordering, so you
2175 * can see that rx_ring/rxdp defined with volatile.
2176 * 2. we commonly use memory barrier to deal with CPU
2177 * re-ordering, but the cost is high.
2179 * In order to solve the high cost of using memory barrier, we
2180 * use the data dependency order under the ARMv8 architecture,
2183 * instr02: load B <- A
2184 * the instr02 will always execute after instr01.
2186 * To construct the data dependency ordering, we use the
2187 * following assignment:
2188 * rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2189 * (1u<<HNS3_RXD_VLD_B)]
2190 * Using gcc compiler under the ARMv8 architecture, the related
2191 * assembly code example as follows:
2192 * note: (1u << HNS3_RXD_VLD_B) equal 0x10
2193 * instr01: ldr w26, [x22, #28] --read bd_base_info
2194 * instr02: and w0, w26, #0x10 --calc bd_base_info & 0x10
2195 * instr03: sub w0, w0, #0x10 --calc (bd_base_info &
2197 * instr04: add x0, x22, x0, lsl #5 --calc copy source addr
2198 * instr05: ldp x2, x3, [x0]
2199 * instr06: stp x2, x3, [x29, #256] --copy BD's [0 ~ 15]B
2200 * instr07: ldp x4, x5, [x0, #16]
2201 * instr08: stp x4, x5, [x29, #272] --copy BD's [16 ~ 31]B
2202 * the instr05~08 depend on x0's value, x0 depent on w26's
2203 * value, the w26 is the bd_base_info, this form the data
2204 * dependency ordering.
2205 * note: if BD is valid, (bd_base_info & (1u<<HNS3_RXD_VLD_B)) -
2206 * (1u<<HNS3_RXD_VLD_B) will always zero, so the
2207 * assignment is correct.
2209 * So we use the data dependency ordering instead of memory
2210 * barrier to improve receive performance.
2212 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2213 (1u << HNS3_RXD_VLD_B)];
2215 nmb = hns3_rx_alloc_buffer(rxq);
2216 if (unlikely(nmb == NULL)) {
2217 dev = &rte_eth_devices[rxq->port_id];
2218 dev->data->rx_mbuf_alloc_failed++;
2223 rxe = &sw_ring[rx_id];
2225 if (unlikely(rx_id == rxq->nb_rx_desc))
2228 rte_prefetch0(sw_ring[rx_id].mbuf);
2229 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
2230 rte_prefetch0(&rx_ring[rx_id]);
2231 rte_prefetch0(&sw_ring[rx_id]);
2237 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2238 rxdp->rx.bd_base_info = 0;
2239 rxdp->addr = dma_addr;
2241 if (first_seg == NULL) {
2243 first_seg->nb_segs = 1;
2245 first_seg->nb_segs++;
2246 last_seg->next = rxm;
2249 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2250 rxm->data_len = rte_le_to_cpu_16(rxd.rx.size);
2252 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
2259 * The last buffer of the received packet. packet len from
2260 * buffer description may contains CRC len, packet len should
2261 * subtract it, same as data len.
2263 first_seg->pkt_len = rte_le_to_cpu_16(rxd.rx.pkt_len);
2266 * This is the last buffer of the received packet. If the CRC
2267 * is not stripped by the hardware:
2268 * - Subtract the CRC length from the total packet length.
2269 * - If the last buffer only contains the whole CRC or a part
2270 * of it, free the mbuf associated to the last buffer. If part
2271 * of the CRC is also contained in the previous mbuf, subtract
2272 * the length of that CRC part from the data length of the
2276 if (unlikely(rxq->crc_len > 0)) {
2277 first_seg->pkt_len -= rxq->crc_len;
2278 recalculate_data_len(first_seg, last_seg, rxm, rxq,
2282 first_seg->port = rxq->port_id;
2283 first_seg->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
2284 first_seg->ol_flags = PKT_RX_RSS_HASH;
2285 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
2286 first_seg->hash.fdir.hi =
2287 rte_le_to_cpu_16(rxd.rx.fd_id);
2288 first_seg->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
2291 gro_size = hns3_get_field(bd_base_info, HNS3_RXD_GRO_SIZE_M,
2292 HNS3_RXD_GRO_SIZE_S);
2293 if (gro_size != 0) {
2294 first_seg->ol_flags |= PKT_RX_LRO;
2295 first_seg->tso_segsz = gro_size;
2298 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
2299 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
2300 ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info,
2301 l234_info, &cksum_err);
2305 first_seg->packet_type = hns3_rx_calc_ptype(rxq,
2306 l234_info, ol_info);
2308 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B))
2309 hns3_rx_set_cksum_flag(first_seg,
2310 first_seg->packet_type,
2312 hns3_rxd_to_vlan_tci(rxq, first_seg, l234_info, &rxd);
2314 rx_pkts[nb_rx++] = first_seg;
2318 rte_pktmbuf_free(first_seg);
2322 rxq->next_to_use = rx_id;
2323 rxq->pkt_first_seg = first_seg;
2324 rxq->pkt_last_seg = last_seg;
2326 rxq->rx_free_hold += nb_rx_bd;
2327 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
2328 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
2329 rxq->rx_free_hold = 0;
2336 hns3_rxq_vec_setup(__rte_unused struct hns3_rx_queue *rxq)
2341 hns3_rx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
2347 hns3_recv_pkts_vec(__rte_unused void *tx_queue,
2348 __rte_unused struct rte_mbuf **rx_pkts,
2349 __rte_unused uint16_t nb_pkts)
2355 hns3_recv_pkts_vec_sve(__rte_unused void *tx_queue,
2356 __rte_unused struct rte_mbuf **rx_pkts,
2357 __rte_unused uint16_t nb_pkts)
2363 hns3_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2364 struct rte_eth_burst_mode *mode)
2366 static const struct {
2367 eth_rx_burst_t pkt_burst;
2370 { hns3_recv_pkts, "Scalar" },
2371 { hns3_recv_scattered_pkts, "Scalar Scattered" },
2372 { hns3_recv_pkts_vec, "Vector Neon" },
2373 { hns3_recv_pkts_vec_sve, "Vector Sve" },
2376 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2380 for (i = 0; i < RTE_DIM(burst_infos); i++) {
2381 if (pkt_burst == burst_infos[i].pkt_burst) {
2382 snprintf(mode->info, sizeof(mode->info), "%s",
2383 burst_infos[i].info);
2393 hns3_check_sve_support(void)
2395 #if defined(RTE_ARCH_ARM64) && defined(CC_SVE_SUPPORT)
2396 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE))
2402 static eth_rx_burst_t
2403 hns3_get_rx_function(struct rte_eth_dev *dev)
2405 struct hns3_adapter *hns = dev->data->dev_private;
2406 uint64_t offloads = dev->data->dev_conf.rxmode.offloads;
2408 if (hns->rx_vec_allowed && hns3_rx_check_vec_support(dev) == 0)
2409 return hns3_check_sve_support() ? hns3_recv_pkts_vec_sve :
2412 if (hns->rx_simple_allowed && !dev->data->scattered_rx &&
2413 (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0)
2414 return hns3_recv_pkts;
2416 return hns3_recv_scattered_pkts;
2420 hns3_tx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_txconf *conf,
2421 uint16_t nb_desc, uint16_t *tx_rs_thresh,
2422 uint16_t *tx_free_thresh, uint16_t idx)
2424 #define HNS3_TX_RS_FREE_THRESH_GAP 8
2425 uint16_t rs_thresh, free_thresh, fast_free_thresh;
2427 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
2428 nb_desc % HNS3_ALIGN_RING_DESC) {
2429 hns3_err(hw, "number (%u) of tx descriptors is invalid",
2434 rs_thresh = (conf->tx_rs_thresh > 0) ?
2435 conf->tx_rs_thresh : HNS3_DEFAULT_TX_RS_THRESH;
2436 free_thresh = (conf->tx_free_thresh > 0) ?
2437 conf->tx_free_thresh : HNS3_DEFAULT_TX_FREE_THRESH;
2438 if (rs_thresh + free_thresh > nb_desc || nb_desc % rs_thresh ||
2439 rs_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP ||
2440 free_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP) {
2441 hns3_err(hw, "tx_rs_thresh (%d) tx_free_thresh (%d) nb_desc "
2442 "(%d) of tx descriptors for port=%d queue=%d check "
2444 rs_thresh, free_thresh, nb_desc, hw->data->port_id,
2449 if (conf->tx_free_thresh == 0) {
2450 /* Fast free Tx memory buffer to improve cache hit rate */
2451 fast_free_thresh = nb_desc - rs_thresh;
2452 if (fast_free_thresh >=
2453 HNS3_TX_FAST_FREE_AHEAD + HNS3_DEFAULT_TX_FREE_THRESH)
2454 free_thresh = fast_free_thresh -
2455 HNS3_TX_FAST_FREE_AHEAD;
2458 *tx_rs_thresh = rs_thresh;
2459 *tx_free_thresh = free_thresh;
2464 hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
2465 unsigned int socket_id, const struct rte_eth_txconf *conf)
2467 struct hns3_adapter *hns = dev->data->dev_private;
2468 uint16_t tx_rs_thresh, tx_free_thresh;
2469 struct hns3_hw *hw = &hns->hw;
2470 struct hns3_queue_info q_info;
2471 struct hns3_tx_queue *txq;
2475 ret = hns3_tx_queue_conf_check(hw, conf, nb_desc,
2476 &tx_rs_thresh, &tx_free_thresh, idx);
2480 if (dev->data->tx_queues[idx] != NULL) {
2481 hns3_tx_queue_release(dev->data->tx_queues[idx]);
2482 dev->data->tx_queues[idx] = NULL;
2486 q_info.socket_id = socket_id;
2487 q_info.nb_desc = nb_desc;
2488 q_info.type = "hns3 TX queue";
2489 q_info.ring_name = "tx_ring";
2490 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
2493 "Failed to alloc mem and reserve DMA mem for tx ring!");
2497 txq->tx_deferred_start = conf->tx_deferred_start;
2498 if (txq->tx_deferred_start && !hns3_dev_indep_txrx_supported(hw)) {
2499 hns3_warn(hw, "deferred start is not supported.");
2500 txq->tx_deferred_start = false;
2503 tx_entry_len = sizeof(struct hns3_entry) * txq->nb_tx_desc;
2504 txq->sw_ring = rte_zmalloc_socket("hns3 TX sw ring", tx_entry_len,
2505 RTE_CACHE_LINE_SIZE, socket_id);
2506 if (txq->sw_ring == NULL) {
2507 hns3_err(hw, "Failed to allocate memory for tx sw ring!");
2508 hns3_tx_queue_release(txq);
2513 txq->next_to_use = 0;
2514 txq->next_to_clean = 0;
2515 txq->tx_bd_ready = txq->nb_tx_desc - 1;
2516 txq->tx_free_thresh = tx_free_thresh;
2517 txq->tx_rs_thresh = tx_rs_thresh;
2518 txq->free = rte_zmalloc_socket("hns3 TX mbuf free array",
2519 sizeof(struct rte_mbuf *) * txq->tx_rs_thresh,
2520 RTE_CACHE_LINE_SIZE, socket_id);
2522 hns3_err(hw, "failed to allocate tx mbuf free array!");
2523 hns3_tx_queue_release(txq);
2527 txq->port_id = dev->data->port_id;
2529 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
2530 * the pvid_sw_shift_en in the queue struct should not be changed,
2531 * because PVID-related operations do not need to be processed by PMD
2532 * driver. For hns3 VF device, whether it needs to process PVID depends
2533 * on the configuration of PF kernel mode netdev driver. And the
2534 * related PF configuration is delivered through the mailbox and finally
2535 * reflectd in port_base_vlan_cfg.
2537 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
2538 txq->pvid_sw_shift_en = hw->port_base_vlan_cfg.state ==
2539 HNS3_PORT_BASE_VLAN_ENABLE;
2541 txq->pvid_sw_shift_en = false;
2542 txq->max_non_tso_bd_num = hw->max_non_tso_bd_num;
2543 txq->configured = true;
2544 txq->io_base = (void *)((char *)hw->io_base +
2545 hns3_get_tqp_reg_offset(idx));
2546 txq->io_tail_reg = (volatile void *)((char *)txq->io_base +
2547 HNS3_RING_TX_TAIL_REG);
2548 txq->min_tx_pkt_len = hw->min_tx_pkt_len;
2549 txq->tso_mode = hw->tso_mode;
2550 txq->over_length_pkt_cnt = 0;
2551 txq->exceed_limit_bd_pkt_cnt = 0;
2552 txq->exceed_limit_bd_reassem_fail = 0;
2553 txq->unsupported_tunnel_pkt_cnt = 0;
2554 txq->queue_full_cnt = 0;
2555 txq->pkt_padding_fail_cnt = 0;
2556 rte_spinlock_lock(&hw->lock);
2557 dev->data->tx_queues[idx] = txq;
2558 rte_spinlock_unlock(&hw->lock);
2564 hns3_tx_free_useless_buffer(struct hns3_tx_queue *txq)
2566 uint16_t tx_next_clean = txq->next_to_clean;
2567 uint16_t tx_next_use = txq->next_to_use;
2568 uint16_t tx_bd_ready = txq->tx_bd_ready;
2569 uint16_t tx_bd_max = txq->nb_tx_desc;
2570 struct hns3_entry *tx_bak_pkt = &txq->sw_ring[tx_next_clean];
2571 struct hns3_desc *desc = &txq->tx_ring[tx_next_clean];
2572 struct rte_mbuf *mbuf;
2574 while ((!(desc->tx.tp_fe_sc_vld_ra_ri &
2575 rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)))) &&
2576 tx_next_use != tx_next_clean) {
2577 mbuf = tx_bak_pkt->mbuf;
2579 rte_pktmbuf_free_seg(mbuf);
2580 tx_bak_pkt->mbuf = NULL;
2588 if (tx_next_clean >= tx_bd_max) {
2590 desc = txq->tx_ring;
2591 tx_bak_pkt = txq->sw_ring;
2595 txq->next_to_clean = tx_next_clean;
2596 txq->tx_bd_ready = tx_bd_ready;
2600 hns3_tso_proc_tunnel(struct hns3_desc *desc, uint64_t ol_flags,
2601 struct rte_mbuf *rxm, uint8_t *l2_len)
2607 tun_flags = ol_flags & PKT_TX_TUNNEL_MASK;
2611 otmp = rte_le_to_cpu_32(desc->tx.ol_type_vlan_len_msec);
2612 switch (tun_flags) {
2613 case PKT_TX_TUNNEL_GENEVE:
2614 case PKT_TX_TUNNEL_VXLAN:
2615 *l2_len = rxm->l2_len - RTE_ETHER_VXLAN_HLEN;
2617 case PKT_TX_TUNNEL_GRE:
2619 * OL4 header size, defined in 4 Bytes, it contains outer
2620 * L4(GRE) length and tunneling length.
2622 ol4_len = hns3_get_field(otmp, HNS3_TXD_L4LEN_M,
2624 *l2_len = rxm->l2_len - (ol4_len << HNS3_L4_LEN_UNIT);
2627 /* For non UDP / GRE tunneling, drop the tunnel packet */
2630 hns3_set_field(otmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2631 rxm->outer_l2_len >> HNS3_L2_LEN_UNIT);
2632 desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(otmp);
2638 hns3_config_gro(struct hns3_hw *hw, bool en)
2640 struct hns3_cfg_gro_status_cmd *req;
2641 struct hns3_cmd_desc desc;
2644 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
2645 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
2647 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
2649 ret = hns3_cmd_send(hw, &desc, 1);
2651 hns3_err(hw, "%s hardware GRO failed, ret = %d",
2652 en ? "enable" : "disable", ret);
2658 hns3_restore_gro_conf(struct hns3_hw *hw)
2664 offloads = hw->data->dev_conf.rxmode.offloads;
2665 gro_en = offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2666 ret = hns3_config_gro(hw, gro_en);
2668 hns3_err(hw, "restore hardware GRO to %s failed, ret = %d",
2669 gro_en ? "enabled" : "disabled", ret);
2675 hns3_pkt_is_tso(struct rte_mbuf *m)
2677 return (m->tso_segsz != 0 && m->ol_flags & PKT_TX_TCP_SEG);
2681 hns3_set_tso(struct hns3_desc *desc, uint64_t ol_flags,
2682 uint32_t paylen, struct rte_mbuf *rxm)
2684 uint8_t l2_len = rxm->l2_len;
2687 if (!hns3_pkt_is_tso(rxm))
2690 if (hns3_tso_proc_tunnel(desc, ol_flags, rxm, &l2_len))
2693 if (paylen <= rxm->tso_segsz)
2696 tmp = rte_le_to_cpu_32(desc->tx.type_cs_vlan_tso_len);
2697 hns3_set_bit(tmp, HNS3_TXD_TSO_B, 1);
2698 hns3_set_bit(tmp, HNS3_TXD_L3CS_B, 1);
2699 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S, HNS3_L4T_TCP);
2700 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
2701 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2702 sizeof(struct rte_tcp_hdr) >> HNS3_L4_LEN_UNIT);
2703 hns3_set_field(tmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2704 l2_len >> HNS3_L2_LEN_UNIT);
2705 desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp);
2706 desc->tx.mss = rte_cpu_to_le_16(rxm->tso_segsz);
2710 hns3_fill_per_desc(struct hns3_desc *desc, struct rte_mbuf *rxm)
2712 desc->addr = rte_mbuf_data_iova(rxm);
2713 desc->tx.send_size = rte_cpu_to_le_16(rte_pktmbuf_data_len(rxm));
2714 desc->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B));
2718 hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc,
2719 struct rte_mbuf *rxm)
2721 uint64_t ol_flags = rxm->ol_flags;
2725 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len;
2726 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
2727 rxm->outer_l2_len + rxm->outer_l3_len : 0;
2728 paylen = rxm->pkt_len - hdr_len;
2729 desc->tx.paylen = rte_cpu_to_le_32(paylen);
2730 hns3_set_tso(desc, ol_flags, paylen, rxm);
2733 * Currently, hardware doesn't support more than two layers VLAN offload
2734 * in Tx direction based on hns3 network engine. So when the number of
2735 * VLANs in the packets represented by rxm plus the number of VLAN
2736 * offload by hardware such as PVID etc, exceeds two, the packets will
2737 * be discarded or the original VLAN of the packets will be overwitted
2738 * by hardware. When the PF PVID is enabled by calling the API function
2739 * named rte_eth_dev_set_vlan_pvid or the VF PVID is enabled by the hns3
2740 * PF kernel ether driver, the outer VLAN tag will always be the PVID.
2741 * To avoid the VLAN of Tx descriptor is overwritten by PVID, it should
2742 * be added to the position close to the IP header when PVID is enabled.
2744 if (!txq->pvid_sw_shift_en && ol_flags & (PKT_TX_VLAN_PKT |
2746 desc->tx.ol_type_vlan_len_msec |=
2747 rte_cpu_to_le_32(BIT(HNS3_TXD_OVLAN_B));
2748 if (ol_flags & PKT_TX_QINQ_PKT)
2749 desc->tx.outer_vlan_tag =
2750 rte_cpu_to_le_16(rxm->vlan_tci_outer);
2752 desc->tx.outer_vlan_tag =
2753 rte_cpu_to_le_16(rxm->vlan_tci);
2756 if (ol_flags & PKT_TX_QINQ_PKT ||
2757 ((ol_flags & PKT_TX_VLAN_PKT) && txq->pvid_sw_shift_en)) {
2758 desc->tx.type_cs_vlan_tso_len |=
2759 rte_cpu_to_le_32(BIT(HNS3_TXD_VLAN_B));
2760 desc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci);
2765 hns3_tx_alloc_mbufs(struct rte_mempool *mb_pool, uint16_t nb_new_buf,
2766 struct rte_mbuf **alloc_mbuf)
2768 #define MAX_NON_TSO_BD_PER_PKT 18
2769 struct rte_mbuf *pkt_segs[MAX_NON_TSO_BD_PER_PKT];
2772 /* Allocate enough mbufs */
2773 if (rte_mempool_get_bulk(mb_pool, (void **)pkt_segs, nb_new_buf))
2776 for (i = 0; i < nb_new_buf - 1; i++)
2777 pkt_segs[i]->next = pkt_segs[i + 1];
2779 pkt_segs[nb_new_buf - 1]->next = NULL;
2780 pkt_segs[0]->nb_segs = nb_new_buf;
2781 *alloc_mbuf = pkt_segs[0];
2787 hns3_pktmbuf_copy_hdr(struct rte_mbuf *new_pkt, struct rte_mbuf *old_pkt)
2789 new_pkt->ol_flags = old_pkt->ol_flags;
2790 new_pkt->pkt_len = rte_pktmbuf_pkt_len(old_pkt);
2791 new_pkt->outer_l2_len = old_pkt->outer_l2_len;
2792 new_pkt->outer_l3_len = old_pkt->outer_l3_len;
2793 new_pkt->l2_len = old_pkt->l2_len;
2794 new_pkt->l3_len = old_pkt->l3_len;
2795 new_pkt->l4_len = old_pkt->l4_len;
2796 new_pkt->vlan_tci_outer = old_pkt->vlan_tci_outer;
2797 new_pkt->vlan_tci = old_pkt->vlan_tci;
2801 hns3_reassemble_tx_pkts(struct rte_mbuf *tx_pkt, struct rte_mbuf **new_pkt,
2802 uint8_t max_non_tso_bd_num)
2804 struct rte_mempool *mb_pool;
2805 struct rte_mbuf *new_mbuf;
2806 struct rte_mbuf *temp_new;
2807 struct rte_mbuf *temp;
2808 uint16_t last_buf_len;
2809 uint16_t nb_new_buf;
2819 mb_pool = tx_pkt->pool;
2820 buf_size = tx_pkt->buf_len - RTE_PKTMBUF_HEADROOM;
2821 nb_new_buf = (rte_pktmbuf_pkt_len(tx_pkt) - 1) / buf_size + 1;
2822 if (nb_new_buf > max_non_tso_bd_num)
2825 last_buf_len = rte_pktmbuf_pkt_len(tx_pkt) % buf_size;
2826 if (last_buf_len == 0)
2827 last_buf_len = buf_size;
2829 /* Allocate enough mbufs */
2830 ret = hns3_tx_alloc_mbufs(mb_pool, nb_new_buf, &new_mbuf);
2834 /* Copy the original packet content to the new mbufs */
2836 s = rte_pktmbuf_mtod(temp, char *);
2837 len_s = rte_pktmbuf_data_len(temp);
2838 temp_new = new_mbuf;
2839 while (temp != NULL && temp_new != NULL) {
2840 d = rte_pktmbuf_mtod(temp_new, char *);
2841 buf_len = temp_new->next == NULL ? last_buf_len : buf_size;
2845 len = RTE_MIN(len_s, len_d);
2849 len_d = len_d - len;
2850 len_s = len_s - len;
2856 s = rte_pktmbuf_mtod(temp, char *);
2857 len_s = rte_pktmbuf_data_len(temp);
2861 temp_new->data_len = buf_len;
2862 temp_new = temp_new->next;
2864 hns3_pktmbuf_copy_hdr(new_mbuf, tx_pkt);
2866 /* free original mbufs */
2867 rte_pktmbuf_free(tx_pkt);
2869 *new_pkt = new_mbuf;
2875 hns3_parse_outer_params(uint64_t ol_flags, uint32_t *ol_type_vlan_len_msec)
2877 uint32_t tmp = *ol_type_vlan_len_msec;
2879 /* (outer) IP header type */
2880 if (ol_flags & PKT_TX_OUTER_IPV4) {
2881 /* OL3 header size, defined in 4 bytes */
2882 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2883 sizeof(struct rte_ipv4_hdr) >> HNS3_L3_LEN_UNIT);
2884 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2885 hns3_set_field(tmp, HNS3_TXD_OL3T_M,
2886 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_CSUM);
2888 hns3_set_field(tmp, HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
2889 HNS3_OL3T_IPV4_NO_CSUM);
2890 } else if (ol_flags & PKT_TX_OUTER_IPV6) {
2891 hns3_set_field(tmp, HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
2893 /* OL3 header size, defined in 4 bytes */
2894 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2895 sizeof(struct rte_ipv6_hdr) >> HNS3_L3_LEN_UNIT);
2898 *ol_type_vlan_len_msec = tmp;
2902 hns3_parse_inner_params(uint64_t ol_flags, uint32_t *ol_type_vlan_len_msec,
2903 struct rte_net_hdr_lens *hdr_lens)
2905 uint32_t tmp = *ol_type_vlan_len_msec;
2908 /* OL2 header size, defined in 2 bytes */
2909 hns3_set_field(tmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
2910 sizeof(struct rte_ether_hdr) >> HNS3_L2_LEN_UNIT);
2912 /* L4TUNT: L4 Tunneling Type */
2913 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2914 case PKT_TX_TUNNEL_GENEVE:
2915 case PKT_TX_TUNNEL_VXLAN:
2916 /* MAC in UDP tunnelling packet, include VxLAN */
2917 hns3_set_field(tmp, HNS3_TXD_TUNTYPE_M, HNS3_TXD_TUNTYPE_S,
2918 HNS3_TUN_MAC_IN_UDP);
2920 * OL4 header size, defined in 4 Bytes, it contains outer
2921 * L4(UDP) length and tunneling length.
2923 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2924 (uint8_t)RTE_ETHER_VXLAN_HLEN >>
2927 case PKT_TX_TUNNEL_GRE:
2928 hns3_set_field(tmp, HNS3_TXD_TUNTYPE_M, HNS3_TXD_TUNTYPE_S,
2931 * OL4 header size, defined in 4 Bytes, it contains outer
2932 * L4(GRE) length and tunneling length.
2934 l4_len = hdr_lens->l4_len + hdr_lens->tunnel_len;
2935 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
2936 l4_len >> HNS3_L4_LEN_UNIT);
2939 /* For non UDP / GRE tunneling, drop the tunnel packet */
2943 *ol_type_vlan_len_msec = tmp;
2949 hns3_parse_tunneling_params(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
2951 struct rte_net_hdr_lens *hdr_lens)
2953 struct hns3_desc *tx_ring = txq->tx_ring;
2954 struct hns3_desc *desc = &tx_ring[tx_desc_id];
2958 hns3_parse_outer_params(ol_flags, &value);
2959 ret = hns3_parse_inner_params(ol_flags, &value, hdr_lens);
2963 desc->tx.ol_type_vlan_len_msec |= rte_cpu_to_le_32(value);
2969 hns3_parse_l3_cksum_params(uint64_t ol_flags, uint32_t *type_cs_vlan_tso_len)
2973 /* Enable L3 checksum offloads */
2974 if (ol_flags & PKT_TX_IPV4) {
2975 tmp = *type_cs_vlan_tso_len;
2976 hns3_set_field(tmp, HNS3_TXD_L3T_M, HNS3_TXD_L3T_S,
2978 /* inner(/normal) L3 header size, defined in 4 bytes */
2979 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2980 sizeof(struct rte_ipv4_hdr) >> HNS3_L3_LEN_UNIT);
2981 if (ol_flags & PKT_TX_IP_CKSUM)
2982 hns3_set_bit(tmp, HNS3_TXD_L3CS_B, 1);
2983 *type_cs_vlan_tso_len = tmp;
2984 } else if (ol_flags & PKT_TX_IPV6) {
2985 tmp = *type_cs_vlan_tso_len;
2986 /* L3T, IPv6 don't do checksum */
2987 hns3_set_field(tmp, HNS3_TXD_L3T_M, HNS3_TXD_L3T_S,
2989 /* inner(/normal) L3 header size, defined in 4 bytes */
2990 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
2991 sizeof(struct rte_ipv6_hdr) >> HNS3_L3_LEN_UNIT);
2992 *type_cs_vlan_tso_len = tmp;
2997 hns3_parse_l4_cksum_params(uint64_t ol_flags, uint32_t *type_cs_vlan_tso_len)
3001 /* Enable L4 checksum offloads */
3002 switch (ol_flags & PKT_TX_L4_MASK) {
3003 case PKT_TX_TCP_CKSUM:
3004 tmp = *type_cs_vlan_tso_len;
3005 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3007 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
3008 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
3009 sizeof(struct rte_tcp_hdr) >> HNS3_L4_LEN_UNIT);
3010 *type_cs_vlan_tso_len = tmp;
3012 case PKT_TX_UDP_CKSUM:
3013 tmp = *type_cs_vlan_tso_len;
3014 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3016 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
3017 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
3018 sizeof(struct rte_udp_hdr) >> HNS3_L4_LEN_UNIT);
3019 *type_cs_vlan_tso_len = tmp;
3021 case PKT_TX_SCTP_CKSUM:
3022 tmp = *type_cs_vlan_tso_len;
3023 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3025 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
3026 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
3027 sizeof(struct rte_sctp_hdr) >> HNS3_L4_LEN_UNIT);
3028 *type_cs_vlan_tso_len = tmp;
3036 hns3_txd_enable_checksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
3039 struct hns3_desc *tx_ring = txq->tx_ring;
3040 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3043 /* inner(/normal) L2 header size, defined in 2 bytes */
3044 hns3_set_field(value, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
3045 sizeof(struct rte_ether_hdr) >> HNS3_L2_LEN_UNIT);
3047 hns3_parse_l3_cksum_params(ol_flags, &value);
3048 hns3_parse_l4_cksum_params(ol_flags, &value);
3050 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(value);
3054 hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num,
3055 uint32_t max_non_tso_bd_num)
3057 struct rte_mbuf *m_first = tx_pkts;
3058 struct rte_mbuf *m_last = tx_pkts;
3059 uint32_t tot_len = 0;
3064 * Hardware requires that the sum of the data length of every 8
3065 * consecutive buffers is greater than MSS in hns3 network engine.
3066 * We simplify it by ensuring pkt_headlen + the first 8 consecutive
3067 * frags greater than gso header len + mss, and the remaining 7
3068 * consecutive frags greater than MSS except the last 7 frags.
3070 if (bd_num <= max_non_tso_bd_num)
3073 for (i = 0; m_last && i < max_non_tso_bd_num - 1;
3074 i++, m_last = m_last->next)
3075 tot_len += m_last->data_len;
3080 /* ensure the first 8 frags is greater than mss + header */
3081 hdr_len = tx_pkts->l2_len + tx_pkts->l3_len + tx_pkts->l4_len;
3082 hdr_len += (tx_pkts->ol_flags & PKT_TX_TUNNEL_MASK) ?
3083 tx_pkts->outer_l2_len + tx_pkts->outer_l3_len : 0;
3084 if (tot_len + m_last->data_len < tx_pkts->tso_segsz + hdr_len)
3088 * ensure the sum of the data length of every 7 consecutive buffer
3089 * is greater than mss except the last one.
3091 for (i = 0; m_last && i < bd_num - max_non_tso_bd_num; i++) {
3092 tot_len -= m_first->data_len;
3093 tot_len += m_last->data_len;
3095 if (tot_len < tx_pkts->tso_segsz)
3098 m_first = m_first->next;
3099 m_last = m_last->next;
3106 hns3_outer_header_cksum_prepare(struct rte_mbuf *m)
3108 uint64_t ol_flags = m->ol_flags;
3109 struct rte_ipv4_hdr *ipv4_hdr;
3110 struct rte_udp_hdr *udp_hdr;
3111 uint32_t paylen, hdr_len;
3113 if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6)))
3116 if (ol_flags & PKT_TX_IPV4) {
3117 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
3120 if (ol_flags & PKT_TX_IP_CKSUM)
3121 ipv4_hdr->hdr_checksum = 0;
3124 if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_UDP_CKSUM &&
3125 ol_flags & PKT_TX_TCP_SEG) {
3126 hdr_len = m->l2_len + m->l3_len + m->l4_len;
3127 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
3128 m->outer_l2_len + m->outer_l3_len : 0;
3129 paylen = m->pkt_len - hdr_len;
3130 if (paylen <= m->tso_segsz)
3132 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3135 udp_hdr->dgram_cksum = 0;
3140 hns3_check_tso_pkt_valid(struct rte_mbuf *m)
3142 uint32_t tmp_data_len_sum = 0;
3143 uint16_t nb_buf = m->nb_segs;
3144 uint32_t paylen, hdr_len;
3145 struct rte_mbuf *m_seg;
3148 if (nb_buf > HNS3_MAX_TSO_BD_PER_PKT)
3151 hdr_len = m->l2_len + m->l3_len + m->l4_len;
3152 hdr_len += (m->ol_flags & PKT_TX_TUNNEL_MASK) ?
3153 m->outer_l2_len + m->outer_l3_len : 0;
3154 if (hdr_len > HNS3_MAX_TSO_HDR_SIZE)
3157 paylen = m->pkt_len - hdr_len;
3158 if (paylen > HNS3_MAX_BD_PAYLEN)
3162 * The TSO header (include outer and inner L2, L3 and L4 header)
3163 * should be provided by three descriptors in maximum in hns3 network
3167 for (i = 0; m_seg != NULL && i < HNS3_MAX_TSO_HDR_BD_NUM && i < nb_buf;
3168 i++, m_seg = m_seg->next) {
3169 tmp_data_len_sum += m_seg->data_len;
3172 if (hdr_len > tmp_data_len_sum)
3178 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3180 hns3_vld_vlan_chk(struct hns3_tx_queue *txq, struct rte_mbuf *m)
3182 struct rte_ether_hdr *eh;
3183 struct rte_vlan_hdr *vh;
3185 if (!txq->pvid_sw_shift_en)
3189 * Due to hardware limitations, we only support two-layer VLAN hardware
3190 * offload in Tx direction based on hns3 network engine, so when PVID is
3191 * enabled, QinQ insert is no longer supported.
3192 * And when PVID is enabled, in the following two cases:
3193 * i) packets with more than two VLAN tags.
3194 * ii) packets with one VLAN tag while the hardware VLAN insert is
3196 * The packets will be regarded as abnormal packets and discarded by
3197 * hardware in Tx direction. For debugging purposes, a validation check
3198 * for these types of packets is added to the '.tx_pkt_prepare' ops
3199 * implementation function named hns3_prep_pkts to inform users that
3200 * these packets will be discarded.
3202 if (m->ol_flags & PKT_TX_QINQ_PKT)
3205 eh = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
3206 if (eh->ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
3207 if (m->ol_flags & PKT_TX_VLAN_PKT)
3210 /* Ensure the incoming packet is not a QinQ packet */
3211 vh = (struct rte_vlan_hdr *)(eh + 1);
3212 if (vh->eth_proto == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN))
3221 hns3_prep_pkt_proc(struct hns3_tx_queue *tx_queue, struct rte_mbuf *m)
3225 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3226 ret = rte_validate_tx_offload(m);
3232 ret = hns3_vld_vlan_chk(tx_queue, m);
3238 if (hns3_pkt_is_tso(m)) {
3239 if (hns3_pkt_need_linearized(m, m->nb_segs,
3240 tx_queue->max_non_tso_bd_num) ||
3241 hns3_check_tso_pkt_valid(m)) {
3246 if (tx_queue->tso_mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) {
3248 * (tso mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) means
3249 * hardware support recalculate the TCP pseudo header
3250 * checksum of packets that need TSO, so network driver
3251 * software not need to recalculate it.
3253 hns3_outer_header_cksum_prepare(m);
3258 ret = rte_net_intel_cksum_prepare(m);
3264 hns3_outer_header_cksum_prepare(m);
3270 hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3276 for (i = 0; i < nb_pkts; i++) {
3278 if (hns3_prep_pkt_proc(tx_queue, m))
3286 hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
3287 const struct rte_mbuf *m, struct rte_net_hdr_lens *hdr_lens)
3289 /* Fill in tunneling parameters if necessary */
3290 if (m->ol_flags & PKT_TX_TUNNEL_MASK) {
3291 (void)rte_net_get_ptype(m, hdr_lens, RTE_PTYPE_ALL_MASK);
3292 if (hns3_parse_tunneling_params(txq, tx_desc_id, m->ol_flags,
3294 txq->unsupported_tunnel_pkt_cnt++;
3298 /* Enable checksum offloading */
3299 if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK)
3300 hns3_txd_enable_checksum(txq, tx_desc_id, m->ol_flags);
3306 hns3_check_non_tso_pkt(uint16_t nb_buf, struct rte_mbuf **m_seg,
3307 struct rte_mbuf *tx_pkt, struct hns3_tx_queue *txq)
3309 uint8_t max_non_tso_bd_num;
3310 struct rte_mbuf *new_pkt;
3313 if (hns3_pkt_is_tso(*m_seg))
3317 * If packet length is greater than HNS3_MAX_FRAME_LEN
3318 * driver support, the packet will be ignored.
3320 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) > HNS3_MAX_FRAME_LEN)) {
3321 txq->over_length_pkt_cnt++;
3325 max_non_tso_bd_num = txq->max_non_tso_bd_num;
3326 if (unlikely(nb_buf > max_non_tso_bd_num)) {
3327 txq->exceed_limit_bd_pkt_cnt++;
3328 ret = hns3_reassemble_tx_pkts(tx_pkt, &new_pkt,
3329 max_non_tso_bd_num);
3331 txq->exceed_limit_bd_reassem_fail++;
3341 hns3_tx_free_buffer_simple(struct hns3_tx_queue *txq)
3343 struct hns3_entry *tx_entry;
3344 struct hns3_desc *desc;
3345 uint16_t tx_next_clean;
3349 if (HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) < txq->tx_rs_thresh)
3353 * All mbufs can be released only when the VLD bits of all
3354 * descriptors in a batch are cleared.
3356 tx_next_clean = (txq->next_to_clean + txq->tx_rs_thresh - 1) %
3358 desc = &txq->tx_ring[tx_next_clean];
3359 for (i = 0; i < txq->tx_rs_thresh; i++) {
3360 if (rte_le_to_cpu_16(desc->tx.tp_fe_sc_vld_ra_ri) &
3361 BIT(HNS3_TXD_VLD_B))
3366 tx_entry = &txq->sw_ring[txq->next_to_clean];
3368 for (i = 0; i < txq->tx_rs_thresh; i++)
3369 rte_prefetch0((tx_entry + i)->mbuf);
3370 for (i = 0; i < txq->tx_rs_thresh; i++, tx_entry++) {
3371 rte_mempool_put(tx_entry->mbuf->pool, tx_entry->mbuf);
3372 tx_entry->mbuf = NULL;
3375 txq->next_to_clean = (tx_next_clean + 1) % txq->nb_tx_desc;
3376 txq->tx_bd_ready += txq->tx_rs_thresh;
3381 hns3_tx_backup_1mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
3383 tx_entry->mbuf = pkts[0];
3387 hns3_tx_backup_4mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
3389 hns3_tx_backup_1mbuf(&tx_entry[0], &pkts[0]);
3390 hns3_tx_backup_1mbuf(&tx_entry[1], &pkts[1]);
3391 hns3_tx_backup_1mbuf(&tx_entry[2], &pkts[2]);
3392 hns3_tx_backup_1mbuf(&tx_entry[3], &pkts[3]);
3396 hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
3398 #define PER_LOOP_NUM 4
3399 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
3403 for (i = 0; i < PER_LOOP_NUM; i++, txdp++, pkts++) {
3404 dma_addr = rte_mbuf_data_iova(*pkts);
3405 txdp->addr = rte_cpu_to_le_64(dma_addr);
3406 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
3407 txdp->tx.paylen = 0;
3408 txdp->tx.type_cs_vlan_tso_len = 0;
3409 txdp->tx.ol_type_vlan_len_msec = 0;
3410 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
3415 hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
3417 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
3420 dma_addr = rte_mbuf_data_iova(*pkts);
3421 txdp->addr = rte_cpu_to_le_64(dma_addr);
3422 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
3423 txdp->tx.paylen = 0;
3424 txdp->tx.type_cs_vlan_tso_len = 0;
3425 txdp->tx.ol_type_vlan_len_msec = 0;
3426 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
3430 hns3_tx_fill_hw_ring(struct hns3_tx_queue *txq,
3431 struct rte_mbuf **pkts,
3434 #define PER_LOOP_NUM 4
3435 #define PER_LOOP_MASK (PER_LOOP_NUM - 1)
3436 struct hns3_desc *txdp = &txq->tx_ring[txq->next_to_use];
3437 struct hns3_entry *tx_entry = &txq->sw_ring[txq->next_to_use];
3438 const uint32_t mainpart = (nb_pkts & ((uint32_t)~PER_LOOP_MASK));
3439 const uint32_t leftover = (nb_pkts & ((uint32_t)PER_LOOP_MASK));
3442 for (i = 0; i < mainpart; i += PER_LOOP_NUM) {
3443 hns3_tx_backup_4mbuf(tx_entry + i, pkts + i);
3444 hns3_tx_setup_4bd(txdp + i, pkts + i);
3446 if (unlikely(leftover > 0)) {
3447 for (i = 0; i < leftover; i++) {
3448 hns3_tx_backup_1mbuf(tx_entry + mainpart + i,
3449 pkts + mainpart + i);
3450 hns3_tx_setup_1bd(txdp + mainpart + i,
3451 pkts + mainpart + i);
3457 hns3_xmit_pkts_simple(void *tx_queue,
3458 struct rte_mbuf **tx_pkts,
3461 struct hns3_tx_queue *txq = tx_queue;
3464 hns3_tx_free_buffer_simple(txq);
3466 nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts);
3467 if (unlikely(nb_pkts == 0)) {
3468 if (txq->tx_bd_ready == 0)
3469 txq->queue_full_cnt++;
3473 txq->tx_bd_ready -= nb_pkts;
3474 if (txq->next_to_use + nb_pkts > txq->nb_tx_desc) {
3475 nb_tx = txq->nb_tx_desc - txq->next_to_use;
3476 hns3_tx_fill_hw_ring(txq, tx_pkts, nb_tx);
3477 txq->next_to_use = 0;
3480 hns3_tx_fill_hw_ring(txq, tx_pkts + nb_tx, nb_pkts - nb_tx);
3481 txq->next_to_use += nb_pkts - nb_tx;
3483 hns3_write_reg_opt(txq->io_tail_reg, nb_pkts);
3489 hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
3491 struct rte_net_hdr_lens hdr_lens = {0};
3492 struct hns3_tx_queue *txq = tx_queue;
3493 struct hns3_entry *tx_bak_pkt;
3494 struct hns3_desc *tx_ring;
3495 struct rte_mbuf *tx_pkt;
3496 struct rte_mbuf *m_seg;
3497 struct hns3_desc *desc;
3498 uint32_t nb_hold = 0;
3499 uint16_t tx_next_use;
3500 uint16_t tx_pkt_num;
3506 /* free useless buffer */
3507 hns3_tx_free_useless_buffer(txq);
3509 tx_next_use = txq->next_to_use;
3510 tx_bd_max = txq->nb_tx_desc;
3511 tx_pkt_num = nb_pkts;
3512 tx_ring = txq->tx_ring;
3515 tx_bak_pkt = &txq->sw_ring[tx_next_use];
3516 for (nb_tx = 0; nb_tx < tx_pkt_num; nb_tx++) {
3517 tx_pkt = *tx_pkts++;
3519 nb_buf = tx_pkt->nb_segs;
3521 if (nb_buf > txq->tx_bd_ready) {
3522 txq->queue_full_cnt++;
3530 * If packet length is less than minimum packet length supported
3531 * by hardware in Tx direction, driver need to pad it to avoid
3534 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) <
3535 txq->min_tx_pkt_len)) {
3539 add_len = txq->min_tx_pkt_len -
3540 rte_pktmbuf_pkt_len(tx_pkt);
3541 appended = rte_pktmbuf_append(tx_pkt, add_len);
3542 if (appended == NULL) {
3543 txq->pkt_padding_fail_cnt++;
3547 memset(appended, 0, add_len);
3552 if (hns3_check_non_tso_pkt(nb_buf, &m_seg, tx_pkt, txq))
3555 if (hns3_parse_cksum(txq, tx_next_use, m_seg, &hdr_lens))
3559 desc = &tx_ring[tx_next_use];
3562 * If the packet is divided into multiple Tx Buffer Descriptors,
3563 * only need to fill vlan, paylen and tso into the first Tx
3564 * Buffer Descriptor.
3566 hns3_fill_first_desc(txq, desc, m_seg);
3569 desc = &tx_ring[tx_next_use];
3571 * Fill valid bits, DMA address and data length for each
3572 * Tx Buffer Descriptor.
3574 hns3_fill_per_desc(desc, m_seg);
3575 tx_bak_pkt->mbuf = m_seg;
3576 m_seg = m_seg->next;
3579 if (tx_next_use >= tx_bd_max) {
3581 tx_bak_pkt = txq->sw_ring;
3585 } while (m_seg != NULL);
3587 /* Add end flag for the last Tx Buffer Descriptor */
3588 desc->tx.tp_fe_sc_vld_ra_ri |=
3589 rte_cpu_to_le_16(BIT(HNS3_TXD_FE_B));
3592 txq->next_to_use = tx_next_use;
3593 txq->tx_bd_ready -= i;
3599 hns3_write_reg_opt(txq->io_tail_reg, nb_hold);
3605 hns3_tx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
3611 hns3_xmit_pkts_vec(__rte_unused void *tx_queue,
3612 __rte_unused struct rte_mbuf **tx_pkts,
3613 __rte_unused uint16_t nb_pkts)
3619 hns3_xmit_pkts_vec_sve(void __rte_unused * tx_queue,
3620 struct rte_mbuf __rte_unused **tx_pkts,
3621 uint16_t __rte_unused nb_pkts)
3627 hns3_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3628 struct rte_eth_burst_mode *mode)
3630 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3631 const char *info = NULL;
3633 if (pkt_burst == hns3_xmit_pkts_simple)
3634 info = "Scalar Simple";
3635 else if (pkt_burst == hns3_xmit_pkts)
3637 else if (pkt_burst == hns3_xmit_pkts_vec)
3638 info = "Vector Neon";
3639 else if (pkt_burst == hns3_xmit_pkts_vec_sve)
3640 info = "Vector Sve";
3645 snprintf(mode->info, sizeof(mode->info), "%s", info);
3650 static eth_tx_burst_t
3651 hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep)
3653 uint64_t offloads = dev->data->dev_conf.txmode.offloads;
3654 struct hns3_adapter *hns = dev->data->dev_private;
3656 if (hns->tx_vec_allowed && hns3_tx_check_vec_support(dev) == 0) {
3658 return hns3_check_sve_support() ? hns3_xmit_pkts_vec_sve :
3662 if (hns->tx_simple_allowed &&
3663 offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)) {
3665 return hns3_xmit_pkts_simple;
3668 *prep = hns3_prep_pkts;
3669 return hns3_xmit_pkts;
3673 hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused,
3674 struct rte_mbuf **pkts __rte_unused,
3675 uint16_t pkts_n __rte_unused)
3680 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)
3682 struct hns3_adapter *hns = eth_dev->data->dev_private;
3683 eth_tx_prep_t prep = NULL;
3685 if (hns->hw.adapter_state == HNS3_NIC_STARTED &&
3686 rte_atomic16_read(&hns->hw.reset.resetting) == 0) {
3687 eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev);
3688 eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep);
3689 eth_dev->tx_pkt_prepare = prep;
3691 eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst;
3692 eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
3693 eth_dev->tx_pkt_prepare = hns3_dummy_rxtx_burst;
3698 hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3699 struct rte_eth_rxq_info *qinfo)
3701 struct hns3_rx_queue *rxq = dev->data->rx_queues[queue_id];
3703 qinfo->mp = rxq->mb_pool;
3704 qinfo->nb_desc = rxq->nb_rx_desc;
3705 qinfo->scattered_rx = dev->data->scattered_rx;
3706 /* Report the HW Rx buffer length to user */
3707 qinfo->rx_buf_size = rxq->rx_buf_len;
3710 * If there are no available Rx buffer descriptors, incoming packets
3711 * are always dropped by hardware based on hns3 network engine.
3713 qinfo->conf.rx_drop_en = 1;
3714 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
3715 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3716 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3720 hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3721 struct rte_eth_txq_info *qinfo)
3723 struct hns3_tx_queue *txq = dev->data->tx_queues[queue_id];
3725 qinfo->nb_desc = txq->nb_tx_desc;
3726 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
3727 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3728 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3729 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3733 hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3735 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3736 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id];
3737 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3740 if (!hns3_dev_indep_txrx_supported(hw))
3743 ret = hns3_reset_queue(hw, rx_queue_id, HNS3_RING_TYPE_RX);
3745 hns3_err(hw, "fail to reset Rx queue %u, ret = %d.",
3750 ret = hns3_init_rxq(hns, rx_queue_id);
3752 hns3_err(hw, "fail to init Rx queue %u, ret = %d.",
3757 hns3_enable_rxq(rxq, true);
3758 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
3764 hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3766 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3767 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id];
3769 if (!hns3_dev_indep_txrx_supported(hw))
3772 hns3_enable_rxq(rxq, false);
3773 hns3_rx_queue_release_mbufs(rxq);
3774 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
3780 hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3782 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3783 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id];
3786 if (!hns3_dev_indep_txrx_supported(hw))
3789 ret = hns3_reset_queue(hw, tx_queue_id, HNS3_RING_TYPE_TX);
3791 hns3_err(hw, "fail to reset Tx queue %u, ret = %d.",
3797 hns3_enable_txq(txq, true);
3798 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
3804 hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3806 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3807 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id];
3809 if (!hns3_dev_indep_txrx_supported(hw))
3812 hns3_enable_txq(txq, false);
3813 hns3_tx_queue_release_mbufs(txq);
3815 * All the mbufs in sw_ring are released and all the pointers in sw_ring
3816 * are set to NULL. If this queue is still called by upper layer,
3817 * residual SW status of this txq may cause these pointers in sw_ring
3818 * which have been set to NULL to be released again. To avoid it,
3822 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;