1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
8 #define HNS3_MIN_RING_DESC 64
9 #define HNS3_MAX_RING_DESC 32768
10 #define HNS3_DEFAULT_RING_DESC 1024
11 #define HNS3_ALIGN_RING_DESC 32
12 #define HNS3_RING_BASE_ALIGN 128
13 #define HNS3_BULK_ALLOC_MBUF_NUM 32
15 #define HNS3_DEFAULT_RX_FREE_THRESH 32
16 #define HNS3_DEFAULT_TX_FREE_THRESH 32
17 #define HNS3_DEFAULT_TX_RS_THRESH 32
18 #define HNS3_TX_FAST_FREE_AHEAD 64
20 #define HNS3_512_BD_BUF_SIZE 512
21 #define HNS3_1K_BD_BUF_SIZE 1024
22 #define HNS3_2K_BD_BUF_SIZE 2048
23 #define HNS3_4K_BD_BUF_SIZE 4096
25 #define HNS3_MIN_BD_BUF_SIZE HNS3_512_BD_BUF_SIZE
26 #define HNS3_MAX_BD_BUF_SIZE HNS3_4K_BD_BUF_SIZE
28 #define HNS3_BD_SIZE_512_TYPE 0
29 #define HNS3_BD_SIZE_1024_TYPE 1
30 #define HNS3_BD_SIZE_2048_TYPE 2
31 #define HNS3_BD_SIZE_4096_TYPE 3
33 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
34 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
35 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
36 #define HNS3_RX_FLAG_L4ID_UDP 0x0
37 #define HNS3_RX_FLAG_L4ID_TCP 0x1
39 #define HNS3_RXD_DMAC_S 0
40 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
41 #define HNS3_RXD_VLAN_S 2
42 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
43 #define HNS3_RXD_L3ID_S 4
44 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
45 #define HNS3_RXD_L4ID_S 8
46 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
47 #define HNS3_RXD_FRAG_B 12
48 #define HNS3_RXD_STRP_TAGP_S 13
49 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
51 #define HNS3_RXD_L2E_B 16
52 #define HNS3_RXD_L3E_B 17
53 #define HNS3_RXD_L4E_B 18
54 #define HNS3_RXD_TRUNCATE_B 19
55 #define HNS3_RXD_HOI_B 20
56 #define HNS3_RXD_DOI_B 21
57 #define HNS3_RXD_OL3E_B 22
58 #define HNS3_RXD_OL4E_B 23
59 #define HNS3_RXD_GRO_COUNT_S 24
60 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
61 #define HNS3_RXD_GRO_FIXID_B 30
62 #define HNS3_RXD_GRO_ECN_B 31
64 #define HNS3_RXD_ODMAC_S 0
65 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
66 #define HNS3_RXD_OVLAN_S 2
67 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
68 #define HNS3_RXD_OL3ID_S 4
69 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
70 #define HNS3_RXD_OL4ID_S 8
71 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
72 #define HNS3_RXD_FBHI_S 12
73 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
74 #define HNS3_RXD_FBLI_S 14
75 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
77 #define HNS3_RXD_BDTYPE_S 0
78 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
79 #define HNS3_RXD_VLD_B 4
80 #define HNS3_RXD_UDP0_B 5
81 #define HNS3_RXD_EXTEND_B 7
82 #define HNS3_RXD_FE_B 8
83 #define HNS3_RXD_LUM_B 9
84 #define HNS3_RXD_CRCP_B 10
85 #define HNS3_RXD_L3L4P_B 11
86 #define HNS3_RXD_TSIND_S 12
87 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
88 #define HNS3_RXD_LKBK_B 15
89 #define HNS3_RXD_GRO_SIZE_S 16
90 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S)
92 #define HNS3_TXD_L3T_S 0
93 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
94 #define HNS3_TXD_L4T_S 2
95 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
96 #define HNS3_TXD_L3CS_B 4
97 #define HNS3_TXD_L4CS_B 5
98 #define HNS3_TXD_VLAN_B 6
99 #define HNS3_TXD_TSO_B 7
101 #define HNS3_TXD_L2LEN_S 8
102 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
103 #define HNS3_TXD_L3LEN_S 16
104 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
105 #define HNS3_TXD_L4LEN_S 24
106 #define HNS3_TXD_L4LEN_M (0xffUL << HNS3_TXD_L4LEN_S)
108 #define HNS3_TXD_OL3T_S 0
109 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
110 #define HNS3_TXD_OVLAN_B 2
111 #define HNS3_TXD_MACSEC_B 3
112 #define HNS3_TXD_TUNTYPE_S 4
113 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
115 #define HNS3_TXD_BDTYPE_S 0
116 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
117 #define HNS3_TXD_FE_B 4
118 #define HNS3_TXD_SC_S 5
119 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
120 #define HNS3_TXD_EXTEND_B 7
121 #define HNS3_TXD_VLD_B 8
122 #define HNS3_TXD_RI_B 9
123 #define HNS3_TXD_RA_B 10
124 #define HNS3_TXD_TSYN_B 11
125 #define HNS3_TXD_DECTTL_S 12
126 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
128 #define HNS3_TXD_MSS_S 0
129 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
131 #define HNS3_L2_LEN_UNIT 1UL
132 #define HNS3_L3_LEN_UNIT 2UL
133 #define HNS3_L4_LEN_UNIT 2UL
135 enum hns3_pkt_l2t_type {
136 HNS3_L2_TYPE_UNICAST,
137 HNS3_L2_TYPE_MULTICAST,
138 HNS3_L2_TYPE_BROADCAST,
139 HNS3_L2_TYPE_INVALID,
142 enum hns3_pkt_l3t_type {
149 enum hns3_pkt_l4t_type {
156 enum hns3_pkt_ol3t_type {
159 HNS3_OL3T_IPV4_NO_CSUM,
163 enum hns3_pkt_tun_type {
170 /* hardware spec ring buffer format */
185 * L3T | L4T | L3CS | L4CS | VLAN | TSO |
188 uint32_t type_cs_vlan_tso_len;
190 uint8_t type_cs_vlan_tso;
196 uint16_t outer_vlan_tag;
199 /* OL3T | OVALAN | MACSEC */
200 uint32_t ol_type_vlan_len_msec;
202 uint8_t ol_type_vlan_msec;
210 uint16_t tp_fe_sc_vld_ra_ri;
224 uint16_t o_dm_vlan_id_fb;
225 uint16_t ot_vlan_tag;
228 uint32_t bd_base_info;
234 struct rte_mbuf *mbuf;
237 struct hns3_rx_queue {
239 volatile void *io_head_reg;
240 struct hns3_adapter *hns;
241 struct hns3_ptype_table *ptype_tbl;
242 struct rte_mempool *mb_pool;
243 struct hns3_desc *rx_ring;
244 uint64_t rx_ring_phys_addr; /* RX ring DMA address */
245 const struct rte_memzone *mz;
246 struct hns3_entry *sw_ring;
248 struct rte_mbuf *pkt_first_seg;
249 struct rte_mbuf *pkt_last_seg;
256 * threshold for the number of BDs waited to passed to hardware. If the
257 * number exceeds the threshold, driver will pass these BDs to hardware.
259 uint16_t rx_free_thresh;
260 uint16_t next_to_use; /* index of next BD to be polled */
261 uint16_t rx_free_hold; /* num of BDs waited to passed to hardware */
264 * port based vlan configuration state.
265 * value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE
269 /* 4 if DEV_RX_OFFLOAD_KEEP_CRC offload set, 0 otherwise */
272 bool rx_deferred_start; /* don't start this queue in dev start */
273 bool configured; /* indicate if rx queue has been configured */
276 uint64_t pkt_len_errors;
277 uint64_t l3_csum_errors;
278 uint64_t l4_csum_errors;
279 uint64_t ol3_csum_errors;
280 uint64_t ol4_csum_errors;
282 struct rte_mbuf *bulk_mbuf[HNS3_BULK_ALLOC_MBUF_NUM];
283 uint16_t bulk_mbuf_num;
286 struct hns3_tx_queue {
288 volatile void *io_tail_reg;
289 struct hns3_adapter *hns;
290 struct hns3_desc *tx_ring;
291 uint64_t tx_ring_phys_addr; /* TX ring DMA address */
292 const struct rte_memzone *mz;
293 struct hns3_entry *sw_ring;
299 * index of next BD whose corresponding rte_mbuf can be released by
302 uint16_t next_to_clean;
303 /* index of next BD to be filled by driver to send packet */
304 uint16_t next_to_use;
305 /* num of remaining BDs ready to be filled by driver to send packet */
306 uint16_t tx_bd_ready;
308 /* threshold for free tx buffer if available BDs less than this value */
309 uint16_t tx_free_thresh;
312 * For better performance in tx datapath, releasing mbuf in batches is
314 * Only checking the VLD bit of the last descriptor in a batch of the
315 * thresh descriptors does not mean that these descriptors are all sent
316 * by hardware successfully. So we need to check that the VLD bits of
317 * all descriptors are cleared. and then free all mbufs in the batch.
319 * Number of mbufs released at a time.
322 uint16_t tx_rs_thresh;
325 * port based vlan configuration state.
326 * value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE
331 * The minimum length of the packet supported by hardware in the Tx
334 uint32_t min_tx_pkt_len;
336 bool tx_deferred_start; /* don't start this queue in dev start */
337 bool configured; /* indicate if tx queue has been configured */
340 * The following items are used for the abnormal errors statistics in
341 * the Tx datapath. When upper level application calls the
342 * rte_eth_tx_burst API function to send multiple packets at a time with
343 * burst mode based on hns3 network engine, there are some abnormal
344 * conditions that cause the driver to fail to operate the hardware to
345 * send packets correctly.
346 * Note: When using burst mode to call the rte_eth_tx_burst API function
347 * to send multiple packets at a time. When the first abnormal error is
348 * detected, add one to the relevant error statistics item, and then
349 * exit the loop of sending multiple packets of the function. That is to
350 * say, even if there are multiple packets in which abnormal errors may
351 * be detected in the burst, the relevant error statistics in the driver
352 * will only be increased by one.
353 * The detail description of the Tx abnormal errors statistic items as
355 * - over_length_pkt_cnt
356 * Total number of greater than HNS3_MAX_FRAME_LEN the driver
359 * - exceed_limit_bd_pkt_cnt
360 * Total number of exceeding the hardware limited bd which process
361 * a packet needed bd numbers.
363 * - exceed_limit_bd_reassem_fail
364 * Total number of exceeding the hardware limited bd fail which
365 * process a packet needed bd numbers and reassemble fail.
367 * - unsupported_tunnel_pkt_cnt
368 * Total number of unsupported tunnel packet. The unsupported tunnel
369 * type: vxlan_gpe, gtp, ipip and MPLSINUDP, MPLSINUDP is a packet
370 * with MPLS-in-UDP RFC 7510 header.
373 * Total count which the available bd numbers in current bd queue is
374 * less than the bd numbers with the pkt process needed.
376 * - pkt_padding_fail_cnt
377 * Total count which the packet length is less than minimum packet
378 * length(struct hns3_tx_queue::min_tx_pkt_len) supported by
379 * hardware in Tx direction and fail to be appended with 0.
381 uint64_t over_length_pkt_cnt;
382 uint64_t exceed_limit_bd_pkt_cnt;
383 uint64_t exceed_limit_bd_reassem_fail;
384 uint64_t unsupported_tunnel_pkt_cnt;
385 uint64_t queue_full_cnt;
386 uint64_t pkt_padding_fail_cnt;
389 #define HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) \
390 ((txq)->nb_tx_desc - 1 - (txq)->tx_bd_ready)
392 struct hns3_queue_info {
393 const char *type; /* point to queue memory name */
394 const char *ring_name; /* point to hardware ring name */
397 unsigned int socket_id;
400 #define HNS3_TX_CKSUM_OFFLOAD_MASK ( \
401 PKT_TX_OUTER_IPV6 | \
402 PKT_TX_OUTER_IPV4 | \
403 PKT_TX_OUTER_IP_CKSUM | \
410 enum hns3_cksum_status {
412 HNS3_L3_CKSUM_ERR = 1,
413 HNS3_L4_CKSUM_ERR = 2,
414 HNS3_OUTER_L3_CKSUM_ERR = 4,
415 HNS3_OUTER_L4_CKSUM_ERR = 8
419 hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,
420 uint32_t bd_base_info, uint32_t l234_info,
423 #define L2E_TRUNC_ERR_FLAG (BIT(HNS3_RXD_L2E_B) | \
424 BIT(HNS3_RXD_TRUNCATE_B))
425 #define CHECKSUM_ERR_FLAG (BIT(HNS3_RXD_L3E_B) | \
426 BIT(HNS3_RXD_L4E_B) | \
427 BIT(HNS3_RXD_OL3E_B) | \
428 BIT(HNS3_RXD_OL4E_B))
433 * If packet len bigger than mtu when recv with no-scattered algorithm,
434 * the first n bd will without FE bit, we need process this sisution.
435 * Note: we don't need add statistic counter because latest BD which
436 * with FE bit will mark HNS3_RXD_L2E_B bit.
438 if (unlikely((bd_base_info & BIT(HNS3_RXD_FE_B)) == 0))
441 if (unlikely((l234_info & L2E_TRUNC_ERR_FLAG) || rxm->pkt_len == 0)) {
442 if (l234_info & BIT(HNS3_RXD_L2E_B))
445 rxq->pkt_len_errors++;
449 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B)) {
450 if (likely((l234_info & CHECKSUM_ERR_FLAG) == 0)) {
455 if (unlikely(l234_info & BIT(HNS3_RXD_L3E_B))) {
456 rxm->ol_flags |= PKT_RX_IP_CKSUM_BAD;
457 rxq->l3_csum_errors++;
458 tmp |= HNS3_L3_CKSUM_ERR;
461 if (unlikely(l234_info & BIT(HNS3_RXD_L4E_B))) {
462 rxm->ol_flags |= PKT_RX_L4_CKSUM_BAD;
463 rxq->l4_csum_errors++;
464 tmp |= HNS3_L4_CKSUM_ERR;
467 if (unlikely(l234_info & BIT(HNS3_RXD_OL3E_B))) {
468 rxq->ol3_csum_errors++;
469 tmp |= HNS3_OUTER_L3_CKSUM_ERR;
472 if (unlikely(l234_info & BIT(HNS3_RXD_OL4E_B))) {
473 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
474 rxq->ol4_csum_errors++;
475 tmp |= HNS3_OUTER_L4_CKSUM_ERR;
484 hns3_rx_set_cksum_flag(struct rte_mbuf *rxm, const uint64_t packet_type,
485 const uint32_t cksum_err)
487 if (unlikely((packet_type & RTE_PTYPE_TUNNEL_MASK))) {
488 if (likely(packet_type & RTE_PTYPE_INNER_L3_MASK) &&
489 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
490 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
491 if (likely(packet_type & RTE_PTYPE_INNER_L4_MASK) &&
492 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
493 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
494 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
495 (cksum_err & HNS3_OUTER_L4_CKSUM_ERR) == 0)
496 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
498 if (likely(packet_type & RTE_PTYPE_L3_MASK) &&
499 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
500 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
501 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
502 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
503 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
507 static inline uint32_t
508 hns3_rx_calc_ptype(struct hns3_rx_queue *rxq, const uint32_t l234_info,
509 const uint32_t ol_info)
511 const struct hns3_ptype_table *const ptype_tbl = rxq->ptype_tbl;
512 uint32_t l2id, l3id, l4id;
513 uint32_t ol3id, ol4id;
515 ol4id = hns3_get_field(ol_info, HNS3_RXD_OL4ID_M, HNS3_RXD_OL4ID_S);
516 ol3id = hns3_get_field(ol_info, HNS3_RXD_OL3ID_M, HNS3_RXD_OL3ID_S);
517 l2id = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,
518 HNS3_RXD_STRP_TAGP_S);
519 l3id = hns3_get_field(l234_info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
520 l4id = hns3_get_field(l234_info, HNS3_RXD_L4ID_M, HNS3_RXD_L4ID_S);
522 if (unlikely(ptype_tbl->ol4table[ol4id]))
523 return ptype_tbl->inner_l2table[l2id] |
524 ptype_tbl->inner_l3table[l3id] |
525 ptype_tbl->inner_l4table[l4id] |
526 ptype_tbl->ol3table[ol3id] | ptype_tbl->ol4table[ol4id];
528 return ptype_tbl->l2table[l2id] | ptype_tbl->l3table[l3id] |
529 ptype_tbl->l4table[l4id];
532 void hns3_dev_rx_queue_release(void *queue);
533 void hns3_dev_tx_queue_release(void *queue);
534 void hns3_free_all_queues(struct rte_eth_dev *dev);
535 int hns3_reset_all_queues(struct hns3_adapter *hns);
536 void hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en);
537 int hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
538 int hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
539 void hns3_enable_all_queues(struct hns3_hw *hw, bool en);
540 int hns3_start_queues(struct hns3_adapter *hns, bool reset_queue);
541 int hns3_stop_queues(struct hns3_adapter *hns, bool reset_queue);
542 void hns3_dev_release_mbufs(struct hns3_adapter *hns);
543 int hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
544 unsigned int socket, const struct rte_eth_rxconf *conf,
545 struct rte_mempool *mp);
546 int hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
547 unsigned int socket, const struct rte_eth_txconf *conf);
548 uint16_t hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
550 uint16_t hns3_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
552 int hns3_rx_burst_mode_get(struct rte_eth_dev *dev,
553 __rte_unused uint16_t queue_id,
554 struct rte_eth_burst_mode *mode);
555 uint16_t hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
557 uint16_t hns3_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
559 uint16_t hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
561 int hns3_tx_burst_mode_get(struct rte_eth_dev *dev,
562 __rte_unused uint16_t queue_id,
563 struct rte_eth_burst_mode *mode);
564 const uint32_t *hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
565 void hns3_init_rx_ptype_tble(struct rte_eth_dev *dev);
566 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev);
567 void hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
568 uint8_t gl_idx, uint16_t gl_value);
569 void hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id,
571 void hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id,
573 int hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
575 int hns3_config_gro(struct hns3_hw *hw, bool en);
576 int hns3_restore_gro_conf(struct hns3_hw *hw);
577 void hns3_update_all_queues_pvid_state(struct hns3_hw *hw);
578 void hns3_rx_scattered_reset(struct rte_eth_dev *dev);
579 void hns3_rx_scattered_calc(struct rte_eth_dev *dev);
580 void hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
581 struct rte_eth_rxq_info *qinfo);
582 void hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
583 struct rte_eth_txq_info *qinfo);
584 #endif /* _HNS3_RXTX_H_ */