1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
8 #define HNS3_MIN_RING_DESC 64
9 #define HNS3_MAX_RING_DESC 32768
10 #define HNS3_DEFAULT_RING_DESC 1024
11 #define HNS3_ALIGN_RING_DESC 32
12 #define HNS3_RING_BASE_ALIGN 128
14 #define HNS3_512_BD_BUF_SIZE 512
15 #define HNS3_1K_BD_BUF_SIZE 1024
16 #define HNS3_2K_BD_BUF_SIZE 2048
17 #define HNS3_4K_BD_BUF_SIZE 4096
19 #define HNS3_MIN_BD_BUF_SIZE HNS3_512_BD_BUF_SIZE
20 #define HNS3_MAX_BD_BUF_SIZE HNS3_4K_BD_BUF_SIZE
22 #define HNS3_BD_SIZE_512_TYPE 0
23 #define HNS3_BD_SIZE_1024_TYPE 1
24 #define HNS3_BD_SIZE_2048_TYPE 2
25 #define HNS3_BD_SIZE_4096_TYPE 3
27 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
28 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
29 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
30 #define HNS3_RX_FLAG_L4ID_UDP 0x0
31 #define HNS3_RX_FLAG_L4ID_TCP 0x1
33 #define HNS3_RXD_DMAC_S 0
34 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
35 #define HNS3_RXD_VLAN_S 2
36 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
37 #define HNS3_RXD_L3ID_S 4
38 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
39 #define HNS3_RXD_L4ID_S 8
40 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
41 #define HNS3_RXD_FRAG_B 12
42 #define HNS3_RXD_STRP_TAGP_S 13
43 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
45 #define HNS3_RXD_L2E_B 16
46 #define HNS3_RXD_L3E_B 17
47 #define HNS3_RXD_L4E_B 18
48 #define HNS3_RXD_TRUNCAT_B 19
49 #define HNS3_RXD_HOI_B 20
50 #define HNS3_RXD_DOI_B 21
51 #define HNS3_RXD_OL3E_B 22
52 #define HNS3_RXD_OL4E_B 23
53 #define HNS3_RXD_GRO_COUNT_S 24
54 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
55 #define HNS3_RXD_GRO_FIXID_B 30
56 #define HNS3_RXD_GRO_ECN_B 31
58 #define HNS3_RXD_ODMAC_S 0
59 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
60 #define HNS3_RXD_OVLAN_S 2
61 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
62 #define HNS3_RXD_OL3ID_S 4
63 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
64 #define HNS3_RXD_OL4ID_S 8
65 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
66 #define HNS3_RXD_FBHI_S 12
67 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
68 #define HNS3_RXD_FBLI_S 14
69 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
71 #define HNS3_RXD_BDTYPE_S 0
72 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
73 #define HNS3_RXD_VLD_B 4
74 #define HNS3_RXD_UDP0_B 5
75 #define HNS3_RXD_EXTEND_B 7
76 #define HNS3_RXD_FE_B 8
77 #define HNS3_RXD_LUM_B 9
78 #define HNS3_RXD_CRCP_B 10
79 #define HNS3_RXD_L3L4P_B 11
80 #define HNS3_RXD_TSIND_S 12
81 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
82 #define HNS3_RXD_LKBK_B 15
83 #define HNS3_RXD_GRO_SIZE_S 16
84 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S)
86 #define HNS3_TXD_L3T_S 0
87 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
88 #define HNS3_TXD_L4T_S 2
89 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
90 #define HNS3_TXD_L3CS_B 4
91 #define HNS3_TXD_L4CS_B 5
92 #define HNS3_TXD_VLAN_B 6
93 #define HNS3_TXD_TSO_B 7
95 #define HNS3_TXD_L2LEN_S 8
96 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
97 #define HNS3_TXD_L3LEN_S 16
98 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
99 #define HNS3_TXD_L4LEN_S 24
100 #define HNS3_TXD_L4LEN_M (0xffUL << HNS3_TXD_L4LEN_S)
102 #define HNS3_TXD_OL3T_S 0
103 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
104 #define HNS3_TXD_OVLAN_B 2
105 #define HNS3_TXD_MACSEC_B 3
106 #define HNS3_TXD_TUNTYPE_S 4
107 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
109 #define HNS3_TXD_BDTYPE_S 0
110 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
111 #define HNS3_TXD_FE_B 4
112 #define HNS3_TXD_SC_S 5
113 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
114 #define HNS3_TXD_EXTEND_B 7
115 #define HNS3_TXD_VLD_B 8
116 #define HNS3_TXD_RI_B 9
117 #define HNS3_TXD_RA_B 10
118 #define HNS3_TXD_TSYN_B 11
119 #define HNS3_TXD_DECTTL_S 12
120 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
122 #define HNS3_TXD_MSS_S 0
123 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
125 #define HNS3_L2_LEN_UNIT 1UL
126 #define HNS3_L3_LEN_UNIT 2UL
127 #define HNS3_L4_LEN_UNIT 2UL
129 enum hns3_pkt_l2t_type {
130 HNS3_L2_TYPE_UNICAST,
131 HNS3_L2_TYPE_MULTICAST,
132 HNS3_L2_TYPE_BROADCAST,
133 HNS3_L2_TYPE_INVALID,
136 enum hns3_pkt_l3t_type {
143 enum hns3_pkt_l4t_type {
150 enum hns3_pkt_ol3t_type {
153 HNS3_OL3T_IPV4_NO_CSUM,
157 enum hns3_pkt_tun_type {
164 /* hardware spec ring buffer format */
179 * L3T | L4T | L3CS | L4CS | VLAN | TSO |
182 uint32_t type_cs_vlan_tso_len;
184 uint8_t type_cs_vlan_tso;
190 uint16_t outer_vlan_tag;
193 /* OL3T | OVALAN | MACSEC */
194 uint32_t ol_type_vlan_len_msec;
196 uint8_t ol_type_vlan_msec;
204 uint16_t tp_fe_sc_vld_ra_ri;
218 uint16_t o_dm_vlan_id_fb;
219 uint16_t ot_vlan_tag;
222 uint32_t bd_base_info;
228 struct rte_mbuf *mbuf;
231 struct hns3_rx_queue {
233 struct hns3_adapter *hns;
234 struct rte_mempool *mb_pool;
235 struct hns3_desc *rx_ring;
236 uint64_t rx_ring_phys_addr; /* RX ring DMA address */
237 const struct rte_memzone *mz;
238 struct hns3_entry *sw_ring;
240 struct rte_mbuf *pkt_first_seg;
241 struct rte_mbuf *pkt_last_seg;
248 uint16_t next_to_clean;
249 uint16_t next_to_use;
251 uint16_t rx_free_thresh;
254 * port based vlan configuration state.
255 * value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE
259 /* 4 if DEV_RX_OFFLOAD_KEEP_CRC offload set, 0 otherwise */
262 bool rx_deferred_start; /* don't start this queue in dev start */
263 bool configured; /* indicate if rx queue has been configured */
266 uint64_t pkt_len_errors;
267 uint64_t l3_csum_erros;
268 uint64_t l4_csum_erros;
269 uint64_t ol3_csum_erros;
270 uint64_t ol4_csum_erros;
273 struct hns3_tx_queue {
275 struct hns3_adapter *hns;
276 struct hns3_desc *tx_ring;
277 uint64_t tx_ring_phys_addr; /* TX ring DMA address */
278 const struct rte_memzone *mz;
279 struct hns3_entry *sw_ring;
284 uint16_t next_to_clean;
285 uint16_t next_to_use;
286 uint16_t tx_bd_ready;
289 * port based vlan configuration state.
290 * value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE
295 * The minimum length of the packet supported by hardware in the Tx
298 uint32_t min_tx_pkt_len;
300 bool tx_deferred_start; /* don't start this queue in dev start */
301 bool configured; /* indicate if tx queue has been configured */
304 * The following items are used for the abnormal errors statistics in
305 * the Tx datapath. When upper level application calls the
306 * rte_eth_tx_burst API function to send multiple packets at a time with
307 * burst mode based on hns3 network engine, there are some abnormal
308 * conditions that cause the driver to fail to operate the hardware to
309 * send packets correctly.
310 * Note: When using burst mode to call the rte_eth_tx_burst API function
311 * to send multiple packets at a time. When the first abnormal error is
312 * detected, add one to the relevant error statistics item, and then
313 * exit the loop of sending multiple packets of the function. That is to
314 * say, even if there are multiple packets in which abnormal errors may
315 * be detected in the burst, the relevant error statistics in the driver
316 * will only be increased by one.
317 * The detail description of the Tx abnormal errors statistic items as
319 * - over_length_pkt_cnt
320 * Total number of greater than HNS3_MAX_FRAME_LEN the driver
323 * - exceed_limit_bd_pkt_cnt
324 * Total number of exceeding the hardware limited bd which process
325 * a packet needed bd numbers.
327 * - exceed_limit_bd_reassem_fail
328 * Total number of exceeding the hardware limited bd fail which
329 * process a packet needed bd numbers and reassemble fail.
331 * - unsupported_tunnel_pkt_cnt
332 * Total number of unsupported tunnel packet. The unsupported tunnel
333 * type: vxlan_gpe, gtp, ipip and MPLSINUDP, MPLSINUDP is a packet
334 * with MPLS-in-UDP RFC 7510 header.
337 * Total count which the available bd numbers in current bd queue is
338 * less than the bd numbers with the pkt process needed.
340 * - pkt_padding_fail_cnt
341 * Total count which the packet length is less than minimum packet
342 * length(struct hns3_tx_queue::min_tx_pkt_len) supported by
343 * hardware in Tx direction and fail to be appended with 0.
345 uint64_t over_length_pkt_cnt;
346 uint64_t exceed_limit_bd_pkt_cnt;
347 uint64_t exceed_limit_bd_reassem_fail;
348 uint64_t unsupported_tunnel_pkt_cnt;
349 uint64_t queue_full_cnt;
350 uint64_t pkt_padding_fail_cnt;
353 struct hns3_queue_info {
354 const char *type; /* point to queue memory name */
355 const char *ring_name; /* point to hardware ring name */
358 unsigned int socket_id;
361 #define HNS3_TX_CKSUM_OFFLOAD_MASK ( \
362 PKT_TX_OUTER_IPV6 | \
363 PKT_TX_OUTER_IPV4 | \
364 PKT_TX_OUTER_IP_CKSUM | \
371 enum hns3_cksum_status {
373 HNS3_L3_CKSUM_ERR = 1,
374 HNS3_L4_CKSUM_ERR = 2,
375 HNS3_OUTER_L3_CKSUM_ERR = 4,
376 HNS3_OUTER_L4_CKSUM_ERR = 8
379 void hns3_dev_rx_queue_release(void *queue);
380 void hns3_dev_tx_queue_release(void *queue);
381 void hns3_free_all_queues(struct rte_eth_dev *dev);
382 int hns3_reset_all_queues(struct hns3_adapter *hns);
383 void hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en);
384 int hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
385 int hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
386 void hns3_enable_all_queues(struct hns3_hw *hw, bool en);
387 int hns3_start_queues(struct hns3_adapter *hns, bool reset_queue);
388 int hns3_stop_queues(struct hns3_adapter *hns, bool reset_queue);
389 void hns3_dev_release_mbufs(struct hns3_adapter *hns);
390 int hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
391 unsigned int socket, const struct rte_eth_rxconf *conf,
392 struct rte_mempool *mp);
393 int hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
394 unsigned int socket, const struct rte_eth_txconf *conf);
395 uint16_t hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
397 uint16_t hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
399 uint16_t hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
401 const uint32_t *hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
402 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev);
403 void hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
404 uint8_t gl_idx, uint16_t gl_value);
405 void hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id,
407 void hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id,
409 int hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
411 int hns3_config_gro(struct hns3_hw *hw, bool en);
412 int hns3_restore_gro_conf(struct hns3_hw *hw);
413 void hns3_update_all_queues_pvid_state(struct hns3_hw *hw);
414 void hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
415 struct rte_eth_rxq_info *qinfo);
416 void hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
417 struct rte_eth_txq_info *qinfo);
418 #endif /* _HNS3_RXTX_H_ */