1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Hisilicon Limited.
7 #include <ethdev_driver.h>
9 #include "hns3_ethdev.h"
10 #include "hns3_rxtx.h"
11 #include "hns3_rxtx_vec.h"
13 #define PG16_128BIT svwhilelt_b16(0, 8)
14 #define PG16_256BIT svwhilelt_b16(0, 16)
15 #define PG32_256BIT svwhilelt_b32(0, 8)
16 #define PG64_64BIT svwhilelt_b64(0, 1)
17 #define PG64_128BIT svwhilelt_b64(0, 2)
18 #define PG64_256BIT svwhilelt_b64(0, 4)
19 #define PG64_ALLBIT svptrue_b64()
22 #define BD_FIELD_ADDR_OFFSET 0
23 #define BD_FIELD_L234_OFFSET 8
24 #define BD_FIELD_XLEN_OFFSET 12
25 #define BD_FIELD_RSS_OFFSET 16
26 #define BD_FIELD_OL_OFFSET 24
27 #define BD_FIELD_VALID_OFFSET 28
30 uint32_t l234_info[HNS3_SVE_DEFAULT_DESCS_PER_LOOP];
31 uint32_t ol_info[HNS3_SVE_DEFAULT_DESCS_PER_LOOP];
32 uint32_t bd_base_info[HNS3_SVE_DEFAULT_DESCS_PER_LOOP];
33 } HNS3_SVE_KEY_FIELD_S;
35 static inline uint32_t
36 hns3_desc_parse_field_sve(struct hns3_rx_queue *rxq,
37 struct rte_mbuf **rx_pkts,
38 HNS3_SVE_KEY_FIELD_S *key,
45 for (i = 0; i < (int)bd_vld_num; i++) {
46 /* init rte_mbuf.rearm_data last 64-bit */
47 rx_pkts[i]->ol_flags = PKT_RX_RSS_HASH;
49 ret = hns3_handle_bdinfo(rxq, rx_pkts[i], key->bd_base_info[i],
50 key->l234_info[i], &cksum_err);
56 rx_pkts[i]->packet_type = hns3_rx_calc_ptype(rxq,
57 key->l234_info[i], key->ol_info[i]);
58 if (likely(key->bd_base_info[i] & BIT(HNS3_RXD_L3L4P_B)))
59 hns3_rx_set_cksum_flag(rx_pkts[i],
60 rx_pkts[i]->packet_type, cksum_err);
62 /* Increment bytes counter */
63 rxq->basic_stats.bytes += rx_pkts[i]->pkt_len;
70 hns3_rx_prefetch_mbuf_sve(struct hns3_entry *sw_ring)
72 svuint64_t prf1st = svld1_u64(PG64_256BIT, (uint64_t *)&sw_ring[0]);
73 svuint64_t prf2st = svld1_u64(PG64_256BIT, (uint64_t *)&sw_ring[4]);
74 svprfd_gather_u64base(PG64_256BIT, prf1st, SV_PLDL1KEEP);
75 svprfd_gather_u64base(PG64_256BIT, prf2st, SV_PLDL1KEEP);
78 static inline uint16_t
79 hns3_recv_burst_vec_sve(struct hns3_rx_queue *__restrict rxq,
80 struct rte_mbuf **__restrict rx_pkts,
82 uint64_t *bd_err_mask)
84 #define XLEN_ADJUST_LEN 32
85 #define RSS_ADJUST_LEN 16
86 #define GEN_VLD_U8_ZIP_INDEX svindex_s8(28, -4)
87 uint16_t rx_id = rxq->next_to_use;
88 struct hns3_entry *sw_ring = &rxq->sw_ring[rx_id];
89 struct hns3_desc *rxdp = &rxq->rx_ring[rx_id];
90 struct hns3_desc *rxdp2;
91 HNS3_SVE_KEY_FIELD_S key_field;
92 uint64_t bd_valid_num;
93 uint32_t parse_retcode;
97 uint16_t xlen_adjust[XLEN_ADJUST_LEN] = {
98 0, 0xffff, 1, 0xffff, /* 1st mbuf: pkt_len and dat_len */
99 2, 0xffff, 3, 0xffff, /* 2st mbuf: pkt_len and dat_len */
100 4, 0xffff, 5, 0xffff, /* 3st mbuf: pkt_len and dat_len */
101 6, 0xffff, 7, 0xffff, /* 4st mbuf: pkt_len and dat_len */
102 8, 0xffff, 9, 0xffff, /* 5st mbuf: pkt_len and dat_len */
103 10, 0xffff, 11, 0xffff, /* 6st mbuf: pkt_len and dat_len */
104 12, 0xffff, 13, 0xffff, /* 7st mbuf: pkt_len and dat_len */
105 14, 0xffff, 15, 0xffff, /* 8st mbuf: pkt_len and dat_len */
108 uint32_t rss_adjust[RSS_ADJUST_LEN] = {
109 0, 0xffff, /* 1st mbuf: rss */
110 1, 0xffff, /* 2st mbuf: rss */
111 2, 0xffff, /* 3st mbuf: rss */
112 3, 0xffff, /* 4st mbuf: rss */
113 4, 0xffff, /* 5st mbuf: rss */
114 5, 0xffff, /* 6st mbuf: rss */
115 6, 0xffff, /* 7st mbuf: rss */
116 7, 0xffff, /* 8st mbuf: rss */
119 svbool_t pg32 = svwhilelt_b32(0, HNS3_SVE_DEFAULT_DESCS_PER_LOOP);
120 svuint16_t xlen_tbl1 = svld1_u16(PG16_256BIT, xlen_adjust);
121 svuint16_t xlen_tbl2 = svld1_u16(PG16_256BIT, &xlen_adjust[16]);
122 svuint32_t rss_tbl1 = svld1_u32(PG32_256BIT, rss_adjust);
123 svuint32_t rss_tbl2 = svld1_u32(PG32_256BIT, &rss_adjust[8]);
125 for (pos = 0; pos < nb_pkts; pos += HNS3_SVE_DEFAULT_DESCS_PER_LOOP,
126 rxdp += HNS3_SVE_DEFAULT_DESCS_PER_LOOP) {
127 svuint64_t vld_clz, mbp1st, mbp2st, mbuf_init;
128 svuint64_t xlen1st, xlen2st, rss1st, rss2st;
129 svuint32_t l234, ol, vld, vld2, xlen, rss;
132 /* calc how many bd valid: part 1 */
133 vld = svld1_gather_u32offset_u32(pg32, (uint32_t *)rxdp,
134 svindex_u32(BD_FIELD_VALID_OFFSET, BD_SIZE));
135 vld2 = svlsl_n_u32_z(pg32, vld,
136 HNS3_UINT32_BIT - 1 - HNS3_RXD_VLD_B);
137 vld2 = svreinterpret_u32_s32(svasr_n_s32_z(pg32,
138 svreinterpret_s32_u32(vld2), HNS3_UINT32_BIT - 1));
140 /* load 4 mbuf pointer */
141 mbp1st = svld1_u64(PG64_256BIT, (uint64_t *)&sw_ring[pos]);
143 /* calc how many bd valid: part 2 */
144 vld_u8 = svtbl_u8(svreinterpret_u8_u32(vld2),
145 svreinterpret_u8_s8(GEN_VLD_U8_ZIP_INDEX));
146 vld_clz = svnot_u64_z(PG64_64BIT, svreinterpret_u64_u8(vld_u8));
147 vld_clz = svclz_u64_z(PG64_64BIT, vld_clz);
148 svst1_u64(PG64_64BIT, &bd_valid_num, vld_clz);
149 bd_valid_num /= HNS3_UINT8_BIT;
151 /* load 4 more mbuf pointer */
152 mbp2st = svld1_u64(PG64_256BIT, (uint64_t *)&sw_ring[pos + 4]);
154 /* use offset to control below data load oper ordering */
155 offset = rxq->offset_table[bd_valid_num];
156 rxdp2 = rxdp + offset;
158 /* store 4 mbuf pointer into rx_pkts */
159 svst1_u64(PG64_256BIT, (uint64_t *)&rx_pkts[pos], mbp1st);
161 /* load key field to vector reg */
162 l234 = svld1_gather_u32offset_u32(pg32, (uint32_t *)rxdp2,
163 svindex_u32(BD_FIELD_L234_OFFSET, BD_SIZE));
164 ol = svld1_gather_u32offset_u32(pg32, (uint32_t *)rxdp2,
165 svindex_u32(BD_FIELD_OL_OFFSET, BD_SIZE));
167 /* store 4 mbuf pointer into rx_pkts again */
168 svst1_u64(PG64_256BIT, (uint64_t *)&rx_pkts[pos + 4], mbp2st);
170 /* load datalen, pktlen and rss_hash */
171 xlen = svld1_gather_u32offset_u32(pg32, (uint32_t *)rxdp2,
172 svindex_u32(BD_FIELD_XLEN_OFFSET, BD_SIZE));
173 rss = svld1_gather_u32offset_u32(pg32, (uint32_t *)rxdp2,
174 svindex_u32(BD_FIELD_RSS_OFFSET, BD_SIZE));
176 /* store key field to stash buffer */
177 svst1_u32(pg32, (uint32_t *)key_field.l234_info, l234);
178 svst1_u32(pg32, (uint32_t *)key_field.bd_base_info, vld);
179 svst1_u32(pg32, (uint32_t *)key_field.ol_info, ol);
181 /* sub crc_len for pkt_len and data_len */
182 xlen = svreinterpret_u32_u16(svsub_n_u16_z(PG16_256BIT,
183 svreinterpret_u16_u32(xlen), rxq->crc_len));
185 /* init mbuf_initializer */
186 mbuf_init = svdup_n_u64(rxq->mbuf_initializer);
188 /* extract datalen, pktlen and rss from xlen and rss */
189 xlen1st = svreinterpret_u64_u16(
190 svtbl_u16(svreinterpret_u16_u32(xlen), xlen_tbl1));
191 xlen2st = svreinterpret_u64_u16(
192 svtbl_u16(svreinterpret_u16_u32(xlen), xlen_tbl2));
193 rss1st = svreinterpret_u64_u32(
194 svtbl_u32(svreinterpret_u32_u32(rss), rss_tbl1));
195 rss2st = svreinterpret_u64_u32(
196 svtbl_u32(svreinterpret_u32_u32(rss), rss_tbl2));
198 /* save mbuf_initializer */
199 svst1_scatter_u64base_offset_u64(PG64_256BIT, mbp1st,
200 offsetof(struct rte_mbuf, rearm_data), mbuf_init);
201 svst1_scatter_u64base_offset_u64(PG64_256BIT, mbp2st,
202 offsetof(struct rte_mbuf, rearm_data), mbuf_init);
204 /* save datalen and pktlen and rss */
205 svst1_scatter_u64base_offset_u64(PG64_256BIT, mbp1st,
206 offsetof(struct rte_mbuf, pkt_len), xlen1st);
207 svst1_scatter_u64base_offset_u64(PG64_256BIT, mbp1st,
208 offsetof(struct rte_mbuf, hash.rss), rss1st);
209 svst1_scatter_u64base_offset_u64(PG64_256BIT, mbp2st,
210 offsetof(struct rte_mbuf, pkt_len), xlen2st);
211 svst1_scatter_u64base_offset_u64(PG64_256BIT, mbp2st,
212 offsetof(struct rte_mbuf, hash.rss), rss2st);
214 rte_prefetch_non_temporal(rxdp +
215 HNS3_SVE_DEFAULT_DESCS_PER_LOOP);
217 parse_retcode = hns3_desc_parse_field_sve(rxq, &rx_pkts[pos],
218 &key_field, bd_valid_num);
219 if (unlikely(parse_retcode))
220 (*bd_err_mask) |= ((uint64_t)parse_retcode) << pos;
222 hns3_rx_prefetch_mbuf_sve(&sw_ring[pos +
223 HNS3_SVE_DEFAULT_DESCS_PER_LOOP]);
225 nb_rx += bd_valid_num;
226 if (unlikely(bd_valid_num < HNS3_SVE_DEFAULT_DESCS_PER_LOOP))
230 rxq->rx_rearm_nb += nb_rx;
231 rxq->next_to_use += nb_rx;
232 if (rxq->next_to_use >= rxq->nb_rx_desc)
233 rxq->next_to_use = 0;
239 hns3_rxq_rearm_mbuf_sve(struct hns3_rx_queue *rxq)
241 #define REARM_LOOP_STEP_NUM 4
242 struct hns3_entry *rxep = &rxq->sw_ring[rxq->rx_rearm_start];
243 struct hns3_desc *rxdp = rxq->rx_ring + rxq->rx_rearm_start;
244 struct hns3_entry *rxep_tmp = rxep;
247 if (unlikely(rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
248 HNS3_DEFAULT_RXQ_REARM_THRESH) < 0)) {
249 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
253 for (i = 0; i < HNS3_DEFAULT_RXQ_REARM_THRESH; i += REARM_LOOP_STEP_NUM,
254 rxep_tmp += REARM_LOOP_STEP_NUM) {
255 svuint64_t prf = svld1_u64(PG64_256BIT, (uint64_t *)rxep_tmp);
256 svprfd_gather_u64base(PG64_256BIT, prf, SV_PLDL1STRM);
259 for (i = 0; i < HNS3_DEFAULT_RXQ_REARM_THRESH; i += REARM_LOOP_STEP_NUM,
260 rxep += REARM_LOOP_STEP_NUM, rxdp += REARM_LOOP_STEP_NUM) {
261 uint64_t iova[REARM_LOOP_STEP_NUM];
262 iova[0] = rxep[0].mbuf->buf_iova;
263 iova[1] = rxep[1].mbuf->buf_iova;
264 iova[2] = rxep[2].mbuf->buf_iova;
265 iova[3] = rxep[3].mbuf->buf_iova;
266 svuint64_t siova = svld1_u64(PG64_256BIT, iova);
267 siova = svadd_n_u64_z(PG64_256BIT, siova, RTE_PKTMBUF_HEADROOM);
268 svuint64_t ol_base = svdup_n_u64(0);
269 svst1_scatter_u64offset_u64(PG64_256BIT,
270 (uint64_t *)&rxdp[0].addr,
271 svindex_u64(BD_FIELD_ADDR_OFFSET, BD_SIZE), siova);
272 svst1_scatter_u64offset_u64(PG64_256BIT,
273 (uint64_t *)&rxdp[0].addr,
274 svindex_u64(BD_FIELD_OL_OFFSET, BD_SIZE), ol_base);
277 rxq->rx_rearm_start += HNS3_DEFAULT_RXQ_REARM_THRESH;
278 if (rxq->rx_rearm_start >= rxq->nb_rx_desc)
279 rxq->rx_rearm_start = 0;
281 rxq->rx_rearm_nb -= HNS3_DEFAULT_RXQ_REARM_THRESH;
283 hns3_write_reg_opt(rxq->io_head_reg, HNS3_DEFAULT_RXQ_REARM_THRESH);
287 hns3_recv_pkts_vec_sve(void *__restrict rx_queue,
288 struct rte_mbuf **__restrict rx_pkts,
291 struct hns3_rx_queue *rxq = rx_queue;
292 struct hns3_desc *rxdp = &rxq->rx_ring[rxq->next_to_use];
293 uint64_t bd_err_mask; /* bit mask indicate whick pkts is error */
296 rte_prefetch_non_temporal(rxdp);
298 nb_pkts = RTE_MIN(nb_pkts, HNS3_DEFAULT_RX_BURST);
299 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, HNS3_SVE_DEFAULT_DESCS_PER_LOOP);
301 if (rxq->rx_rearm_nb > HNS3_DEFAULT_RXQ_REARM_THRESH)
302 hns3_rxq_rearm_mbuf_sve(rxq);
304 if (unlikely(!(rxdp->rx.bd_base_info &
305 rte_cpu_to_le_32(1u << HNS3_RXD_VLD_B))))
308 hns3_rx_prefetch_mbuf_sve(&rxq->sw_ring[rxq->next_to_use]);
311 nb_rx = hns3_recv_burst_vec_sve(rxq, rx_pkts, nb_pkts, &bd_err_mask);
312 if (unlikely(bd_err_mask))
313 nb_rx = hns3_rx_reassemble_pkts(rx_pkts, nb_rx, bd_err_mask);
319 hns3_tx_free_buffers_sve(struct hns3_tx_queue *txq)
321 #define HNS3_SVE_CHECK_DESCS_PER_LOOP 8
322 #define TX_VLD_U8_ZIP_INDEX svindex_u8(0, 4)
323 svbool_t pg32 = svwhilelt_b32(0, HNS3_SVE_CHECK_DESCS_PER_LOOP);
324 svuint32_t vld, vld2;
327 struct hns3_desc *tx_desc;
331 * All mbufs can be released only when the VLD bits of all
332 * descriptors in a batch are cleared.
334 /* do logical OR operation for all desc's valid field */
335 vld = svdup_n_u32(0);
336 tx_desc = &txq->tx_ring[txq->next_to_clean];
337 for (i = 0; i < txq->tx_rs_thresh; i += HNS3_SVE_CHECK_DESCS_PER_LOOP,
338 tx_desc += HNS3_SVE_CHECK_DESCS_PER_LOOP) {
339 vld2 = svld1_gather_u32offset_u32(pg32, (uint32_t *)tx_desc,
340 svindex_u32(BD_FIELD_VALID_OFFSET, BD_SIZE));
341 vld = svorr_u32_z(pg32, vld, vld2);
343 /* shift left and then right to get all valid bit */
344 vld = svlsl_n_u32_z(pg32, vld,
345 HNS3_UINT32_BIT - 1 - HNS3_TXD_VLD_B);
346 vld = svreinterpret_u32_s32(svasr_n_s32_z(pg32,
347 svreinterpret_s32_u32(vld), HNS3_UINT32_BIT - 1));
348 /* use tbl to compress 32bit-lane to 8bit-lane */
349 vld_u8 = svtbl_u8(svreinterpret_u8_u32(vld), TX_VLD_U8_ZIP_INDEX);
350 /* dump compressed 64bit to variable */
351 svst1_u64(PG64_64BIT, &vld_all, svreinterpret_u64_u8(vld_u8));
355 hns3_tx_bulk_free_buffers(txq);
359 hns3_tx_fill_hw_ring_sve(struct hns3_tx_queue *txq,
360 struct rte_mbuf **pkts,
363 #define DATA_OFF_LEN_VAL_MASK 0xFFFF
364 struct hns3_desc *txdp = &txq->tx_ring[txq->next_to_use];
365 struct hns3_entry *tx_entry = &txq->sw_ring[txq->next_to_use];
366 const uint64_t valid_bit = (BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B)) <<
368 svuint64_t base_addr, buf_iova, data_off, data_len, addr;
369 svuint64_t offsets = svindex_u64(0, BD_SIZE);
371 svbool_t pg = svwhilelt_b64_u32(i, nb_pkts);
374 base_addr = svld1_u64(pg, (uint64_t *)pkts);
375 /* calc mbuf's field buf_iova address */
376 buf_iova = svadd_n_u64_z(pg, base_addr,
377 offsetof(struct rte_mbuf, buf_iova));
378 /* calc mbuf's field data_off address */
379 data_off = svadd_n_u64_z(pg, base_addr,
380 offsetof(struct rte_mbuf, data_off));
381 /* calc mbuf's field data_len address */
382 data_len = svadd_n_u64_z(pg, base_addr,
383 offsetof(struct rte_mbuf, data_len));
384 /* store mbuf to tx_entry */
385 svst1_u64(pg, (uint64_t *)tx_entry, base_addr);
386 /* read pkts->buf_iova */
387 buf_iova = svld1_gather_u64base_u64(pg, buf_iova);
388 /* read pkts->data_off's 64bit val */
389 data_off = svld1_gather_u64base_u64(pg, data_off);
390 /* read pkts->data_len's 64bit val */
391 data_len = svld1_gather_u64base_u64(pg, data_len);
392 /* zero data_off high 48bit by svand ops */
393 data_off = svand_n_u64_z(pg, data_off, DATA_OFF_LEN_VAL_MASK);
394 /* zero data_len high 48bit by svand ops */
395 data_len = svand_n_u64_z(pg, data_len, DATA_OFF_LEN_VAL_MASK);
396 /* calc mbuf data region iova addr */
397 addr = svadd_u64_z(pg, buf_iova, data_off);
398 /* shift due data_len's offset is 2byte of BD's second 8byte */
399 data_len = svlsl_n_u64_z(pg, data_len, HNS3_UINT16_BIT);
400 /* save offset 0~7byte of every BD */
401 svst1_scatter_u64offset_u64(pg, (uint64_t *)&txdp->addr,
403 /* save offset 8~15byte of every BD */
404 svst1_scatter_u64offset_u64(pg, (uint64_t *)&txdp->tx.vlan_tag,
406 /* save offset 16~23byte of every BD */
407 svst1_scatter_u64offset_u64(pg,
408 (uint64_t *)&txdp->tx.outer_vlan_tag,
409 offsets, svdup_n_u64(0));
410 /* save offset 24~31byte of every BD */
411 svst1_scatter_u64offset_u64(pg, (uint64_t *)&txdp->tx.paylen,
412 offsets, svdup_n_u64(valid_bit));
414 /* Increment bytes counter */
416 for (idx = 0; idx < svcntd(); idx++)
417 txq->basic_stats.bytes += pkts[idx]->pkt_len;
419 /* update index for next loop */
423 tx_entry += svcntd();
424 pg = svwhilelt_b64_u32(i, nb_pkts);
425 } while (svptest_any(svptrue_b64(), pg));
429 hns3_xmit_fixed_burst_vec_sve(void *__restrict tx_queue,
430 struct rte_mbuf **__restrict tx_pkts,
433 struct hns3_tx_queue *txq = (struct hns3_tx_queue *)tx_queue;
436 if (txq->tx_bd_ready < txq->tx_free_thresh)
437 hns3_tx_free_buffers_sve(txq);
439 nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts);
440 if (unlikely(nb_pkts == 0)) {
441 txq->queue_full_cnt++;
445 if (txq->next_to_use + nb_pkts > txq->nb_tx_desc) {
446 nb_tx = txq->nb_tx_desc - txq->next_to_use;
447 hns3_tx_fill_hw_ring_sve(txq, tx_pkts, nb_tx);
448 txq->next_to_use = 0;
451 hns3_tx_fill_hw_ring_sve(txq, tx_pkts + nb_tx, nb_pkts - nb_tx);
452 txq->next_to_use += nb_pkts - nb_tx;
454 txq->tx_bd_ready -= nb_pkts;
455 hns3_write_reg_opt(txq->io_tail_reg, nb_pkts);
461 hns3_xmit_pkts_vec_sve(void *tx_queue,
462 struct rte_mbuf **tx_pkts,
465 struct hns3_tx_queue *txq = (struct hns3_tx_queue *)tx_queue;
466 uint16_t ret, new_burst;
470 new_burst = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
471 ret = hns3_xmit_fixed_burst_vec_sve(tx_queue, &tx_pkts[nb_tx],