1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #include <rte_ethdev.h>
7 #include <rte_malloc.h>
9 #include "hns3_ethdev.h"
10 #include "hns3_rxtx.h"
11 #include "hns3_logs.h"
12 #include "hns3_regs.h"
14 /* The statistics of the per-rxq basic stats */
15 static const struct hns3_xstats_name_offset hns3_rxq_basic_stats_strings[] = {
17 HNS3_RXQ_BASIC_STATS_FIELD_OFFSET(packets)},
19 HNS3_RXQ_BASIC_STATS_FIELD_OFFSET(bytes)},
21 HNS3_RXQ_BASIC_STATS_FIELD_OFFSET(errors)}
24 /* The statistics of the per-txq basic stats */
25 static const struct hns3_xstats_name_offset hns3_txq_basic_stats_strings[] = {
27 HNS3_TXQ_BASIC_STATS_FIELD_OFFSET(packets)},
29 HNS3_TXQ_BASIC_STATS_FIELD_OFFSET(bytes)}
33 static const struct hns3_xstats_name_offset hns3_mac_strings[] = {
34 {"mac_tx_mac_pause_num",
35 HNS3_MAC_STATS_OFFSET(mac_tx_mac_pause_num)},
36 {"mac_rx_mac_pause_num",
37 HNS3_MAC_STATS_OFFSET(mac_rx_mac_pause_num)},
38 {"mac_tx_control_pkt_num",
39 HNS3_MAC_STATS_OFFSET(mac_tx_ctrl_pkt_num)},
40 {"mac_rx_control_pkt_num",
41 HNS3_MAC_STATS_OFFSET(mac_rx_ctrl_pkt_num)},
42 {"mac_tx_pfc_pkt_num",
43 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pause_pkt_num)},
44 {"mac_tx_pfc_pri0_pkt_num",
45 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri0_pkt_num)},
46 {"mac_tx_pfc_pri1_pkt_num",
47 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri1_pkt_num)},
48 {"mac_tx_pfc_pri2_pkt_num",
49 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri2_pkt_num)},
50 {"mac_tx_pfc_pri3_pkt_num",
51 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri3_pkt_num)},
52 {"mac_tx_pfc_pri4_pkt_num",
53 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri4_pkt_num)},
54 {"mac_tx_pfc_pri5_pkt_num",
55 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri5_pkt_num)},
56 {"mac_tx_pfc_pri6_pkt_num",
57 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri6_pkt_num)},
58 {"mac_tx_pfc_pri7_pkt_num",
59 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri7_pkt_num)},
60 {"mac_rx_pfc_pkt_num",
61 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pause_pkt_num)},
62 {"mac_rx_pfc_pri0_pkt_num",
63 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri0_pkt_num)},
64 {"mac_rx_pfc_pri1_pkt_num",
65 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri1_pkt_num)},
66 {"mac_rx_pfc_pri2_pkt_num",
67 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri2_pkt_num)},
68 {"mac_rx_pfc_pri3_pkt_num",
69 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri3_pkt_num)},
70 {"mac_rx_pfc_pri4_pkt_num",
71 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri4_pkt_num)},
72 {"mac_rx_pfc_pri5_pkt_num",
73 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri5_pkt_num)},
74 {"mac_rx_pfc_pri6_pkt_num",
75 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri6_pkt_num)},
76 {"mac_rx_pfc_pri7_pkt_num",
77 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri7_pkt_num)},
78 {"mac_tx_total_pkt_num",
79 HNS3_MAC_STATS_OFFSET(mac_tx_total_pkt_num)},
80 {"mac_tx_total_oct_num",
81 HNS3_MAC_STATS_OFFSET(mac_tx_total_oct_num)},
82 {"mac_tx_good_pkt_num",
83 HNS3_MAC_STATS_OFFSET(mac_tx_good_pkt_num)},
84 {"mac_tx_bad_pkt_num",
85 HNS3_MAC_STATS_OFFSET(mac_tx_bad_pkt_num)},
86 {"mac_tx_good_oct_num",
87 HNS3_MAC_STATS_OFFSET(mac_tx_good_oct_num)},
88 {"mac_tx_bad_oct_num",
89 HNS3_MAC_STATS_OFFSET(mac_tx_bad_oct_num)},
90 {"mac_tx_uni_pkt_num",
91 HNS3_MAC_STATS_OFFSET(mac_tx_uni_pkt_num)},
92 {"mac_tx_multi_pkt_num",
93 HNS3_MAC_STATS_OFFSET(mac_tx_multi_pkt_num)},
94 {"mac_tx_broad_pkt_num",
95 HNS3_MAC_STATS_OFFSET(mac_tx_broad_pkt_num)},
96 {"mac_tx_undersize_pkt_num",
97 HNS3_MAC_STATS_OFFSET(mac_tx_undersize_pkt_num)},
98 {"mac_tx_oversize_pkt_num",
99 HNS3_MAC_STATS_OFFSET(mac_tx_oversize_pkt_num)},
100 {"mac_tx_64_oct_pkt_num",
101 HNS3_MAC_STATS_OFFSET(mac_tx_64_oct_pkt_num)},
102 {"mac_tx_65_127_oct_pkt_num",
103 HNS3_MAC_STATS_OFFSET(mac_tx_65_127_oct_pkt_num)},
104 {"mac_tx_128_255_oct_pkt_num",
105 HNS3_MAC_STATS_OFFSET(mac_tx_128_255_oct_pkt_num)},
106 {"mac_tx_256_511_oct_pkt_num",
107 HNS3_MAC_STATS_OFFSET(mac_tx_256_511_oct_pkt_num)},
108 {"mac_tx_512_1023_oct_pkt_num",
109 HNS3_MAC_STATS_OFFSET(mac_tx_512_1023_oct_pkt_num)},
110 {"mac_tx_1024_1518_oct_pkt_num",
111 HNS3_MAC_STATS_OFFSET(mac_tx_1024_1518_oct_pkt_num)},
112 {"mac_tx_1519_2047_oct_pkt_num",
113 HNS3_MAC_STATS_OFFSET(mac_tx_1519_2047_oct_pkt_num)},
114 {"mac_tx_2048_4095_oct_pkt_num",
115 HNS3_MAC_STATS_OFFSET(mac_tx_2048_4095_oct_pkt_num)},
116 {"mac_tx_4096_8191_oct_pkt_num",
117 HNS3_MAC_STATS_OFFSET(mac_tx_4096_8191_oct_pkt_num)},
118 {"mac_tx_8192_9216_oct_pkt_num",
119 HNS3_MAC_STATS_OFFSET(mac_tx_8192_9216_oct_pkt_num)},
120 {"mac_tx_9217_12287_oct_pkt_num",
121 HNS3_MAC_STATS_OFFSET(mac_tx_9217_12287_oct_pkt_num)},
122 {"mac_tx_12288_16383_oct_pkt_num",
123 HNS3_MAC_STATS_OFFSET(mac_tx_12288_16383_oct_pkt_num)},
124 {"mac_tx_1519_max_good_pkt_num",
125 HNS3_MAC_STATS_OFFSET(mac_tx_1519_max_good_oct_pkt_num)},
126 {"mac_tx_1519_max_bad_pkt_num",
127 HNS3_MAC_STATS_OFFSET(mac_tx_1519_max_bad_oct_pkt_num)},
128 {"mac_rx_total_pkt_num",
129 HNS3_MAC_STATS_OFFSET(mac_rx_total_pkt_num)},
130 {"mac_rx_total_oct_num",
131 HNS3_MAC_STATS_OFFSET(mac_rx_total_oct_num)},
132 {"mac_rx_good_pkt_num",
133 HNS3_MAC_STATS_OFFSET(mac_rx_good_pkt_num)},
134 {"mac_rx_bad_pkt_num",
135 HNS3_MAC_STATS_OFFSET(mac_rx_bad_pkt_num)},
136 {"mac_rx_good_oct_num",
137 HNS3_MAC_STATS_OFFSET(mac_rx_good_oct_num)},
138 {"mac_rx_bad_oct_num",
139 HNS3_MAC_STATS_OFFSET(mac_rx_bad_oct_num)},
140 {"mac_rx_uni_pkt_num",
141 HNS3_MAC_STATS_OFFSET(mac_rx_uni_pkt_num)},
142 {"mac_rx_multi_pkt_num",
143 HNS3_MAC_STATS_OFFSET(mac_rx_multi_pkt_num)},
144 {"mac_rx_broad_pkt_num",
145 HNS3_MAC_STATS_OFFSET(mac_rx_broad_pkt_num)},
146 {"mac_rx_undersize_pkt_num",
147 HNS3_MAC_STATS_OFFSET(mac_rx_undersize_pkt_num)},
148 {"mac_rx_oversize_pkt_num",
149 HNS3_MAC_STATS_OFFSET(mac_rx_oversize_pkt_num)},
150 {"mac_rx_64_oct_pkt_num",
151 HNS3_MAC_STATS_OFFSET(mac_rx_64_oct_pkt_num)},
152 {"mac_rx_65_127_oct_pkt_num",
153 HNS3_MAC_STATS_OFFSET(mac_rx_65_127_oct_pkt_num)},
154 {"mac_rx_128_255_oct_pkt_num",
155 HNS3_MAC_STATS_OFFSET(mac_rx_128_255_oct_pkt_num)},
156 {"mac_rx_256_511_oct_pkt_num",
157 HNS3_MAC_STATS_OFFSET(mac_rx_256_511_oct_pkt_num)},
158 {"mac_rx_512_1023_oct_pkt_num",
159 HNS3_MAC_STATS_OFFSET(mac_rx_512_1023_oct_pkt_num)},
160 {"mac_rx_1024_1518_oct_pkt_num",
161 HNS3_MAC_STATS_OFFSET(mac_rx_1024_1518_oct_pkt_num)},
162 {"mac_rx_1519_2047_oct_pkt_num",
163 HNS3_MAC_STATS_OFFSET(mac_rx_1519_2047_oct_pkt_num)},
164 {"mac_rx_2048_4095_oct_pkt_num",
165 HNS3_MAC_STATS_OFFSET(mac_rx_2048_4095_oct_pkt_num)},
166 {"mac_rx_4096_8191_oct_pkt_num",
167 HNS3_MAC_STATS_OFFSET(mac_rx_4096_8191_oct_pkt_num)},
168 {"mac_rx_8192_9216_oct_pkt_num",
169 HNS3_MAC_STATS_OFFSET(mac_rx_8192_9216_oct_pkt_num)},
170 {"mac_rx_9217_12287_oct_pkt_num",
171 HNS3_MAC_STATS_OFFSET(mac_rx_9217_12287_oct_pkt_num)},
172 {"mac_rx_12288_16383_oct_pkt_num",
173 HNS3_MAC_STATS_OFFSET(mac_rx_12288_16383_oct_pkt_num)},
174 {"mac_rx_1519_max_good_pkt_num",
175 HNS3_MAC_STATS_OFFSET(mac_rx_1519_max_good_oct_pkt_num)},
176 {"mac_rx_1519_max_bad_pkt_num",
177 HNS3_MAC_STATS_OFFSET(mac_rx_1519_max_bad_oct_pkt_num)},
178 {"mac_tx_fragment_pkt_num",
179 HNS3_MAC_STATS_OFFSET(mac_tx_fragment_pkt_num)},
180 {"mac_tx_undermin_pkt_num",
181 HNS3_MAC_STATS_OFFSET(mac_tx_undermin_pkt_num)},
182 {"mac_tx_jabber_pkt_num",
183 HNS3_MAC_STATS_OFFSET(mac_tx_jabber_pkt_num)},
184 {"mac_tx_err_all_pkt_num",
185 HNS3_MAC_STATS_OFFSET(mac_tx_err_all_pkt_num)},
186 {"mac_tx_from_app_good_pkt_num",
187 HNS3_MAC_STATS_OFFSET(mac_tx_from_app_good_pkt_num)},
188 {"mac_tx_from_app_bad_pkt_num",
189 HNS3_MAC_STATS_OFFSET(mac_tx_from_app_bad_pkt_num)},
190 {"mac_rx_fragment_pkt_num",
191 HNS3_MAC_STATS_OFFSET(mac_rx_fragment_pkt_num)},
192 {"mac_rx_undermin_pkt_num",
193 HNS3_MAC_STATS_OFFSET(mac_rx_undermin_pkt_num)},
194 {"mac_rx_jabber_pkt_num",
195 HNS3_MAC_STATS_OFFSET(mac_rx_jabber_pkt_num)},
196 {"mac_rx_fcs_err_pkt_num",
197 HNS3_MAC_STATS_OFFSET(mac_rx_fcs_err_pkt_num)},
198 {"mac_rx_send_app_good_pkt_num",
199 HNS3_MAC_STATS_OFFSET(mac_rx_send_app_good_pkt_num)},
200 {"mac_rx_send_app_bad_pkt_num",
201 HNS3_MAC_STATS_OFFSET(mac_rx_send_app_bad_pkt_num)}
204 /* The statistic of reset */
205 static const struct hns3_xstats_name_offset hns3_reset_stats_strings[] = {
207 HNS3_RESET_STATS_FIELD_OFFSET(request_cnt)},
209 HNS3_RESET_STATS_FIELD_OFFSET(global_cnt)},
211 HNS3_RESET_STATS_FIELD_OFFSET(imp_cnt)},
213 HNS3_RESET_STATS_FIELD_OFFSET(exec_cnt)},
214 {"RESET_SUCCESS_CNT",
215 HNS3_RESET_STATS_FIELD_OFFSET(success_cnt)},
217 HNS3_RESET_STATS_FIELD_OFFSET(fail_cnt)},
219 HNS3_RESET_STATS_FIELD_OFFSET(merge_cnt)}
222 /* The statistic of errors in Rx BD */
223 static const struct hns3_xstats_name_offset hns3_rx_bd_error_strings[] = {
225 HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(pkt_len_errors)},
227 HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(l2_errors)}
230 /* The dfx statistic in Rx datapath */
231 static const struct hns3_xstats_name_offset hns3_rxq_dfx_stats_strings[] = {
232 {"L3_CHECKSUM_ERRORS",
233 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(l3_csum_errors)},
234 {"L4_CHECKSUM_ERRORS",
235 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(l4_csum_errors)},
236 {"OL3_CHECKSUM_ERRORS",
237 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(ol3_csum_errors)},
238 {"OL4_CHECKSUM_ERRORS",
239 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(ol4_csum_errors)}
242 /* The dfx statistic in Tx datapath */
243 static const struct hns3_xstats_name_offset hns3_txq_dfx_stats_strings[] = {
244 {"OVER_LENGTH_PKT_CNT",
245 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(over_length_pkt_cnt)},
246 {"EXCEED_LIMITED_BD_PKT_CNT",
247 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(exceed_limit_bd_pkt_cnt)},
248 {"EXCEED_LIMITED_BD_PKT_REASSEMBLE_FAIL_CNT",
249 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(exceed_limit_bd_reassem_fail)},
250 {"UNSUPPORTED_TUNNEL_PKT_CNT",
251 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(unsupported_tunnel_pkt_cnt)},
253 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(queue_full_cnt)},
254 {"SHORT_PKT_PAD_FAIL_CNT",
255 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(pkt_padding_fail_cnt)}
258 /* The statistic of rx queue */
259 static const struct hns3_xstats_name_offset hns3_rx_queue_strings[] = {
260 {"RX_QUEUE_FBD", HNS3_RING_RX_FBDNUM_REG}
263 /* The statistic of tx queue */
264 static const struct hns3_xstats_name_offset hns3_tx_queue_strings[] = {
265 {"TX_QUEUE_FBD", HNS3_RING_TX_FBDNUM_REG}
268 /* The statistic of imissed packet */
269 static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = {
271 HNS3_IMISSED_STATS_FIELD_OFFSET(rpu_rx_drop_cnt)},
273 HNS3_IMISSED_STATS_FIELD_OFFSET(ssu_rx_drop_cnt)},
276 #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \
277 sizeof(hns3_mac_strings[0]))
279 #define HNS3_NUM_RESET_XSTATS (sizeof(hns3_reset_stats_strings) / \
280 sizeof(hns3_reset_stats_strings[0]))
282 #define HNS3_NUM_RX_BD_ERROR_XSTATS (sizeof(hns3_rx_bd_error_strings) / \
283 sizeof(hns3_rx_bd_error_strings[0]))
285 #define HNS3_NUM_RXQ_DFX_XSTATS (sizeof(hns3_rxq_dfx_stats_strings) / \
286 sizeof(hns3_rxq_dfx_stats_strings[0]))
288 #define HNS3_NUM_TXQ_DFX_XSTATS (sizeof(hns3_txq_dfx_stats_strings) / \
289 sizeof(hns3_txq_dfx_stats_strings[0]))
291 #define HNS3_NUM_RX_QUEUE_STATS (sizeof(hns3_rx_queue_strings) / \
292 sizeof(hns3_rx_queue_strings[0]))
294 #define HNS3_NUM_TX_QUEUE_STATS (sizeof(hns3_tx_queue_strings) / \
295 sizeof(hns3_tx_queue_strings[0]))
297 #define HNS3_NUM_RXQ_BASIC_STATS (sizeof(hns3_rxq_basic_stats_strings) / \
298 sizeof(hns3_rxq_basic_stats_strings[0]))
300 #define HNS3_NUM_TXQ_BASIC_STATS (sizeof(hns3_txq_basic_stats_strings) / \
301 sizeof(hns3_txq_basic_stats_strings[0]))
303 #define HNS3_NUM_IMISSED_XSTATS (sizeof(hns3_imissed_stats_strings) / \
304 sizeof(hns3_imissed_stats_strings[0]))
306 #define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_RESET_XSTATS)
308 static void hns3_tqp_stats_clear(struct hns3_hw *hw);
311 * Query all the MAC statistics data of Network ICL command ,opcode id: 0x0034.
312 * This command is used before send 'query_mac_stat command', the descriptor
313 * number of 'query_mac_stat command' must match with reg_num in this command.
315 * Pointer to structure hns3_hw.
320 hns3_update_mac_stats(struct hns3_hw *hw, const uint32_t desc_num)
322 uint64_t *data = (uint64_t *)(&hw->mac_stats);
323 struct hns3_cmd_desc *desc;
328 desc = rte_malloc("hns3_mac_desc",
329 desc_num * sizeof(struct hns3_cmd_desc), 0);
331 hns3_err(hw, "Mac_update_stats alloced desc malloc fail");
335 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_STATS_MAC_ALL, true);
336 ret = hns3_cmd_send(hw, desc, desc_num);
338 hns3_err(hw, "Update complete MAC pkt stats fail : %d", ret);
343 for (i = 0; i < desc_num; i++) {
344 /* For special opcode 0034, only the first desc has the head */
346 desc_data = (uint64_t *)(&desc[i].data[0]);
347 n = HNS3_RD_FIRST_STATS_NUM;
349 desc_data = (uint64_t *)(&desc[i]);
350 n = HNS3_RD_OTHER_STATS_NUM;
353 for (k = 0; k < n; k++) {
354 *data += rte_le_to_cpu_64(*desc_data);
365 * Query Mac stat reg num command ,opcode id: 0x0033.
366 * This command is used before send 'query_mac_stat command', the descriptor
367 * number of 'query_mac_stat command' must match with reg_num in this command.
369 * Pointer to structure rte_eth_stats.
374 hns3_mac_query_reg_num(struct rte_eth_dev *dev, uint32_t *desc_num)
376 struct hns3_adapter *hns = dev->data->dev_private;
377 struct hns3_hw *hw = &hns->hw;
378 struct hns3_cmd_desc desc;
383 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_REG_NUM, true);
384 ret = hns3_cmd_send(hw, &desc, 1);
389 * The num of MAC statistics registers that are provided by IMP in this
392 desc_data = (uint32_t *)(&desc.data[0]);
393 reg_num = rte_le_to_cpu_32(*desc_data);
396 * The descriptor number of 'query_additional_mac_stat command' is
397 * '1 + (reg_num-3)/4 + ((reg_num-3)%4 !=0)';
398 * This value is 83 in this version
400 *desc_num = 1 + ((reg_num - 3) >> 2) +
401 (uint32_t)(((reg_num - 3) & 0x3) ? 1 : 0);
407 hns3_query_update_mac_stats(struct rte_eth_dev *dev)
409 struct hns3_adapter *hns = dev->data->dev_private;
410 struct hns3_hw *hw = &hns->hw;
414 ret = hns3_mac_query_reg_num(dev, &desc_num);
416 ret = hns3_update_mac_stats(hw, desc_num);
418 hns3_err(hw, "Query mac reg num fail : %d", ret);
423 hns3_update_port_rpu_drop_stats(struct hns3_hw *hw)
425 struct hns3_rx_missed_stats *stats = &hw->imissed_stats;
426 struct hns3_query_rpu_cmd *req;
427 struct hns3_cmd_desc desc;
432 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_DFX_RPU_REG_0, true);
433 req = (struct hns3_query_rpu_cmd *)desc.data;
436 * tc_num is 0, means rpu stats of all TC channels will be
440 req->tc_queue_num = rte_cpu_to_le_32(tc_num);
441 ret = hns3_cmd_send(hw, &desc, 1);
443 hns3_err(hw, "failed to query RPU stats: %d", ret);
447 cnt = rte_le_to_cpu_32(req->rpu_rx_pkt_drop_cnt);
448 stats->rpu_rx_drop_cnt += cnt;
454 hns3_update_function_rpu_drop_stats(struct hns3_hw *hw)
456 struct hns3_rx_missed_stats *stats = &hw->imissed_stats;
458 stats->rpu_rx_drop_cnt += hns3_read_dev(hw, HNS3_RPU_DROP_CNT_REG);
462 hns3_update_rpu_drop_stats(struct hns3_hw *hw)
464 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
467 if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && !hns->is_vf)
468 ret = hns3_update_port_rpu_drop_stats(hw);
469 else if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2)
470 hns3_update_function_rpu_drop_stats(hw);
476 hns3_get_ssu_drop_stats(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
477 int bd_num, bool is_rx)
479 struct hns3_query_ssu_cmd *req;
483 for (i = 0; i < bd_num - 1; i++) {
484 hns3_cmd_setup_basic_desc(&desc[i],
485 HNS3_OPC_SSU_DROP_REG, true);
486 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
488 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_SSU_DROP_REG, true);
489 req = (struct hns3_query_ssu_cmd *)desc[0].data;
490 req->rxtx = is_rx ? 0 : 1;
491 ret = hns3_cmd_send(hw, desc, bd_num);
497 hns3_update_port_rx_ssu_drop_stats(struct hns3_hw *hw)
499 struct hns3_rx_missed_stats *stats = &hw->imissed_stats;
500 struct hns3_cmd_desc desc[HNS3_OPC_SSU_DROP_REG_NUM];
501 struct hns3_query_ssu_cmd *req;
505 ret = hns3_get_ssu_drop_stats(hw, desc, HNS3_OPC_SSU_DROP_REG_NUM,
508 hns3_err(hw, "failed to get Rx SSU drop stats, ret = %d", ret);
512 req = (struct hns3_query_ssu_cmd *)desc[0].data;
513 cnt = rte_le_to_cpu_32(req->oq_drop_cnt) +
514 rte_le_to_cpu_32(req->full_drop_cnt) +
515 rte_le_to_cpu_32(req->part_drop_cnt);
517 stats->ssu_rx_drop_cnt += cnt;
523 hns3_update_port_tx_ssu_drop_stats(struct hns3_hw *hw)
525 struct hns3_cmd_desc desc[HNS3_OPC_SSU_DROP_REG_NUM];
526 struct hns3_query_ssu_cmd *req;
530 ret = hns3_get_ssu_drop_stats(hw, desc, HNS3_OPC_SSU_DROP_REG_NUM,
533 hns3_err(hw, "failed to get Tx SSU drop stats, ret = %d", ret);
537 req = (struct hns3_query_ssu_cmd *)desc[0].data;
538 cnt = rte_le_to_cpu_32(req->oq_drop_cnt) +
539 rte_le_to_cpu_32(req->full_drop_cnt) +
540 rte_le_to_cpu_32(req->part_drop_cnt);
542 hw->oerror_stats += cnt;
548 hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear)
550 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
553 if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && hns->is_vf)
556 if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2 && !hns->is_vf) {
557 ret = hns3_update_port_rx_ssu_drop_stats(hw);
562 ret = hns3_update_rpu_drop_stats(hw);
567 memset(&hw->imissed_stats, 0, sizeof(hw->imissed_stats));
573 hns3_update_oerror_stats(struct hns3_hw *hw, bool is_clear)
575 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
578 if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 || hns->is_vf)
581 ret = hns3_update_port_tx_ssu_drop_stats(hw);
586 hw->oerror_stats = 0;
592 * Query tqp tx queue statistics ,opcode id: 0x0B03.
593 * Query tqp rx queue statistics ,opcode id: 0x0B13.
594 * Get all statistics of a port.
596 * Pointer to Ethernet device.
598 * Pointer to structure rte_eth_stats.
603 hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats)
605 struct hns3_adapter *hns = eth_dev->data->dev_private;
606 struct hns3_hw *hw = &hns->hw;
607 struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats;
608 struct hns3_tqp_stats *stats = &hw->tqp_stats;
609 struct hns3_rx_queue *rxq;
610 struct hns3_tx_queue *txq;
615 /* Update imissed stats */
616 ret = hns3_update_imissed_stats(hw, false);
618 hns3_err(hw, "update imissed stats failed, ret = %d",
622 rte_stats->imissed = imissed_stats->rpu_rx_drop_cnt +
623 imissed_stats->ssu_rx_drop_cnt;
625 /* Get the error stats and bytes of received packets */
626 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
627 rxq = eth_dev->data->rx_queues[i];
631 cnt = hns3_read_dev(rxq, HNS3_RING_RX_PKTNUM_RECORD_REG);
633 * Read hardware and software in adjacent positions to minumize
634 * the timing variance.
636 rte_stats->ierrors += rxq->err_stats.l2_errors +
637 rxq->err_stats.pkt_len_errors;
638 stats->rcb_rx_ring_pktnum_rcd += cnt;
639 stats->rcb_rx_ring_pktnum[i] += cnt;
640 rte_stats->ibytes += rxq->basic_stats.bytes;
643 /* Reads all the stats of a txq in a loop to keep them synchronized */
644 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
645 txq = eth_dev->data->tx_queues[i];
649 cnt = hns3_read_dev(txq, HNS3_RING_TX_PKTNUM_RECORD_REG);
650 stats->rcb_tx_ring_pktnum_rcd += cnt;
651 stats->rcb_tx_ring_pktnum[i] += cnt;
652 rte_stats->obytes += txq->basic_stats.bytes;
655 ret = hns3_update_oerror_stats(hw, false);
657 hns3_err(hw, "update oerror stats failed, ret = %d",
661 rte_stats->oerrors = hw->oerror_stats;
664 * If HW statistics are reset by stats_reset, but a lot of residual
665 * packets exist in the hardware queue and these packets are error
666 * packets, flip overflow may occurred. So return 0 in this case.
668 rte_stats->ipackets =
669 stats->rcb_rx_ring_pktnum_rcd > rte_stats->ierrors ?
670 stats->rcb_rx_ring_pktnum_rcd - rte_stats->ierrors : 0;
671 rte_stats->opackets = stats->rcb_tx_ring_pktnum_rcd -
673 rte_stats->rx_nombuf = eth_dev->data->rx_mbuf_alloc_failed;
679 hns3_stats_reset(struct rte_eth_dev *eth_dev)
681 struct hns3_adapter *hns = eth_dev->data->dev_private;
682 struct hns3_hw *hw = &hns->hw;
683 struct hns3_rx_queue *rxq;
684 struct hns3_tx_queue *txq;
689 * Note: Reading hardware statistics of imissed registers will
692 ret = hns3_update_imissed_stats(hw, true);
694 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
699 * Note: Reading hardware statistics of oerror registers will
702 ret = hns3_update_oerror_stats(hw, true);
704 hns3_err(hw, "clear oerror stats failed, ret = %d",
709 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
710 rxq = eth_dev->data->rx_queues[i];
714 rxq->err_stats.pkt_len_errors = 0;
715 rxq->err_stats.l2_errors = 0;
718 /* Clear all the stats of a rxq in a loop to keep them synchronized */
719 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
720 rxq = eth_dev->data->rx_queues[i];
724 memset(&rxq->basic_stats, 0,
725 sizeof(struct hns3_rx_basic_stats));
727 /* This register is read-clear */
728 (void)hns3_read_dev(rxq, HNS3_RING_RX_PKTNUM_RECORD_REG);
729 rxq->err_stats.pkt_len_errors = 0;
730 rxq->err_stats.l2_errors = 0;
733 /* Clear all the stats of a txq in a loop to keep them synchronized */
734 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
735 txq = eth_dev->data->tx_queues[i];
739 memset(&txq->basic_stats, 0,
740 sizeof(struct hns3_tx_basic_stats));
742 /* This register is read-clear */
743 (void)hns3_read_dev(txq, HNS3_RING_TX_PKTNUM_RECORD_REG);
746 hns3_tqp_stats_clear(hw);
752 hns3_mac_stats_reset(__rte_unused struct rte_eth_dev *dev)
754 struct hns3_adapter *hns = dev->data->dev_private;
755 struct hns3_hw *hw = &hns->hw;
756 struct hns3_mac_stats *mac_stats = &hw->mac_stats;
759 ret = hns3_query_update_mac_stats(dev);
761 hns3_err(hw, "Clear Mac stats fail : %d", ret);
765 memset(mac_stats, 0, sizeof(struct hns3_mac_stats));
771 hns3_get_imissed_stats_num(struct hns3_adapter *hns)
773 #define NO_IMISSED_STATS_NUM 0
774 #define RPU_STATS_ITEM_NUM 1
775 struct hns3_hw *hw = &hns->hw;
777 if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && hns->is_vf)
778 return NO_IMISSED_STATS_NUM;
780 if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2 && !hns->is_vf)
781 return HNS3_NUM_IMISSED_XSTATS;
783 return RPU_STATS_ITEM_NUM;
786 /* This function calculates the number of xstats based on the current config */
788 hns3_xstats_calc_num(struct rte_eth_dev *dev)
790 #define HNS3_PF_VF_RX_COMM_STATS_NUM (HNS3_NUM_RX_BD_ERROR_XSTATS + \
791 HNS3_NUM_RXQ_DFX_XSTATS + \
792 HNS3_NUM_RX_QUEUE_STATS + \
793 HNS3_NUM_RXQ_BASIC_STATS)
794 #define HNS3_PF_VF_TX_COMM_STATS_NUM (HNS3_NUM_TXQ_DFX_XSTATS + \
795 HNS3_NUM_TX_QUEUE_STATS + \
796 HNS3_NUM_TXQ_BASIC_STATS)
798 struct hns3_adapter *hns = dev->data->dev_private;
799 uint16_t nb_rx_q = dev->data->nb_rx_queues;
800 uint16_t nb_tx_q = dev->data->nb_tx_queues;
801 int rx_comm_stats_num = nb_rx_q * HNS3_PF_VF_RX_COMM_STATS_NUM;
802 int tx_comm_stats_num = nb_tx_q * HNS3_PF_VF_TX_COMM_STATS_NUM;
805 stats_num = rx_comm_stats_num + tx_comm_stats_num;
806 stats_num += hns3_get_imissed_stats_num(hns);
809 stats_num += HNS3_NUM_RESET_XSTATS;
811 stats_num += HNS3_FIX_NUM_STATS;
817 hns3_queue_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
820 struct hns3_adapter *hns = dev->data->dev_private;
821 struct hns3_hw *hw = &hns->hw;
825 /* Get rx queue stats */
826 for (j = 0; j < dev->data->nb_rx_queues; j++) {
827 for (i = 0; i < HNS3_NUM_RX_QUEUE_STATS; i++) {
828 reg_offset = hns3_get_tqp_reg_offset(j);
829 xstats[*count].value = hns3_read_dev(hw,
830 reg_offset + hns3_rx_queue_strings[i].offset);
831 xstats[*count].id = *count;
836 /* Get tx queue stats */
837 for (j = 0; j < dev->data->nb_tx_queues; j++) {
838 for (i = 0; i < HNS3_NUM_TX_QUEUE_STATS; i++) {
839 reg_offset = hns3_get_tqp_reg_offset(j);
840 xstats[*count].value = hns3_read_dev(hw,
841 reg_offset + hns3_tx_queue_strings[i].offset);
842 xstats[*count].id = *count;
849 hns3_rxq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
852 struct hns3_rx_dfx_stats *dfx_stats;
853 struct hns3_rx_queue *rxq;
857 for (i = 0; i < dev->data->nb_rx_queues; i++) {
858 rxq = (struct hns3_rx_queue *)dev->data->rx_queues[i];
862 dfx_stats = &rxq->dfx_stats;
863 for (j = 0; j < HNS3_NUM_RXQ_DFX_XSTATS; j++) {
864 val = (char *)dfx_stats +
865 hns3_rxq_dfx_stats_strings[j].offset;
866 xstats[*count].value = *(uint64_t *)val;
867 xstats[*count].id = *count;
874 hns3_txq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
877 struct hns3_tx_dfx_stats *dfx_stats;
878 struct hns3_tx_queue *txq;
882 for (i = 0; i < dev->data->nb_tx_queues; i++) {
883 txq = (struct hns3_tx_queue *)dev->data->tx_queues[i];
887 dfx_stats = &txq->dfx_stats;
888 for (j = 0; j < HNS3_NUM_TXQ_DFX_XSTATS; j++) {
889 val = (char *)dfx_stats +
890 hns3_txq_dfx_stats_strings[j].offset;
891 xstats[*count].value = *(uint64_t *)val;
892 xstats[*count].id = *count;
899 hns3_tqp_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
902 hns3_rxq_dfx_stats_get(dev, xstats, count);
903 hns3_txq_dfx_stats_get(dev, xstats, count);
907 hns3_rxq_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
910 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
911 struct hns3_tqp_stats *stats = &hw->tqp_stats;
912 struct hns3_rx_basic_stats *rxq_stats;
913 struct hns3_rx_queue *rxq;
918 for (i = 0; i < dev->data->nb_rx_queues; i++) {
919 rxq = dev->data->rx_queues[i];
923 cnt = hns3_read_dev(rxq, HNS3_RING_RX_PKTNUM_RECORD_REG);
925 * Read hardware and software in adjacent positions to minimize
926 * the time difference.
928 rxq_stats = &rxq->basic_stats;
929 rxq_stats->errors = rxq->err_stats.l2_errors +
930 rxq->err_stats.pkt_len_errors;
931 stats->rcb_rx_ring_pktnum_rcd += cnt;
932 stats->rcb_rx_ring_pktnum[i] += cnt;
935 * If HW statistics are reset by stats_reset, but a lot of
936 * residual packets exist in the hardware queue and these
937 * packets are error packets, flip overflow may occurred.
938 * So return 0 in this case.
941 stats->rcb_rx_ring_pktnum[i] > rxq_stats->errors ?
942 stats->rcb_rx_ring_pktnum[i] - rxq_stats->errors : 0;
943 for (j = 0; j < HNS3_NUM_RXQ_BASIC_STATS; j++) {
944 val = (char *)rxq_stats +
945 hns3_rxq_basic_stats_strings[j].offset;
946 xstats[*count].value = *(uint64_t *)val;
947 xstats[*count].id = *count;
954 hns3_txq_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
957 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
958 struct hns3_tqp_stats *stats = &hw->tqp_stats;
959 struct hns3_tx_basic_stats *txq_stats;
960 struct hns3_tx_queue *txq;
965 for (i = 0; i < dev->data->nb_tx_queues; i++) {
966 txq = dev->data->tx_queues[i];
970 cnt = hns3_read_dev(txq, HNS3_RING_TX_PKTNUM_RECORD_REG);
971 stats->rcb_tx_ring_pktnum_rcd += cnt;
972 stats->rcb_tx_ring_pktnum[i] += cnt;
974 txq_stats = &txq->basic_stats;
975 txq_stats->packets = stats->rcb_tx_ring_pktnum[i];
977 for (j = 0; j < HNS3_NUM_TXQ_BASIC_STATS; j++) {
978 val = (char *)txq_stats +
979 hns3_txq_basic_stats_strings[j].offset;
980 xstats[*count].value = *(uint64_t *)val;
981 xstats[*count].id = *count;
988 hns3_tqp_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
991 hns3_rxq_basic_stats_get(dev, xstats, count);
992 hns3_txq_basic_stats_get(dev, xstats, count);
996 hns3_imissed_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
999 struct hns3_adapter *hns = dev->data->dev_private;
1000 struct hns3_hw *hw = &hns->hw;
1001 struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats;
1002 int imissed_stats_num;
1007 imissed_stats_num = hns3_get_imissed_stats_num(hns);
1009 for (i = 0; i < imissed_stats_num; i++) {
1010 addr = (char *)imissed_stats +
1011 hns3_imissed_stats_strings[i].offset;
1012 xstats[cnt].value = *(uint64_t *)addr;
1013 xstats[cnt].id = cnt;
1021 * Retrieve extended(tqp | Mac) statistics of an Ethernet device.
1023 * Pointer to Ethernet device.
1025 * A pointer to a table of structure of type *rte_eth_xstat*
1026 * to be filled with device statistics ids and values.
1027 * This parameter can be set to NULL if n is 0.
1029 * The size of the xstats array (number of elements).
1031 * 0 on fail, count(The size of the statistics elements) on success.
1034 hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1037 struct hns3_adapter *hns = dev->data->dev_private;
1038 struct hns3_hw *hw = &hns->hw;
1039 struct hns3_mac_stats *mac_stats = &hw->mac_stats;
1040 struct hns3_reset_stats *reset_stats = &hw->reset.stats;
1041 struct hns3_rx_bd_errors_stats *rx_err_stats;
1042 struct hns3_rx_queue *rxq;
1051 count = hns3_xstats_calc_num(dev);
1057 hns3_tqp_basic_stats_get(dev, xstats, &count);
1060 /* Update Mac stats */
1061 ret = hns3_query_update_mac_stats(dev);
1063 hns3_err(hw, "Update Mac stats fail : %d", ret);
1067 /* Get MAC stats from hw->hw_xstats.mac_stats struct */
1068 for (i = 0; i < HNS3_NUM_MAC_STATS; i++) {
1069 addr = (char *)mac_stats + hns3_mac_strings[i].offset;
1070 xstats[count].value = *(uint64_t *)addr;
1071 xstats[count].id = count;
1076 ret = hns3_update_imissed_stats(hw, false);
1078 hns3_err(hw, "update imissed stats failed, ret = %d",
1083 hns3_imissed_stats_get(dev, xstats, &count);
1085 /* Get the reset stat */
1086 for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) {
1087 addr = (char *)reset_stats + hns3_reset_stats_strings[i].offset;
1088 xstats[count].value = *(uint64_t *)addr;
1089 xstats[count].id = count;
1093 /* Get the Rx BD errors stats */
1094 for (j = 0; j < dev->data->nb_rx_queues; j++) {
1095 for (i = 0; i < HNS3_NUM_RX_BD_ERROR_XSTATS; i++) {
1096 rxq = dev->data->rx_queues[j];
1098 rx_err_stats = &rxq->err_stats;
1099 addr = (char *)rx_err_stats +
1100 hns3_rx_bd_error_strings[i].offset;
1101 xstats[count].value = *(uint64_t *)addr;
1102 xstats[count].id = count;
1108 hns3_tqp_dfx_stats_get(dev, xstats, &count);
1109 hns3_queue_stats_get(dev, xstats, &count);
1115 hns3_tqp_basic_stats_name_get(struct rte_eth_dev *dev,
1116 struct rte_eth_xstat_name *xstats_names,
1121 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1122 for (j = 0; j < HNS3_NUM_RXQ_BASIC_STATS; j++) {
1123 snprintf(xstats_names[*count].name,
1124 sizeof(xstats_names[*count].name),
1126 hns3_rxq_basic_stats_strings[j].name);
1130 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1131 for (j = 0; j < HNS3_NUM_TXQ_BASIC_STATS; j++) {
1132 snprintf(xstats_names[*count].name,
1133 sizeof(xstats_names[*count].name),
1135 hns3_txq_basic_stats_strings[j].name);
1142 hns3_tqp_dfx_stats_name_get(struct rte_eth_dev *dev,
1143 struct rte_eth_xstat_name *xstats_names,
1148 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1149 for (j = 0; j < HNS3_NUM_RXQ_DFX_XSTATS; j++) {
1150 snprintf(xstats_names[*count].name,
1151 sizeof(xstats_names[*count].name),
1153 hns3_rxq_dfx_stats_strings[j].name);
1158 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1159 for (j = 0; j < HNS3_NUM_TXQ_DFX_XSTATS; j++) {
1160 snprintf(xstats_names[*count].name,
1161 sizeof(xstats_names[*count].name),
1163 hns3_txq_dfx_stats_strings[j].name);
1170 hns3_imissed_stats_name_get(struct rte_eth_dev *dev,
1171 struct rte_eth_xstat_name *xstats_names,
1174 struct hns3_adapter *hns = dev->data->dev_private;
1175 uint32_t cnt = *count;
1176 int imissed_stats_num;
1179 imissed_stats_num = hns3_get_imissed_stats_num(hns);
1181 for (i = 0; i < imissed_stats_num; i++) {
1182 snprintf(xstats_names[cnt].name,
1183 sizeof(xstats_names[cnt].name),
1184 "%s", hns3_imissed_stats_strings[i].name);
1192 * Retrieve names of extended statistics of an Ethernet device.
1194 * There is an assumption that 'xstat_names' and 'xstats' arrays are matched
1196 * xstats_names[i].name => xstats[i].value
1198 * And the array index is same with id field of 'struct rte_eth_xstat':
1201 * This assumption makes key-value pair matching less flexible but simpler.
1204 * Pointer to Ethernet device.
1205 * @param xstats_names
1206 * An rte_eth_xstat_name array of at least *size* elements to
1207 * be filled. If set to NULL, the function returns the required number
1210 * The size of the xstats_names array (number of elements).
1212 * - A positive value lower or equal to size: success. The return value
1213 * is the number of entries filled in the stats table.
1216 hns3_dev_xstats_get_names(struct rte_eth_dev *dev,
1217 struct rte_eth_xstat_name *xstats_names,
1218 __rte_unused unsigned int size)
1220 struct hns3_adapter *hns = dev->data->dev_private;
1221 int cnt_stats = hns3_xstats_calc_num(dev);
1225 if (xstats_names == NULL)
1228 hns3_tqp_basic_stats_name_get(dev, xstats_names, &count);
1230 /* Note: size limited checked in rte_eth_xstats_get_names() */
1232 /* Get MAC name from hw->hw_xstats.mac_stats struct */
1233 for (i = 0; i < HNS3_NUM_MAC_STATS; i++) {
1234 snprintf(xstats_names[count].name,
1235 sizeof(xstats_names[count].name),
1236 "%s", hns3_mac_strings[i].name);
1241 hns3_imissed_stats_name_get(dev, xstats_names, &count);
1243 for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) {
1244 snprintf(xstats_names[count].name,
1245 sizeof(xstats_names[count].name),
1246 "%s", hns3_reset_stats_strings[i].name);
1250 for (j = 0; j < dev->data->nb_rx_queues; j++) {
1251 for (i = 0; i < HNS3_NUM_RX_BD_ERROR_XSTATS; i++) {
1252 snprintf(xstats_names[count].name,
1253 sizeof(xstats_names[count].name),
1255 hns3_rx_bd_error_strings[i].name);
1260 hns3_tqp_dfx_stats_name_get(dev, xstats_names, &count);
1262 for (j = 0; j < dev->data->nb_rx_queues; j++) {
1263 for (i = 0; i < HNS3_NUM_RX_QUEUE_STATS; i++) {
1264 snprintf(xstats_names[count].name,
1265 sizeof(xstats_names[count].name),
1266 "rx_q%u_%s", j, hns3_rx_queue_strings[i].name);
1271 for (j = 0; j < dev->data->nb_tx_queues; j++) {
1272 for (i = 0; i < HNS3_NUM_TX_QUEUE_STATS; i++) {
1273 snprintf(xstats_names[count].name,
1274 sizeof(xstats_names[count].name),
1275 "tx_q%u_%s", j, hns3_tx_queue_strings[i].name);
1284 * Retrieve extended statistics of an Ethernet device.
1287 * Pointer to Ethernet device.
1289 * A pointer to an ids array passed by application. This tells which
1290 * statistics values function should retrieve. This parameter
1291 * can be set to NULL if size is 0. In this case function will retrieve
1292 * all avalible statistics.
1294 * A pointer to a table to be filled with device statistics values.
1296 * The size of the ids array (number of elements).
1298 * - A positive value lower or equal to size: success. The return value
1299 * is the number of entries filled in the stats table.
1300 * - A positive value higher than size: error, the given statistics table
1301 * is too small. The return value corresponds to the size that should
1302 * be given to succeed. The entries in the table are not valid and
1303 * shall not be used by the caller.
1307 hns3_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1308 uint64_t *values, uint32_t size)
1310 const uint32_t cnt_stats = hns3_xstats_calc_num(dev);
1311 struct hns3_adapter *hns = dev->data->dev_private;
1312 struct rte_eth_xstat *values_copy;
1313 struct hns3_hw *hw = &hns->hw;
1314 uint32_t count_value;
1318 if (ids == NULL && values == NULL)
1322 if (size < cnt_stats)
1325 len = cnt_stats * sizeof(struct rte_eth_xstat);
1326 values_copy = rte_zmalloc("hns3_xstats_values", len, 0);
1327 if (values_copy == NULL) {
1328 hns3_err(hw, "Failed to allocate 0x%" PRIx64 " bytes needed "
1329 "to store statistics values", len);
1333 count_value = hns3_dev_xstats_get(dev, values_copy, cnt_stats);
1334 if (count_value != cnt_stats) {
1335 rte_free(values_copy);
1339 if (ids == NULL && values != NULL) {
1340 for (i = 0; i < cnt_stats; i++)
1341 memcpy(&values[i], &values_copy[i].value,
1344 rte_free(values_copy);
1348 for (i = 0; i < size; i++) {
1349 if (ids[i] >= cnt_stats) {
1350 hns3_err(hw, "ids[%u] (%" PRIu64 ") is invalid, "
1351 "should < %u", i, ids[i], cnt_stats);
1352 rte_free(values_copy);
1355 memcpy(&values[i], &values_copy[ids[i]].value,
1359 rte_free(values_copy);
1364 * Retrieve names of extended statistics of an Ethernet device.
1367 * Pointer to Ethernet device.
1369 * IDs array given by app to retrieve specific statistics
1370 * @param xstats_names
1371 * An rte_eth_xstat_name array of at least *size* elements to
1372 * be filled. If set to NULL, the function returns the required number
1375 * The size of the xstats_names array (number of elements).
1377 * - A positive value lower or equal to size: success. The return value
1378 * is the number of entries filled in the stats table.
1379 * - A positive value higher than size: error, the given statistics table
1380 * is too small. The return value corresponds to the size that should
1381 * be given to succeed. The entries in the table are not valid and
1382 * shall not be used by the caller.
1385 hns3_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
1386 const uint64_t *ids,
1387 struct rte_eth_xstat_name *xstats_names,
1390 const uint32_t cnt_stats = hns3_xstats_calc_num(dev);
1391 struct hns3_adapter *hns = dev->data->dev_private;
1392 struct rte_eth_xstat_name *names_copy;
1393 struct hns3_hw *hw = &hns->hw;
1397 if (xstats_names == NULL)
1401 if (size < cnt_stats)
1404 return hns3_dev_xstats_get_names(dev, xstats_names, cnt_stats);
1407 len = cnt_stats * sizeof(struct rte_eth_xstat_name);
1408 names_copy = rte_zmalloc("hns3_xstats_names", len, 0);
1409 if (names_copy == NULL) {
1410 hns3_err(hw, "Failed to allocate 0x%" PRIx64 " bytes needed "
1411 "to store statistics names", len);
1415 (void)hns3_dev_xstats_get_names(dev, names_copy, cnt_stats);
1417 for (i = 0; i < size; i++) {
1418 if (ids[i] >= cnt_stats) {
1419 hns3_err(hw, "ids[%u] (%" PRIu64 ") is invalid, "
1420 "should < %u", i, ids[i], cnt_stats);
1421 rte_free(names_copy);
1424 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1425 "%s", names_copy[ids[i]].name);
1428 rte_free(names_copy);
1433 hns3_tqp_dfx_stats_clear(struct rte_eth_dev *dev)
1435 struct hns3_rx_queue *rxq;
1436 struct hns3_tx_queue *txq;
1439 /* Clear Rx dfx stats */
1440 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1441 rxq = dev->data->rx_queues[i];
1443 memset(&rxq->dfx_stats, 0,
1444 sizeof(struct hns3_rx_dfx_stats));
1447 /* Clear Tx dfx stats */
1448 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1449 txq = dev->data->tx_queues[i];
1451 memset(&txq->dfx_stats, 0,
1452 sizeof(struct hns3_tx_dfx_stats));
1457 hns3_dev_xstats_reset(struct rte_eth_dev *dev)
1459 struct hns3_adapter *hns = dev->data->dev_private;
1462 /* Clear tqp stats */
1463 ret = hns3_stats_reset(dev);
1467 hns3_tqp_dfx_stats_clear(dev);
1469 /* Clear reset stats */
1470 memset(&hns->hw.reset.stats, 0, sizeof(struct hns3_reset_stats));
1475 /* HW registers are cleared on read */
1476 ret = hns3_mac_stats_reset(dev);
1484 hns3_tqp_stats_init(struct hns3_hw *hw)
1486 struct hns3_tqp_stats *tqp_stats = &hw->tqp_stats;
1488 tqp_stats->rcb_rx_ring_pktnum = rte_zmalloc("hns3_rx_ring_pkt_num",
1489 sizeof(uint64_t) * hw->tqps_num, 0);
1490 if (tqp_stats->rcb_rx_ring_pktnum == NULL) {
1491 hns3_err(hw, "failed to allocate rx_ring pkt_num.");
1495 tqp_stats->rcb_tx_ring_pktnum = rte_zmalloc("hns3_tx_ring_pkt_num",
1496 sizeof(uint64_t) * hw->tqps_num, 0);
1497 if (tqp_stats->rcb_tx_ring_pktnum == NULL) {
1498 hns3_err(hw, "failed to allocate tx_ring pkt_num.");
1499 rte_free(tqp_stats->rcb_rx_ring_pktnum);
1500 tqp_stats->rcb_rx_ring_pktnum = NULL;
1508 hns3_tqp_stats_uninit(struct hns3_hw *hw)
1510 struct hns3_tqp_stats *tqp_stats = &hw->tqp_stats;
1512 rte_free(tqp_stats->rcb_rx_ring_pktnum);
1513 tqp_stats->rcb_rx_ring_pktnum = NULL;
1514 rte_free(tqp_stats->rcb_tx_ring_pktnum);
1515 tqp_stats->rcb_tx_ring_pktnum = NULL;
1519 hns3_tqp_stats_clear(struct hns3_hw *hw)
1521 struct hns3_tqp_stats *stats = &hw->tqp_stats;
1523 stats->rcb_rx_ring_pktnum_rcd = 0;
1524 stats->rcb_tx_ring_pktnum_rcd = 0;
1525 memset(stats->rcb_rx_ring_pktnum, 0, sizeof(uint64_t) * hw->tqps_num);
1526 memset(stats->rcb_tx_ring_pktnum, 0, sizeof(uint64_t) * hw->tqps_num);