1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #include <rte_ethdev.h>
7 #include <rte_malloc.h>
9 #include "hns3_ethdev.h"
10 #include "hns3_rxtx.h"
11 #include "hns3_logs.h"
12 #include "hns3_regs.h"
15 static const struct hns3_xstats_name_offset hns3_mac_strings[] = {
16 {"mac_tx_mac_pause_num",
17 HNS3_MAC_STATS_OFFSET(mac_tx_mac_pause_num)},
18 {"mac_rx_mac_pause_num",
19 HNS3_MAC_STATS_OFFSET(mac_rx_mac_pause_num)},
20 {"mac_tx_control_pkt_num",
21 HNS3_MAC_STATS_OFFSET(mac_tx_ctrl_pkt_num)},
22 {"mac_rx_control_pkt_num",
23 HNS3_MAC_STATS_OFFSET(mac_rx_ctrl_pkt_num)},
24 {"mac_tx_pfc_pkt_num",
25 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pause_pkt_num)},
26 {"mac_tx_pfc_pri0_pkt_num",
27 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri0_pkt_num)},
28 {"mac_tx_pfc_pri1_pkt_num",
29 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri1_pkt_num)},
30 {"mac_tx_pfc_pri2_pkt_num",
31 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri2_pkt_num)},
32 {"mac_tx_pfc_pri3_pkt_num",
33 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri3_pkt_num)},
34 {"mac_tx_pfc_pri4_pkt_num",
35 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri4_pkt_num)},
36 {"mac_tx_pfc_pri5_pkt_num",
37 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri5_pkt_num)},
38 {"mac_tx_pfc_pri6_pkt_num",
39 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri6_pkt_num)},
40 {"mac_tx_pfc_pri7_pkt_num",
41 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri7_pkt_num)},
42 {"mac_rx_pfc_pkt_num",
43 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pause_pkt_num)},
44 {"mac_rx_pfc_pri0_pkt_num",
45 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri0_pkt_num)},
46 {"mac_rx_pfc_pri1_pkt_num",
47 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri1_pkt_num)},
48 {"mac_rx_pfc_pri2_pkt_num",
49 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri2_pkt_num)},
50 {"mac_rx_pfc_pri3_pkt_num",
51 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri3_pkt_num)},
52 {"mac_rx_pfc_pri4_pkt_num",
53 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri4_pkt_num)},
54 {"mac_rx_pfc_pri5_pkt_num",
55 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri5_pkt_num)},
56 {"mac_rx_pfc_pri6_pkt_num",
57 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri6_pkt_num)},
58 {"mac_rx_pfc_pri7_pkt_num",
59 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri7_pkt_num)},
60 {"mac_tx_total_pkt_num",
61 HNS3_MAC_STATS_OFFSET(mac_tx_total_pkt_num)},
62 {"mac_tx_total_oct_num",
63 HNS3_MAC_STATS_OFFSET(mac_tx_total_oct_num)},
64 {"mac_tx_good_pkt_num",
65 HNS3_MAC_STATS_OFFSET(mac_tx_good_pkt_num)},
66 {"mac_tx_bad_pkt_num",
67 HNS3_MAC_STATS_OFFSET(mac_tx_bad_pkt_num)},
68 {"mac_tx_good_oct_num",
69 HNS3_MAC_STATS_OFFSET(mac_tx_good_oct_num)},
70 {"mac_tx_bad_oct_num",
71 HNS3_MAC_STATS_OFFSET(mac_tx_bad_oct_num)},
72 {"mac_tx_uni_pkt_num",
73 HNS3_MAC_STATS_OFFSET(mac_tx_uni_pkt_num)},
74 {"mac_tx_multi_pkt_num",
75 HNS3_MAC_STATS_OFFSET(mac_tx_multi_pkt_num)},
76 {"mac_tx_broad_pkt_num",
77 HNS3_MAC_STATS_OFFSET(mac_tx_broad_pkt_num)},
78 {"mac_tx_undersize_pkt_num",
79 HNS3_MAC_STATS_OFFSET(mac_tx_undersize_pkt_num)},
80 {"mac_tx_oversize_pkt_num",
81 HNS3_MAC_STATS_OFFSET(mac_tx_oversize_pkt_num)},
82 {"mac_tx_64_oct_pkt_num",
83 HNS3_MAC_STATS_OFFSET(mac_tx_64_oct_pkt_num)},
84 {"mac_tx_65_127_oct_pkt_num",
85 HNS3_MAC_STATS_OFFSET(mac_tx_65_127_oct_pkt_num)},
86 {"mac_tx_128_255_oct_pkt_num",
87 HNS3_MAC_STATS_OFFSET(mac_tx_128_255_oct_pkt_num)},
88 {"mac_tx_256_511_oct_pkt_num",
89 HNS3_MAC_STATS_OFFSET(mac_tx_256_511_oct_pkt_num)},
90 {"mac_tx_512_1023_oct_pkt_num",
91 HNS3_MAC_STATS_OFFSET(mac_tx_512_1023_oct_pkt_num)},
92 {"mac_tx_1024_1518_oct_pkt_num",
93 HNS3_MAC_STATS_OFFSET(mac_tx_1024_1518_oct_pkt_num)},
94 {"mac_tx_1519_2047_oct_pkt_num",
95 HNS3_MAC_STATS_OFFSET(mac_tx_1519_2047_oct_pkt_num)},
96 {"mac_tx_2048_4095_oct_pkt_num",
97 HNS3_MAC_STATS_OFFSET(mac_tx_2048_4095_oct_pkt_num)},
98 {"mac_tx_4096_8191_oct_pkt_num",
99 HNS3_MAC_STATS_OFFSET(mac_tx_4096_8191_oct_pkt_num)},
100 {"mac_tx_8192_9216_oct_pkt_num",
101 HNS3_MAC_STATS_OFFSET(mac_tx_8192_9216_oct_pkt_num)},
102 {"mac_tx_9217_12287_oct_pkt_num",
103 HNS3_MAC_STATS_OFFSET(mac_tx_9217_12287_oct_pkt_num)},
104 {"mac_tx_12288_16383_oct_pkt_num",
105 HNS3_MAC_STATS_OFFSET(mac_tx_12288_16383_oct_pkt_num)},
106 {"mac_tx_1519_max_good_pkt_num",
107 HNS3_MAC_STATS_OFFSET(mac_tx_1519_max_good_oct_pkt_num)},
108 {"mac_tx_1519_max_bad_pkt_num",
109 HNS3_MAC_STATS_OFFSET(mac_tx_1519_max_bad_oct_pkt_num)},
110 {"mac_rx_total_pkt_num",
111 HNS3_MAC_STATS_OFFSET(mac_rx_total_pkt_num)},
112 {"mac_rx_total_oct_num",
113 HNS3_MAC_STATS_OFFSET(mac_rx_total_oct_num)},
114 {"mac_rx_good_pkt_num",
115 HNS3_MAC_STATS_OFFSET(mac_rx_good_pkt_num)},
116 {"mac_rx_bad_pkt_num",
117 HNS3_MAC_STATS_OFFSET(mac_rx_bad_pkt_num)},
118 {"mac_rx_good_oct_num",
119 HNS3_MAC_STATS_OFFSET(mac_rx_good_oct_num)},
120 {"mac_rx_bad_oct_num",
121 HNS3_MAC_STATS_OFFSET(mac_rx_bad_oct_num)},
122 {"mac_rx_uni_pkt_num",
123 HNS3_MAC_STATS_OFFSET(mac_rx_uni_pkt_num)},
124 {"mac_rx_multi_pkt_num",
125 HNS3_MAC_STATS_OFFSET(mac_rx_multi_pkt_num)},
126 {"mac_rx_broad_pkt_num",
127 HNS3_MAC_STATS_OFFSET(mac_rx_broad_pkt_num)},
128 {"mac_rx_undersize_pkt_num",
129 HNS3_MAC_STATS_OFFSET(mac_rx_undersize_pkt_num)},
130 {"mac_rx_oversize_pkt_num",
131 HNS3_MAC_STATS_OFFSET(mac_rx_oversize_pkt_num)},
132 {"mac_rx_64_oct_pkt_num",
133 HNS3_MAC_STATS_OFFSET(mac_rx_64_oct_pkt_num)},
134 {"mac_rx_65_127_oct_pkt_num",
135 HNS3_MAC_STATS_OFFSET(mac_rx_65_127_oct_pkt_num)},
136 {"mac_rx_128_255_oct_pkt_num",
137 HNS3_MAC_STATS_OFFSET(mac_rx_128_255_oct_pkt_num)},
138 {"mac_rx_256_511_oct_pkt_num",
139 HNS3_MAC_STATS_OFFSET(mac_rx_256_511_oct_pkt_num)},
140 {"mac_rx_512_1023_oct_pkt_num",
141 HNS3_MAC_STATS_OFFSET(mac_rx_512_1023_oct_pkt_num)},
142 {"mac_rx_1024_1518_oct_pkt_num",
143 HNS3_MAC_STATS_OFFSET(mac_rx_1024_1518_oct_pkt_num)},
144 {"mac_rx_1519_2047_oct_pkt_num",
145 HNS3_MAC_STATS_OFFSET(mac_rx_1519_2047_oct_pkt_num)},
146 {"mac_rx_2048_4095_oct_pkt_num",
147 HNS3_MAC_STATS_OFFSET(mac_rx_2048_4095_oct_pkt_num)},
148 {"mac_rx_4096_8191_oct_pkt_num",
149 HNS3_MAC_STATS_OFFSET(mac_rx_4096_8191_oct_pkt_num)},
150 {"mac_rx_8192_9216_oct_pkt_num",
151 HNS3_MAC_STATS_OFFSET(mac_rx_8192_9216_oct_pkt_num)},
152 {"mac_rx_9217_12287_oct_pkt_num",
153 HNS3_MAC_STATS_OFFSET(mac_rx_9217_12287_oct_pkt_num)},
154 {"mac_rx_12288_16383_oct_pkt_num",
155 HNS3_MAC_STATS_OFFSET(mac_rx_12288_16383_oct_pkt_num)},
156 {"mac_rx_1519_max_good_pkt_num",
157 HNS3_MAC_STATS_OFFSET(mac_rx_1519_max_good_oct_pkt_num)},
158 {"mac_rx_1519_max_bad_pkt_num",
159 HNS3_MAC_STATS_OFFSET(mac_rx_1519_max_bad_oct_pkt_num)},
160 {"mac_tx_fragment_pkt_num",
161 HNS3_MAC_STATS_OFFSET(mac_tx_fragment_pkt_num)},
162 {"mac_tx_undermin_pkt_num",
163 HNS3_MAC_STATS_OFFSET(mac_tx_undermin_pkt_num)},
164 {"mac_tx_jabber_pkt_num",
165 HNS3_MAC_STATS_OFFSET(mac_tx_jabber_pkt_num)},
166 {"mac_tx_err_all_pkt_num",
167 HNS3_MAC_STATS_OFFSET(mac_tx_err_all_pkt_num)},
168 {"mac_tx_from_app_good_pkt_num",
169 HNS3_MAC_STATS_OFFSET(mac_tx_from_app_good_pkt_num)},
170 {"mac_tx_from_app_bad_pkt_num",
171 HNS3_MAC_STATS_OFFSET(mac_tx_from_app_bad_pkt_num)},
172 {"mac_rx_fragment_pkt_num",
173 HNS3_MAC_STATS_OFFSET(mac_rx_fragment_pkt_num)},
174 {"mac_rx_undermin_pkt_num",
175 HNS3_MAC_STATS_OFFSET(mac_rx_undermin_pkt_num)},
176 {"mac_rx_jabber_pkt_num",
177 HNS3_MAC_STATS_OFFSET(mac_rx_jabber_pkt_num)},
178 {"mac_rx_fcs_err_pkt_num",
179 HNS3_MAC_STATS_OFFSET(mac_rx_fcs_err_pkt_num)},
180 {"mac_rx_send_app_good_pkt_num",
181 HNS3_MAC_STATS_OFFSET(mac_rx_send_app_good_pkt_num)},
182 {"mac_rx_send_app_bad_pkt_num",
183 HNS3_MAC_STATS_OFFSET(mac_rx_send_app_bad_pkt_num)}
186 static const struct hns3_xstats_name_offset hns3_error_int_stats_strings[] = {
187 {"MAC_AFIFO_TNL_INT_R",
188 HNS3_ERR_INT_STATS_FIELD_OFFSET(mac_afifo_tnl_int_cnt)},
189 {"PPU_MPF_ABNORMAL_INT_ST2_MSIX",
190 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_msix_cnt)},
191 {"SSU_PORT_BASED_ERR_INT_MSIX",
192 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_pf_int_cnt)},
193 {"PPP_PF_ABNORMAL_INT_ST0",
194 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_pf_abnormal_int_cnt)},
195 {"PPU_PF_ABNORMAL_INT_ST_MSIX",
196 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_msix_cnt)},
197 {"IMP_TCM_ECC_INT_STS",
198 HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_tcm_ecc_int_cnt)},
199 {"CMDQ_MEM_ECC_INT_STS",
200 HNS3_ERR_INT_STATS_FIELD_OFFSET(cmdq_mem_ecc_int_cnt)},
201 {"IMP_RD_POISON_INT_STS",
202 HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_rd_poison_int_cnt)},
203 {"TQP_INT_ECC_INT_STS",
204 HNS3_ERR_INT_STATS_FIELD_OFFSET(tqp_int_ecc_int_cnt)},
206 HNS3_ERR_INT_STATS_FIELD_OFFSET(msix_ecc_int_cnt)},
207 {"SSU_ECC_MULTI_BIT_INT_0",
208 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_0_cnt)},
209 {"SSU_ECC_MULTI_BIT_INT_1",
210 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_1_cnt)},
211 {"SSU_COMMON_ERR_INT",
212 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_common_ecc_int_cnt)},
214 HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_int_cnt)},
215 {"PPP_MPF_ABNORMAL_INT_ST1",
216 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st1_cnt)},
217 {"PPP_MPF_ABNORMAL_INT_ST3",
218 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st3_cnt)},
219 {"PPU_MPF_ABNORMAL_INT_ST1",
220 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st1_cnt)},
221 {"PPU_MPF_ABNORMAL_INT_ST2_RAS",
222 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_ras_cnt)},
223 {"PPU_MPF_ABNORMAL_INT_ST3",
224 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st3_cnt)},
226 HNS3_ERR_INT_STATS_FIELD_OFFSET(tm_sch_int_cnt)},
228 HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_fifo_int_cnt)},
230 HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_ecc_int_cnt)},
232 HNS3_ERR_INT_STATS_FIELD_OFFSET(ncsi_ecc_int_cnt)},
233 {"SSU_PORT_BASED_ERR_INT_RAS",
234 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_err_int_cnt)},
235 {"SSU_FIFO_OVERFLOW_INT",
236 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_fifo_overflow_int_cnt)},
238 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ets_tcg_int_cnt)},
239 {"IGU_EGU_TNL_INT_STS",
240 HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_egu_tnl_int_cnt)},
241 {"PPU_PF_ABNORMAL_INT_ST_RAS",
242 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_ras_cnt)},
245 /* The statistic of reset */
246 static const struct hns3_xstats_name_offset hns3_reset_stats_strings[] = {
248 HNS3_RESET_STATS_FIELD_OFFSET(request_cnt)},
250 HNS3_RESET_STATS_FIELD_OFFSET(global_cnt)},
252 HNS3_RESET_STATS_FIELD_OFFSET(imp_cnt)},
254 HNS3_RESET_STATS_FIELD_OFFSET(exec_cnt)},
255 {"RESET_SUCCESS_CNT",
256 HNS3_RESET_STATS_FIELD_OFFSET(success_cnt)},
258 HNS3_RESET_STATS_FIELD_OFFSET(fail_cnt)},
260 HNS3_RESET_STATS_FIELD_OFFSET(merge_cnt)}
263 /* The statistic of errors in Rx BD */
264 static const struct hns3_xstats_name_offset hns3_rx_bd_error_strings[] = {
265 {"RX_PKT_LEN_ERRORS",
266 HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(pkt_len_errors)},
268 HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(l2_errors)},
269 {"RX_L3_CHECKSUM_ERRORS",
270 HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(l3_csum_errors)},
271 {"RX_L4_CHECKSUM_ERRORS",
272 HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(l4_csum_errors)},
273 {"RX_OL3_CHECKSUM_ERRORS",
274 HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(ol3_csum_errors)},
275 {"RX_OL4_CHECKSUM_ERRORS",
276 HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(ol4_csum_errors)}
279 /* The statistic of the Tx errors */
280 static const struct hns3_xstats_name_offset hns3_tx_errors_strings[] = {
281 {"TX_OVER_LENGTH_PKT_CNT",
282 HNS3_TX_ERROR_STATS_FIELD_OFFSET(over_length_pkt_cnt)},
283 {"TX_EXCEED_LIMITED_BD_PKT_CNT",
284 HNS3_TX_ERROR_STATS_FIELD_OFFSET(exceed_limit_bd_pkt_cnt)},
285 {"TX_EXCEED_LIMITED_BD_PKT_REASSEMBLE_FAIL_CNT",
286 HNS3_TX_ERROR_STATS_FIELD_OFFSET(exceed_limit_bd_reassem_fail)},
287 {"TX_UNSUPPORTED_TUNNEL_PKT_CNT",
288 HNS3_TX_ERROR_STATS_FIELD_OFFSET(unsupported_tunnel_pkt_cnt)},
289 {"TX_QUEUE_FULL_CNT",
290 HNS3_TX_ERROR_STATS_FIELD_OFFSET(queue_full_cnt)},
291 {"TX_SHORT_PKT_PAD_FAIL_CNT",
292 HNS3_TX_ERROR_STATS_FIELD_OFFSET(pkt_padding_fail_cnt)}
295 /* The statistic of rx queue */
296 static const struct hns3_xstats_name_offset hns3_rx_queue_strings[] = {
297 {"RX_QUEUE_FBD", HNS3_RING_RX_FBDNUM_REG}
300 /* The statistic of tx queue */
301 static const struct hns3_xstats_name_offset hns3_tx_queue_strings[] = {
302 {"TX_QUEUE_FBD", HNS3_RING_TX_FBDNUM_REG}
305 #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \
306 sizeof(hns3_mac_strings[0]))
308 #define HNS3_NUM_ERROR_INT_XSTATS (sizeof(hns3_error_int_stats_strings) / \
309 sizeof(hns3_error_int_stats_strings[0]))
311 #define HNS3_NUM_RESET_XSTATS (sizeof(hns3_reset_stats_strings) / \
312 sizeof(hns3_reset_stats_strings[0]))
314 #define HNS3_NUM_RX_BD_ERROR_XSTATS (sizeof(hns3_rx_bd_error_strings) / \
315 sizeof(hns3_rx_bd_error_strings[0]))
317 #define HNS3_NUM_TX_ERRORS_XSTATS (sizeof(hns3_tx_errors_strings) / \
318 sizeof(hns3_tx_errors_strings[0]))
320 #define HNS3_NUM_RX_QUEUE_STATS (sizeof(hns3_rx_queue_strings) / \
321 sizeof(hns3_rx_queue_strings[0]))
323 #define HNS3_NUM_TX_QUEUE_STATS (sizeof(hns3_tx_queue_strings) / \
324 sizeof(hns3_tx_queue_strings[0]))
326 #define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_ERROR_INT_XSTATS + \
327 HNS3_NUM_RESET_XSTATS)
329 static void hns3_tqp_stats_clear(struct hns3_hw *hw);
332 * Query all the MAC statistics data of Network ICL command ,opcode id: 0x0034.
333 * This command is used before send 'query_mac_stat command', the descriptor
334 * number of 'query_mac_stat command' must match with reg_num in this command.
336 * Pointer to structure hns3_hw.
341 hns3_update_mac_stats(struct hns3_hw *hw, const uint32_t desc_num)
343 uint64_t *data = (uint64_t *)(&hw->mac_stats);
344 struct hns3_cmd_desc *desc;
349 desc = rte_malloc("hns3_mac_desc",
350 desc_num * sizeof(struct hns3_cmd_desc), 0);
352 hns3_err(hw, "Mac_update_stats alloced desc malloc fail");
356 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_STATS_MAC_ALL, true);
357 ret = hns3_cmd_send(hw, desc, desc_num);
359 hns3_err(hw, "Update complete MAC pkt stats fail : %d", ret);
364 for (i = 0; i < desc_num; i++) {
365 /* For special opcode 0034, only the first desc has the head */
367 desc_data = (uint64_t *)(&desc[i].data[0]);
368 n = HNS3_RD_FIRST_STATS_NUM;
370 desc_data = (uint64_t *)(&desc[i]);
371 n = HNS3_RD_OTHER_STATS_NUM;
374 for (k = 0; k < n; k++) {
375 *data += rte_le_to_cpu_64(*desc_data);
386 * Query Mac stat reg num command ,opcode id: 0x0033.
387 * This command is used before send 'query_mac_stat command', the descriptor
388 * number of 'query_mac_stat command' must match with reg_num in this command.
390 * Pointer to structure rte_eth_stats.
395 hns3_mac_query_reg_num(struct rte_eth_dev *dev, uint32_t *desc_num)
397 struct hns3_adapter *hns = dev->data->dev_private;
398 struct hns3_hw *hw = &hns->hw;
399 struct hns3_cmd_desc desc;
404 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_REG_NUM, true);
405 ret = hns3_cmd_send(hw, &desc, 1);
410 * The num of MAC statistics registers that are provided by IMP in this
413 desc_data = (uint32_t *)(&desc.data[0]);
414 reg_num = rte_le_to_cpu_32(*desc_data);
417 * The descriptor number of 'query_additional_mac_stat command' is
418 * '1 + (reg_num-3)/4 + ((reg_num-3)%4 !=0)';
419 * This value is 83 in this version
421 *desc_num = 1 + ((reg_num - 3) >> 2) +
422 (uint32_t)(((reg_num - 3) & 0x3) ? 1 : 0);
428 hns3_query_update_mac_stats(struct rte_eth_dev *dev)
430 struct hns3_adapter *hns = dev->data->dev_private;
431 struct hns3_hw *hw = &hns->hw;
435 ret = hns3_mac_query_reg_num(dev, &desc_num);
437 ret = hns3_update_mac_stats(hw, desc_num);
439 hns3_err(hw, "Query mac reg num fail : %d", ret);
443 /* Get tqp stats from register */
445 hns3_update_tqp_stats(struct hns3_hw *hw)
447 struct hns3_tqp_stats *stats = &hw->tqp_stats;
448 struct hns3_cmd_desc desc;
453 for (i = 0; i < hw->tqps_num; i++) {
454 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_RX_STATUS,
457 desc.data[0] = rte_cpu_to_le_32((uint32_t)i);
458 ret = hns3_cmd_send(hw, &desc, 1);
460 hns3_err(hw, "Failed to query RX No.%u queue stat: %d",
464 cnt = rte_le_to_cpu_32(desc.data[1]);
465 stats->rcb_rx_ring_pktnum_rcd += cnt;
466 stats->rcb_rx_ring_pktnum[i] += cnt;
468 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_TX_STATUS,
471 desc.data[0] = rte_cpu_to_le_32((uint32_t)i);
472 ret = hns3_cmd_send(hw, &desc, 1);
474 hns3_err(hw, "Failed to query TX No.%u queue stat: %d",
478 cnt = rte_le_to_cpu_32(desc.data[1]);
479 stats->rcb_tx_ring_pktnum_rcd += cnt;
480 stats->rcb_tx_ring_pktnum[i] += cnt;
487 * Query tqp tx queue statistics ,opcode id: 0x0B03.
488 * Query tqp rx queue statistics ,opcode id: 0x0B13.
489 * Get all statistics of a port.
491 * Pointer to Ethernet device.
493 * Pointer to structure rte_eth_stats.
498 hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats)
500 struct hns3_adapter *hns = eth_dev->data->dev_private;
501 struct hns3_hw *hw = &hns->hw;
502 struct hns3_tqp_stats *stats = &hw->tqp_stats;
503 struct hns3_rx_queue *rxq;
504 struct hns3_tx_queue *txq;
510 /* Update tqp stats by read register */
511 ret = hns3_update_tqp_stats(hw);
513 hns3_err(hw, "Update tqp stats fail : %d", ret);
517 /* Get the error stats of received packets */
518 num = RTE_MIN(RTE_ETHDEV_QUEUE_STAT_CNTRS, eth_dev->data->nb_rx_queues);
519 for (i = 0; i != num; ++i) {
520 rxq = eth_dev->data->rx_queues[i];
522 cnt = rxq->l2_errors + rxq->pkt_len_errors;
523 rte_stats->q_errors[i] = cnt;
524 rte_stats->q_ipackets[i] =
525 stats->rcb_rx_ring_pktnum[i] - cnt;
526 rte_stats->ierrors += cnt;
529 /* Get the error stats of transmitted packets */
530 num = RTE_MIN(RTE_ETHDEV_QUEUE_STAT_CNTRS, eth_dev->data->nb_tx_queues);
531 for (i = 0; i < num; i++) {
532 txq = eth_dev->data->tx_queues[i];
534 rte_stats->q_opackets[i] = stats->rcb_tx_ring_pktnum[i];
537 rte_stats->oerrors = 0;
538 rte_stats->ipackets = stats->rcb_rx_ring_pktnum_rcd -
540 rte_stats->opackets = stats->rcb_tx_ring_pktnum_rcd -
542 rte_stats->rx_nombuf = eth_dev->data->rx_mbuf_alloc_failed;
548 hns3_stats_reset(struct rte_eth_dev *eth_dev)
550 struct hns3_adapter *hns = eth_dev->data->dev_private;
551 struct hns3_hw *hw = &hns->hw;
552 struct hns3_cmd_desc desc_reset;
553 struct hns3_rx_queue *rxq;
558 * Note: Reading hardware statistics of rx/tx queue packet number
561 for (i = 0; i < hw->tqps_num; i++) {
562 hns3_cmd_setup_basic_desc(&desc_reset, HNS3_OPC_QUERY_RX_STATUS,
564 desc_reset.data[0] = rte_cpu_to_le_32((uint32_t)i);
565 ret = hns3_cmd_send(hw, &desc_reset, 1);
567 hns3_err(hw, "Failed to reset RX No.%u queue stat: %d",
572 hns3_cmd_setup_basic_desc(&desc_reset, HNS3_OPC_QUERY_TX_STATUS,
574 desc_reset.data[0] = rte_cpu_to_le_32((uint32_t)i);
575 ret = hns3_cmd_send(hw, &desc_reset, 1);
577 hns3_err(hw, "Failed to reset TX No.%u queue stat: %d",
584 * Clear soft stats of rx error packet which will be dropped
587 for (i = 0; i < eth_dev->data->nb_rx_queues; ++i) {
588 rxq = eth_dev->data->rx_queues[i];
590 rxq->pkt_len_errors = 0;
595 hns3_tqp_stats_clear(hw);
601 hns3_mac_stats_reset(__rte_unused struct rte_eth_dev *dev)
603 struct hns3_adapter *hns = dev->data->dev_private;
604 struct hns3_hw *hw = &hns->hw;
605 struct hns3_mac_stats *mac_stats = &hw->mac_stats;
608 ret = hns3_query_update_mac_stats(dev);
610 hns3_err(hw, "Clear Mac stats fail : %d", ret);
614 memset(mac_stats, 0, sizeof(struct hns3_mac_stats));
619 /* This function calculates the number of xstats based on the current config */
621 hns3_xstats_calc_num(struct rte_eth_dev *dev)
623 struct hns3_adapter *hns = dev->data->dev_private;
624 int bderr_stats = dev->data->nb_rx_queues * HNS3_NUM_RX_BD_ERROR_XSTATS;
625 int tx_err_stats = dev->data->nb_tx_queues * HNS3_NUM_TX_ERRORS_XSTATS;
626 int rx_queue_stats = dev->data->nb_rx_queues * HNS3_NUM_RX_QUEUE_STATS;
627 int tx_queue_stats = dev->data->nb_tx_queues * HNS3_NUM_TX_QUEUE_STATS;
630 return bderr_stats + tx_err_stats + rx_queue_stats +
631 tx_queue_stats + HNS3_NUM_RESET_XSTATS;
633 return bderr_stats + tx_err_stats + rx_queue_stats +
634 tx_queue_stats + HNS3_FIX_NUM_STATS;
638 hns3_get_queue_stats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
641 struct hns3_adapter *hns = dev->data->dev_private;
642 struct hns3_hw *hw = &hns->hw;
646 /* Get rx queue stats */
647 for (j = 0; j < dev->data->nb_rx_queues; j++) {
648 for (i = 0; i < HNS3_NUM_RX_QUEUE_STATS; i++) {
649 reg_offset = hns3_get_tqp_reg_offset(j);
650 xstats[*count].value = hns3_read_dev(hw,
651 reg_offset + hns3_rx_queue_strings[i].offset);
652 xstats[*count].id = *count;
657 /* Get tx queue stats */
658 for (j = 0; j < dev->data->nb_tx_queues; j++) {
659 for (i = 0; i < HNS3_NUM_TX_QUEUE_STATS; i++) {
660 reg_offset = hns3_get_tqp_reg_offset(j);
661 xstats[*count].value = hns3_read_dev(hw,
662 reg_offset + hns3_tx_queue_strings[i].offset);
663 xstats[*count].id = *count;
670 hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err)
672 struct hns3_pf *pf = &hns->pf;
676 for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) {
677 if (strcmp(hns3_error_int_stats_strings[i].name, err) == 0) {
678 addr = (char *)&pf->abn_int_stats +
679 hns3_error_int_stats_strings[i].offset;
680 *(uint64_t *)addr += 1;
687 * Retrieve extended(tqp | Mac) statistics of an Ethernet device.
689 * Pointer to Ethernet device.
691 * A pointer to a table of structure of type *rte_eth_xstat*
692 * to be filled with device statistics ids and values.
693 * This parameter can be set to NULL if n is 0.
695 * The size of the xstats array (number of elements).
697 * 0 on fail, count(The size of the statistics elements) on success.
700 hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
703 struct hns3_adapter *hns = dev->data->dev_private;
704 struct hns3_pf *pf = &hns->pf;
705 struct hns3_hw *hw = &hns->hw;
706 struct hns3_mac_stats *mac_stats = &hw->mac_stats;
707 struct hns3_reset_stats *reset_stats = &hw->reset.stats;
708 struct hns3_rx_queue *rxq;
709 struct hns3_tx_queue *txq;
718 count = hns3_xstats_calc_num(dev);
725 /* Update Mac stats */
726 ret = hns3_query_update_mac_stats(dev);
728 hns3_err(hw, "Update Mac stats fail : %d", ret);
732 /* Get MAC stats from hw->hw_xstats.mac_stats struct */
733 for (i = 0; i < HNS3_NUM_MAC_STATS; i++) {
734 addr = (char *)mac_stats + hns3_mac_strings[i].offset;
735 xstats[count].value = *(uint64_t *)addr;
736 xstats[count].id = count;
740 for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) {
741 addr = (char *)&pf->abn_int_stats +
742 hns3_error_int_stats_strings[i].offset;
743 xstats[count].value = *(uint64_t *)addr;
744 xstats[count].id = count;
749 /* Get the reset stat */
750 for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) {
751 addr = (char *)reset_stats + hns3_reset_stats_strings[i].offset;
752 xstats[count].value = *(uint64_t *)addr;
753 xstats[count].id = count;
757 /* Get the Rx BD errors stats */
758 for (j = 0; j < dev->data->nb_rx_queues; j++) {
759 for (i = 0; i < HNS3_NUM_RX_BD_ERROR_XSTATS; i++) {
760 rxq = dev->data->rx_queues[j];
761 addr = (char *)rxq + hns3_rx_bd_error_strings[i].offset;
762 xstats[count].value = *(uint64_t *)addr;
763 xstats[count].id = count;
768 /* Get the Tx errors stats */
769 for (j = 0; j < dev->data->nb_tx_queues; j++) {
770 for (i = 0; i < HNS3_NUM_TX_ERRORS_XSTATS; i++) {
771 txq = dev->data->tx_queues[j];
772 addr = (char *)txq + hns3_tx_errors_strings[i].offset;
773 xstats[count].value = *(uint64_t *)addr;
774 xstats[count].id = count;
779 hns3_get_queue_stats(dev, xstats, &count);
784 * Retrieve names of extended statistics of an Ethernet device.
786 * There is an assumption that 'xstat_names' and 'xstats' arrays are matched
788 * xstats_names[i].name => xstats[i].value
790 * And the array index is same with id field of 'struct rte_eth_xstat':
793 * This assumption makes key-value pair matching less flexible but simpler.
796 * Pointer to Ethernet device.
797 * @param xstats_names
798 * An rte_eth_xstat_name array of at least *size* elements to
799 * be filled. If set to NULL, the function returns the required number
802 * The size of the xstats_names array (number of elements).
804 * - A positive value lower or equal to size: success. The return value
805 * is the number of entries filled in the stats table.
808 hns3_dev_xstats_get_names(struct rte_eth_dev *dev,
809 struct rte_eth_xstat_name *xstats_names,
810 __rte_unused unsigned int size)
812 struct hns3_adapter *hns = dev->data->dev_private;
813 int cnt_stats = hns3_xstats_calc_num(dev);
817 if (xstats_names == NULL)
820 /* Note: size limited checked in rte_eth_xstats_get_names() */
822 /* Get MAC name from hw->hw_xstats.mac_stats struct */
823 for (i = 0; i < HNS3_NUM_MAC_STATS; i++) {
824 snprintf(xstats_names[count].name,
825 sizeof(xstats_names[count].name),
826 "%s", hns3_mac_strings[i].name);
830 for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) {
831 snprintf(xstats_names[count].name,
832 sizeof(xstats_names[count].name),
833 "%s", hns3_error_int_stats_strings[i].name);
837 for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) {
838 snprintf(xstats_names[count].name,
839 sizeof(xstats_names[count].name),
840 "%s", hns3_reset_stats_strings[i].name);
844 for (j = 0; j < dev->data->nb_rx_queues; j++) {
845 for (i = 0; i < HNS3_NUM_RX_BD_ERROR_XSTATS; i++) {
846 snprintf(xstats_names[count].name,
847 sizeof(xstats_names[count].name),
849 hns3_rx_bd_error_strings[i].name);
854 for (j = 0; j < dev->data->nb_tx_queues; j++) {
855 for (i = 0; i < HNS3_NUM_TX_ERRORS_XSTATS; i++) {
856 snprintf(xstats_names[count].name,
857 sizeof(xstats_names[count].name),
859 hns3_tx_errors_strings[i].name);
864 for (j = 0; j < dev->data->nb_rx_queues; j++) {
865 for (i = 0; i < HNS3_NUM_RX_QUEUE_STATS; i++) {
866 snprintf(xstats_names[count].name,
867 sizeof(xstats_names[count].name),
868 "rx_q%u%s", j, hns3_rx_queue_strings[i].name);
873 for (j = 0; j < dev->data->nb_tx_queues; j++) {
874 for (i = 0; i < HNS3_NUM_TX_QUEUE_STATS; i++) {
875 snprintf(xstats_names[count].name,
876 sizeof(xstats_names[count].name),
877 "tx_q%u%s", j, hns3_tx_queue_strings[i].name);
886 * Retrieve extended statistics of an Ethernet device.
889 * Pointer to Ethernet device.
891 * A pointer to an ids array passed by application. This tells which
892 * statistics values function should retrieve. This parameter
893 * can be set to NULL if size is 0. In this case function will retrieve
894 * all avalible statistics.
896 * A pointer to a table to be filled with device statistics values.
898 * The size of the ids array (number of elements).
900 * - A positive value lower or equal to size: success. The return value
901 * is the number of entries filled in the stats table.
902 * - A positive value higher than size: error, the given statistics table
903 * is too small. The return value corresponds to the size that should
904 * be given to succeed. The entries in the table are not valid and
905 * shall not be used by the caller.
909 hns3_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
910 uint64_t *values, uint32_t size)
912 const uint32_t cnt_stats = hns3_xstats_calc_num(dev);
913 struct hns3_adapter *hns = dev->data->dev_private;
914 struct rte_eth_xstat *values_copy;
915 struct hns3_hw *hw = &hns->hw;
916 uint32_t count_value;
921 if (ids == NULL && values == NULL)
925 if (size < cnt_stats)
928 /* Update tqp stats by read register */
929 ret = hns3_update_tqp_stats(hw);
931 hns3_err(hw, "Update tqp stats fail : %d", ret);
935 len = cnt_stats * sizeof(struct rte_eth_xstat);
936 values_copy = rte_zmalloc("hns3_xstats_values", len, 0);
937 if (values_copy == NULL) {
938 hns3_err(hw, "Failed to allocate %" PRIx64 " bytes needed "
939 "to store statistics values", len);
943 count_value = hns3_dev_xstats_get(dev, values_copy, cnt_stats);
944 if (count_value != cnt_stats) {
945 rte_free(values_copy);
949 if (ids == NULL && values != NULL) {
950 for (i = 0; i < cnt_stats; i++)
951 memcpy(&values[i], &values_copy[i].value,
954 rte_free(values_copy);
958 for (i = 0; i < size; i++) {
959 if (ids[i] >= cnt_stats) {
960 hns3_err(hw, "ids[%u] (%" PRIx64 ") is invalid, "
961 "should < %u", i, ids[i], cnt_stats);
962 rte_free(values_copy);
965 memcpy(&values[i], &values_copy[ids[i]].value,
969 rte_free(values_copy);
974 * Retrieve names of extended statistics of an Ethernet device.
977 * Pointer to Ethernet device.
978 * @param xstats_names
979 * An rte_eth_xstat_name array of at least *size* elements to
980 * be filled. If set to NULL, the function returns the required number
983 * IDs array given by app to retrieve specific statistics
985 * The size of the xstats_names array (number of elements).
987 * - A positive value lower or equal to size: success. The return value
988 * is the number of entries filled in the stats table.
989 * - A positive value higher than size: error, the given statistics table
990 * is too small. The return value corresponds to the size that should
991 * be given to succeed. The entries in the table are not valid and
992 * shall not be used by the caller.
995 hns3_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
996 struct rte_eth_xstat_name *xstats_names,
997 const uint64_t *ids, uint32_t size)
999 const uint32_t cnt_stats = hns3_xstats_calc_num(dev);
1000 struct hns3_adapter *hns = dev->data->dev_private;
1001 struct rte_eth_xstat_name *names_copy;
1002 struct hns3_hw *hw = &hns->hw;
1006 if (xstats_names == NULL)
1010 if (size < cnt_stats)
1013 return hns3_dev_xstats_get_names(dev, xstats_names, cnt_stats);
1016 len = cnt_stats * sizeof(struct rte_eth_xstat_name);
1017 names_copy = rte_zmalloc("hns3_xstats_names", len, 0);
1018 if (names_copy == NULL) {
1019 hns3_err(hw, "Failed to allocate %" PRIx64 " bytes needed "
1020 "to store statistics names", len);
1024 (void)hns3_dev_xstats_get_names(dev, names_copy, cnt_stats);
1026 for (i = 0; i < size; i++) {
1027 if (ids[i] >= cnt_stats) {
1028 hns3_err(hw, "ids[%u] (%" PRIx64 ") is invalid, "
1029 "should < %u", i, ids[i], cnt_stats);
1030 rte_free(names_copy);
1033 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1034 "%s", names_copy[ids[i]].name);
1037 rte_free(names_copy);
1042 hns3_tqp_dfx_stats_clear(struct rte_eth_dev *dev)
1044 struct hns3_rx_queue *rxq;
1045 struct hns3_tx_queue *txq;
1048 /* Clear Rx dfx stats */
1049 for (i = 0; i < dev->data->nb_rx_queues; ++i) {
1050 rxq = dev->data->rx_queues[i];
1052 rxq->l3_csum_errors = 0;
1053 rxq->l4_csum_errors = 0;
1054 rxq->ol3_csum_errors = 0;
1055 rxq->ol4_csum_errors = 0;
1059 /* Clear Tx dfx stats */
1060 for (i = 0; i < dev->data->nb_tx_queues; ++i) {
1061 txq = dev->data->tx_queues[i];
1063 txq->over_length_pkt_cnt = 0;
1064 txq->exceed_limit_bd_pkt_cnt = 0;
1065 txq->exceed_limit_bd_reassem_fail = 0;
1066 txq->unsupported_tunnel_pkt_cnt = 0;
1067 txq->queue_full_cnt = 0;
1068 txq->pkt_padding_fail_cnt = 0;
1074 hns3_dev_xstats_reset(struct rte_eth_dev *dev)
1076 struct hns3_adapter *hns = dev->data->dev_private;
1077 struct hns3_pf *pf = &hns->pf;
1080 /* Clear tqp stats */
1081 ret = hns3_stats_reset(dev);
1085 /* Clear reset stats */
1086 memset(&hns->hw.reset.stats, 0, sizeof(struct hns3_reset_stats));
1088 hns3_tqp_dfx_stats_clear(dev);
1093 /* HW registers are cleared on read */
1094 ret = hns3_mac_stats_reset(dev);
1098 /* Clear error stats */
1099 memset(&pf->abn_int_stats, 0, sizeof(struct hns3_err_msix_intr_stats));
1105 hns3_tqp_stats_init(struct hns3_hw *hw)
1107 struct hns3_tqp_stats *tqp_stats = &hw->tqp_stats;
1109 tqp_stats->rcb_rx_ring_pktnum = rte_zmalloc("hns3_rx_ring_pkt_num",
1110 sizeof(uint64_t) * hw->tqps_num, 0);
1111 if (tqp_stats->rcb_rx_ring_pktnum == NULL) {
1112 hns3_err(hw, "failed to allocate rx_ring pkt_num.");
1116 tqp_stats->rcb_tx_ring_pktnum = rte_zmalloc("hns3_tx_ring_pkt_num",
1117 sizeof(uint64_t) * hw->tqps_num, 0);
1118 if (tqp_stats->rcb_tx_ring_pktnum == NULL) {
1119 hns3_err(hw, "failed to allocate tx_ring pkt_num.");
1120 rte_free(tqp_stats->rcb_rx_ring_pktnum);
1121 tqp_stats->rcb_rx_ring_pktnum = NULL;
1129 hns3_tqp_stats_uninit(struct hns3_hw *hw)
1131 struct hns3_tqp_stats *tqp_stats = &hw->tqp_stats;
1133 rte_free(tqp_stats->rcb_rx_ring_pktnum);
1134 tqp_stats->rcb_rx_ring_pktnum = NULL;
1135 rte_free(tqp_stats->rcb_tx_ring_pktnum);
1136 tqp_stats->rcb_tx_ring_pktnum = NULL;
1140 hns3_tqp_stats_clear(struct hns3_hw *hw)
1142 struct hns3_tqp_stats *stats = &hw->tqp_stats;
1144 stats->rcb_rx_ring_pktnum_rcd = 0;
1145 stats->rcb_tx_ring_pktnum_rcd = 0;
1146 memset(stats->rcb_rx_ring_pktnum, 0, sizeof(uint64_t) * hw->tqps_num);
1147 memset(stats->rcb_tx_ring_pktnum, 0, sizeof(uint64_t) * hw->tqps_num);