1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #include <rte_ethdev.h>
7 #include <rte_malloc.h>
9 #include "hns3_ethdev.h"
10 #include "hns3_rxtx.h"
11 #include "hns3_logs.h"
12 #include "hns3_regs.h"
14 /* The statistics of the per-rxq basic stats */
15 static const struct hns3_xstats_name_offset hns3_rxq_basic_stats_strings[] = {
17 HNS3_RXQ_BASIC_STATS_FIELD_OFFSET(packets)},
19 HNS3_RXQ_BASIC_STATS_FIELD_OFFSET(bytes)},
21 HNS3_RXQ_BASIC_STATS_FIELD_OFFSET(errors)}
24 /* The statistics of the per-txq basic stats */
25 static const struct hns3_xstats_name_offset hns3_txq_basic_stats_strings[] = {
27 HNS3_TXQ_BASIC_STATS_FIELD_OFFSET(packets)},
29 HNS3_TXQ_BASIC_STATS_FIELD_OFFSET(bytes)}
33 static const struct hns3_xstats_name_offset hns3_mac_strings[] = {
34 {"mac_tx_mac_pause_num",
35 HNS3_MAC_STATS_OFFSET(mac_tx_mac_pause_num)},
36 {"mac_rx_mac_pause_num",
37 HNS3_MAC_STATS_OFFSET(mac_rx_mac_pause_num)},
38 {"mac_tx_control_pkt_num",
39 HNS3_MAC_STATS_OFFSET(mac_tx_ctrl_pkt_num)},
40 {"mac_rx_control_pkt_num",
41 HNS3_MAC_STATS_OFFSET(mac_rx_ctrl_pkt_num)},
42 {"mac_tx_pfc_pkt_num",
43 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pause_pkt_num)},
44 {"mac_tx_pfc_pri0_pkt_num",
45 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri0_pkt_num)},
46 {"mac_tx_pfc_pri1_pkt_num",
47 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri1_pkt_num)},
48 {"mac_tx_pfc_pri2_pkt_num",
49 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri2_pkt_num)},
50 {"mac_tx_pfc_pri3_pkt_num",
51 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri3_pkt_num)},
52 {"mac_tx_pfc_pri4_pkt_num",
53 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri4_pkt_num)},
54 {"mac_tx_pfc_pri5_pkt_num",
55 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri5_pkt_num)},
56 {"mac_tx_pfc_pri6_pkt_num",
57 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri6_pkt_num)},
58 {"mac_tx_pfc_pri7_pkt_num",
59 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri7_pkt_num)},
60 {"mac_rx_pfc_pkt_num",
61 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pause_pkt_num)},
62 {"mac_rx_pfc_pri0_pkt_num",
63 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri0_pkt_num)},
64 {"mac_rx_pfc_pri1_pkt_num",
65 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri1_pkt_num)},
66 {"mac_rx_pfc_pri2_pkt_num",
67 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri2_pkt_num)},
68 {"mac_rx_pfc_pri3_pkt_num",
69 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri3_pkt_num)},
70 {"mac_rx_pfc_pri4_pkt_num",
71 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri4_pkt_num)},
72 {"mac_rx_pfc_pri5_pkt_num",
73 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri5_pkt_num)},
74 {"mac_rx_pfc_pri6_pkt_num",
75 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri6_pkt_num)},
76 {"mac_rx_pfc_pri7_pkt_num",
77 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri7_pkt_num)},
78 {"mac_tx_total_pkt_num",
79 HNS3_MAC_STATS_OFFSET(mac_tx_total_pkt_num)},
80 {"mac_tx_total_oct_num",
81 HNS3_MAC_STATS_OFFSET(mac_tx_total_oct_num)},
82 {"mac_tx_good_pkt_num",
83 HNS3_MAC_STATS_OFFSET(mac_tx_good_pkt_num)},
84 {"mac_tx_bad_pkt_num",
85 HNS3_MAC_STATS_OFFSET(mac_tx_bad_pkt_num)},
86 {"mac_tx_good_oct_num",
87 HNS3_MAC_STATS_OFFSET(mac_tx_good_oct_num)},
88 {"mac_tx_bad_oct_num",
89 HNS3_MAC_STATS_OFFSET(mac_tx_bad_oct_num)},
90 {"mac_tx_uni_pkt_num",
91 HNS3_MAC_STATS_OFFSET(mac_tx_uni_pkt_num)},
92 {"mac_tx_multi_pkt_num",
93 HNS3_MAC_STATS_OFFSET(mac_tx_multi_pkt_num)},
94 {"mac_tx_broad_pkt_num",
95 HNS3_MAC_STATS_OFFSET(mac_tx_broad_pkt_num)},
96 {"mac_tx_undersize_pkt_num",
97 HNS3_MAC_STATS_OFFSET(mac_tx_undersize_pkt_num)},
98 {"mac_tx_oversize_pkt_num",
99 HNS3_MAC_STATS_OFFSET(mac_tx_oversize_pkt_num)},
100 {"mac_tx_64_oct_pkt_num",
101 HNS3_MAC_STATS_OFFSET(mac_tx_64_oct_pkt_num)},
102 {"mac_tx_65_127_oct_pkt_num",
103 HNS3_MAC_STATS_OFFSET(mac_tx_65_127_oct_pkt_num)},
104 {"mac_tx_128_255_oct_pkt_num",
105 HNS3_MAC_STATS_OFFSET(mac_tx_128_255_oct_pkt_num)},
106 {"mac_tx_256_511_oct_pkt_num",
107 HNS3_MAC_STATS_OFFSET(mac_tx_256_511_oct_pkt_num)},
108 {"mac_tx_512_1023_oct_pkt_num",
109 HNS3_MAC_STATS_OFFSET(mac_tx_512_1023_oct_pkt_num)},
110 {"mac_tx_1024_1518_oct_pkt_num",
111 HNS3_MAC_STATS_OFFSET(mac_tx_1024_1518_oct_pkt_num)},
112 {"mac_tx_1519_2047_oct_pkt_num",
113 HNS3_MAC_STATS_OFFSET(mac_tx_1519_2047_oct_pkt_num)},
114 {"mac_tx_2048_4095_oct_pkt_num",
115 HNS3_MAC_STATS_OFFSET(mac_tx_2048_4095_oct_pkt_num)},
116 {"mac_tx_4096_8191_oct_pkt_num",
117 HNS3_MAC_STATS_OFFSET(mac_tx_4096_8191_oct_pkt_num)},
118 {"mac_tx_8192_9216_oct_pkt_num",
119 HNS3_MAC_STATS_OFFSET(mac_tx_8192_9216_oct_pkt_num)},
120 {"mac_tx_9217_12287_oct_pkt_num",
121 HNS3_MAC_STATS_OFFSET(mac_tx_9217_12287_oct_pkt_num)},
122 {"mac_tx_12288_16383_oct_pkt_num",
123 HNS3_MAC_STATS_OFFSET(mac_tx_12288_16383_oct_pkt_num)},
124 {"mac_tx_1519_max_good_pkt_num",
125 HNS3_MAC_STATS_OFFSET(mac_tx_1519_max_good_oct_pkt_num)},
126 {"mac_tx_1519_max_bad_pkt_num",
127 HNS3_MAC_STATS_OFFSET(mac_tx_1519_max_bad_oct_pkt_num)},
128 {"mac_rx_total_pkt_num",
129 HNS3_MAC_STATS_OFFSET(mac_rx_total_pkt_num)},
130 {"mac_rx_total_oct_num",
131 HNS3_MAC_STATS_OFFSET(mac_rx_total_oct_num)},
132 {"mac_rx_good_pkt_num",
133 HNS3_MAC_STATS_OFFSET(mac_rx_good_pkt_num)},
134 {"mac_rx_bad_pkt_num",
135 HNS3_MAC_STATS_OFFSET(mac_rx_bad_pkt_num)},
136 {"mac_rx_good_oct_num",
137 HNS3_MAC_STATS_OFFSET(mac_rx_good_oct_num)},
138 {"mac_rx_bad_oct_num",
139 HNS3_MAC_STATS_OFFSET(mac_rx_bad_oct_num)},
140 {"mac_rx_uni_pkt_num",
141 HNS3_MAC_STATS_OFFSET(mac_rx_uni_pkt_num)},
142 {"mac_rx_multi_pkt_num",
143 HNS3_MAC_STATS_OFFSET(mac_rx_multi_pkt_num)},
144 {"mac_rx_broad_pkt_num",
145 HNS3_MAC_STATS_OFFSET(mac_rx_broad_pkt_num)},
146 {"mac_rx_undersize_pkt_num",
147 HNS3_MAC_STATS_OFFSET(mac_rx_undersize_pkt_num)},
148 {"mac_rx_oversize_pkt_num",
149 HNS3_MAC_STATS_OFFSET(mac_rx_oversize_pkt_num)},
150 {"mac_rx_64_oct_pkt_num",
151 HNS3_MAC_STATS_OFFSET(mac_rx_64_oct_pkt_num)},
152 {"mac_rx_65_127_oct_pkt_num",
153 HNS3_MAC_STATS_OFFSET(mac_rx_65_127_oct_pkt_num)},
154 {"mac_rx_128_255_oct_pkt_num",
155 HNS3_MAC_STATS_OFFSET(mac_rx_128_255_oct_pkt_num)},
156 {"mac_rx_256_511_oct_pkt_num",
157 HNS3_MAC_STATS_OFFSET(mac_rx_256_511_oct_pkt_num)},
158 {"mac_rx_512_1023_oct_pkt_num",
159 HNS3_MAC_STATS_OFFSET(mac_rx_512_1023_oct_pkt_num)},
160 {"mac_rx_1024_1518_oct_pkt_num",
161 HNS3_MAC_STATS_OFFSET(mac_rx_1024_1518_oct_pkt_num)},
162 {"mac_rx_1519_2047_oct_pkt_num",
163 HNS3_MAC_STATS_OFFSET(mac_rx_1519_2047_oct_pkt_num)},
164 {"mac_rx_2048_4095_oct_pkt_num",
165 HNS3_MAC_STATS_OFFSET(mac_rx_2048_4095_oct_pkt_num)},
166 {"mac_rx_4096_8191_oct_pkt_num",
167 HNS3_MAC_STATS_OFFSET(mac_rx_4096_8191_oct_pkt_num)},
168 {"mac_rx_8192_9216_oct_pkt_num",
169 HNS3_MAC_STATS_OFFSET(mac_rx_8192_9216_oct_pkt_num)},
170 {"mac_rx_9217_12287_oct_pkt_num",
171 HNS3_MAC_STATS_OFFSET(mac_rx_9217_12287_oct_pkt_num)},
172 {"mac_rx_12288_16383_oct_pkt_num",
173 HNS3_MAC_STATS_OFFSET(mac_rx_12288_16383_oct_pkt_num)},
174 {"mac_rx_1519_max_good_pkt_num",
175 HNS3_MAC_STATS_OFFSET(mac_rx_1519_max_good_oct_pkt_num)},
176 {"mac_rx_1519_max_bad_pkt_num",
177 HNS3_MAC_STATS_OFFSET(mac_rx_1519_max_bad_oct_pkt_num)},
178 {"mac_tx_fragment_pkt_num",
179 HNS3_MAC_STATS_OFFSET(mac_tx_fragment_pkt_num)},
180 {"mac_tx_undermin_pkt_num",
181 HNS3_MAC_STATS_OFFSET(mac_tx_undermin_pkt_num)},
182 {"mac_tx_jabber_pkt_num",
183 HNS3_MAC_STATS_OFFSET(mac_tx_jabber_pkt_num)},
184 {"mac_tx_err_all_pkt_num",
185 HNS3_MAC_STATS_OFFSET(mac_tx_err_all_pkt_num)},
186 {"mac_tx_from_app_good_pkt_num",
187 HNS3_MAC_STATS_OFFSET(mac_tx_from_app_good_pkt_num)},
188 {"mac_tx_from_app_bad_pkt_num",
189 HNS3_MAC_STATS_OFFSET(mac_tx_from_app_bad_pkt_num)},
190 {"mac_rx_fragment_pkt_num",
191 HNS3_MAC_STATS_OFFSET(mac_rx_fragment_pkt_num)},
192 {"mac_rx_undermin_pkt_num",
193 HNS3_MAC_STATS_OFFSET(mac_rx_undermin_pkt_num)},
194 {"mac_rx_jabber_pkt_num",
195 HNS3_MAC_STATS_OFFSET(mac_rx_jabber_pkt_num)},
196 {"mac_rx_fcs_err_pkt_num",
197 HNS3_MAC_STATS_OFFSET(mac_rx_fcs_err_pkt_num)},
198 {"mac_rx_send_app_good_pkt_num",
199 HNS3_MAC_STATS_OFFSET(mac_rx_send_app_good_pkt_num)},
200 {"mac_rx_send_app_bad_pkt_num",
201 HNS3_MAC_STATS_OFFSET(mac_rx_send_app_bad_pkt_num)}
204 /* The statistic of reset */
205 static const struct hns3_xstats_name_offset hns3_reset_stats_strings[] = {
207 HNS3_RESET_STATS_FIELD_OFFSET(request_cnt)},
209 HNS3_RESET_STATS_FIELD_OFFSET(global_cnt)},
211 HNS3_RESET_STATS_FIELD_OFFSET(imp_cnt)},
213 HNS3_RESET_STATS_FIELD_OFFSET(exec_cnt)},
214 {"RESET_SUCCESS_CNT",
215 HNS3_RESET_STATS_FIELD_OFFSET(success_cnt)},
217 HNS3_RESET_STATS_FIELD_OFFSET(fail_cnt)},
219 HNS3_RESET_STATS_FIELD_OFFSET(merge_cnt)}
222 /* The statistic of errors in Rx BD */
223 static const struct hns3_xstats_name_offset hns3_rx_bd_error_strings[] = {
225 HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(pkt_len_errors)},
227 HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(l2_errors)}
230 /* The dfx statistic in Rx datapath */
231 static const struct hns3_xstats_name_offset hns3_rxq_dfx_stats_strings[] = {
232 {"L3_CHECKSUM_ERRORS",
233 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(l3_csum_errors)},
234 {"L4_CHECKSUM_ERRORS",
235 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(l4_csum_errors)},
236 {"OL3_CHECKSUM_ERRORS",
237 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(ol3_csum_errors)},
238 {"OL4_CHECKSUM_ERRORS",
239 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(ol4_csum_errors)}
242 /* The dfx statistic in Tx datapath */
243 static const struct hns3_xstats_name_offset hns3_txq_dfx_stats_strings[] = {
244 {"OVER_LENGTH_PKT_CNT",
245 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(over_length_pkt_cnt)},
246 {"EXCEED_LIMITED_BD_PKT_CNT",
247 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(exceed_limit_bd_pkt_cnt)},
248 {"EXCEED_LIMITED_BD_PKT_REASSEMBLE_FAIL_CNT",
249 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(exceed_limit_bd_reassem_fail)},
250 {"UNSUPPORTED_TUNNEL_PKT_CNT",
251 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(unsupported_tunnel_pkt_cnt)},
253 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(queue_full_cnt)},
254 {"SHORT_PKT_PAD_FAIL_CNT",
255 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(pkt_padding_fail_cnt)}
258 /* The statistic of rx queue */
259 static const struct hns3_xstats_name_offset hns3_rx_queue_strings[] = {
260 {"RX_QUEUE_FBD", HNS3_RING_RX_FBDNUM_REG}
263 /* The statistic of tx queue */
264 static const struct hns3_xstats_name_offset hns3_tx_queue_strings[] = {
265 {"TX_QUEUE_FBD", HNS3_RING_TX_FBDNUM_REG}
268 /* The statistic of imissed packet */
269 static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = {
271 HNS3_IMISSED_STATS_FIELD_OFFSET(rpu_rx_drop_cnt)},
273 HNS3_IMISSED_STATS_FIELD_OFFSET(ssu_rx_drop_cnt)},
276 #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \
277 sizeof(hns3_mac_strings[0]))
279 #define HNS3_NUM_RESET_XSTATS (sizeof(hns3_reset_stats_strings) / \
280 sizeof(hns3_reset_stats_strings[0]))
282 #define HNS3_NUM_RX_BD_ERROR_XSTATS (sizeof(hns3_rx_bd_error_strings) / \
283 sizeof(hns3_rx_bd_error_strings[0]))
285 #define HNS3_NUM_RXQ_DFX_XSTATS (sizeof(hns3_rxq_dfx_stats_strings) / \
286 sizeof(hns3_rxq_dfx_stats_strings[0]))
288 #define HNS3_NUM_TXQ_DFX_XSTATS (sizeof(hns3_txq_dfx_stats_strings) / \
289 sizeof(hns3_txq_dfx_stats_strings[0]))
291 #define HNS3_NUM_RX_QUEUE_STATS (sizeof(hns3_rx_queue_strings) / \
292 sizeof(hns3_rx_queue_strings[0]))
294 #define HNS3_NUM_TX_QUEUE_STATS (sizeof(hns3_tx_queue_strings) / \
295 sizeof(hns3_tx_queue_strings[0]))
297 #define HNS3_NUM_RXQ_BASIC_STATS (sizeof(hns3_rxq_basic_stats_strings) / \
298 sizeof(hns3_rxq_basic_stats_strings[0]))
300 #define HNS3_NUM_TXQ_BASIC_STATS (sizeof(hns3_txq_basic_stats_strings) / \
301 sizeof(hns3_txq_basic_stats_strings[0]))
303 #define HNS3_NUM_IMISSED_XSTATS (sizeof(hns3_imissed_stats_strings) / \
304 sizeof(hns3_imissed_stats_strings[0]))
306 #define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_RESET_XSTATS)
308 static void hns3_tqp_stats_clear(struct hns3_hw *hw);
311 hns3_update_mac_stats(struct hns3_hw *hw)
313 #define HNS3_MAC_STATS_REG_NUM_PER_DESC 4
315 uint64_t *data = (uint64_t *)(&hw->mac_stats);
316 struct hns3_cmd_desc *desc;
317 uint32_t stats_iterms;
323 /* The first desc has a 64-bit header, so need to consider it. */
324 desc_num = hw->mac_stats_reg_num / HNS3_MAC_STATS_REG_NUM_PER_DESC + 1;
325 desc = rte_malloc("hns3_mac_desc",
326 desc_num * sizeof(struct hns3_cmd_desc), 0);
328 hns3_err(hw, "Mac_update_stats alloced desc malloc fail");
332 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_STATS_MAC_ALL, true);
333 ret = hns3_cmd_send(hw, desc, desc_num);
335 hns3_err(hw, "Update complete MAC pkt stats fail : %d", ret);
340 stats_iterms = RTE_MIN(sizeof(hw->mac_stats) / sizeof(uint64_t),
341 hw->mac_stats_reg_num);
342 desc_data = (uint64_t *)(&desc[0].data[0]);
343 for (i = 0; i < stats_iterms; i++) {
345 * Data memory is continuous and only the first descriptor has a
346 * header in this command.
348 *data += rte_le_to_cpu_64(*desc_data);
358 hns3_mac_query_reg_num(struct hns3_hw *hw, uint32_t *reg_num)
360 #define HNS3_MAC_STATS_RSV_REG_NUM_ON_HIP08_B 3
361 struct hns3_cmd_desc desc;
364 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_REG_NUM, true);
365 ret = hns3_cmd_send(hw, &desc, 1);
367 hns3_err(hw, "failed to query MAC statistic reg number, ret = %d",
372 /* The number of MAC statistics registers are provided by firmware. */
373 *reg_num = rte_le_to_cpu_32(desc.data[0]);
375 hns3_err(hw, "MAC statistic reg number is invalid!");
380 * If driver doesn't request the firmware to report more MAC statistics
381 * iterms and the total number of MAC statistics registers by using new
382 * method, firmware will only reports the number of valid statistics
383 * registers. However, structure hns3_mac_stats in driver contains valid
384 * and reserved statistics iterms. In this case, the total register
385 * number must be added to three reserved statistics registers.
387 *reg_num += HNS3_MAC_STATS_RSV_REG_NUM_ON_HIP08_B;
393 hns3_query_mac_stats_reg_num(struct hns3_hw *hw)
395 uint32_t mac_stats_reg_num = 0;
398 ret = hns3_mac_query_reg_num(hw, &mac_stats_reg_num);
402 hw->mac_stats_reg_num = mac_stats_reg_num;
403 if (hw->mac_stats_reg_num > sizeof(hw->mac_stats) / sizeof(uint64_t))
404 hns3_warn(hw, "MAC stats reg number from firmware is greater than stats iterms in driver.");
410 hns3_query_update_mac_stats(struct rte_eth_dev *dev)
412 struct hns3_adapter *hns = dev->data->dev_private;
413 struct hns3_hw *hw = &hns->hw;
415 return hns3_update_mac_stats(hw);
419 hns3_update_port_rpu_drop_stats(struct hns3_hw *hw)
421 struct hns3_rx_missed_stats *stats = &hw->imissed_stats;
422 struct hns3_query_rpu_cmd *req;
423 struct hns3_cmd_desc desc;
428 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_DFX_RPU_REG_0, true);
429 req = (struct hns3_query_rpu_cmd *)desc.data;
432 * tc_num is 0, means rpu stats of all TC channels will be
436 req->tc_queue_num = rte_cpu_to_le_32(tc_num);
437 ret = hns3_cmd_send(hw, &desc, 1);
439 hns3_err(hw, "failed to query RPU stats: %d", ret);
443 cnt = rte_le_to_cpu_32(req->rpu_rx_pkt_drop_cnt);
444 stats->rpu_rx_drop_cnt += cnt;
450 hns3_update_function_rpu_drop_stats(struct hns3_hw *hw)
452 struct hns3_rx_missed_stats *stats = &hw->imissed_stats;
454 stats->rpu_rx_drop_cnt += hns3_read_dev(hw, HNS3_RPU_DROP_CNT_REG);
458 hns3_update_rpu_drop_stats(struct hns3_hw *hw)
460 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
463 if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && !hns->is_vf)
464 ret = hns3_update_port_rpu_drop_stats(hw);
465 else if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2)
466 hns3_update_function_rpu_drop_stats(hw);
472 hns3_get_ssu_drop_stats(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
473 int bd_num, bool is_rx)
475 struct hns3_query_ssu_cmd *req;
479 for (i = 0; i < bd_num - 1; i++) {
480 hns3_cmd_setup_basic_desc(&desc[i],
481 HNS3_OPC_SSU_DROP_REG, true);
482 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
484 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_SSU_DROP_REG, true);
485 req = (struct hns3_query_ssu_cmd *)desc[0].data;
486 req->rxtx = is_rx ? 0 : 1;
487 ret = hns3_cmd_send(hw, desc, bd_num);
493 hns3_update_port_rx_ssu_drop_stats(struct hns3_hw *hw)
495 struct hns3_rx_missed_stats *stats = &hw->imissed_stats;
496 struct hns3_cmd_desc desc[HNS3_OPC_SSU_DROP_REG_NUM];
497 struct hns3_query_ssu_cmd *req;
501 ret = hns3_get_ssu_drop_stats(hw, desc, HNS3_OPC_SSU_DROP_REG_NUM,
504 hns3_err(hw, "failed to get Rx SSU drop stats, ret = %d", ret);
508 req = (struct hns3_query_ssu_cmd *)desc[0].data;
509 cnt = rte_le_to_cpu_32(req->oq_drop_cnt) +
510 rte_le_to_cpu_32(req->full_drop_cnt) +
511 rte_le_to_cpu_32(req->part_drop_cnt);
513 stats->ssu_rx_drop_cnt += cnt;
519 hns3_update_port_tx_ssu_drop_stats(struct hns3_hw *hw)
521 struct hns3_cmd_desc desc[HNS3_OPC_SSU_DROP_REG_NUM];
522 struct hns3_query_ssu_cmd *req;
526 ret = hns3_get_ssu_drop_stats(hw, desc, HNS3_OPC_SSU_DROP_REG_NUM,
529 hns3_err(hw, "failed to get Tx SSU drop stats, ret = %d", ret);
533 req = (struct hns3_query_ssu_cmd *)desc[0].data;
534 cnt = rte_le_to_cpu_32(req->oq_drop_cnt) +
535 rte_le_to_cpu_32(req->full_drop_cnt) +
536 rte_le_to_cpu_32(req->part_drop_cnt);
538 hw->oerror_stats += cnt;
544 hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear)
546 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
549 if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && hns->is_vf)
552 if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2 && !hns->is_vf) {
553 ret = hns3_update_port_rx_ssu_drop_stats(hw);
558 ret = hns3_update_rpu_drop_stats(hw);
563 memset(&hw->imissed_stats, 0, sizeof(hw->imissed_stats));
569 hns3_update_oerror_stats(struct hns3_hw *hw, bool is_clear)
571 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
574 if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 || hns->is_vf)
577 ret = hns3_update_port_tx_ssu_drop_stats(hw);
582 hw->oerror_stats = 0;
588 * Query tqp tx queue statistics ,opcode id: 0x0B03.
589 * Query tqp rx queue statistics ,opcode id: 0x0B13.
590 * Get all statistics of a port.
592 * Pointer to Ethernet device.
594 * Pointer to structure rte_eth_stats.
599 hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats)
601 struct hns3_adapter *hns = eth_dev->data->dev_private;
602 struct hns3_hw *hw = &hns->hw;
603 struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats;
604 struct hns3_tqp_stats *stats = &hw->tqp_stats;
605 struct hns3_rx_queue *rxq;
606 struct hns3_tx_queue *txq;
611 /* Update imissed stats */
612 ret = hns3_update_imissed_stats(hw, false);
614 hns3_err(hw, "update imissed stats failed, ret = %d",
618 rte_stats->imissed = imissed_stats->rpu_rx_drop_cnt +
619 imissed_stats->ssu_rx_drop_cnt;
621 /* Get the error stats and bytes of received packets */
622 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
623 rxq = eth_dev->data->rx_queues[i];
627 cnt = hns3_read_dev(rxq, HNS3_RING_RX_PKTNUM_RECORD_REG);
629 * Read hardware and software in adjacent positions to minimize
630 * the timing variance.
632 rte_stats->ierrors += rxq->err_stats.l2_errors +
633 rxq->err_stats.pkt_len_errors;
634 stats->rcb_rx_ring_pktnum_rcd += cnt;
635 stats->rcb_rx_ring_pktnum[i] += cnt;
636 rte_stats->ibytes += rxq->basic_stats.bytes;
639 /* Reads all the stats of a txq in a loop to keep them synchronized */
640 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
641 txq = eth_dev->data->tx_queues[i];
645 cnt = hns3_read_dev(txq, HNS3_RING_TX_PKTNUM_RECORD_REG);
646 stats->rcb_tx_ring_pktnum_rcd += cnt;
647 stats->rcb_tx_ring_pktnum[i] += cnt;
648 rte_stats->obytes += txq->basic_stats.bytes;
651 ret = hns3_update_oerror_stats(hw, false);
653 hns3_err(hw, "update oerror stats failed, ret = %d",
657 rte_stats->oerrors = hw->oerror_stats;
660 * If HW statistics are reset by stats_reset, but a lot of residual
661 * packets exist in the hardware queue and these packets are error
662 * packets, flip overflow may occurred. So return 0 in this case.
664 rte_stats->ipackets =
665 stats->rcb_rx_ring_pktnum_rcd > rte_stats->ierrors ?
666 stats->rcb_rx_ring_pktnum_rcd - rte_stats->ierrors : 0;
667 rte_stats->opackets = stats->rcb_tx_ring_pktnum_rcd -
669 rte_stats->rx_nombuf = eth_dev->data->rx_mbuf_alloc_failed;
675 hns3_stats_reset(struct rte_eth_dev *eth_dev)
677 struct hns3_adapter *hns = eth_dev->data->dev_private;
678 struct hns3_hw *hw = &hns->hw;
679 struct hns3_rx_queue *rxq;
680 struct hns3_tx_queue *txq;
685 * Note: Reading hardware statistics of imissed registers will
688 ret = hns3_update_imissed_stats(hw, true);
690 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
695 * Note: Reading hardware statistics of oerror registers will
698 ret = hns3_update_oerror_stats(hw, true);
700 hns3_err(hw, "clear oerror stats failed, ret = %d",
705 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
706 rxq = eth_dev->data->rx_queues[i];
710 rxq->err_stats.pkt_len_errors = 0;
711 rxq->err_stats.l2_errors = 0;
714 /* Clear all the stats of a rxq in a loop to keep them synchronized */
715 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
716 rxq = eth_dev->data->rx_queues[i];
720 memset(&rxq->basic_stats, 0,
721 sizeof(struct hns3_rx_basic_stats));
723 /* This register is read-clear */
724 (void)hns3_read_dev(rxq, HNS3_RING_RX_PKTNUM_RECORD_REG);
725 rxq->err_stats.pkt_len_errors = 0;
726 rxq->err_stats.l2_errors = 0;
729 /* Clear all the stats of a txq in a loop to keep them synchronized */
730 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
731 txq = eth_dev->data->tx_queues[i];
735 memset(&txq->basic_stats, 0,
736 sizeof(struct hns3_tx_basic_stats));
738 /* This register is read-clear */
739 (void)hns3_read_dev(txq, HNS3_RING_TX_PKTNUM_RECORD_REG);
742 hns3_tqp_stats_clear(hw);
748 hns3_mac_stats_reset(__rte_unused struct rte_eth_dev *dev)
750 struct hns3_adapter *hns = dev->data->dev_private;
751 struct hns3_hw *hw = &hns->hw;
752 struct hns3_mac_stats *mac_stats = &hw->mac_stats;
755 ret = hns3_query_update_mac_stats(dev);
757 hns3_err(hw, "Clear Mac stats fail : %d", ret);
761 memset(mac_stats, 0, sizeof(struct hns3_mac_stats));
767 hns3_get_imissed_stats_num(struct hns3_adapter *hns)
769 #define NO_IMISSED_STATS_NUM 0
770 #define RPU_STATS_ITEM_NUM 1
771 struct hns3_hw *hw = &hns->hw;
773 if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && hns->is_vf)
774 return NO_IMISSED_STATS_NUM;
776 if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2 && !hns->is_vf)
777 return HNS3_NUM_IMISSED_XSTATS;
779 return RPU_STATS_ITEM_NUM;
782 /* This function calculates the number of xstats based on the current config */
784 hns3_xstats_calc_num(struct rte_eth_dev *dev)
786 #define HNS3_PF_VF_RX_COMM_STATS_NUM (HNS3_NUM_RX_BD_ERROR_XSTATS + \
787 HNS3_NUM_RXQ_DFX_XSTATS + \
788 HNS3_NUM_RX_QUEUE_STATS + \
789 HNS3_NUM_RXQ_BASIC_STATS)
790 #define HNS3_PF_VF_TX_COMM_STATS_NUM (HNS3_NUM_TXQ_DFX_XSTATS + \
791 HNS3_NUM_TX_QUEUE_STATS + \
792 HNS3_NUM_TXQ_BASIC_STATS)
794 struct hns3_adapter *hns = dev->data->dev_private;
795 uint16_t nb_rx_q = dev->data->nb_rx_queues;
796 uint16_t nb_tx_q = dev->data->nb_tx_queues;
797 int rx_comm_stats_num = nb_rx_q * HNS3_PF_VF_RX_COMM_STATS_NUM;
798 int tx_comm_stats_num = nb_tx_q * HNS3_PF_VF_TX_COMM_STATS_NUM;
801 stats_num = rx_comm_stats_num + tx_comm_stats_num;
802 stats_num += hns3_get_imissed_stats_num(hns);
805 stats_num += HNS3_NUM_RESET_XSTATS;
807 stats_num += HNS3_FIX_NUM_STATS;
813 hns3_queue_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
816 struct hns3_adapter *hns = dev->data->dev_private;
817 struct hns3_hw *hw = &hns->hw;
821 /* Get rx queue stats */
822 for (j = 0; j < dev->data->nb_rx_queues; j++) {
823 for (i = 0; i < HNS3_NUM_RX_QUEUE_STATS; i++) {
824 reg_offset = hns3_get_tqp_reg_offset(j);
825 xstats[*count].value = hns3_read_dev(hw,
826 reg_offset + hns3_rx_queue_strings[i].offset);
827 xstats[*count].id = *count;
832 /* Get tx queue stats */
833 for (j = 0; j < dev->data->nb_tx_queues; j++) {
834 for (i = 0; i < HNS3_NUM_TX_QUEUE_STATS; i++) {
835 reg_offset = hns3_get_tqp_reg_offset(j);
836 xstats[*count].value = hns3_read_dev(hw,
837 reg_offset + hns3_tx_queue_strings[i].offset);
838 xstats[*count].id = *count;
845 hns3_rxq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
848 struct hns3_rx_dfx_stats *dfx_stats;
849 struct hns3_rx_queue *rxq;
853 for (i = 0; i < dev->data->nb_rx_queues; i++) {
854 rxq = (struct hns3_rx_queue *)dev->data->rx_queues[i];
858 dfx_stats = &rxq->dfx_stats;
859 for (j = 0; j < HNS3_NUM_RXQ_DFX_XSTATS; j++) {
860 val = (char *)dfx_stats +
861 hns3_rxq_dfx_stats_strings[j].offset;
862 xstats[*count].value = *(uint64_t *)val;
863 xstats[*count].id = *count;
870 hns3_txq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
873 struct hns3_tx_dfx_stats *dfx_stats;
874 struct hns3_tx_queue *txq;
878 for (i = 0; i < dev->data->nb_tx_queues; i++) {
879 txq = (struct hns3_tx_queue *)dev->data->tx_queues[i];
883 dfx_stats = &txq->dfx_stats;
884 for (j = 0; j < HNS3_NUM_TXQ_DFX_XSTATS; j++) {
885 val = (char *)dfx_stats +
886 hns3_txq_dfx_stats_strings[j].offset;
887 xstats[*count].value = *(uint64_t *)val;
888 xstats[*count].id = *count;
895 hns3_tqp_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
898 hns3_rxq_dfx_stats_get(dev, xstats, count);
899 hns3_txq_dfx_stats_get(dev, xstats, count);
903 hns3_rxq_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
906 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
907 struct hns3_tqp_stats *stats = &hw->tqp_stats;
908 struct hns3_rx_basic_stats *rxq_stats;
909 struct hns3_rx_queue *rxq;
914 for (i = 0; i < dev->data->nb_rx_queues; i++) {
915 rxq = dev->data->rx_queues[i];
919 cnt = hns3_read_dev(rxq, HNS3_RING_RX_PKTNUM_RECORD_REG);
921 * Read hardware and software in adjacent positions to minimize
922 * the time difference.
924 rxq_stats = &rxq->basic_stats;
925 rxq_stats->errors = rxq->err_stats.l2_errors +
926 rxq->err_stats.pkt_len_errors;
927 stats->rcb_rx_ring_pktnum_rcd += cnt;
928 stats->rcb_rx_ring_pktnum[i] += cnt;
931 * If HW statistics are reset by stats_reset, but a lot of
932 * residual packets exist in the hardware queue and these
933 * packets are error packets, flip overflow may occurred.
934 * So return 0 in this case.
937 stats->rcb_rx_ring_pktnum[i] > rxq_stats->errors ?
938 stats->rcb_rx_ring_pktnum[i] - rxq_stats->errors : 0;
939 for (j = 0; j < HNS3_NUM_RXQ_BASIC_STATS; j++) {
940 val = (char *)rxq_stats +
941 hns3_rxq_basic_stats_strings[j].offset;
942 xstats[*count].value = *(uint64_t *)val;
943 xstats[*count].id = *count;
950 hns3_txq_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
953 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
954 struct hns3_tqp_stats *stats = &hw->tqp_stats;
955 struct hns3_tx_basic_stats *txq_stats;
956 struct hns3_tx_queue *txq;
961 for (i = 0; i < dev->data->nb_tx_queues; i++) {
962 txq = dev->data->tx_queues[i];
966 cnt = hns3_read_dev(txq, HNS3_RING_TX_PKTNUM_RECORD_REG);
967 stats->rcb_tx_ring_pktnum_rcd += cnt;
968 stats->rcb_tx_ring_pktnum[i] += cnt;
970 txq_stats = &txq->basic_stats;
971 txq_stats->packets = stats->rcb_tx_ring_pktnum[i];
973 for (j = 0; j < HNS3_NUM_TXQ_BASIC_STATS; j++) {
974 val = (char *)txq_stats +
975 hns3_txq_basic_stats_strings[j].offset;
976 xstats[*count].value = *(uint64_t *)val;
977 xstats[*count].id = *count;
984 hns3_tqp_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
987 hns3_rxq_basic_stats_get(dev, xstats, count);
988 hns3_txq_basic_stats_get(dev, xstats, count);
992 hns3_imissed_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
995 struct hns3_adapter *hns = dev->data->dev_private;
996 struct hns3_hw *hw = &hns->hw;
997 struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats;
998 int imissed_stats_num;
1003 imissed_stats_num = hns3_get_imissed_stats_num(hns);
1005 for (i = 0; i < imissed_stats_num; i++) {
1006 addr = (char *)imissed_stats +
1007 hns3_imissed_stats_strings[i].offset;
1008 xstats[cnt].value = *(uint64_t *)addr;
1009 xstats[cnt].id = cnt;
1017 * Retrieve extended(tqp | Mac) statistics of an Ethernet device.
1019 * Pointer to Ethernet device.
1021 * A pointer to a table of structure of type *rte_eth_xstat*
1022 * to be filled with device statistics ids and values.
1023 * This parameter can be set to NULL if n is 0.
1025 * The size of the xstats array (number of elements).
1027 * 0 on fail, count(The size of the statistics elements) on success.
1030 hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1033 struct hns3_adapter *hns = dev->data->dev_private;
1034 struct hns3_hw *hw = &hns->hw;
1035 struct hns3_mac_stats *mac_stats = &hw->mac_stats;
1036 struct hns3_reset_stats *reset_stats = &hw->reset.stats;
1037 struct hns3_rx_bd_errors_stats *rx_err_stats;
1038 struct hns3_rx_queue *rxq;
1047 count = hns3_xstats_calc_num(dev);
1053 hns3_tqp_basic_stats_get(dev, xstats, &count);
1056 /* Update Mac stats */
1057 ret = hns3_query_update_mac_stats(dev);
1059 hns3_err(hw, "Update Mac stats fail : %d", ret);
1063 /* Get MAC stats from hw->hw_xstats.mac_stats struct */
1064 for (i = 0; i < HNS3_NUM_MAC_STATS; i++) {
1065 addr = (char *)mac_stats + hns3_mac_strings[i].offset;
1066 xstats[count].value = *(uint64_t *)addr;
1067 xstats[count].id = count;
1072 ret = hns3_update_imissed_stats(hw, false);
1074 hns3_err(hw, "update imissed stats failed, ret = %d",
1079 hns3_imissed_stats_get(dev, xstats, &count);
1081 /* Get the reset stat */
1082 for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) {
1083 addr = (char *)reset_stats + hns3_reset_stats_strings[i].offset;
1084 xstats[count].value = *(uint64_t *)addr;
1085 xstats[count].id = count;
1089 /* Get the Rx BD errors stats */
1090 for (j = 0; j < dev->data->nb_rx_queues; j++) {
1091 for (i = 0; i < HNS3_NUM_RX_BD_ERROR_XSTATS; i++) {
1092 rxq = dev->data->rx_queues[j];
1094 rx_err_stats = &rxq->err_stats;
1095 addr = (char *)rx_err_stats +
1096 hns3_rx_bd_error_strings[i].offset;
1097 xstats[count].value = *(uint64_t *)addr;
1098 xstats[count].id = count;
1104 hns3_tqp_dfx_stats_get(dev, xstats, &count);
1105 hns3_queue_stats_get(dev, xstats, &count);
1111 hns3_tqp_basic_stats_name_get(struct rte_eth_dev *dev,
1112 struct rte_eth_xstat_name *xstats_names,
1117 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1118 for (j = 0; j < HNS3_NUM_RXQ_BASIC_STATS; j++) {
1119 snprintf(xstats_names[*count].name,
1120 sizeof(xstats_names[*count].name),
1122 hns3_rxq_basic_stats_strings[j].name);
1126 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1127 for (j = 0; j < HNS3_NUM_TXQ_BASIC_STATS; j++) {
1128 snprintf(xstats_names[*count].name,
1129 sizeof(xstats_names[*count].name),
1131 hns3_txq_basic_stats_strings[j].name);
1138 hns3_tqp_dfx_stats_name_get(struct rte_eth_dev *dev,
1139 struct rte_eth_xstat_name *xstats_names,
1144 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1145 for (j = 0; j < HNS3_NUM_RXQ_DFX_XSTATS; j++) {
1146 snprintf(xstats_names[*count].name,
1147 sizeof(xstats_names[*count].name),
1149 hns3_rxq_dfx_stats_strings[j].name);
1154 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1155 for (j = 0; j < HNS3_NUM_TXQ_DFX_XSTATS; j++) {
1156 snprintf(xstats_names[*count].name,
1157 sizeof(xstats_names[*count].name),
1159 hns3_txq_dfx_stats_strings[j].name);
1166 hns3_imissed_stats_name_get(struct rte_eth_dev *dev,
1167 struct rte_eth_xstat_name *xstats_names,
1170 struct hns3_adapter *hns = dev->data->dev_private;
1171 uint32_t cnt = *count;
1172 int imissed_stats_num;
1175 imissed_stats_num = hns3_get_imissed_stats_num(hns);
1177 for (i = 0; i < imissed_stats_num; i++) {
1178 snprintf(xstats_names[cnt].name,
1179 sizeof(xstats_names[cnt].name),
1180 "%s", hns3_imissed_stats_strings[i].name);
1188 * Retrieve names of extended statistics of an Ethernet device.
1190 * There is an assumption that 'xstat_names' and 'xstats' arrays are matched
1192 * xstats_names[i].name => xstats[i].value
1194 * And the array index is same with id field of 'struct rte_eth_xstat':
1197 * This assumption makes key-value pair matching less flexible but simpler.
1200 * Pointer to Ethernet device.
1201 * @param xstats_names
1202 * An rte_eth_xstat_name array of at least *size* elements to
1203 * be filled. If set to NULL, the function returns the required number
1206 * The size of the xstats_names array (number of elements).
1208 * - A positive value lower or equal to size: success. The return value
1209 * is the number of entries filled in the stats table.
1212 hns3_dev_xstats_get_names(struct rte_eth_dev *dev,
1213 struct rte_eth_xstat_name *xstats_names,
1214 __rte_unused unsigned int size)
1216 struct hns3_adapter *hns = dev->data->dev_private;
1217 int cnt_stats = hns3_xstats_calc_num(dev);
1221 if (xstats_names == NULL)
1224 hns3_tqp_basic_stats_name_get(dev, xstats_names, &count);
1226 /* Note: size limited checked in rte_eth_xstats_get_names() */
1228 /* Get MAC name from hw->hw_xstats.mac_stats struct */
1229 for (i = 0; i < HNS3_NUM_MAC_STATS; i++) {
1230 snprintf(xstats_names[count].name,
1231 sizeof(xstats_names[count].name),
1232 "%s", hns3_mac_strings[i].name);
1237 hns3_imissed_stats_name_get(dev, xstats_names, &count);
1239 for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) {
1240 snprintf(xstats_names[count].name,
1241 sizeof(xstats_names[count].name),
1242 "%s", hns3_reset_stats_strings[i].name);
1246 for (j = 0; j < dev->data->nb_rx_queues; j++) {
1247 for (i = 0; i < HNS3_NUM_RX_BD_ERROR_XSTATS; i++) {
1248 snprintf(xstats_names[count].name,
1249 sizeof(xstats_names[count].name),
1251 hns3_rx_bd_error_strings[i].name);
1256 hns3_tqp_dfx_stats_name_get(dev, xstats_names, &count);
1258 for (j = 0; j < dev->data->nb_rx_queues; j++) {
1259 for (i = 0; i < HNS3_NUM_RX_QUEUE_STATS; i++) {
1260 snprintf(xstats_names[count].name,
1261 sizeof(xstats_names[count].name),
1262 "rx_q%u_%s", j, hns3_rx_queue_strings[i].name);
1267 for (j = 0; j < dev->data->nb_tx_queues; j++) {
1268 for (i = 0; i < HNS3_NUM_TX_QUEUE_STATS; i++) {
1269 snprintf(xstats_names[count].name,
1270 sizeof(xstats_names[count].name),
1271 "tx_q%u_%s", j, hns3_tx_queue_strings[i].name);
1280 * Retrieve extended statistics of an Ethernet device.
1283 * Pointer to Ethernet device.
1285 * A pointer to an ids array passed by application. This tells which
1286 * statistics values function should retrieve. This parameter
1287 * can be set to NULL if size is 0. In this case function will retrieve
1288 * all available statistics.
1290 * A pointer to a table to be filled with device statistics values.
1292 * The size of the ids array (number of elements).
1294 * - A positive value lower or equal to size: success. The return value
1295 * is the number of entries filled in the stats table.
1296 * - A positive value higher than size: error, the given statistics table
1297 * is too small. The return value corresponds to the size that should
1298 * be given to succeed. The entries in the table are not valid and
1299 * shall not be used by the caller.
1303 hns3_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1304 uint64_t *values, uint32_t size)
1306 const uint32_t cnt_stats = hns3_xstats_calc_num(dev);
1307 struct hns3_adapter *hns = dev->data->dev_private;
1308 struct rte_eth_xstat *values_copy;
1309 struct hns3_hw *hw = &hns->hw;
1310 uint32_t count_value;
1314 if (ids == NULL && values == NULL)
1318 if (size < cnt_stats)
1321 len = cnt_stats * sizeof(struct rte_eth_xstat);
1322 values_copy = rte_zmalloc("hns3_xstats_values", len, 0);
1323 if (values_copy == NULL) {
1324 hns3_err(hw, "Failed to allocate 0x%" PRIx64 " bytes needed "
1325 "to store statistics values", len);
1329 count_value = hns3_dev_xstats_get(dev, values_copy, cnt_stats);
1330 if (count_value != cnt_stats) {
1331 rte_free(values_copy);
1335 if (ids == NULL && values != NULL) {
1336 for (i = 0; i < cnt_stats; i++)
1337 memcpy(&values[i], &values_copy[i].value,
1340 rte_free(values_copy);
1344 for (i = 0; i < size; i++) {
1345 if (ids[i] >= cnt_stats) {
1346 hns3_err(hw, "ids[%u] (%" PRIu64 ") is invalid, "
1347 "should < %u", i, ids[i], cnt_stats);
1348 rte_free(values_copy);
1351 memcpy(&values[i], &values_copy[ids[i]].value,
1355 rte_free(values_copy);
1360 * Retrieve names of extended statistics of an Ethernet device.
1363 * Pointer to Ethernet device.
1365 * IDs array given by app to retrieve specific statistics
1366 * @param xstats_names
1367 * An rte_eth_xstat_name array of at least *size* elements to
1368 * be filled. If set to NULL, the function returns the required number
1371 * The size of the xstats_names array (number of elements).
1373 * - A positive value lower or equal to size: success. The return value
1374 * is the number of entries filled in the stats table.
1375 * - A positive value higher than size: error, the given statistics table
1376 * is too small. The return value corresponds to the size that should
1377 * be given to succeed. The entries in the table are not valid and
1378 * shall not be used by the caller.
1381 hns3_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
1382 const uint64_t *ids,
1383 struct rte_eth_xstat_name *xstats_names,
1386 const uint32_t cnt_stats = hns3_xstats_calc_num(dev);
1387 struct hns3_adapter *hns = dev->data->dev_private;
1388 struct rte_eth_xstat_name *names_copy;
1389 struct hns3_hw *hw = &hns->hw;
1393 if (xstats_names == NULL)
1397 if (size < cnt_stats)
1400 return hns3_dev_xstats_get_names(dev, xstats_names, cnt_stats);
1403 len = cnt_stats * sizeof(struct rte_eth_xstat_name);
1404 names_copy = rte_zmalloc("hns3_xstats_names", len, 0);
1405 if (names_copy == NULL) {
1406 hns3_err(hw, "Failed to allocate 0x%" PRIx64 " bytes needed "
1407 "to store statistics names", len);
1411 (void)hns3_dev_xstats_get_names(dev, names_copy, cnt_stats);
1413 for (i = 0; i < size; i++) {
1414 if (ids[i] >= cnt_stats) {
1415 hns3_err(hw, "ids[%u] (%" PRIu64 ") is invalid, "
1416 "should < %u", i, ids[i], cnt_stats);
1417 rte_free(names_copy);
1420 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1421 "%s", names_copy[ids[i]].name);
1424 rte_free(names_copy);
1429 hns3_tqp_dfx_stats_clear(struct rte_eth_dev *dev)
1431 struct hns3_rx_queue *rxq;
1432 struct hns3_tx_queue *txq;
1435 /* Clear Rx dfx stats */
1436 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1437 rxq = dev->data->rx_queues[i];
1439 memset(&rxq->dfx_stats, 0,
1440 sizeof(struct hns3_rx_dfx_stats));
1443 /* Clear Tx dfx stats */
1444 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1445 txq = dev->data->tx_queues[i];
1447 memset(&txq->dfx_stats, 0,
1448 sizeof(struct hns3_tx_dfx_stats));
1453 hns3_dev_xstats_reset(struct rte_eth_dev *dev)
1455 struct hns3_adapter *hns = dev->data->dev_private;
1458 /* Clear tqp stats */
1459 ret = hns3_stats_reset(dev);
1463 hns3_tqp_dfx_stats_clear(dev);
1465 /* Clear reset stats */
1466 memset(&hns->hw.reset.stats, 0, sizeof(struct hns3_reset_stats));
1471 /* HW registers are cleared on read */
1472 ret = hns3_mac_stats_reset(dev);
1480 hns3_tqp_stats_init(struct hns3_hw *hw)
1482 struct hns3_tqp_stats *tqp_stats = &hw->tqp_stats;
1484 tqp_stats->rcb_rx_ring_pktnum = rte_zmalloc("hns3_rx_ring_pkt_num",
1485 sizeof(uint64_t) * hw->tqps_num, 0);
1486 if (tqp_stats->rcb_rx_ring_pktnum == NULL) {
1487 hns3_err(hw, "failed to allocate rx_ring pkt_num.");
1491 tqp_stats->rcb_tx_ring_pktnum = rte_zmalloc("hns3_tx_ring_pkt_num",
1492 sizeof(uint64_t) * hw->tqps_num, 0);
1493 if (tqp_stats->rcb_tx_ring_pktnum == NULL) {
1494 hns3_err(hw, "failed to allocate tx_ring pkt_num.");
1495 rte_free(tqp_stats->rcb_rx_ring_pktnum);
1496 tqp_stats->rcb_rx_ring_pktnum = NULL;
1504 hns3_tqp_stats_uninit(struct hns3_hw *hw)
1506 struct hns3_tqp_stats *tqp_stats = &hw->tqp_stats;
1508 rte_free(tqp_stats->rcb_rx_ring_pktnum);
1509 tqp_stats->rcb_rx_ring_pktnum = NULL;
1510 rte_free(tqp_stats->rcb_tx_ring_pktnum);
1511 tqp_stats->rcb_tx_ring_pktnum = NULL;
1515 hns3_tqp_stats_clear(struct hns3_hw *hw)
1517 struct hns3_tqp_stats *stats = &hw->tqp_stats;
1519 stats->rcb_rx_ring_pktnum_rcd = 0;
1520 stats->rcb_tx_ring_pktnum_rcd = 0;
1521 memset(stats->rcb_rx_ring_pktnum, 0, sizeof(uint64_t) * hw->tqps_num);
1522 memset(stats->rcb_tx_ring_pktnum, 0, sizeof(uint64_t) * hw->tqps_num);