1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #include <rte_ethdev.h>
7 #include <rte_malloc.h>
9 #include "hns3_ethdev.h"
10 #include "hns3_rxtx.h"
11 #include "hns3_logs.h"
12 #include "hns3_regs.h"
14 /* The statistics of the per-rxq basic stats */
15 static const struct hns3_xstats_name_offset hns3_rxq_basic_stats_strings[] = {
17 HNS3_RXQ_BASIC_STATS_FIELD_OFFSET(packets)},
19 HNS3_RXQ_BASIC_STATS_FIELD_OFFSET(bytes)},
21 HNS3_RXQ_BASIC_STATS_FIELD_OFFSET(errors)}
24 /* The statistics of the per-txq basic stats */
25 static const struct hns3_xstats_name_offset hns3_txq_basic_stats_strings[] = {
27 HNS3_TXQ_BASIC_STATS_FIELD_OFFSET(packets)},
29 HNS3_TXQ_BASIC_STATS_FIELD_OFFSET(bytes)}
33 static const struct hns3_xstats_name_offset hns3_mac_strings[] = {
34 {"mac_tx_mac_pause_num",
35 HNS3_MAC_STATS_OFFSET(mac_tx_mac_pause_num)},
36 {"mac_rx_mac_pause_num",
37 HNS3_MAC_STATS_OFFSET(mac_rx_mac_pause_num)},
38 {"mac_tx_control_pkt_num",
39 HNS3_MAC_STATS_OFFSET(mac_tx_ctrl_pkt_num)},
40 {"mac_rx_control_pkt_num",
41 HNS3_MAC_STATS_OFFSET(mac_rx_ctrl_pkt_num)},
42 {"mac_tx_pfc_pkt_num",
43 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pause_pkt_num)},
44 {"mac_tx_pfc_pri0_pkt_num",
45 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri0_pkt_num)},
46 {"mac_tx_pfc_pri1_pkt_num",
47 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri1_pkt_num)},
48 {"mac_tx_pfc_pri2_pkt_num",
49 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri2_pkt_num)},
50 {"mac_tx_pfc_pri3_pkt_num",
51 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri3_pkt_num)},
52 {"mac_tx_pfc_pri4_pkt_num",
53 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri4_pkt_num)},
54 {"mac_tx_pfc_pri5_pkt_num",
55 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri5_pkt_num)},
56 {"mac_tx_pfc_pri6_pkt_num",
57 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri6_pkt_num)},
58 {"mac_tx_pfc_pri7_pkt_num",
59 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri7_pkt_num)},
60 {"mac_rx_pfc_pkt_num",
61 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pause_pkt_num)},
62 {"mac_rx_pfc_pri0_pkt_num",
63 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri0_pkt_num)},
64 {"mac_rx_pfc_pri1_pkt_num",
65 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri1_pkt_num)},
66 {"mac_rx_pfc_pri2_pkt_num",
67 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri2_pkt_num)},
68 {"mac_rx_pfc_pri3_pkt_num",
69 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri3_pkt_num)},
70 {"mac_rx_pfc_pri4_pkt_num",
71 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri4_pkt_num)},
72 {"mac_rx_pfc_pri5_pkt_num",
73 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri5_pkt_num)},
74 {"mac_rx_pfc_pri6_pkt_num",
75 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri6_pkt_num)},
76 {"mac_rx_pfc_pri7_pkt_num",
77 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri7_pkt_num)},
78 {"mac_tx_total_pkt_num",
79 HNS3_MAC_STATS_OFFSET(mac_tx_total_pkt_num)},
80 {"mac_tx_total_oct_num",
81 HNS3_MAC_STATS_OFFSET(mac_tx_total_oct_num)},
82 {"mac_tx_good_pkt_num",
83 HNS3_MAC_STATS_OFFSET(mac_tx_good_pkt_num)},
84 {"mac_tx_bad_pkt_num",
85 HNS3_MAC_STATS_OFFSET(mac_tx_bad_pkt_num)},
86 {"mac_tx_good_oct_num",
87 HNS3_MAC_STATS_OFFSET(mac_tx_good_oct_num)},
88 {"mac_tx_bad_oct_num",
89 HNS3_MAC_STATS_OFFSET(mac_tx_bad_oct_num)},
90 {"mac_tx_uni_pkt_num",
91 HNS3_MAC_STATS_OFFSET(mac_tx_uni_pkt_num)},
92 {"mac_tx_multi_pkt_num",
93 HNS3_MAC_STATS_OFFSET(mac_tx_multi_pkt_num)},
94 {"mac_tx_broad_pkt_num",
95 HNS3_MAC_STATS_OFFSET(mac_tx_broad_pkt_num)},
96 {"mac_tx_undersize_pkt_num",
97 HNS3_MAC_STATS_OFFSET(mac_tx_undersize_pkt_num)},
98 {"mac_tx_oversize_pkt_num",
99 HNS3_MAC_STATS_OFFSET(mac_tx_oversize_pkt_num)},
100 {"mac_tx_64_oct_pkt_num",
101 HNS3_MAC_STATS_OFFSET(mac_tx_64_oct_pkt_num)},
102 {"mac_tx_65_127_oct_pkt_num",
103 HNS3_MAC_STATS_OFFSET(mac_tx_65_127_oct_pkt_num)},
104 {"mac_tx_128_255_oct_pkt_num",
105 HNS3_MAC_STATS_OFFSET(mac_tx_128_255_oct_pkt_num)},
106 {"mac_tx_256_511_oct_pkt_num",
107 HNS3_MAC_STATS_OFFSET(mac_tx_256_511_oct_pkt_num)},
108 {"mac_tx_512_1023_oct_pkt_num",
109 HNS3_MAC_STATS_OFFSET(mac_tx_512_1023_oct_pkt_num)},
110 {"mac_tx_1024_1518_oct_pkt_num",
111 HNS3_MAC_STATS_OFFSET(mac_tx_1024_1518_oct_pkt_num)},
112 {"mac_tx_1519_2047_oct_pkt_num",
113 HNS3_MAC_STATS_OFFSET(mac_tx_1519_2047_oct_pkt_num)},
114 {"mac_tx_2048_4095_oct_pkt_num",
115 HNS3_MAC_STATS_OFFSET(mac_tx_2048_4095_oct_pkt_num)},
116 {"mac_tx_4096_8191_oct_pkt_num",
117 HNS3_MAC_STATS_OFFSET(mac_tx_4096_8191_oct_pkt_num)},
118 {"mac_tx_8192_9216_oct_pkt_num",
119 HNS3_MAC_STATS_OFFSET(mac_tx_8192_9216_oct_pkt_num)},
120 {"mac_tx_9217_12287_oct_pkt_num",
121 HNS3_MAC_STATS_OFFSET(mac_tx_9217_12287_oct_pkt_num)},
122 {"mac_tx_12288_16383_oct_pkt_num",
123 HNS3_MAC_STATS_OFFSET(mac_tx_12288_16383_oct_pkt_num)},
124 {"mac_tx_1519_max_good_pkt_num",
125 HNS3_MAC_STATS_OFFSET(mac_tx_1519_max_good_oct_pkt_num)},
126 {"mac_tx_1519_max_bad_pkt_num",
127 HNS3_MAC_STATS_OFFSET(mac_tx_1519_max_bad_oct_pkt_num)},
128 {"mac_rx_total_pkt_num",
129 HNS3_MAC_STATS_OFFSET(mac_rx_total_pkt_num)},
130 {"mac_rx_total_oct_num",
131 HNS3_MAC_STATS_OFFSET(mac_rx_total_oct_num)},
132 {"mac_rx_good_pkt_num",
133 HNS3_MAC_STATS_OFFSET(mac_rx_good_pkt_num)},
134 {"mac_rx_bad_pkt_num",
135 HNS3_MAC_STATS_OFFSET(mac_rx_bad_pkt_num)},
136 {"mac_rx_good_oct_num",
137 HNS3_MAC_STATS_OFFSET(mac_rx_good_oct_num)},
138 {"mac_rx_bad_oct_num",
139 HNS3_MAC_STATS_OFFSET(mac_rx_bad_oct_num)},
140 {"mac_rx_uni_pkt_num",
141 HNS3_MAC_STATS_OFFSET(mac_rx_uni_pkt_num)},
142 {"mac_rx_multi_pkt_num",
143 HNS3_MAC_STATS_OFFSET(mac_rx_multi_pkt_num)},
144 {"mac_rx_broad_pkt_num",
145 HNS3_MAC_STATS_OFFSET(mac_rx_broad_pkt_num)},
146 {"mac_rx_undersize_pkt_num",
147 HNS3_MAC_STATS_OFFSET(mac_rx_undersize_pkt_num)},
148 {"mac_rx_oversize_pkt_num",
149 HNS3_MAC_STATS_OFFSET(mac_rx_oversize_pkt_num)},
150 {"mac_rx_64_oct_pkt_num",
151 HNS3_MAC_STATS_OFFSET(mac_rx_64_oct_pkt_num)},
152 {"mac_rx_65_127_oct_pkt_num",
153 HNS3_MAC_STATS_OFFSET(mac_rx_65_127_oct_pkt_num)},
154 {"mac_rx_128_255_oct_pkt_num",
155 HNS3_MAC_STATS_OFFSET(mac_rx_128_255_oct_pkt_num)},
156 {"mac_rx_256_511_oct_pkt_num",
157 HNS3_MAC_STATS_OFFSET(mac_rx_256_511_oct_pkt_num)},
158 {"mac_rx_512_1023_oct_pkt_num",
159 HNS3_MAC_STATS_OFFSET(mac_rx_512_1023_oct_pkt_num)},
160 {"mac_rx_1024_1518_oct_pkt_num",
161 HNS3_MAC_STATS_OFFSET(mac_rx_1024_1518_oct_pkt_num)},
162 {"mac_rx_1519_2047_oct_pkt_num",
163 HNS3_MAC_STATS_OFFSET(mac_rx_1519_2047_oct_pkt_num)},
164 {"mac_rx_2048_4095_oct_pkt_num",
165 HNS3_MAC_STATS_OFFSET(mac_rx_2048_4095_oct_pkt_num)},
166 {"mac_rx_4096_8191_oct_pkt_num",
167 HNS3_MAC_STATS_OFFSET(mac_rx_4096_8191_oct_pkt_num)},
168 {"mac_rx_8192_9216_oct_pkt_num",
169 HNS3_MAC_STATS_OFFSET(mac_rx_8192_9216_oct_pkt_num)},
170 {"mac_rx_9217_12287_oct_pkt_num",
171 HNS3_MAC_STATS_OFFSET(mac_rx_9217_12287_oct_pkt_num)},
172 {"mac_rx_12288_16383_oct_pkt_num",
173 HNS3_MAC_STATS_OFFSET(mac_rx_12288_16383_oct_pkt_num)},
174 {"mac_rx_1519_max_good_pkt_num",
175 HNS3_MAC_STATS_OFFSET(mac_rx_1519_max_good_oct_pkt_num)},
176 {"mac_rx_1519_max_bad_pkt_num",
177 HNS3_MAC_STATS_OFFSET(mac_rx_1519_max_bad_oct_pkt_num)},
178 {"mac_tx_fragment_pkt_num",
179 HNS3_MAC_STATS_OFFSET(mac_tx_fragment_pkt_num)},
180 {"mac_tx_undermin_pkt_num",
181 HNS3_MAC_STATS_OFFSET(mac_tx_undermin_pkt_num)},
182 {"mac_tx_jabber_pkt_num",
183 HNS3_MAC_STATS_OFFSET(mac_tx_jabber_pkt_num)},
184 {"mac_tx_err_all_pkt_num",
185 HNS3_MAC_STATS_OFFSET(mac_tx_err_all_pkt_num)},
186 {"mac_tx_from_app_good_pkt_num",
187 HNS3_MAC_STATS_OFFSET(mac_tx_from_app_good_pkt_num)},
188 {"mac_tx_from_app_bad_pkt_num",
189 HNS3_MAC_STATS_OFFSET(mac_tx_from_app_bad_pkt_num)},
190 {"mac_rx_fragment_pkt_num",
191 HNS3_MAC_STATS_OFFSET(mac_rx_fragment_pkt_num)},
192 {"mac_rx_undermin_pkt_num",
193 HNS3_MAC_STATS_OFFSET(mac_rx_undermin_pkt_num)},
194 {"mac_rx_jabber_pkt_num",
195 HNS3_MAC_STATS_OFFSET(mac_rx_jabber_pkt_num)},
196 {"mac_rx_fcs_err_pkt_num",
197 HNS3_MAC_STATS_OFFSET(mac_rx_fcs_err_pkt_num)},
198 {"mac_rx_send_app_good_pkt_num",
199 HNS3_MAC_STATS_OFFSET(mac_rx_send_app_good_pkt_num)},
200 {"mac_rx_send_app_bad_pkt_num",
201 HNS3_MAC_STATS_OFFSET(mac_rx_send_app_bad_pkt_num)}
204 static const struct hns3_xstats_name_offset hns3_error_int_stats_strings[] = {
205 {"MAC_AFIFO_TNL_INT_R",
206 HNS3_ERR_INT_STATS_FIELD_OFFSET(mac_afifo_tnl_int_cnt)},
207 {"PPU_MPF_ABNORMAL_INT_ST2_MSIX",
208 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_msix_cnt)},
209 {"SSU_PORT_BASED_ERR_INT_MSIX",
210 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_pf_int_cnt)},
211 {"PPP_PF_ABNORMAL_INT_ST0",
212 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_pf_abnormal_int_cnt)},
213 {"PPU_PF_ABNORMAL_INT_ST_MSIX",
214 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_msix_cnt)},
215 {"IMP_TCM_ECC_INT_STS",
216 HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_tcm_ecc_int_cnt)},
217 {"CMDQ_MEM_ECC_INT_STS",
218 HNS3_ERR_INT_STATS_FIELD_OFFSET(cmdq_mem_ecc_int_cnt)},
219 {"IMP_RD_POISON_INT_STS",
220 HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_rd_poison_int_cnt)},
221 {"TQP_INT_ECC_INT_STS",
222 HNS3_ERR_INT_STATS_FIELD_OFFSET(tqp_int_ecc_int_cnt)},
224 HNS3_ERR_INT_STATS_FIELD_OFFSET(msix_ecc_int_cnt)},
225 {"SSU_ECC_MULTI_BIT_INT_0",
226 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_0_cnt)},
227 {"SSU_ECC_MULTI_BIT_INT_1",
228 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_1_cnt)},
229 {"SSU_COMMON_ERR_INT",
230 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_common_ecc_int_cnt)},
232 HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_int_cnt)},
233 {"PPP_MPF_ABNORMAL_INT_ST1",
234 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st1_cnt)},
235 {"PPP_MPF_ABNORMAL_INT_ST3",
236 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st3_cnt)},
237 {"PPU_MPF_ABNORMAL_INT_ST1",
238 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st1_cnt)},
239 {"PPU_MPF_ABNORMAL_INT_ST2_RAS",
240 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_ras_cnt)},
241 {"PPU_MPF_ABNORMAL_INT_ST3",
242 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st3_cnt)},
244 HNS3_ERR_INT_STATS_FIELD_OFFSET(tm_sch_int_cnt)},
246 HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_fifo_int_cnt)},
248 HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_ecc_int_cnt)},
250 HNS3_ERR_INT_STATS_FIELD_OFFSET(ncsi_ecc_int_cnt)},
251 {"SSU_PORT_BASED_ERR_INT_RAS",
252 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_err_int_cnt)},
253 {"SSU_FIFO_OVERFLOW_INT",
254 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_fifo_overflow_int_cnt)},
256 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ets_tcg_int_cnt)},
257 {"IGU_EGU_TNL_INT_STS",
258 HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_egu_tnl_int_cnt)},
259 {"PPU_PF_ABNORMAL_INT_ST_RAS",
260 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_ras_cnt)},
263 /* The statistic of reset */
264 static const struct hns3_xstats_name_offset hns3_reset_stats_strings[] = {
266 HNS3_RESET_STATS_FIELD_OFFSET(request_cnt)},
268 HNS3_RESET_STATS_FIELD_OFFSET(global_cnt)},
270 HNS3_RESET_STATS_FIELD_OFFSET(imp_cnt)},
272 HNS3_RESET_STATS_FIELD_OFFSET(exec_cnt)},
273 {"RESET_SUCCESS_CNT",
274 HNS3_RESET_STATS_FIELD_OFFSET(success_cnt)},
276 HNS3_RESET_STATS_FIELD_OFFSET(fail_cnt)},
278 HNS3_RESET_STATS_FIELD_OFFSET(merge_cnt)}
281 /* The statistic of errors in Rx BD */
282 static const struct hns3_xstats_name_offset hns3_rx_bd_error_strings[] = {
284 HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(pkt_len_errors)},
286 HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(l2_errors)}
289 /* The dfx statistic in Rx datapath */
290 static const struct hns3_xstats_name_offset hns3_rxq_dfx_stats_strings[] = {
291 {"L3_CHECKSUM_ERRORS",
292 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(l3_csum_errors)},
293 {"L4_CHECKSUM_ERRORS",
294 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(l4_csum_errors)},
295 {"OL3_CHECKSUM_ERRORS",
296 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(ol3_csum_errors)},
297 {"OL4_CHECKSUM_ERRORS",
298 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(ol4_csum_errors)}
301 /* The dfx statistic in Tx datapath */
302 static const struct hns3_xstats_name_offset hns3_txq_dfx_stats_strings[] = {
303 {"OVER_LENGTH_PKT_CNT",
304 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(over_length_pkt_cnt)},
305 {"EXCEED_LIMITED_BD_PKT_CNT",
306 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(exceed_limit_bd_pkt_cnt)},
307 {"EXCEED_LIMITED_BD_PKT_REASSEMBLE_FAIL_CNT",
308 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(exceed_limit_bd_reassem_fail)},
309 {"UNSUPPORTED_TUNNEL_PKT_CNT",
310 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(unsupported_tunnel_pkt_cnt)},
312 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(queue_full_cnt)},
313 {"SHORT_PKT_PAD_FAIL_CNT",
314 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(pkt_padding_fail_cnt)}
317 /* The statistic of rx queue */
318 static const struct hns3_xstats_name_offset hns3_rx_queue_strings[] = {
319 {"RX_QUEUE_FBD", HNS3_RING_RX_FBDNUM_REG}
322 /* The statistic of tx queue */
323 static const struct hns3_xstats_name_offset hns3_tx_queue_strings[] = {
324 {"TX_QUEUE_FBD", HNS3_RING_TX_FBDNUM_REG}
327 #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \
328 sizeof(hns3_mac_strings[0]))
330 #define HNS3_NUM_ERROR_INT_XSTATS (sizeof(hns3_error_int_stats_strings) / \
331 sizeof(hns3_error_int_stats_strings[0]))
333 #define HNS3_NUM_RESET_XSTATS (sizeof(hns3_reset_stats_strings) / \
334 sizeof(hns3_reset_stats_strings[0]))
336 #define HNS3_NUM_RX_BD_ERROR_XSTATS (sizeof(hns3_rx_bd_error_strings) / \
337 sizeof(hns3_rx_bd_error_strings[0]))
339 #define HNS3_NUM_RXQ_DFX_XSTATS (sizeof(hns3_rxq_dfx_stats_strings) / \
340 sizeof(hns3_rxq_dfx_stats_strings[0]))
342 #define HNS3_NUM_TXQ_DFX_XSTATS (sizeof(hns3_txq_dfx_stats_strings) / \
343 sizeof(hns3_txq_dfx_stats_strings[0]))
345 #define HNS3_NUM_RX_QUEUE_STATS (sizeof(hns3_rx_queue_strings) / \
346 sizeof(hns3_rx_queue_strings[0]))
348 #define HNS3_NUM_TX_QUEUE_STATS (sizeof(hns3_tx_queue_strings) / \
349 sizeof(hns3_tx_queue_strings[0]))
351 #define HNS3_NUM_RXQ_BASIC_STATS (sizeof(hns3_rxq_basic_stats_strings) / \
352 sizeof(hns3_rxq_basic_stats_strings[0]))
354 #define HNS3_NUM_TXQ_BASIC_STATS (sizeof(hns3_txq_basic_stats_strings) / \
355 sizeof(hns3_txq_basic_stats_strings[0]))
357 #define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_ERROR_INT_XSTATS + \
358 HNS3_NUM_RESET_XSTATS)
360 static void hns3_tqp_stats_clear(struct hns3_hw *hw);
363 * Query all the MAC statistics data of Network ICL command ,opcode id: 0x0034.
364 * This command is used before send 'query_mac_stat command', the descriptor
365 * number of 'query_mac_stat command' must match with reg_num in this command.
367 * Pointer to structure hns3_hw.
372 hns3_update_mac_stats(struct hns3_hw *hw, const uint32_t desc_num)
374 uint64_t *data = (uint64_t *)(&hw->mac_stats);
375 struct hns3_cmd_desc *desc;
380 desc = rte_malloc("hns3_mac_desc",
381 desc_num * sizeof(struct hns3_cmd_desc), 0);
383 hns3_err(hw, "Mac_update_stats alloced desc malloc fail");
387 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_STATS_MAC_ALL, true);
388 ret = hns3_cmd_send(hw, desc, desc_num);
390 hns3_err(hw, "Update complete MAC pkt stats fail : %d", ret);
395 for (i = 0; i < desc_num; i++) {
396 /* For special opcode 0034, only the first desc has the head */
398 desc_data = (uint64_t *)(&desc[i].data[0]);
399 n = HNS3_RD_FIRST_STATS_NUM;
401 desc_data = (uint64_t *)(&desc[i]);
402 n = HNS3_RD_OTHER_STATS_NUM;
405 for (k = 0; k < n; k++) {
406 *data += rte_le_to_cpu_64(*desc_data);
417 * Query Mac stat reg num command ,opcode id: 0x0033.
418 * This command is used before send 'query_mac_stat command', the descriptor
419 * number of 'query_mac_stat command' must match with reg_num in this command.
421 * Pointer to structure rte_eth_stats.
426 hns3_mac_query_reg_num(struct rte_eth_dev *dev, uint32_t *desc_num)
428 struct hns3_adapter *hns = dev->data->dev_private;
429 struct hns3_hw *hw = &hns->hw;
430 struct hns3_cmd_desc desc;
435 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_REG_NUM, true);
436 ret = hns3_cmd_send(hw, &desc, 1);
441 * The num of MAC statistics registers that are provided by IMP in this
444 desc_data = (uint32_t *)(&desc.data[0]);
445 reg_num = rte_le_to_cpu_32(*desc_data);
448 * The descriptor number of 'query_additional_mac_stat command' is
449 * '1 + (reg_num-3)/4 + ((reg_num-3)%4 !=0)';
450 * This value is 83 in this version
452 *desc_num = 1 + ((reg_num - 3) >> 2) +
453 (uint32_t)(((reg_num - 3) & 0x3) ? 1 : 0);
459 hns3_query_update_mac_stats(struct rte_eth_dev *dev)
461 struct hns3_adapter *hns = dev->data->dev_private;
462 struct hns3_hw *hw = &hns->hw;
466 ret = hns3_mac_query_reg_num(dev, &desc_num);
468 ret = hns3_update_mac_stats(hw, desc_num);
470 hns3_err(hw, "Query mac reg num fail : %d", ret);
474 /* Get tqp stats from register */
476 hns3_update_tqp_stats(struct hns3_hw *hw)
478 struct hns3_tqp_stats *stats = &hw->tqp_stats;
479 struct hns3_cmd_desc desc;
484 for (i = 0; i < hw->tqps_num; i++) {
485 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_RX_STATUS,
488 desc.data[0] = rte_cpu_to_le_32((uint32_t)i);
489 ret = hns3_cmd_send(hw, &desc, 1);
491 hns3_err(hw, "Failed to query RX No.%u queue stat: %d",
495 cnt = rte_le_to_cpu_32(desc.data[1]);
496 stats->rcb_rx_ring_pktnum_rcd += cnt;
497 stats->rcb_rx_ring_pktnum[i] += cnt;
499 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_TX_STATUS,
502 desc.data[0] = rte_cpu_to_le_32((uint32_t)i);
503 ret = hns3_cmd_send(hw, &desc, 1);
505 hns3_err(hw, "Failed to query TX No.%u queue stat: %d",
509 cnt = rte_le_to_cpu_32(desc.data[1]);
510 stats->rcb_tx_ring_pktnum_rcd += cnt;
511 stats->rcb_tx_ring_pktnum[i] += cnt;
518 * Query tqp tx queue statistics ,opcode id: 0x0B03.
519 * Query tqp rx queue statistics ,opcode id: 0x0B13.
520 * Get all statistics of a port.
522 * Pointer to Ethernet device.
524 * Pointer to structure rte_eth_stats.
529 hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats)
531 struct hns3_adapter *hns = eth_dev->data->dev_private;
532 struct hns3_hw *hw = &hns->hw;
533 struct hns3_tqp_stats *stats = &hw->tqp_stats;
534 struct hns3_rx_queue *rxq;
539 /* Update tqp stats by read register */
540 ret = hns3_update_tqp_stats(hw);
542 hns3_err(hw, "Update tqp stats fail : %d", ret);
546 /* Get the error stats of received packets */
547 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
548 rxq = eth_dev->data->rx_queues[i];
550 cnt = rxq->err_stats.l2_errors +
551 rxq->err_stats.pkt_len_errors;
552 rte_stats->ierrors += cnt;
556 rte_stats->oerrors = 0;
558 * If HW statistics are reset by stats_reset, but a lot of residual
559 * packets exist in the hardware queue and these packets are error
560 * packets, flip overflow may occurred. So return 0 in this case.
562 rte_stats->ipackets =
563 stats->rcb_rx_ring_pktnum_rcd > rte_stats->ierrors ?
564 stats->rcb_rx_ring_pktnum_rcd - rte_stats->ierrors : 0;
565 rte_stats->opackets = stats->rcb_tx_ring_pktnum_rcd -
567 rte_stats->rx_nombuf = eth_dev->data->rx_mbuf_alloc_failed;
573 hns3_stats_reset(struct rte_eth_dev *eth_dev)
575 struct hns3_adapter *hns = eth_dev->data->dev_private;
576 struct hns3_hw *hw = &hns->hw;
577 struct hns3_cmd_desc desc_reset;
578 struct hns3_rx_queue *rxq;
583 * Note: Reading hardware statistics of rx/tx queue packet number
586 for (i = 0; i < hw->tqps_num; i++) {
587 hns3_cmd_setup_basic_desc(&desc_reset, HNS3_OPC_QUERY_RX_STATUS,
589 desc_reset.data[0] = rte_cpu_to_le_32((uint32_t)i);
590 ret = hns3_cmd_send(hw, &desc_reset, 1);
592 hns3_err(hw, "Failed to reset RX No.%u queue stat: %d",
597 hns3_cmd_setup_basic_desc(&desc_reset, HNS3_OPC_QUERY_TX_STATUS,
599 desc_reset.data[0] = rte_cpu_to_le_32((uint32_t)i);
600 ret = hns3_cmd_send(hw, &desc_reset, 1);
602 hns3_err(hw, "Failed to reset TX No.%u queue stat: %d",
609 * Clear soft stats of rx error packet which will be dropped
612 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
613 rxq = eth_dev->data->rx_queues[i];
615 rxq->err_stats.pkt_len_errors = 0;
616 rxq->err_stats.l2_errors = 0;
621 * 'packets' in hns3_tx_basic_stats and hns3_rx_basic_stats come
622 * from hw->tqp_stats. And clearing tqp stats is like clearing
625 hns3_tqp_stats_clear(hw);
631 hns3_mac_stats_reset(__rte_unused struct rte_eth_dev *dev)
633 struct hns3_adapter *hns = dev->data->dev_private;
634 struct hns3_hw *hw = &hns->hw;
635 struct hns3_mac_stats *mac_stats = &hw->mac_stats;
638 ret = hns3_query_update_mac_stats(dev);
640 hns3_err(hw, "Clear Mac stats fail : %d", ret);
644 memset(mac_stats, 0, sizeof(struct hns3_mac_stats));
649 /* This function calculates the number of xstats based on the current config */
651 hns3_xstats_calc_num(struct rte_eth_dev *dev)
653 #define HNS3_PF_VF_RX_COMM_STATS_NUM (HNS3_NUM_RX_BD_ERROR_XSTATS + \
654 HNS3_NUM_RXQ_DFX_XSTATS + \
655 HNS3_NUM_RX_QUEUE_STATS + \
656 HNS3_NUM_RXQ_BASIC_STATS)
657 #define HNS3_PF_VF_TX_COMM_STATS_NUM (HNS3_NUM_TXQ_DFX_XSTATS + \
658 HNS3_NUM_TX_QUEUE_STATS + \
659 HNS3_NUM_TXQ_BASIC_STATS)
661 struct hns3_adapter *hns = dev->data->dev_private;
662 uint16_t nb_rx_q = dev->data->nb_rx_queues;
663 uint16_t nb_tx_q = dev->data->nb_tx_queues;
664 int rx_comm_stats_num = nb_rx_q * HNS3_PF_VF_RX_COMM_STATS_NUM;
665 int tx_comm_stats_num = nb_tx_q * HNS3_PF_VF_TX_COMM_STATS_NUM;
668 return rx_comm_stats_num + tx_comm_stats_num +
669 HNS3_NUM_RESET_XSTATS;
671 return rx_comm_stats_num + tx_comm_stats_num +
676 hns3_queue_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
679 struct hns3_adapter *hns = dev->data->dev_private;
680 struct hns3_hw *hw = &hns->hw;
684 /* Get rx queue stats */
685 for (j = 0; j < dev->data->nb_rx_queues; j++) {
686 for (i = 0; i < HNS3_NUM_RX_QUEUE_STATS; i++) {
687 reg_offset = hns3_get_tqp_reg_offset(j);
688 xstats[*count].value = hns3_read_dev(hw,
689 reg_offset + hns3_rx_queue_strings[i].offset);
690 xstats[*count].id = *count;
695 /* Get tx queue stats */
696 for (j = 0; j < dev->data->nb_tx_queues; j++) {
697 for (i = 0; i < HNS3_NUM_TX_QUEUE_STATS; i++) {
698 reg_offset = hns3_get_tqp_reg_offset(j);
699 xstats[*count].value = hns3_read_dev(hw,
700 reg_offset + hns3_tx_queue_strings[i].offset);
701 xstats[*count].id = *count;
708 hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err)
710 struct hns3_pf *pf = &hns->pf;
714 for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) {
715 if (strcmp(hns3_error_int_stats_strings[i].name, err) == 0) {
716 addr = (char *)&pf->abn_int_stats +
717 hns3_error_int_stats_strings[i].offset;
718 *(uint64_t *)addr += 1;
725 hns3_rxq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
728 struct hns3_rx_dfx_stats *dfx_stats;
729 struct hns3_rx_queue *rxq;
733 for (i = 0; i < dev->data->nb_rx_queues; i++) {
734 rxq = (struct hns3_rx_queue *)dev->data->rx_queues[i];
738 dfx_stats = &rxq->dfx_stats;
739 for (j = 0; j < HNS3_NUM_RXQ_DFX_XSTATS; j++) {
740 val = (char *)dfx_stats +
741 hns3_rxq_dfx_stats_strings[j].offset;
742 xstats[*count].value = *(uint64_t *)val;
743 xstats[*count].id = *count;
750 hns3_txq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
753 struct hns3_tx_dfx_stats *dfx_stats;
754 struct hns3_tx_queue *txq;
758 for (i = 0; i < dev->data->nb_tx_queues; i++) {
759 txq = (struct hns3_tx_queue *)dev->data->tx_queues[i];
763 dfx_stats = &txq->dfx_stats;
764 for (j = 0; j < HNS3_NUM_TXQ_DFX_XSTATS; j++) {
765 val = (char *)dfx_stats +
766 hns3_txq_dfx_stats_strings[j].offset;
767 xstats[*count].value = *(uint64_t *)val;
768 xstats[*count].id = *count;
775 hns3_tqp_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
778 hns3_rxq_dfx_stats_get(dev, xstats, count);
779 hns3_txq_dfx_stats_get(dev, xstats, count);
783 hns3_rxq_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
786 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
787 struct hns3_tqp_stats *stats = &hw->tqp_stats;
788 struct hns3_rx_basic_stats *rxq_stats;
789 struct hns3_rx_queue *rxq;
793 for (i = 0; i < dev->data->nb_rx_queues; i++) {
794 rxq = dev->data->rx_queues[i];
798 rxq_stats = &rxq->basic_stats;
799 rxq_stats->errors = rxq->err_stats.l2_errors +
800 rxq->err_stats.pkt_len_errors;
802 * If HW statistics are reset by stats_reset, but a lot of
803 * residual packets exist in the hardware queue and these
804 * packets are error packets, flip overflow may occurred.
805 * So return 0 in this case.
808 stats->rcb_rx_ring_pktnum[i] > rxq_stats->errors ?
809 stats->rcb_rx_ring_pktnum[i] - rxq_stats->errors : 0;
810 rxq_stats->bytes = 0;
811 for (j = 0; j < HNS3_NUM_RXQ_BASIC_STATS; j++) {
812 val = (char *)rxq_stats +
813 hns3_rxq_basic_stats_strings[j].offset;
814 xstats[*count].value = *(uint64_t *)val;
815 xstats[*count].id = *count;
822 hns3_txq_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
825 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
826 struct hns3_tqp_stats *stats = &hw->tqp_stats;
827 struct hns3_tx_basic_stats *txq_stats;
828 struct hns3_tx_queue *txq;
832 for (i = 0; i < dev->data->nb_tx_queues; i++) {
833 txq = dev->data->tx_queues[i];
837 txq_stats = &txq->basic_stats;
838 txq_stats->packets = stats->rcb_tx_ring_pktnum[i];
839 txq_stats->bytes = 0;
840 for (j = 0; j < HNS3_NUM_TXQ_BASIC_STATS; j++) {
841 val = (char *)txq_stats +
842 hns3_txq_basic_stats_strings[j].offset;
843 xstats[*count].value = *(uint64_t *)val;
844 xstats[*count].id = *count;
851 hns3_tqp_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
854 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
857 /* Update tqp stats by read register */
858 ret = hns3_update_tqp_stats(hw);
860 hns3_err(hw, "Update tqp stats fail, ret = %d.", ret);
864 hns3_rxq_basic_stats_get(dev, xstats, count);
865 hns3_txq_basic_stats_get(dev, xstats, count);
871 * The function is only called by hns3_dev_xstats_reset to clear
872 * basic stats of per-queue. TQP stats are all cleared in hns3_stats_reset
873 * which is called before this function.
876 * Pointer to Ethernet device.
879 hns3_tqp_basic_stats_clear(struct rte_eth_dev *dev)
881 struct hns3_tx_queue *txq;
882 struct hns3_rx_queue *rxq;
885 for (i = 0; i < dev->data->nb_rx_queues; i++) {
886 rxq = dev->data->rx_queues[i];
888 memset(&rxq->basic_stats, 0,
889 sizeof(struct hns3_rx_basic_stats));
892 for (i = 0; i < dev->data->nb_tx_queues; i++) {
893 txq = dev->data->tx_queues[i];
895 memset(&txq->basic_stats, 0,
896 sizeof(struct hns3_tx_basic_stats));
901 * Retrieve extended(tqp | Mac) statistics of an Ethernet device.
903 * Pointer to Ethernet device.
905 * A pointer to a table of structure of type *rte_eth_xstat*
906 * to be filled with device statistics ids and values.
907 * This parameter can be set to NULL if n is 0.
909 * The size of the xstats array (number of elements).
911 * 0 on fail, count(The size of the statistics elements) on success.
914 hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
917 struct hns3_adapter *hns = dev->data->dev_private;
918 struct hns3_pf *pf = &hns->pf;
919 struct hns3_hw *hw = &hns->hw;
920 struct hns3_mac_stats *mac_stats = &hw->mac_stats;
921 struct hns3_reset_stats *reset_stats = &hw->reset.stats;
922 struct hns3_rx_bd_errors_stats *rx_err_stats;
923 struct hns3_rx_queue *rxq;
932 count = hns3_xstats_calc_num(dev);
938 ret = hns3_tqp_basic_stats_get(dev, xstats, &count);
943 /* Update Mac stats */
944 ret = hns3_query_update_mac_stats(dev);
946 hns3_err(hw, "Update Mac stats fail : %d", ret);
950 /* Get MAC stats from hw->hw_xstats.mac_stats struct */
951 for (i = 0; i < HNS3_NUM_MAC_STATS; i++) {
952 addr = (char *)mac_stats + hns3_mac_strings[i].offset;
953 xstats[count].value = *(uint64_t *)addr;
954 xstats[count].id = count;
958 for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) {
959 addr = (char *)&pf->abn_int_stats +
960 hns3_error_int_stats_strings[i].offset;
961 xstats[count].value = *(uint64_t *)addr;
962 xstats[count].id = count;
967 /* Get the reset stat */
968 for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) {
969 addr = (char *)reset_stats + hns3_reset_stats_strings[i].offset;
970 xstats[count].value = *(uint64_t *)addr;
971 xstats[count].id = count;
975 /* Get the Rx BD errors stats */
976 for (j = 0; j < dev->data->nb_rx_queues; j++) {
977 for (i = 0; i < HNS3_NUM_RX_BD_ERROR_XSTATS; i++) {
978 rxq = dev->data->rx_queues[j];
980 rx_err_stats = &rxq->err_stats;
981 addr = (char *)rx_err_stats +
982 hns3_rx_bd_error_strings[i].offset;
983 xstats[count].value = *(uint64_t *)addr;
984 xstats[count].id = count;
990 hns3_tqp_dfx_stats_get(dev, xstats, &count);
991 hns3_queue_stats_get(dev, xstats, &count);
997 hns3_tqp_basic_stats_name_get(struct rte_eth_dev *dev,
998 struct rte_eth_xstat_name *xstats_names,
1003 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1004 for (j = 0; j < HNS3_NUM_RXQ_BASIC_STATS; j++) {
1005 snprintf(xstats_names[*count].name,
1006 sizeof(xstats_names[*count].name),
1008 hns3_rxq_basic_stats_strings[j].name);
1012 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1013 for (j = 0; j < HNS3_NUM_TXQ_BASIC_STATS; j++) {
1014 snprintf(xstats_names[*count].name,
1015 sizeof(xstats_names[*count].name),
1017 hns3_txq_basic_stats_strings[j].name);
1024 hns3_tqp_dfx_stats_name_get(struct rte_eth_dev *dev,
1025 struct rte_eth_xstat_name *xstats_names,
1030 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1031 for (j = 0; j < HNS3_NUM_RXQ_DFX_XSTATS; j++) {
1032 snprintf(xstats_names[*count].name,
1033 sizeof(xstats_names[*count].name),
1035 hns3_rxq_dfx_stats_strings[j].name);
1040 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1041 for (j = 0; j < HNS3_NUM_TXQ_DFX_XSTATS; j++) {
1042 snprintf(xstats_names[*count].name,
1043 sizeof(xstats_names[*count].name),
1045 hns3_txq_dfx_stats_strings[j].name);
1052 * Retrieve names of extended statistics of an Ethernet device.
1054 * There is an assumption that 'xstat_names' and 'xstats' arrays are matched
1056 * xstats_names[i].name => xstats[i].value
1058 * And the array index is same with id field of 'struct rte_eth_xstat':
1061 * This assumption makes key-value pair matching less flexible but simpler.
1064 * Pointer to Ethernet device.
1065 * @param xstats_names
1066 * An rte_eth_xstat_name array of at least *size* elements to
1067 * be filled. If set to NULL, the function returns the required number
1070 * The size of the xstats_names array (number of elements).
1072 * - A positive value lower or equal to size: success. The return value
1073 * is the number of entries filled in the stats table.
1076 hns3_dev_xstats_get_names(struct rte_eth_dev *dev,
1077 struct rte_eth_xstat_name *xstats_names,
1078 __rte_unused unsigned int size)
1080 struct hns3_adapter *hns = dev->data->dev_private;
1081 int cnt_stats = hns3_xstats_calc_num(dev);
1085 if (xstats_names == NULL)
1088 hns3_tqp_basic_stats_name_get(dev, xstats_names, &count);
1090 /* Note: size limited checked in rte_eth_xstats_get_names() */
1092 /* Get MAC name from hw->hw_xstats.mac_stats struct */
1093 for (i = 0; i < HNS3_NUM_MAC_STATS; i++) {
1094 snprintf(xstats_names[count].name,
1095 sizeof(xstats_names[count].name),
1096 "%s", hns3_mac_strings[i].name);
1100 for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) {
1101 snprintf(xstats_names[count].name,
1102 sizeof(xstats_names[count].name),
1103 "%s", hns3_error_int_stats_strings[i].name);
1107 for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) {
1108 snprintf(xstats_names[count].name,
1109 sizeof(xstats_names[count].name),
1110 "%s", hns3_reset_stats_strings[i].name);
1114 for (j = 0; j < dev->data->nb_rx_queues; j++) {
1115 for (i = 0; i < HNS3_NUM_RX_BD_ERROR_XSTATS; i++) {
1116 snprintf(xstats_names[count].name,
1117 sizeof(xstats_names[count].name),
1119 hns3_rx_bd_error_strings[i].name);
1124 hns3_tqp_dfx_stats_name_get(dev, xstats_names, &count);
1126 for (j = 0; j < dev->data->nb_rx_queues; j++) {
1127 for (i = 0; i < HNS3_NUM_RX_QUEUE_STATS; i++) {
1128 snprintf(xstats_names[count].name,
1129 sizeof(xstats_names[count].name),
1130 "rx_q%u_%s", j, hns3_rx_queue_strings[i].name);
1135 for (j = 0; j < dev->data->nb_tx_queues; j++) {
1136 for (i = 0; i < HNS3_NUM_TX_QUEUE_STATS; i++) {
1137 snprintf(xstats_names[count].name,
1138 sizeof(xstats_names[count].name),
1139 "tx_q%u_%s", j, hns3_tx_queue_strings[i].name);
1148 * Retrieve extended statistics of an Ethernet device.
1151 * Pointer to Ethernet device.
1153 * A pointer to an ids array passed by application. This tells which
1154 * statistics values function should retrieve. This parameter
1155 * can be set to NULL if size is 0. In this case function will retrieve
1156 * all avalible statistics.
1158 * A pointer to a table to be filled with device statistics values.
1160 * The size of the ids array (number of elements).
1162 * - A positive value lower or equal to size: success. The return value
1163 * is the number of entries filled in the stats table.
1164 * - A positive value higher than size: error, the given statistics table
1165 * is too small. The return value corresponds to the size that should
1166 * be given to succeed. The entries in the table are not valid and
1167 * shall not be used by the caller.
1171 hns3_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1172 uint64_t *values, uint32_t size)
1174 const uint32_t cnt_stats = hns3_xstats_calc_num(dev);
1175 struct hns3_adapter *hns = dev->data->dev_private;
1176 struct rte_eth_xstat *values_copy;
1177 struct hns3_hw *hw = &hns->hw;
1178 uint32_t count_value;
1182 if (ids == NULL && values == NULL)
1186 if (size < cnt_stats)
1189 len = cnt_stats * sizeof(struct rte_eth_xstat);
1190 values_copy = rte_zmalloc("hns3_xstats_values", len, 0);
1191 if (values_copy == NULL) {
1192 hns3_err(hw, "Failed to allocate %" PRIx64 " bytes needed "
1193 "to store statistics values", len);
1197 count_value = hns3_dev_xstats_get(dev, values_copy, cnt_stats);
1198 if (count_value != cnt_stats) {
1199 rte_free(values_copy);
1203 if (ids == NULL && values != NULL) {
1204 for (i = 0; i < cnt_stats; i++)
1205 memcpy(&values[i], &values_copy[i].value,
1208 rte_free(values_copy);
1212 for (i = 0; i < size; i++) {
1213 if (ids[i] >= cnt_stats) {
1214 hns3_err(hw, "ids[%u] (%" PRIx64 ") is invalid, "
1215 "should < %u", i, ids[i], cnt_stats);
1216 rte_free(values_copy);
1219 memcpy(&values[i], &values_copy[ids[i]].value,
1223 rte_free(values_copy);
1228 * Retrieve names of extended statistics of an Ethernet device.
1231 * Pointer to Ethernet device.
1232 * @param xstats_names
1233 * An rte_eth_xstat_name array of at least *size* elements to
1234 * be filled. If set to NULL, the function returns the required number
1237 * IDs array given by app to retrieve specific statistics
1239 * The size of the xstats_names array (number of elements).
1241 * - A positive value lower or equal to size: success. The return value
1242 * is the number of entries filled in the stats table.
1243 * - A positive value higher than size: error, the given statistics table
1244 * is too small. The return value corresponds to the size that should
1245 * be given to succeed. The entries in the table are not valid and
1246 * shall not be used by the caller.
1249 hns3_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
1250 struct rte_eth_xstat_name *xstats_names,
1251 const uint64_t *ids, uint32_t size)
1253 const uint32_t cnt_stats = hns3_xstats_calc_num(dev);
1254 struct hns3_adapter *hns = dev->data->dev_private;
1255 struct rte_eth_xstat_name *names_copy;
1256 struct hns3_hw *hw = &hns->hw;
1260 if (xstats_names == NULL)
1264 if (size < cnt_stats)
1267 return hns3_dev_xstats_get_names(dev, xstats_names, cnt_stats);
1270 len = cnt_stats * sizeof(struct rte_eth_xstat_name);
1271 names_copy = rte_zmalloc("hns3_xstats_names", len, 0);
1272 if (names_copy == NULL) {
1273 hns3_err(hw, "Failed to allocate %" PRIx64 " bytes needed "
1274 "to store statistics names", len);
1278 (void)hns3_dev_xstats_get_names(dev, names_copy, cnt_stats);
1280 for (i = 0; i < size; i++) {
1281 if (ids[i] >= cnt_stats) {
1282 hns3_err(hw, "ids[%u] (%" PRIx64 ") is invalid, "
1283 "should < %u", i, ids[i], cnt_stats);
1284 rte_free(names_copy);
1287 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1288 "%s", names_copy[ids[i]].name);
1291 rte_free(names_copy);
1296 hns3_tqp_dfx_stats_clear(struct rte_eth_dev *dev)
1298 struct hns3_rx_queue *rxq;
1299 struct hns3_tx_queue *txq;
1302 /* Clear Rx dfx stats */
1303 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1304 rxq = dev->data->rx_queues[i];
1306 memset(&rxq->dfx_stats, 0,
1307 sizeof(struct hns3_rx_dfx_stats));
1310 /* Clear Tx dfx stats */
1311 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1312 txq = dev->data->tx_queues[i];
1314 memset(&txq->dfx_stats, 0,
1315 sizeof(struct hns3_tx_dfx_stats));
1320 hns3_dev_xstats_reset(struct rte_eth_dev *dev)
1322 struct hns3_adapter *hns = dev->data->dev_private;
1323 struct hns3_pf *pf = &hns->pf;
1326 /* Clear tqp stats */
1327 ret = hns3_stats_reset(dev);
1331 hns3_tqp_basic_stats_clear(dev);
1332 hns3_tqp_dfx_stats_clear(dev);
1334 /* Clear reset stats */
1335 memset(&hns->hw.reset.stats, 0, sizeof(struct hns3_reset_stats));
1340 /* HW registers are cleared on read */
1341 ret = hns3_mac_stats_reset(dev);
1345 /* Clear error stats */
1346 memset(&pf->abn_int_stats, 0, sizeof(struct hns3_err_msix_intr_stats));
1352 hns3_tqp_stats_init(struct hns3_hw *hw)
1354 struct hns3_tqp_stats *tqp_stats = &hw->tqp_stats;
1356 tqp_stats->rcb_rx_ring_pktnum = rte_zmalloc("hns3_rx_ring_pkt_num",
1357 sizeof(uint64_t) * hw->tqps_num, 0);
1358 if (tqp_stats->rcb_rx_ring_pktnum == NULL) {
1359 hns3_err(hw, "failed to allocate rx_ring pkt_num.");
1363 tqp_stats->rcb_tx_ring_pktnum = rte_zmalloc("hns3_tx_ring_pkt_num",
1364 sizeof(uint64_t) * hw->tqps_num, 0);
1365 if (tqp_stats->rcb_tx_ring_pktnum == NULL) {
1366 hns3_err(hw, "failed to allocate tx_ring pkt_num.");
1367 rte_free(tqp_stats->rcb_rx_ring_pktnum);
1368 tqp_stats->rcb_rx_ring_pktnum = NULL;
1376 hns3_tqp_stats_uninit(struct hns3_hw *hw)
1378 struct hns3_tqp_stats *tqp_stats = &hw->tqp_stats;
1380 rte_free(tqp_stats->rcb_rx_ring_pktnum);
1381 tqp_stats->rcb_rx_ring_pktnum = NULL;
1382 rte_free(tqp_stats->rcb_tx_ring_pktnum);
1383 tqp_stats->rcb_tx_ring_pktnum = NULL;
1387 hns3_tqp_stats_clear(struct hns3_hw *hw)
1389 struct hns3_tqp_stats *stats = &hw->tqp_stats;
1391 stats->rcb_rx_ring_pktnum_rcd = 0;
1392 stats->rcb_tx_ring_pktnum_rcd = 0;
1393 memset(stats->rcb_rx_ring_pktnum, 0, sizeof(uint64_t) * hw->tqps_num);
1394 memset(stats->rcb_tx_ring_pktnum, 0, sizeof(uint64_t) * hw->tqps_num);