1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ***************************************************************************/
34 #ifndef _I40E_ADMINQ_CMD_H_
35 #define _I40E_ADMINQ_CMD_H_
37 /* This header file defines the i40e Admin Queue commands and is shared between
38 * i40e Firmware and Software.
40 * This file needs to comply with the Linux Kernel coding style.
43 #define I40E_FW_API_VERSION_MAJOR 0x0001
44 #define I40E_FW_API_VERSION_MINOR 0x0005
70 /* Flags sub-structure
71 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
72 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
75 /* command flags and offsets*/
76 #define I40E_AQ_FLAG_DD_SHIFT 0
77 #define I40E_AQ_FLAG_CMP_SHIFT 1
78 #define I40E_AQ_FLAG_ERR_SHIFT 2
79 #define I40E_AQ_FLAG_VFE_SHIFT 3
80 #define I40E_AQ_FLAG_LB_SHIFT 9
81 #define I40E_AQ_FLAG_RD_SHIFT 10
82 #define I40E_AQ_FLAG_VFC_SHIFT 11
83 #define I40E_AQ_FLAG_BUF_SHIFT 12
84 #define I40E_AQ_FLAG_SI_SHIFT 13
85 #define I40E_AQ_FLAG_EI_SHIFT 14
86 #define I40E_AQ_FLAG_FE_SHIFT 15
88 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
89 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
90 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
91 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
92 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
93 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
94 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
95 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
96 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
97 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
98 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
101 enum i40e_admin_queue_err {
102 I40E_AQ_RC_OK = 0, /* success */
103 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
104 I40E_AQ_RC_ENOENT = 2, /* No such element */
105 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
106 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
107 I40E_AQ_RC_EIO = 5, /* I/O error */
108 I40E_AQ_RC_ENXIO = 6, /* No such resource */
109 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
110 I40E_AQ_RC_EAGAIN = 8, /* Try again */
111 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
112 I40E_AQ_RC_EACCES = 10, /* Permission denied */
113 I40E_AQ_RC_EFAULT = 11, /* Bad address */
114 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
115 I40E_AQ_RC_EEXIST = 13, /* object already exists */
116 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
117 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
118 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
119 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
120 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
121 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
122 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
123 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
124 I40E_AQ_RC_EFBIG = 22, /* File too large */
127 /* Admin Queue command opcodes */
128 enum i40e_admin_queue_opc {
130 i40e_aqc_opc_get_version = 0x0001,
131 i40e_aqc_opc_driver_version = 0x0002,
132 i40e_aqc_opc_queue_shutdown = 0x0003,
133 i40e_aqc_opc_set_pf_context = 0x0004,
135 /* resource ownership */
136 i40e_aqc_opc_request_resource = 0x0008,
137 i40e_aqc_opc_release_resource = 0x0009,
139 i40e_aqc_opc_list_func_capabilities = 0x000A,
140 i40e_aqc_opc_list_dev_capabilities = 0x000B,
144 i40e_aqc_opc_set_proxy_config = 0x0104,
145 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
149 i40e_aqc_opc_mac_address_read = 0x0107,
150 i40e_aqc_opc_mac_address_write = 0x0108,
153 i40e_aqc_opc_clear_pxe_mode = 0x0110,
157 i40e_aqc_opc_set_wol_filter = 0x0120,
158 i40e_aqc_opc_get_wake_reason = 0x0121,
159 i40e_aqc_opc_clear_all_wol_filters = 0x025E,
162 /* internal switch commands */
163 i40e_aqc_opc_get_switch_config = 0x0200,
164 i40e_aqc_opc_add_statistics = 0x0201,
165 i40e_aqc_opc_remove_statistics = 0x0202,
166 i40e_aqc_opc_set_port_parameters = 0x0203,
167 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
168 i40e_aqc_opc_set_switch_config = 0x0205,
169 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
170 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
172 i40e_aqc_opc_add_vsi = 0x0210,
173 i40e_aqc_opc_update_vsi_parameters = 0x0211,
174 i40e_aqc_opc_get_vsi_parameters = 0x0212,
176 i40e_aqc_opc_add_pv = 0x0220,
177 i40e_aqc_opc_update_pv_parameters = 0x0221,
178 i40e_aqc_opc_get_pv_parameters = 0x0222,
180 i40e_aqc_opc_add_veb = 0x0230,
181 i40e_aqc_opc_update_veb_parameters = 0x0231,
182 i40e_aqc_opc_get_veb_parameters = 0x0232,
184 i40e_aqc_opc_delete_element = 0x0243,
186 i40e_aqc_opc_add_macvlan = 0x0250,
187 i40e_aqc_opc_remove_macvlan = 0x0251,
188 i40e_aqc_opc_add_vlan = 0x0252,
189 i40e_aqc_opc_remove_vlan = 0x0253,
190 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
191 i40e_aqc_opc_add_tag = 0x0255,
192 i40e_aqc_opc_remove_tag = 0x0256,
193 i40e_aqc_opc_add_multicast_etag = 0x0257,
194 i40e_aqc_opc_remove_multicast_etag = 0x0258,
195 i40e_aqc_opc_update_tag = 0x0259,
196 i40e_aqc_opc_add_control_packet_filter = 0x025A,
197 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
198 i40e_aqc_opc_add_cloud_filters = 0x025C,
199 i40e_aqc_opc_remove_cloud_filters = 0x025D,
200 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
202 i40e_aqc_opc_add_mirror_rule = 0x0260,
203 i40e_aqc_opc_delete_mirror_rule = 0x0261,
206 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
207 i40e_aqc_opc_dcb_updated = 0x0302,
210 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
211 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
212 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
213 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
214 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
215 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
217 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
218 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
219 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
220 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
221 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
222 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
223 i40e_aqc_opc_query_port_ets_config = 0x0419,
224 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
225 i40e_aqc_opc_suspend_port_tx = 0x041B,
226 i40e_aqc_opc_resume_port_tx = 0x041C,
227 i40e_aqc_opc_configure_partition_bw = 0x041D,
229 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
230 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
233 i40e_aqc_opc_get_phy_abilities = 0x0600,
234 i40e_aqc_opc_set_phy_config = 0x0601,
235 i40e_aqc_opc_set_mac_config = 0x0603,
236 i40e_aqc_opc_set_link_restart_an = 0x0605,
237 i40e_aqc_opc_get_link_status = 0x0607,
238 i40e_aqc_opc_set_phy_int_mask = 0x0613,
239 i40e_aqc_opc_get_local_advt_reg = 0x0614,
240 i40e_aqc_opc_set_local_advt_reg = 0x0615,
241 i40e_aqc_opc_get_partner_advt = 0x0616,
242 i40e_aqc_opc_set_lb_modes = 0x0618,
243 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
244 i40e_aqc_opc_set_phy_debug = 0x0622,
245 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
246 i40e_aqc_opc_run_phy_activity = 0x0626,
249 i40e_aqc_opc_nvm_read = 0x0701,
250 i40e_aqc_opc_nvm_erase = 0x0702,
251 i40e_aqc_opc_nvm_update = 0x0703,
252 i40e_aqc_opc_nvm_config_read = 0x0704,
253 i40e_aqc_opc_nvm_config_write = 0x0705,
254 i40e_aqc_opc_oem_post_update = 0x0720,
255 i40e_aqc_opc_thermal_sensor = 0x0721,
257 /* virtualization commands */
258 i40e_aqc_opc_send_msg_to_pf = 0x0801,
259 i40e_aqc_opc_send_msg_to_vf = 0x0802,
260 i40e_aqc_opc_send_msg_to_peer = 0x0803,
262 /* alternate structure */
263 i40e_aqc_opc_alternate_write = 0x0900,
264 i40e_aqc_opc_alternate_write_indirect = 0x0901,
265 i40e_aqc_opc_alternate_read = 0x0902,
266 i40e_aqc_opc_alternate_read_indirect = 0x0903,
267 i40e_aqc_opc_alternate_write_done = 0x0904,
268 i40e_aqc_opc_alternate_set_mode = 0x0905,
269 i40e_aqc_opc_alternate_clear_port = 0x0906,
272 i40e_aqc_opc_lldp_get_mib = 0x0A00,
273 i40e_aqc_opc_lldp_update_mib = 0x0A01,
274 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
275 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
276 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
277 i40e_aqc_opc_lldp_stop = 0x0A05,
278 i40e_aqc_opc_lldp_start = 0x0A06,
279 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
280 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
281 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
283 /* Tunnel commands */
284 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
285 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
287 i40e_aqc_opc_set_rss_key = 0x0B02,
288 i40e_aqc_opc_set_rss_lut = 0x0B03,
289 i40e_aqc_opc_get_rss_key = 0x0B04,
290 i40e_aqc_opc_get_rss_lut = 0x0B05,
294 i40e_aqc_opc_event_lan_overflow = 0x1001,
297 i40e_aqc_opc_oem_parameter_change = 0xFE00,
298 i40e_aqc_opc_oem_device_status_change = 0xFE01,
299 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
300 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
303 i40e_aqc_opc_debug_read_reg = 0xFF03,
304 i40e_aqc_opc_debug_write_reg = 0xFF04,
305 i40e_aqc_opc_debug_modify_reg = 0xFF07,
306 i40e_aqc_opc_debug_dump_internals = 0xFF08,
309 /* command structures and indirect data structures */
311 /* Structure naming conventions:
312 * - no suffix for direct command descriptor structures
313 * - _data for indirect sent data
314 * - _resp for indirect return data (data which is both will use _data)
315 * - _completion for direct return data
316 * - _element_ for repeated elements (may also be _data or _resp)
318 * Command structures are expected to overlay the params.raw member of the basic
319 * descriptor, and as such cannot exceed 16 bytes in length.
322 /* This macro is used to generate a compilation error if a structure
323 * is not exactly the correct length. It gives a divide by zero error if the
324 * structure is not of the correct size, otherwise it creates an enum that is
327 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
328 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
330 /* This macro is used extensively to ensure that command structures are 16
331 * bytes in length as they have to map to the raw array of that size.
333 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
335 /* internal (0x00XX) commands */
337 /* Get version (direct 0x0001) */
338 struct i40e_aqc_get_version {
347 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
349 /* Send driver version (indirect 0x0002) */
350 struct i40e_aqc_driver_version {
354 u8 driver_subbuild_ver;
360 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
362 /* Queue Shutdown (direct 0x0003) */
363 struct i40e_aqc_queue_shutdown {
364 __le32 driver_unloading;
365 #define I40E_AQ_DRIVER_UNLOADING 0x1
369 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
371 /* Set PF context (0x0004, direct) */
372 struct i40e_aqc_set_pf_context {
377 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
379 /* Request resource ownership (direct 0x0008)
380 * Release resource ownership (direct 0x0009)
382 #define I40E_AQ_RESOURCE_NVM 1
383 #define I40E_AQ_RESOURCE_SDP 2
384 #define I40E_AQ_RESOURCE_ACCESS_READ 1
385 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
386 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
387 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
389 struct i40e_aqc_request_resource {
393 __le32 resource_number;
397 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
399 /* Get function capabilities (indirect 0x000A)
400 * Get device capabilities (indirect 0x000B)
402 struct i40e_aqc_list_capabilites {
404 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
412 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
414 struct i40e_aqc_list_capabilities_element_resp {
426 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
427 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
428 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
429 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
430 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
431 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
432 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
433 #define I40E_AQ_CAP_ID_SRIOV 0x0012
434 #define I40E_AQ_CAP_ID_VF 0x0013
435 #define I40E_AQ_CAP_ID_VMDQ 0x0014
436 #define I40E_AQ_CAP_ID_8021QBG 0x0015
437 #define I40E_AQ_CAP_ID_8021QBR 0x0016
438 #define I40E_AQ_CAP_ID_VSI 0x0017
439 #define I40E_AQ_CAP_ID_DCB 0x0018
440 #define I40E_AQ_CAP_ID_FCOE 0x0021
441 #define I40E_AQ_CAP_ID_ISCSI 0x0022
442 #define I40E_AQ_CAP_ID_RSS 0x0040
443 #define I40E_AQ_CAP_ID_RXQ 0x0041
444 #define I40E_AQ_CAP_ID_TXQ 0x0042
445 #define I40E_AQ_CAP_ID_MSIX 0x0043
446 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
447 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
448 #define I40E_AQ_CAP_ID_1588 0x0046
449 #define I40E_AQ_CAP_ID_IWARP 0x0051
450 #define I40E_AQ_CAP_ID_LED 0x0061
451 #define I40E_AQ_CAP_ID_SDP 0x0062
452 #define I40E_AQ_CAP_ID_MDIO 0x0063
453 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
454 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
455 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
456 #define I40E_AQ_CAP_ID_CEM 0x00F2
458 /* Set CPPM Configuration (direct 0x0103) */
459 struct i40e_aqc_cppm_configuration {
460 __le16 command_flags;
461 #define I40E_AQ_CPPM_EN_LTRC 0x0800
462 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
463 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
464 #define I40E_AQ_CPPM_EN_HPTC 0x4000
465 #define I40E_AQ_CPPM_EN_DMARC 0x8000
474 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
476 /* Set ARP Proxy command / response (indirect 0x0104) */
477 struct i40e_aqc_arp_proxy_data {
478 __le16 command_flags;
479 #define I40E_AQ_ARP_INIT_IPV4 0x0800
480 #define I40E_AQ_ARP_UNSUP_CTL 0x1000
481 #define I40E_AQ_ARP_ENA 0x2000
482 #define I40E_AQ_ARP_ADD_IPV4 0x4000
483 #define I40E_AQ_ARP_DEL_IPV4 0x8000
485 __le32 enabled_offloads;
486 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
487 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
493 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
495 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
496 struct i40e_aqc_ns_proxy_data {
497 __le16 table_idx_mac_addr_0;
498 __le16 table_idx_mac_addr_1;
499 __le16 table_idx_ipv6_0;
500 __le16 table_idx_ipv6_1;
502 #define I40E_AQ_NS_PROXY_ADD_0 0x0001
503 #define I40E_AQ_NS_PROXY_DEL_0 0x0002
504 #define I40E_AQ_NS_PROXY_ADD_1 0x0004
505 #define I40E_AQ_NS_PROXY_DEL_1 0x0008
506 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
507 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
508 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
509 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
510 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
511 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
512 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
513 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
514 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
517 u8 local_mac_addr[6];
518 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
522 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
524 /* Manage LAA Command (0x0106) - obsolete */
525 struct i40e_aqc_mng_laa {
526 __le16 command_flags;
527 #define I40E_AQ_LAA_FLAG_WR 0x8000
534 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
536 /* Manage MAC Address Read Command (indirect 0x0107) */
537 struct i40e_aqc_mac_address_read {
538 __le16 command_flags;
539 #define I40E_AQC_LAN_ADDR_VALID 0x10
540 #define I40E_AQC_SAN_ADDR_VALID 0x20
541 #define I40E_AQC_PORT_ADDR_VALID 0x40
542 #define I40E_AQC_WOL_ADDR_VALID 0x80
543 #define I40E_AQC_MC_MAG_EN_VALID 0x100
544 #define I40E_AQC_ADDR_VALID_MASK 0x1F0
550 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
552 struct i40e_aqc_mac_address_read_data {
559 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
561 /* Manage MAC Address Write Command (0x0108) */
562 struct i40e_aqc_mac_address_write {
563 __le16 command_flags;
564 #define I40E_AQC_MC_MAG_EN 0x0100
565 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
566 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
567 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
568 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
569 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
576 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
578 /* PXE commands (0x011x) */
580 /* Clear PXE Command and response (direct 0x0110) */
581 struct i40e_aqc_clear_pxe {
586 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
589 /* Set WoL Filter (0x0120) */
591 struct i40e_aqc_set_wol_filter {
593 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
594 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
595 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
596 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
598 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
599 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
600 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
602 #define I40E_AQC_SET_WOL_FILTER 0x8000
603 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
604 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
605 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
607 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
608 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
614 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
616 struct i40e_aqc_set_wol_filter_data {
621 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
623 /* Get Wake Reason (0x0121) */
625 struct i40e_aqc_get_wake_reason_completion {
628 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
629 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
630 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
631 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
632 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
633 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
637 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
639 #endif /* X722_SUPPORT */
640 /* Switch configuration commands (0x02xx) */
642 /* Used by many indirect commands that only pass an seid and a buffer in the
645 struct i40e_aqc_switch_seid {
652 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
654 /* Get Switch Configuration command (indirect 0x0200)
655 * uses i40e_aqc_switch_seid for the descriptor
657 struct i40e_aqc_get_switch_config_header_resp {
663 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
665 struct i40e_aqc_switch_config_element_resp {
667 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
668 #define I40E_AQ_SW_ELEM_TYPE_PF 2
669 #define I40E_AQ_SW_ELEM_TYPE_VF 3
670 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
671 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
672 #define I40E_AQ_SW_ELEM_TYPE_PV 16
673 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
674 #define I40E_AQ_SW_ELEM_TYPE_PA 18
675 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
677 #define I40E_AQ_SW_ELEM_REV_1 1
680 __le16 downlink_seid;
683 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
684 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
685 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
690 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
692 /* Get Switch Configuration (indirect 0x0200)
693 * an array of elements are returned in the response buffer
694 * the first in the array is the header, remainder are elements
696 struct i40e_aqc_get_switch_config_resp {
697 struct i40e_aqc_get_switch_config_header_resp header;
698 struct i40e_aqc_switch_config_element_resp element[1];
701 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
703 /* Add Statistics (direct 0x0201)
704 * Remove Statistics (direct 0x0202)
706 struct i40e_aqc_add_remove_statistics {
713 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
715 /* Set Port Parameters command (direct 0x0203) */
716 struct i40e_aqc_set_port_parameters {
717 __le16 command_flags;
718 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
719 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
720 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
721 __le16 bad_frame_vsi;
722 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
723 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
724 __le16 default_seid; /* reserved for command */
728 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
730 /* Get Switch Resource Allocation (indirect 0x0204) */
731 struct i40e_aqc_get_switch_resource_alloc {
732 u8 num_entries; /* reserved for command */
738 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
740 /* expect an array of these structs in the response buffer */
741 struct i40e_aqc_switch_resource_alloc_element_resp {
743 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
744 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
745 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
746 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
747 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
748 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
749 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
750 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
751 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
752 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
753 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
754 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
755 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
756 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
757 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
758 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
759 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
760 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
761 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
766 __le16 total_unalloced;
770 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
772 /* Set Switch Configuration (direct 0x0205) */
773 struct i40e_aqc_set_switch_config {
775 /* flags used for both fields below */
776 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
777 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
782 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
784 /* Read Receive control registers (direct 0x0206)
785 * Write Receive control registers (direct 0x0207)
786 * used for accessing Rx control registers that can be
787 * slow and need special handling when under high Rx load
789 struct i40e_aqc_rx_ctl_reg_read_write {
796 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
798 /* Add VSI (indirect 0x0210)
799 * this indirect command uses struct i40e_aqc_vsi_properties_data
800 * as the indirect buffer (128 bytes)
802 * Update VSI (indirect 0x211)
803 * uses the same data structure as Add VSI
805 * Get VSI (indirect 0x0212)
806 * uses the same completion and data structure as Add VSI
808 struct i40e_aqc_add_get_update_vsi {
811 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
812 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
813 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
818 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
819 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
820 #define I40E_AQ_VSI_TYPE_VF 0x0
821 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
822 #define I40E_AQ_VSI_TYPE_PF 0x2
823 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
824 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
829 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
831 struct i40e_aqc_add_get_update_vsi_completion {
840 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
842 struct i40e_aqc_vsi_properties_data {
843 /* first 96 byte are written by SW */
844 __le16 valid_sections;
845 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
846 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
847 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
848 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
849 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
850 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
851 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
852 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
853 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
854 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
856 __le16 switch_id; /* 12bit id combined with flags below */
857 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
858 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
859 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
860 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
861 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
863 /* security section */
865 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
866 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
867 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
870 __le16 pvid; /* VLANS include priority bits */
873 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
874 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
875 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
876 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
877 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
878 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
879 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
880 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
881 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
882 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
883 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
884 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
885 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
886 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
887 u8 pvlan_reserved[3];
888 /* ingress egress up sections */
889 __le32 ingress_table; /* bitmap, 3 bits per up */
890 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
891 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
892 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
893 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
894 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
895 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
896 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
897 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
898 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
899 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
900 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
901 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
902 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
903 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
904 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
905 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
906 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
907 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
908 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
909 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
910 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
911 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
912 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
913 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
914 __le32 egress_table; /* same defines as for ingress table */
915 /* cascaded PV section */
918 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
919 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
920 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
921 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
922 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
923 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
924 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
925 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
926 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
928 /* queue mapping section */
929 __le16 mapping_flags;
930 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
931 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
932 __le16 queue_mapping[16];
933 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
934 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
935 __le16 tc_mapping[8];
936 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
937 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
938 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
939 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
940 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
941 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
942 /* queueing option section */
943 u8 queueing_opt_flags;
945 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
946 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
948 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
949 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
951 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
952 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
954 u8 queueing_opt_reserved[3];
955 /* scheduler section */
958 /* outer up section */
959 __le32 outer_up_table; /* same structure and defines as ingress tbl */
961 /* last 32 bytes are written by FW */
963 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
964 __le16 stat_counter_idx;
966 u8 resp_reserved[12];
969 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
971 /* Add Port Virtualizer (direct 0x0220)
972 * also used for update PV (direct 0x0221) but only flags are used
973 * (IS_CTRL_PORT only works on add PV)
975 struct i40e_aqc_add_update_pv {
976 __le16 command_flags;
977 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
978 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
979 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
980 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
982 __le16 connected_seid;
986 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
988 struct i40e_aqc_add_update_pv_completion {
989 /* reserved for update; for add also encodes error if rc == ENOSPC */
991 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
992 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
993 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
994 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
998 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
1000 /* Get PV Params (direct 0x0222)
1001 * uses i40e_aqc_switch_seid for the descriptor
1004 struct i40e_aqc_get_pv_params_completion {
1006 __le16 default_stag;
1007 __le16 pv_flags; /* same flags as add_pv */
1008 #define I40E_AQC_GET_PV_PV_TYPE 0x1
1009 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1010 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1012 __le16 default_port_seid;
1015 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1017 /* Add VEB (direct 0x0230) */
1018 struct i40e_aqc_add_veb {
1020 __le16 downlink_seid;
1022 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1023 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1024 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1025 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1026 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1027 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1028 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1029 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1034 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1036 struct i40e_aqc_add_veb_completion {
1039 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1041 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1042 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1043 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1044 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1045 __le16 statistic_index;
1050 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1052 /* Get VEB Parameters (direct 0x0232)
1053 * uses i40e_aqc_switch_seid for the descriptor
1055 struct i40e_aqc_get_veb_parameters_completion {
1058 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1059 __le16 statistic_index;
1065 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1067 /* Delete Element (direct 0x0243)
1068 * uses the generic i40e_aqc_switch_seid
1071 /* Add MAC-VLAN (indirect 0x0250) */
1073 /* used for the command for most vlan commands */
1074 struct i40e_aqc_macvlan {
1075 __le16 num_addresses;
1077 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1078 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1079 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1080 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1085 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1087 /* indirect data for command and response */
1088 struct i40e_aqc_add_macvlan_element_data {
1092 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1093 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1094 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1095 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1096 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1097 __le16 queue_number;
1098 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1099 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1100 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1101 /* response section */
1103 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1104 #define I40E_AQC_MM_HASH_MATCH 0x02
1105 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1109 struct i40e_aqc_add_remove_macvlan_completion {
1110 __le16 perfect_mac_used;
1111 __le16 perfect_mac_free;
1112 __le16 unicast_hash_free;
1113 __le16 multicast_hash_free;
1118 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1120 /* Remove MAC-VLAN (indirect 0x0251)
1121 * uses i40e_aqc_macvlan for the descriptor
1122 * data points to an array of num_addresses of elements
1125 struct i40e_aqc_remove_macvlan_element_data {
1129 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1130 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1131 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1132 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1136 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1137 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1138 u8 reply_reserved[3];
1141 /* Add VLAN (indirect 0x0252)
1142 * Remove VLAN (indirect 0x0253)
1143 * use the generic i40e_aqc_macvlan for the command
1145 struct i40e_aqc_add_remove_vlan_element_data {
1148 /* flags for add VLAN */
1149 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1150 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1151 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1152 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1153 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1154 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1155 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1156 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1157 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1158 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1159 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1160 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1161 /* flags for remove VLAN */
1162 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1165 /* flags for add VLAN */
1166 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1167 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1168 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1169 /* flags for remove VLAN */
1170 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1171 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1175 struct i40e_aqc_add_remove_vlan_completion {
1183 /* Set VSI Promiscuous Modes (direct 0x0254) */
1184 struct i40e_aqc_set_vsi_promiscuous_modes {
1185 __le16 promiscuous_flags;
1187 /* flags used for both fields above */
1188 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1189 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1190 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1191 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1192 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1193 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1195 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1197 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1198 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1202 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1204 /* Add S/E-tag command (direct 0x0255)
1205 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1207 struct i40e_aqc_add_tag {
1209 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1211 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1212 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1213 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1215 __le16 queue_number;
1219 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1221 struct i40e_aqc_add_remove_tag_completion {
1227 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1229 /* Remove S/E-tag command (direct 0x0256)
1230 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1232 struct i40e_aqc_remove_tag {
1234 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1235 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1236 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1241 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1243 /* Add multicast E-Tag (direct 0x0257)
1244 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1245 * and no external data
1247 struct i40e_aqc_add_remove_mcast_etag {
1250 u8 num_unicast_etags;
1252 __le32 addr_high; /* address of array of 2-byte s-tags */
1256 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1258 struct i40e_aqc_add_remove_mcast_etag_completion {
1260 __le16 mcast_etags_used;
1261 __le16 mcast_etags_free;
1267 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1269 /* Update S/E-Tag (direct 0x0259) */
1270 struct i40e_aqc_update_tag {
1272 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1273 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1274 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1280 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1282 struct i40e_aqc_update_tag_completion {
1288 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1290 /* Add Control Packet filter (direct 0x025A)
1291 * Remove Control Packet filter (direct 0x025B)
1292 * uses the i40e_aqc_add_oveb_cloud,
1293 * and the generic direct completion structure
1295 struct i40e_aqc_add_remove_control_packet_filter {
1299 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1300 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1301 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1302 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1303 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1305 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1306 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1307 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1312 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1314 struct i40e_aqc_add_remove_control_packet_filter_completion {
1315 __le16 mac_etype_used;
1317 __le16 mac_etype_free;
1322 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1324 /* Add Cloud filters (indirect 0x025C)
1325 * Remove Cloud filters (indirect 0x025D)
1326 * uses the i40e_aqc_add_remove_cloud_filters,
1327 * and the generic indirect completion structure
1329 struct i40e_aqc_add_remove_cloud_filters {
1333 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1334 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1335 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1341 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1343 struct i40e_aqc_add_remove_cloud_filters_element_data {
1357 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1358 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1359 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1360 /* 0x0000 reserved */
1361 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1362 /* 0x0002 reserved */
1363 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1364 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1365 /* 0x0005 reserved */
1366 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1367 /* 0x0007 reserved */
1368 /* 0x0008 reserved */
1369 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1370 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1371 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1372 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1374 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1375 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1376 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1377 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1378 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1380 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1381 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1382 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1383 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1384 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1385 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1386 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1387 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1389 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1390 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1391 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1395 __le16 queue_number;
1396 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1397 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1398 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1400 /* response section */
1401 u8 allocation_result;
1402 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1403 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1404 u8 response_reserved[7];
1407 struct i40e_aqc_remove_cloud_filters_completion {
1408 __le16 perfect_ovlan_used;
1409 __le16 perfect_ovlan_free;
1416 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1418 /* Add Mirror Rule (indirect or direct 0x0260)
1419 * Delete Mirror Rule (indirect or direct 0x0261)
1420 * note: some rule types (4,5) do not use an external buffer.
1421 * take care to set the flags correctly.
1423 struct i40e_aqc_add_delete_mirror_rule {
1426 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1427 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1428 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1429 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1430 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1431 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1432 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1433 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1435 __le16 destination; /* VSI for add, rule id for delete */
1436 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1440 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1442 struct i40e_aqc_add_delete_mirror_rule_completion {
1444 __le16 rule_id; /* only used on add */
1445 __le16 mirror_rules_used;
1446 __le16 mirror_rules_free;
1451 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1455 /* PFC Ignore (direct 0x0301)
1456 * the command and response use the same descriptor structure
1458 struct i40e_aqc_pfc_ignore {
1460 u8 command_flags; /* unused on response */
1461 #define I40E_AQC_PFC_IGNORE_SET 0x80
1462 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1466 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1468 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1469 * with no parameters
1472 /* TX scheduler 0x04xx */
1474 /* Almost all the indirect commands use
1475 * this generic struct to pass the SEID in param0
1477 struct i40e_aqc_tx_sched_ind {
1484 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1486 /* Several commands respond with a set of queue set handles */
1487 struct i40e_aqc_qs_handles_resp {
1488 __le16 qs_handles[8];
1491 /* Configure VSI BW limits (direct 0x0400) */
1492 struct i40e_aqc_configure_vsi_bw_limit {
1497 u8 max_credit; /* 0-3, limit = 2^max */
1501 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1503 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1504 * responds with i40e_aqc_qs_handles_resp
1506 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1509 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1511 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1512 __le16 tc_bw_max[2];
1516 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1518 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1519 * responds with i40e_aqc_qs_handles_resp
1521 struct i40e_aqc_configure_vsi_tc_bw_data {
1524 u8 tc_bw_credits[8];
1526 __le16 qs_handles[8];
1529 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1531 /* Query vsi bw configuration (indirect 0x0408) */
1532 struct i40e_aqc_query_vsi_bw_config_resp {
1534 u8 tc_suspended_bits;
1536 __le16 qs_handles[8];
1538 __le16 port_bw_limit;
1540 u8 max_bw; /* 0-3, limit = 2^max */
1544 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1546 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1547 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1550 u8 share_credits[8];
1553 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1554 __le16 tc_bw_max[2];
1557 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1559 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1560 struct i40e_aqc_configure_switching_comp_bw_limit {
1565 u8 max_bw; /* 0-3, limit = 2^max */
1569 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1571 /* Enable Physical Port ETS (indirect 0x0413)
1572 * Modify Physical Port ETS (indirect 0x0414)
1573 * Disable Physical Port ETS (indirect 0x0415)
1575 struct i40e_aqc_configure_switching_comp_ets_data {
1579 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1580 u8 tc_strict_priority_flags;
1582 u8 tc_bw_share_credits[8];
1586 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1588 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1589 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1592 __le16 tc_bw_credit[8];
1594 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1595 __le16 tc_bw_max[2];
1599 I40E_CHECK_STRUCT_LEN(0x40,
1600 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1602 /* Configure Switching Component Bandwidth Allocation per Tc
1605 struct i40e_aqc_configure_switching_comp_bw_config_data {
1608 u8 absolute_credits; /* bool */
1609 u8 tc_bw_share_credits[8];
1613 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1615 /* Query Switching Component Configuration (indirect 0x0418) */
1616 struct i40e_aqc_query_switching_comp_ets_config_resp {
1619 __le16 port_bw_limit;
1621 u8 tc_bw_max; /* 0-3, limit = 2^max */
1625 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1627 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1628 struct i40e_aqc_query_port_ets_config_resp {
1632 u8 tc_strict_priority_bits;
1634 u8 tc_bw_share_credits[8];
1635 __le16 tc_bw_limits[8];
1637 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1638 __le16 tc_bw_max[2];
1642 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1644 /* Query Switching Component Bandwidth Allocation per Traffic Type
1647 struct i40e_aqc_query_switching_comp_bw_config_resp {
1650 u8 absolute_credits_enable; /* bool */
1651 u8 tc_bw_share_credits[8];
1652 __le16 tc_bw_limits[8];
1654 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1655 __le16 tc_bw_max[2];
1658 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1660 /* Suspend/resume port TX traffic
1661 * (direct 0x041B and 0x041C) uses the generic SEID struct
1664 /* Configure partition BW
1667 struct i40e_aqc_configure_partition_bw_data {
1668 __le16 pf_valid_bits;
1669 u8 min_bw[16]; /* guaranteed bandwidth */
1670 u8 max_bw[16]; /* bandwidth limit */
1673 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1675 /* Get and set the active HMC resource profile and status.
1676 * (direct 0x0500) and (direct 0x0501)
1678 struct i40e_aq_get_set_hmc_resource_profile {
1684 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1686 enum i40e_aq_hmc_profile {
1687 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1688 I40E_HMC_PROFILE_DEFAULT = 1,
1689 I40E_HMC_PROFILE_FAVOR_VF = 2,
1690 I40E_HMC_PROFILE_EQUAL = 3,
1693 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1695 /* set in param0 for get phy abilities to report qualified modules */
1696 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1697 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1699 enum i40e_aq_phy_type {
1700 I40E_PHY_TYPE_SGMII = 0x0,
1701 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1702 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1703 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1704 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1705 I40E_PHY_TYPE_XAUI = 0x5,
1706 I40E_PHY_TYPE_XFI = 0x6,
1707 I40E_PHY_TYPE_SFI = 0x7,
1708 I40E_PHY_TYPE_XLAUI = 0x8,
1709 I40E_PHY_TYPE_XLPPI = 0x9,
1710 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1711 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1712 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1713 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1714 I40E_PHY_TYPE_100BASE_TX = 0x11,
1715 I40E_PHY_TYPE_1000BASE_T = 0x12,
1716 I40E_PHY_TYPE_10GBASE_T = 0x13,
1717 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1718 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1719 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1720 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1721 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1722 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1723 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1724 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1725 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1726 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1727 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1728 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1729 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1730 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1731 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1735 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1736 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1737 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1738 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1739 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1740 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1742 enum i40e_aq_link_speed {
1743 I40E_LINK_SPEED_UNKNOWN = 0,
1744 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1745 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1746 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1747 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1748 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT),
1749 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT),
1752 struct i40e_aqc_module_desc {
1760 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1762 struct i40e_aq_get_phy_abilities_resp {
1763 __le32 phy_type; /* bitmap using the above enum for offsets */
1764 u8 link_speed; /* bitmap using the above enum bit patterns */
1766 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1767 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1768 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1769 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1770 #define I40E_AQ_PHY_AN_ENABLED 0x10
1771 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1772 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
1773 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
1774 __le16 eee_capability;
1775 #define I40E_AQ_EEE_100BASE_TX 0x0002
1776 #define I40E_AQ_EEE_1000BASE_T 0x0004
1777 #define I40E_AQ_EEE_10GBASE_T 0x0008
1778 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1779 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1780 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1783 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1785 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1786 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1787 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1788 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1789 u8 fec_cfg_curr_mod_ext_info;
1790 #define I40E_AQ_ENABLE_FEC_KR 0x01
1791 #define I40E_AQ_ENABLE_FEC_RS 0x02
1792 #define I40E_AQ_REQUEST_FEC_KR 0x04
1793 #define I40E_AQ_REQUEST_FEC_RS 0x08
1794 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
1796 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
1797 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5
1802 u8 qualified_module_count;
1803 #define I40E_AQ_PHY_MAX_QMS 16
1804 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1807 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1809 /* Set PHY Config (direct 0x0601) */
1810 struct i40e_aq_set_phy_config { /* same bits as above in all */
1814 /* bits 0-2 use the values from get_phy_abilities_resp */
1815 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1816 #define I40E_AQ_PHY_ENABLE_AN 0x10
1817 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1818 __le16 eee_capability;
1822 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1823 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1824 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1825 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1827 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1828 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
1829 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
1830 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
1831 #define I40E_AQ_SET_FEC_AUTO BIT(4)
1832 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1833 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1837 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1839 /* Set MAC Config command data structure (direct 0x0603) */
1840 struct i40e_aq_set_mac_config {
1841 __le16 max_frame_size;
1843 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1844 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1845 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1846 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1847 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1848 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1849 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1850 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1851 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1852 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1853 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1854 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1855 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1856 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1857 u8 tx_timer_priority; /* bitmap */
1858 __le16 tx_timer_value;
1859 __le16 fc_refresh_threshold;
1863 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1865 /* Restart Auto-Negotiation (direct 0x605) */
1866 struct i40e_aqc_set_link_restart_an {
1868 #define I40E_AQ_PHY_RESTART_AN 0x02
1869 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1873 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1875 /* Get Link Status cmd & response data structure (direct 0x0607) */
1876 struct i40e_aqc_get_link_status {
1877 __le16 command_flags; /* only field set on command */
1878 #define I40E_AQ_LSE_MASK 0x3
1879 #define I40E_AQ_LSE_NOP 0x0
1880 #define I40E_AQ_LSE_DISABLE 0x2
1881 #define I40E_AQ_LSE_ENABLE 0x3
1882 /* only response uses this flag */
1883 #define I40E_AQ_LSE_IS_ENABLED 0x1
1884 u8 phy_type; /* i40e_aq_phy_type */
1885 u8 link_speed; /* i40e_aq_link_speed */
1887 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1888 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1889 #define I40E_AQ_LINK_FAULT 0x02
1890 #define I40E_AQ_LINK_FAULT_TX 0x04
1891 #define I40E_AQ_LINK_FAULT_RX 0x08
1892 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1893 #define I40E_AQ_LINK_UP_PORT 0x20
1894 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1895 #define I40E_AQ_SIGNAL_DETECT 0x80
1897 #define I40E_AQ_AN_COMPLETED 0x01
1898 #define I40E_AQ_LP_AN_ABILITY 0x02
1899 #define I40E_AQ_PD_FAULT 0x04
1900 #define I40E_AQ_FEC_EN 0x08
1901 #define I40E_AQ_PHY_LOW_POWER 0x10
1902 #define I40E_AQ_LINK_PAUSE_TX 0x20
1903 #define I40E_AQ_LINK_PAUSE_RX 0x40
1904 #define I40E_AQ_QUALIFIED_MODULE 0x80
1906 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1907 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1908 #define I40E_AQ_LINK_TX_SHIFT 0x02
1909 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1910 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1911 #define I40E_AQ_LINK_TX_DRAINED 0x01
1912 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1913 #define I40E_AQ_LINK_FORCED_40G 0x10
1914 /* 25G Error Codes */
1915 #define I40E_AQ_25G_NO_ERR 0X00
1916 #define I40E_AQ_25G_NOT_PRESENT 0X01
1917 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
1918 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
1919 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
1920 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
1921 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1922 __le16 max_frame_size;
1924 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
1925 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
1926 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1927 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1929 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
1930 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
1931 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
1932 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
1933 #define I40E_AQ_PWR_CLASS_MASK 0x03
1937 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1939 /* Set event mask command (direct 0x613) */
1940 struct i40e_aqc_set_phy_int_mask {
1943 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1944 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1945 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1946 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1947 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1948 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1949 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1950 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1951 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1955 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1957 /* Get Local AN advt register (direct 0x0614)
1958 * Set Local AN advt register (direct 0x0615)
1959 * Get Link Partner AN advt register (direct 0x0616)
1961 struct i40e_aqc_an_advt_reg {
1962 __le32 local_an_reg0;
1963 __le16 local_an_reg1;
1967 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1969 /* Set Loopback mode (0x0618) */
1970 struct i40e_aqc_set_lb_mode {
1972 #define I40E_AQ_LB_PHY_LOCAL 0x01
1973 #define I40E_AQ_LB_PHY_REMOTE 0x02
1974 #define I40E_AQ_LB_MAC_LOCAL 0x04
1978 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1980 /* Set PHY Debug command (0x0622) */
1981 struct i40e_aqc_set_phy_debug {
1983 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1984 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1985 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1986 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1987 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1988 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1989 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1990 /* Disable link manageability on a single port */
1991 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1992 /* Disable link manageability on all ports needs both bits 4 and 5 */
1993 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
1997 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1999 enum i40e_aq_phy_reg_type {
2000 I40E_AQC_PHY_REG_INTERNAL = 0x1,
2001 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
2002 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2005 /* Run PHY Activity (0x0626) */
2006 struct i40e_aqc_run_phy_activity {
2015 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
2017 /* NVM Read command (indirect 0x0701)
2018 * NVM Erase commands (direct 0x0702)
2019 * NVM Update commands (indirect 0x0703)
2021 struct i40e_aqc_nvm_update {
2023 #define I40E_AQ_NVM_LAST_CMD 0x01
2024 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2032 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2034 /* NVM Config Read (indirect 0x0704) */
2035 struct i40e_aqc_nvm_config_read {
2037 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2038 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2039 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2040 __le16 element_count;
2041 __le16 element_id; /* Feature/field ID */
2042 __le16 element_id_msw; /* MSWord of field ID */
2043 __le32 address_high;
2047 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2049 /* NVM Config Write (indirect 0x0705) */
2050 struct i40e_aqc_nvm_config_write {
2052 __le16 element_count;
2054 __le32 address_high;
2058 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2060 /* Used for 0x0704 as well as for 0x0705 commands */
2061 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2062 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2063 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2064 #define I40E_AQ_ANVM_FEATURE 0
2065 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
2066 struct i40e_aqc_nvm_config_data_feature {
2068 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2069 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2070 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2071 __le16 feature_options;
2072 __le16 feature_selection;
2075 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2077 struct i40e_aqc_nvm_config_data_immediate_field {
2080 __le16 field_options;
2084 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2086 /* OEM Post Update (indirect 0x0720)
2087 * no command data struct used
2089 struct i40e_aqc_nvm_oem_post_update {
2090 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2095 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2097 struct i40e_aqc_nvm_oem_post_update_buffer {
2104 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2106 /* Thermal Sensor (indirect 0x0721)
2107 * read or set thermal sensor configs and values
2108 * takes a sensor and command specific data buffer, not detailed here
2110 struct i40e_aqc_thermal_sensor {
2112 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2113 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2114 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2120 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2122 /* Send to PF command (indirect 0x0801) id is only used by PF
2123 * Send to VF command (indirect 0x0802) id is only used by PF
2124 * Send to Peer PF command (indirect 0x0803)
2126 struct i40e_aqc_pf_vf_message {
2133 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2135 /* Alternate structure */
2137 /* Direct write (direct 0x0900)
2138 * Direct read (direct 0x0902)
2140 struct i40e_aqc_alternate_write {
2147 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2149 /* Indirect write (indirect 0x0901)
2150 * Indirect read (indirect 0x0903)
2153 struct i40e_aqc_alternate_ind_write {
2160 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2162 /* Done alternate write (direct 0x0904)
2165 struct i40e_aqc_alternate_write_done {
2167 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2168 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2169 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2170 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2174 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2176 /* Set OEM mode (direct 0x0905) */
2177 struct i40e_aqc_alternate_set_mode {
2179 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2180 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2184 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2186 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2188 /* async events 0x10xx */
2190 /* Lan Queue Overflow Event (direct, 0x1001) */
2191 struct i40e_aqc_lan_overflow {
2192 __le32 prtdcb_rupto;
2197 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2199 /* Get LLDP MIB (indirect 0x0A00) */
2200 struct i40e_aqc_lldp_get_mib {
2203 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2204 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2205 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2206 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2207 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2208 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2209 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2210 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2211 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2212 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2213 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2221 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2223 /* Configure LLDP MIB Change Event (direct 0x0A01)
2224 * also used for the event (with type in the command field)
2226 struct i40e_aqc_lldp_update_mib {
2228 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2229 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2235 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2237 /* Add LLDP TLV (indirect 0x0A02)
2238 * Delete LLDP TLV (indirect 0x0A04)
2240 struct i40e_aqc_lldp_add_tlv {
2241 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2249 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2251 /* Update LLDP TLV (indirect 0x0A03) */
2252 struct i40e_aqc_lldp_update_tlv {
2253 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2262 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2264 /* Stop LLDP (direct 0x0A05) */
2265 struct i40e_aqc_lldp_stop {
2267 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2268 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2272 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2274 /* Start LLDP (direct 0x0A06) */
2276 struct i40e_aqc_lldp_start {
2278 #define I40E_AQ_LLDP_AGENT_START 0x1
2282 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2284 /* Get CEE DCBX Oper Config (0x0A07)
2285 * uses the generic descriptor struct
2286 * returns below as indirect response
2289 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2290 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2291 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2292 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2293 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2294 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2296 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2297 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2298 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2299 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2300 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2301 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2302 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2303 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2304 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2305 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2306 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2307 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2309 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2310 * word boundary layout issues, which the Linux compilers silently deal
2311 * with by adding padding, making the actual struct larger than designed.
2312 * However, the FW compiler for the NIC is less lenient and complains
2313 * about the struct. Hence, the struct defined here has an extra byte in
2314 * fields reserved3 and reserved4 to directly acknowledge that padding,
2315 * and the new length is used in the length check macro.
2317 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2325 __le16 oper_app_prio;
2330 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2332 struct i40e_aqc_get_cee_dcb_cfg_resp {
2337 __le16 oper_app_prio;
2342 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2344 /* Set Local LLDP MIB (indirect 0x0A08)
2345 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2347 struct i40e_aqc_lldp_set_local_mib {
2348 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2349 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2350 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2351 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2352 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2353 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2354 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2355 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2360 __le32 address_high;
2364 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2366 struct i40e_aqc_lldp_set_local_mib_resp {
2367 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
2372 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
2374 /* Stop/Start LLDP Agent (direct 0x0A09)
2375 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2377 struct i40e_aqc_lldp_stop_start_specific_agent {
2378 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2379 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2380 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2385 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2387 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2388 struct i40e_aqc_add_udp_tunnel {
2392 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2393 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2394 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2395 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2399 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2401 struct i40e_aqc_add_udp_tunnel_completion {
2403 u8 filter_entry_index;
2405 #define I40E_AQC_SINGLE_PF 0x0
2406 #define I40E_AQC_MULTIPLE_PFS 0x1
2411 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2413 /* remove UDP Tunnel command (0x0B01) */
2414 struct i40e_aqc_remove_udp_tunnel {
2416 u8 index; /* 0 to 15 */
2420 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2422 struct i40e_aqc_del_udp_tunnel_completion {
2424 u8 index; /* 0 to 15 */
2426 u8 total_filters_used;
2430 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2433 struct i40e_aqc_get_set_rss_key {
2434 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2435 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2436 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2437 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2444 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2446 struct i40e_aqc_get_set_rss_key_data {
2447 u8 standard_rss_key[0x28];
2448 u8 extended_hash_key[0xc];
2451 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2453 struct i40e_aqc_get_set_rss_lut {
2454 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2455 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2456 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2457 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2459 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2460 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2461 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2463 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2464 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2471 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2474 /* tunnel key structure 0x0B10 */
2476 struct i40e_aqc_tunnel_key_structure {
2479 u8 key1_len; /* 0 to 15 */
2480 u8 key2_len; /* 0 to 15 */
2482 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2483 /* response flags */
2484 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2485 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2486 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2487 u8 network_key_index;
2488 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2489 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2490 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2491 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2495 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2497 /* OEM mode commands (direct 0xFE0x) */
2498 struct i40e_aqc_oem_param_change {
2500 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2501 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2502 #define I40E_AQ_OEM_PARAM_MAC 2
2503 __le32 param_value1;
2504 __le16 param_value2;
2508 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2510 struct i40e_aqc_oem_state_change {
2512 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2513 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2517 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2519 /* Initialize OCSD (0xFE02, direct) */
2520 struct i40e_aqc_opc_oem_ocsd_initialize {
2523 __le32 ocsd_memory_block_addr_high;
2524 __le32 ocsd_memory_block_addr_low;
2525 __le32 requested_update_interval;
2528 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2530 /* Initialize OCBB (0xFE03, direct) */
2531 struct i40e_aqc_opc_oem_ocbb_initialize {
2534 __le32 ocbb_memory_block_addr_high;
2535 __le32 ocbb_memory_block_addr_low;
2539 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2541 /* debug commands */
2543 /* get device id (0xFF00) uses the generic structure */
2545 /* set test more (0xFF01, internal) */
2547 struct i40e_acq_set_test_mode {
2549 #define I40E_AQ_TEST_PARTIAL 0
2550 #define I40E_AQ_TEST_FULL 1
2551 #define I40E_AQ_TEST_NVM 2
2554 #define I40E_AQ_TEST_OPEN 0
2555 #define I40E_AQ_TEST_CLOSE 1
2556 #define I40E_AQ_TEST_INC 2
2558 __le32 address_high;
2562 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2564 /* Debug Read Register command (0xFF03)
2565 * Debug Write Register command (0xFF04)
2567 struct i40e_aqc_debug_reg_read_write {
2574 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2576 /* Scatter/gather Reg Read (indirect 0xFF05)
2577 * Scatter/gather Reg Write (indirect 0xFF06)
2580 /* i40e_aq_desc is used for the command */
2581 struct i40e_aqc_debug_reg_sg_element_data {
2586 /* Debug Modify register (direct 0xFF07) */
2587 struct i40e_aqc_debug_modify_reg {
2594 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2596 /* dump internal data (0xFF08, indirect) */
2598 #define I40E_AQ_CLUSTER_ID_AUX 0
2599 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2600 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2601 #define I40E_AQ_CLUSTER_ID_HMC 3
2602 #define I40E_AQ_CLUSTER_ID_MAC0 4
2603 #define I40E_AQ_CLUSTER_ID_MAC1 5
2604 #define I40E_AQ_CLUSTER_ID_MAC2 6
2605 #define I40E_AQ_CLUSTER_ID_MAC3 7
2606 #define I40E_AQ_CLUSTER_ID_DCB 8
2607 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2608 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2609 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2611 struct i40e_aqc_debug_dump_internals {
2616 __le32 address_high;
2620 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2622 struct i40e_aqc_debug_modify_internals {
2624 u8 cluster_specific_params[7];
2625 __le32 address_high;
2629 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2631 #endif /* _I40E_ADMINQ_CMD_H_ */