1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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32 ***************************************************************************/
34 #ifndef _I40E_ADMINQ_CMD_H_
35 #define _I40E_ADMINQ_CMD_H_
37 /* This header file defines the i40e Admin Queue commands and is shared between
38 * i40e Firmware and Software.
40 * This file needs to comply with the Linux Kernel coding style.
43 #define I40E_FW_API_VERSION_MAJOR 0x0001
44 #define I40E_FW_API_VERSION_MINOR 0x0005
70 /* Flags sub-structure
71 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
72 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
75 /* command flags and offsets*/
76 #define I40E_AQ_FLAG_DD_SHIFT 0
77 #define I40E_AQ_FLAG_CMP_SHIFT 1
78 #define I40E_AQ_FLAG_ERR_SHIFT 2
79 #define I40E_AQ_FLAG_VFE_SHIFT 3
80 #define I40E_AQ_FLAG_LB_SHIFT 9
81 #define I40E_AQ_FLAG_RD_SHIFT 10
82 #define I40E_AQ_FLAG_VFC_SHIFT 11
83 #define I40E_AQ_FLAG_BUF_SHIFT 12
84 #define I40E_AQ_FLAG_SI_SHIFT 13
85 #define I40E_AQ_FLAG_EI_SHIFT 14
86 #define I40E_AQ_FLAG_FE_SHIFT 15
88 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
89 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
90 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
91 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
92 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
93 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
94 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
95 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
96 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
97 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
98 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
101 enum i40e_admin_queue_err {
102 I40E_AQ_RC_OK = 0, /* success */
103 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
104 I40E_AQ_RC_ENOENT = 2, /* No such element */
105 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
106 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
107 I40E_AQ_RC_EIO = 5, /* I/O error */
108 I40E_AQ_RC_ENXIO = 6, /* No such resource */
109 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
110 I40E_AQ_RC_EAGAIN = 8, /* Try again */
111 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
112 I40E_AQ_RC_EACCES = 10, /* Permission denied */
113 I40E_AQ_RC_EFAULT = 11, /* Bad address */
114 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
115 I40E_AQ_RC_EEXIST = 13, /* object already exists */
116 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
117 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
118 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
119 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
120 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
121 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
122 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
123 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
124 I40E_AQ_RC_EFBIG = 22, /* File too large */
127 /* Admin Queue command opcodes */
128 enum i40e_admin_queue_opc {
130 i40e_aqc_opc_get_version = 0x0001,
131 i40e_aqc_opc_driver_version = 0x0002,
132 i40e_aqc_opc_queue_shutdown = 0x0003,
133 i40e_aqc_opc_set_pf_context = 0x0004,
135 /* resource ownership */
136 i40e_aqc_opc_request_resource = 0x0008,
137 i40e_aqc_opc_release_resource = 0x0009,
139 i40e_aqc_opc_list_func_capabilities = 0x000A,
140 i40e_aqc_opc_list_dev_capabilities = 0x000B,
144 i40e_aqc_opc_set_proxy_config = 0x0104,
145 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
149 i40e_aqc_opc_mac_address_read = 0x0107,
150 i40e_aqc_opc_mac_address_write = 0x0108,
153 i40e_aqc_opc_clear_pxe_mode = 0x0110,
157 i40e_aqc_opc_set_wol_filter = 0x0120,
158 i40e_aqc_opc_get_wake_reason = 0x0121,
161 /* internal switch commands */
162 i40e_aqc_opc_get_switch_config = 0x0200,
163 i40e_aqc_opc_add_statistics = 0x0201,
164 i40e_aqc_opc_remove_statistics = 0x0202,
165 i40e_aqc_opc_set_port_parameters = 0x0203,
166 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
167 i40e_aqc_opc_set_switch_config = 0x0205,
168 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
169 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
171 i40e_aqc_opc_add_vsi = 0x0210,
172 i40e_aqc_opc_update_vsi_parameters = 0x0211,
173 i40e_aqc_opc_get_vsi_parameters = 0x0212,
175 i40e_aqc_opc_add_pv = 0x0220,
176 i40e_aqc_opc_update_pv_parameters = 0x0221,
177 i40e_aqc_opc_get_pv_parameters = 0x0222,
179 i40e_aqc_opc_add_veb = 0x0230,
180 i40e_aqc_opc_update_veb_parameters = 0x0231,
181 i40e_aqc_opc_get_veb_parameters = 0x0232,
183 i40e_aqc_opc_delete_element = 0x0243,
185 i40e_aqc_opc_add_macvlan = 0x0250,
186 i40e_aqc_opc_remove_macvlan = 0x0251,
187 i40e_aqc_opc_add_vlan = 0x0252,
188 i40e_aqc_opc_remove_vlan = 0x0253,
189 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
190 i40e_aqc_opc_add_tag = 0x0255,
191 i40e_aqc_opc_remove_tag = 0x0256,
192 i40e_aqc_opc_add_multicast_etag = 0x0257,
193 i40e_aqc_opc_remove_multicast_etag = 0x0258,
194 i40e_aqc_opc_update_tag = 0x0259,
195 i40e_aqc_opc_add_control_packet_filter = 0x025A,
196 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
197 i40e_aqc_opc_add_cloud_filters = 0x025C,
198 i40e_aqc_opc_remove_cloud_filters = 0x025D,
200 i40e_aqc_opc_add_mirror_rule = 0x0260,
201 i40e_aqc_opc_delete_mirror_rule = 0x0261,
204 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
205 i40e_aqc_opc_dcb_updated = 0x0302,
208 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
209 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
210 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
211 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
212 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
213 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
215 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
216 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
217 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
218 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
219 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
220 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
221 i40e_aqc_opc_query_port_ets_config = 0x0419,
222 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
223 i40e_aqc_opc_suspend_port_tx = 0x041B,
224 i40e_aqc_opc_resume_port_tx = 0x041C,
225 i40e_aqc_opc_configure_partition_bw = 0x041D,
228 i40e_aqc_opc_get_phy_abilities = 0x0600,
229 i40e_aqc_opc_set_phy_config = 0x0601,
230 i40e_aqc_opc_set_mac_config = 0x0603,
231 i40e_aqc_opc_set_link_restart_an = 0x0605,
232 i40e_aqc_opc_get_link_status = 0x0607,
233 i40e_aqc_opc_set_phy_int_mask = 0x0613,
234 i40e_aqc_opc_get_local_advt_reg = 0x0614,
235 i40e_aqc_opc_set_local_advt_reg = 0x0615,
236 i40e_aqc_opc_get_partner_advt = 0x0616,
237 i40e_aqc_opc_set_lb_modes = 0x0618,
238 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
239 i40e_aqc_opc_set_phy_debug = 0x0622,
240 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
241 i40e_aqc_opc_run_phy_activity = 0x0626,
244 i40e_aqc_opc_nvm_read = 0x0701,
245 i40e_aqc_opc_nvm_erase = 0x0702,
246 i40e_aqc_opc_nvm_update = 0x0703,
247 i40e_aqc_opc_nvm_config_read = 0x0704,
248 i40e_aqc_opc_nvm_config_write = 0x0705,
249 i40e_aqc_opc_oem_post_update = 0x0720,
250 i40e_aqc_opc_thermal_sensor = 0x0721,
252 /* virtualization commands */
253 i40e_aqc_opc_send_msg_to_pf = 0x0801,
254 i40e_aqc_opc_send_msg_to_vf = 0x0802,
255 i40e_aqc_opc_send_msg_to_peer = 0x0803,
257 /* alternate structure */
258 i40e_aqc_opc_alternate_write = 0x0900,
259 i40e_aqc_opc_alternate_write_indirect = 0x0901,
260 i40e_aqc_opc_alternate_read = 0x0902,
261 i40e_aqc_opc_alternate_read_indirect = 0x0903,
262 i40e_aqc_opc_alternate_write_done = 0x0904,
263 i40e_aqc_opc_alternate_set_mode = 0x0905,
264 i40e_aqc_opc_alternate_clear_port = 0x0906,
267 i40e_aqc_opc_lldp_get_mib = 0x0A00,
268 i40e_aqc_opc_lldp_update_mib = 0x0A01,
269 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
270 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
271 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
272 i40e_aqc_opc_lldp_stop = 0x0A05,
273 i40e_aqc_opc_lldp_start = 0x0A06,
274 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
275 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
276 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
278 /* Tunnel commands */
279 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
280 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
282 i40e_aqc_opc_set_rss_key = 0x0B02,
283 i40e_aqc_opc_set_rss_lut = 0x0B03,
284 i40e_aqc_opc_get_rss_key = 0x0B04,
285 i40e_aqc_opc_get_rss_lut = 0x0B05,
289 i40e_aqc_opc_event_lan_overflow = 0x1001,
292 i40e_aqc_opc_oem_parameter_change = 0xFE00,
293 i40e_aqc_opc_oem_device_status_change = 0xFE01,
294 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
295 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
298 i40e_aqc_opc_debug_read_reg = 0xFF03,
299 i40e_aqc_opc_debug_write_reg = 0xFF04,
300 i40e_aqc_opc_debug_modify_reg = 0xFF07,
301 i40e_aqc_opc_debug_dump_internals = 0xFF08,
304 /* command structures and indirect data structures */
306 /* Structure naming conventions:
307 * - no suffix for direct command descriptor structures
308 * - _data for indirect sent data
309 * - _resp for indirect return data (data which is both will use _data)
310 * - _completion for direct return data
311 * - _element_ for repeated elements (may also be _data or _resp)
313 * Command structures are expected to overlay the params.raw member of the basic
314 * descriptor, and as such cannot exceed 16 bytes in length.
317 /* This macro is used to generate a compilation error if a structure
318 * is not exactly the correct length. It gives a divide by zero error if the
319 * structure is not of the correct size, otherwise it creates an enum that is
322 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
323 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
325 /* This macro is used extensively to ensure that command structures are 16
326 * bytes in length as they have to map to the raw array of that size.
328 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
330 /* internal (0x00XX) commands */
332 /* Get version (direct 0x0001) */
333 struct i40e_aqc_get_version {
342 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
344 /* Send driver version (indirect 0x0002) */
345 struct i40e_aqc_driver_version {
349 u8 driver_subbuild_ver;
355 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
357 /* Queue Shutdown (direct 0x0003) */
358 struct i40e_aqc_queue_shutdown {
359 __le32 driver_unloading;
360 #define I40E_AQ_DRIVER_UNLOADING 0x1
364 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
366 /* Set PF context (0x0004, direct) */
367 struct i40e_aqc_set_pf_context {
372 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
374 /* Request resource ownership (direct 0x0008)
375 * Release resource ownership (direct 0x0009)
377 #define I40E_AQ_RESOURCE_NVM 1
378 #define I40E_AQ_RESOURCE_SDP 2
379 #define I40E_AQ_RESOURCE_ACCESS_READ 1
380 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
381 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
382 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
384 struct i40e_aqc_request_resource {
388 __le32 resource_number;
392 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
394 /* Get function capabilities (indirect 0x000A)
395 * Get device capabilities (indirect 0x000B)
397 struct i40e_aqc_list_capabilites {
399 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
407 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
409 struct i40e_aqc_list_capabilities_element_resp {
421 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
422 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
423 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
424 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
425 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
426 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
427 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
428 #define I40E_AQ_CAP_ID_SRIOV 0x0012
429 #define I40E_AQ_CAP_ID_VF 0x0013
430 #define I40E_AQ_CAP_ID_VMDQ 0x0014
431 #define I40E_AQ_CAP_ID_8021QBG 0x0015
432 #define I40E_AQ_CAP_ID_8021QBR 0x0016
433 #define I40E_AQ_CAP_ID_VSI 0x0017
434 #define I40E_AQ_CAP_ID_DCB 0x0018
435 #define I40E_AQ_CAP_ID_FCOE 0x0021
436 #define I40E_AQ_CAP_ID_ISCSI 0x0022
437 #define I40E_AQ_CAP_ID_RSS 0x0040
438 #define I40E_AQ_CAP_ID_RXQ 0x0041
439 #define I40E_AQ_CAP_ID_TXQ 0x0042
440 #define I40E_AQ_CAP_ID_MSIX 0x0043
441 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
442 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
443 #define I40E_AQ_CAP_ID_1588 0x0046
444 #define I40E_AQ_CAP_ID_IWARP 0x0051
445 #define I40E_AQ_CAP_ID_LED 0x0061
446 #define I40E_AQ_CAP_ID_SDP 0x0062
447 #define I40E_AQ_CAP_ID_MDIO 0x0063
448 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
449 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
450 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
451 #define I40E_AQ_CAP_ID_CEM 0x00F2
453 /* Set CPPM Configuration (direct 0x0103) */
454 struct i40e_aqc_cppm_configuration {
455 __le16 command_flags;
456 #define I40E_AQ_CPPM_EN_LTRC 0x0800
457 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
458 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
459 #define I40E_AQ_CPPM_EN_HPTC 0x4000
460 #define I40E_AQ_CPPM_EN_DMARC 0x8000
469 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
471 /* Set ARP Proxy command / response (indirect 0x0104) */
472 struct i40e_aqc_arp_proxy_data {
473 __le16 command_flags;
474 #define I40E_AQ_ARP_INIT_IPV4 0x0008
475 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
476 #define I40E_AQ_ARP_ENA 0x0020
477 #define I40E_AQ_ARP_ADD_IPV4 0x0040
478 #define I40E_AQ_ARP_DEL_IPV4 0x0080
486 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
488 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
489 struct i40e_aqc_ns_proxy_data {
490 __le16 table_idx_mac_addr_0;
491 __le16 table_idx_mac_addr_1;
492 __le16 table_idx_ipv6_0;
493 __le16 table_idx_ipv6_1;
495 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
496 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
497 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
498 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
499 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
500 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
501 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
502 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
503 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
504 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
505 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
508 u8 local_mac_addr[6];
509 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
513 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
515 /* Manage LAA Command (0x0106) - obsolete */
516 struct i40e_aqc_mng_laa {
517 __le16 command_flags;
518 #define I40E_AQ_LAA_FLAG_WR 0x8000
525 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
527 /* Manage MAC Address Read Command (indirect 0x0107) */
528 struct i40e_aqc_mac_address_read {
529 __le16 command_flags;
530 #define I40E_AQC_LAN_ADDR_VALID 0x10
531 #define I40E_AQC_SAN_ADDR_VALID 0x20
532 #define I40E_AQC_PORT_ADDR_VALID 0x40
533 #define I40E_AQC_WOL_ADDR_VALID 0x80
534 #define I40E_AQC_MC_MAG_EN_VALID 0x100
535 #define I40E_AQC_ADDR_VALID_MASK 0x1F0
541 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
543 struct i40e_aqc_mac_address_read_data {
550 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
552 /* Manage MAC Address Write Command (0x0108) */
553 struct i40e_aqc_mac_address_write {
554 __le16 command_flags;
555 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
556 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
557 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
558 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
559 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
566 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
568 /* PXE commands (0x011x) */
570 /* Clear PXE Command and response (direct 0x0110) */
571 struct i40e_aqc_clear_pxe {
576 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
579 /* Set WoL Filter (0x0120) */
581 struct i40e_aqc_set_wol_filter {
583 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
585 #define I40E_AQC_SET_WOL_FILTER 0x8000
586 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
588 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
589 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
595 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
597 /* Get Wake Reason (0x0121) */
599 struct i40e_aqc_get_wake_reason_completion {
605 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
607 struct i40e_aqc_set_wol_filter_data {
612 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
614 #endif /* X722_SUPPORT */
615 /* Switch configuration commands (0x02xx) */
617 /* Used by many indirect commands that only pass an seid and a buffer in the
620 struct i40e_aqc_switch_seid {
627 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
629 /* Get Switch Configuration command (indirect 0x0200)
630 * uses i40e_aqc_switch_seid for the descriptor
632 struct i40e_aqc_get_switch_config_header_resp {
638 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
640 struct i40e_aqc_switch_config_element_resp {
642 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
643 #define I40E_AQ_SW_ELEM_TYPE_PF 2
644 #define I40E_AQ_SW_ELEM_TYPE_VF 3
645 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
646 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
647 #define I40E_AQ_SW_ELEM_TYPE_PV 16
648 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
649 #define I40E_AQ_SW_ELEM_TYPE_PA 18
650 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
652 #define I40E_AQ_SW_ELEM_REV_1 1
655 __le16 downlink_seid;
658 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
659 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
660 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
665 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
667 /* Get Switch Configuration (indirect 0x0200)
668 * an array of elements are returned in the response buffer
669 * the first in the array is the header, remainder are elements
671 struct i40e_aqc_get_switch_config_resp {
672 struct i40e_aqc_get_switch_config_header_resp header;
673 struct i40e_aqc_switch_config_element_resp element[1];
676 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
678 /* Add Statistics (direct 0x0201)
679 * Remove Statistics (direct 0x0202)
681 struct i40e_aqc_add_remove_statistics {
688 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
690 /* Set Port Parameters command (direct 0x0203) */
691 struct i40e_aqc_set_port_parameters {
692 __le16 command_flags;
693 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
694 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
695 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
696 __le16 bad_frame_vsi;
697 __le16 default_seid; /* reserved for command */
701 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
703 /* Get Switch Resource Allocation (indirect 0x0204) */
704 struct i40e_aqc_get_switch_resource_alloc {
705 u8 num_entries; /* reserved for command */
711 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
713 /* expect an array of these structs in the response buffer */
714 struct i40e_aqc_switch_resource_alloc_element_resp {
716 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
717 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
718 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
719 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
720 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
721 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
722 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
723 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
724 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
725 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
726 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
727 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
728 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
729 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
730 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
731 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
732 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
733 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
734 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
739 __le16 total_unalloced;
743 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
745 /* Set Switch Configuration (direct 0x0205) */
746 struct i40e_aqc_set_switch_config {
748 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
749 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
754 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
756 /* Read Receive control registers (direct 0x0206)
757 * Write Receive control registers (direct 0x0207)
758 * used for accessing Rx control registers that can be
759 * slow and need special handling when under high Rx load
761 struct i40e_aqc_rx_ctl_reg_read_write {
768 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
770 /* Add VSI (indirect 0x0210)
771 * this indirect command uses struct i40e_aqc_vsi_properties_data
772 * as the indirect buffer (128 bytes)
774 * Update VSI (indirect 0x211)
775 * uses the same data structure as Add VSI
777 * Get VSI (indirect 0x0212)
778 * uses the same completion and data structure as Add VSI
780 struct i40e_aqc_add_get_update_vsi {
783 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
784 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
785 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
790 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
791 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
792 #define I40E_AQ_VSI_TYPE_VF 0x0
793 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
794 #define I40E_AQ_VSI_TYPE_PF 0x2
795 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
796 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
801 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
803 struct i40e_aqc_add_get_update_vsi_completion {
812 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
814 struct i40e_aqc_vsi_properties_data {
815 /* first 96 byte are written by SW */
816 __le16 valid_sections;
817 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
818 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
819 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
820 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
821 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
822 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
823 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
824 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
825 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
826 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
828 __le16 switch_id; /* 12bit id combined with flags below */
829 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
830 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
831 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
832 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
833 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
835 /* security section */
837 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
838 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
839 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
842 __le16 pvid; /* VLANS include priority bits */
845 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
846 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
847 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
848 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
849 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
850 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
851 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
852 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
853 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
854 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
855 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
856 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
857 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
858 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
859 u8 pvlan_reserved[3];
860 /* ingress egress up sections */
861 __le32 ingress_table; /* bitmap, 3 bits per up */
862 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
863 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
864 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
865 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
866 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
867 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
868 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
869 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
870 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
871 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
872 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
873 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
874 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
875 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
876 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
877 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
878 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
879 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
880 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
881 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
882 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
883 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
884 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
885 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
886 __le32 egress_table; /* same defines as for ingress table */
887 /* cascaded PV section */
890 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
891 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
892 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
893 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
894 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
895 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
896 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
897 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
898 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
900 /* queue mapping section */
901 __le16 mapping_flags;
902 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
903 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
904 __le16 queue_mapping[16];
905 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
906 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
907 __le16 tc_mapping[8];
908 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
909 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
910 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
911 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
912 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
913 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
914 /* queueing option section */
915 u8 queueing_opt_flags;
917 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
918 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
920 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
921 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
923 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
924 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
926 u8 queueing_opt_reserved[3];
927 /* scheduler section */
930 /* outer up section */
931 __le32 outer_up_table; /* same structure and defines as ingress tbl */
933 /* last 32 bytes are written by FW */
935 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
936 __le16 stat_counter_idx;
938 u8 resp_reserved[12];
941 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
943 /* Add Port Virtualizer (direct 0x0220)
944 * also used for update PV (direct 0x0221) but only flags are used
945 * (IS_CTRL_PORT only works on add PV)
947 struct i40e_aqc_add_update_pv {
948 __le16 command_flags;
949 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
950 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
951 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
952 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
954 __le16 connected_seid;
958 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
960 struct i40e_aqc_add_update_pv_completion {
961 /* reserved for update; for add also encodes error if rc == ENOSPC */
963 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
964 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
965 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
966 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
970 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
972 /* Get PV Params (direct 0x0222)
973 * uses i40e_aqc_switch_seid for the descriptor
976 struct i40e_aqc_get_pv_params_completion {
979 __le16 pv_flags; /* same flags as add_pv */
980 #define I40E_AQC_GET_PV_PV_TYPE 0x1
981 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
982 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
984 __le16 default_port_seid;
987 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
989 /* Add VEB (direct 0x0230) */
990 struct i40e_aqc_add_veb {
992 __le16 downlink_seid;
994 #define I40E_AQC_ADD_VEB_FLOATING 0x1
995 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
996 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
997 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
998 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
999 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1000 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1001 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1006 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1008 struct i40e_aqc_add_veb_completion {
1011 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1013 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1014 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1015 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1016 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1017 __le16 statistic_index;
1022 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1024 /* Get VEB Parameters (direct 0x0232)
1025 * uses i40e_aqc_switch_seid for the descriptor
1027 struct i40e_aqc_get_veb_parameters_completion {
1030 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1031 __le16 statistic_index;
1037 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1039 /* Delete Element (direct 0x0243)
1040 * uses the generic i40e_aqc_switch_seid
1043 /* Add MAC-VLAN (indirect 0x0250) */
1045 /* used for the command for most vlan commands */
1046 struct i40e_aqc_macvlan {
1047 __le16 num_addresses;
1049 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1050 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1051 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1052 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1057 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1059 /* indirect data for command and response */
1060 struct i40e_aqc_add_macvlan_element_data {
1064 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1065 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1066 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1067 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1068 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1069 __le16 queue_number;
1070 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1071 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1072 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1073 /* response section */
1075 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1076 #define I40E_AQC_MM_HASH_MATCH 0x02
1077 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1081 struct i40e_aqc_add_remove_macvlan_completion {
1082 __le16 perfect_mac_used;
1083 __le16 perfect_mac_free;
1084 __le16 unicast_hash_free;
1085 __le16 multicast_hash_free;
1090 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1092 /* Remove MAC-VLAN (indirect 0x0251)
1093 * uses i40e_aqc_macvlan for the descriptor
1094 * data points to an array of num_addresses of elements
1097 struct i40e_aqc_remove_macvlan_element_data {
1101 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1102 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1103 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1104 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1108 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1109 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1110 u8 reply_reserved[3];
1113 /* Add VLAN (indirect 0x0252)
1114 * Remove VLAN (indirect 0x0253)
1115 * use the generic i40e_aqc_macvlan for the command
1117 struct i40e_aqc_add_remove_vlan_element_data {
1120 /* flags for add VLAN */
1121 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1122 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1123 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1124 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1125 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1126 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1127 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1128 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1129 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1130 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1131 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1132 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1133 /* flags for remove VLAN */
1134 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1137 /* flags for add VLAN */
1138 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1139 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1140 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1141 /* flags for remove VLAN */
1142 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1143 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1147 struct i40e_aqc_add_remove_vlan_completion {
1155 /* Set VSI Promiscuous Modes (direct 0x0254) */
1156 struct i40e_aqc_set_vsi_promiscuous_modes {
1157 __le16 promiscuous_flags;
1159 /* flags used for both fields above */
1160 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1161 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1162 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1163 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1164 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1165 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1167 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1169 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1170 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1174 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1176 /* Add S/E-tag command (direct 0x0255)
1177 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1179 struct i40e_aqc_add_tag {
1181 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1183 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1184 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1185 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1187 __le16 queue_number;
1191 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1193 struct i40e_aqc_add_remove_tag_completion {
1199 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1201 /* Remove S/E-tag command (direct 0x0256)
1202 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1204 struct i40e_aqc_remove_tag {
1206 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1207 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1208 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1213 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1215 /* Add multicast E-Tag (direct 0x0257)
1216 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1217 * and no external data
1219 struct i40e_aqc_add_remove_mcast_etag {
1222 u8 num_unicast_etags;
1224 __le32 addr_high; /* address of array of 2-byte s-tags */
1228 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1230 struct i40e_aqc_add_remove_mcast_etag_completion {
1232 __le16 mcast_etags_used;
1233 __le16 mcast_etags_free;
1239 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1241 /* Update S/E-Tag (direct 0x0259) */
1242 struct i40e_aqc_update_tag {
1244 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1245 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1246 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1252 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1254 struct i40e_aqc_update_tag_completion {
1260 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1262 /* Add Control Packet filter (direct 0x025A)
1263 * Remove Control Packet filter (direct 0x025B)
1264 * uses the i40e_aqc_add_oveb_cloud,
1265 * and the generic direct completion structure
1267 struct i40e_aqc_add_remove_control_packet_filter {
1271 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1272 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1273 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1274 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1275 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1277 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1278 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1279 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1284 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1286 struct i40e_aqc_add_remove_control_packet_filter_completion {
1287 __le16 mac_etype_used;
1289 __le16 mac_etype_free;
1294 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1296 /* Add Cloud filters (indirect 0x025C)
1297 * Remove Cloud filters (indirect 0x025D)
1298 * uses the i40e_aqc_add_remove_cloud_filters,
1299 * and the generic indirect completion structure
1301 struct i40e_aqc_add_remove_cloud_filters {
1305 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1306 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1307 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1313 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1315 struct i40e_aqc_add_remove_cloud_filters_element_data {
1329 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1330 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1331 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1332 /* 0x0000 reserved */
1333 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1334 /* 0x0002 reserved */
1335 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1336 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1337 /* 0x0005 reserved */
1338 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1339 /* 0x0007 reserved */
1340 /* 0x0008 reserved */
1341 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1342 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1343 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1344 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1346 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1347 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1348 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1349 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1350 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1352 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1353 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1354 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1355 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1356 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1357 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1358 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1359 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1361 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1362 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1363 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1367 __le16 queue_number;
1368 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1369 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1370 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1372 /* response section */
1373 u8 allocation_result;
1374 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1375 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1376 u8 response_reserved[7];
1379 struct i40e_aqc_remove_cloud_filters_completion {
1380 __le16 perfect_ovlan_used;
1381 __le16 perfect_ovlan_free;
1388 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1390 /* Add Mirror Rule (indirect or direct 0x0260)
1391 * Delete Mirror Rule (indirect or direct 0x0261)
1392 * note: some rule types (4,5) do not use an external buffer.
1393 * take care to set the flags correctly.
1395 struct i40e_aqc_add_delete_mirror_rule {
1398 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1399 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1400 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1401 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1402 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1403 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1404 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1405 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1407 __le16 destination; /* VSI for add, rule id for delete */
1408 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1412 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1414 struct i40e_aqc_add_delete_mirror_rule_completion {
1416 __le16 rule_id; /* only used on add */
1417 __le16 mirror_rules_used;
1418 __le16 mirror_rules_free;
1423 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1427 /* PFC Ignore (direct 0x0301)
1428 * the command and response use the same descriptor structure
1430 struct i40e_aqc_pfc_ignore {
1432 u8 command_flags; /* unused on response */
1433 #define I40E_AQC_PFC_IGNORE_SET 0x80
1434 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1438 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1440 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1441 * with no parameters
1444 /* TX scheduler 0x04xx */
1446 /* Almost all the indirect commands use
1447 * this generic struct to pass the SEID in param0
1449 struct i40e_aqc_tx_sched_ind {
1456 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1458 /* Several commands respond with a set of queue set handles */
1459 struct i40e_aqc_qs_handles_resp {
1460 __le16 qs_handles[8];
1463 /* Configure VSI BW limits (direct 0x0400) */
1464 struct i40e_aqc_configure_vsi_bw_limit {
1469 u8 max_credit; /* 0-3, limit = 2^max */
1473 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1475 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1476 * responds with i40e_aqc_qs_handles_resp
1478 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1481 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1483 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1484 __le16 tc_bw_max[2];
1488 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1490 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1491 * responds with i40e_aqc_qs_handles_resp
1493 struct i40e_aqc_configure_vsi_tc_bw_data {
1496 u8 tc_bw_credits[8];
1498 __le16 qs_handles[8];
1501 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1503 /* Query vsi bw configuration (indirect 0x0408) */
1504 struct i40e_aqc_query_vsi_bw_config_resp {
1506 u8 tc_suspended_bits;
1508 __le16 qs_handles[8];
1510 __le16 port_bw_limit;
1512 u8 max_bw; /* 0-3, limit = 2^max */
1516 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1518 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1519 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1522 u8 share_credits[8];
1525 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1526 __le16 tc_bw_max[2];
1529 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1531 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1532 struct i40e_aqc_configure_switching_comp_bw_limit {
1537 u8 max_bw; /* 0-3, limit = 2^max */
1541 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1543 /* Enable Physical Port ETS (indirect 0x0413)
1544 * Modify Physical Port ETS (indirect 0x0414)
1545 * Disable Physical Port ETS (indirect 0x0415)
1547 struct i40e_aqc_configure_switching_comp_ets_data {
1551 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1552 u8 tc_strict_priority_flags;
1554 u8 tc_bw_share_credits[8];
1558 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1560 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1561 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1564 __le16 tc_bw_credit[8];
1566 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1567 __le16 tc_bw_max[2];
1571 I40E_CHECK_STRUCT_LEN(0x40,
1572 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1574 /* Configure Switching Component Bandwidth Allocation per Tc
1577 struct i40e_aqc_configure_switching_comp_bw_config_data {
1580 u8 absolute_credits; /* bool */
1581 u8 tc_bw_share_credits[8];
1585 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1587 /* Query Switching Component Configuration (indirect 0x0418) */
1588 struct i40e_aqc_query_switching_comp_ets_config_resp {
1591 __le16 port_bw_limit;
1593 u8 tc_bw_max; /* 0-3, limit = 2^max */
1597 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1599 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1600 struct i40e_aqc_query_port_ets_config_resp {
1604 u8 tc_strict_priority_bits;
1606 u8 tc_bw_share_credits[8];
1607 __le16 tc_bw_limits[8];
1609 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1610 __le16 tc_bw_max[2];
1614 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1616 /* Query Switching Component Bandwidth Allocation per Traffic Type
1619 struct i40e_aqc_query_switching_comp_bw_config_resp {
1622 u8 absolute_credits_enable; /* bool */
1623 u8 tc_bw_share_credits[8];
1624 __le16 tc_bw_limits[8];
1626 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1627 __le16 tc_bw_max[2];
1630 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1632 /* Suspend/resume port TX traffic
1633 * (direct 0x041B and 0x041C) uses the generic SEID struct
1636 /* Configure partition BW
1639 struct i40e_aqc_configure_partition_bw_data {
1640 __le16 pf_valid_bits;
1641 u8 min_bw[16]; /* guaranteed bandwidth */
1642 u8 max_bw[16]; /* bandwidth limit */
1645 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1647 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1649 /* set in param0 for get phy abilities to report qualified modules */
1650 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1651 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1653 enum i40e_aq_phy_type {
1654 I40E_PHY_TYPE_SGMII = 0x0,
1655 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1656 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1657 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1658 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1659 I40E_PHY_TYPE_XAUI = 0x5,
1660 I40E_PHY_TYPE_XFI = 0x6,
1661 I40E_PHY_TYPE_SFI = 0x7,
1662 I40E_PHY_TYPE_XLAUI = 0x8,
1663 I40E_PHY_TYPE_XLPPI = 0x9,
1664 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1665 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1666 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1667 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1668 I40E_PHY_TYPE_100BASE_TX = 0x11,
1669 I40E_PHY_TYPE_1000BASE_T = 0x12,
1670 I40E_PHY_TYPE_10GBASE_T = 0x13,
1671 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1672 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1673 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1674 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1675 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1676 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1677 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1678 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1679 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1680 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1681 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1682 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1683 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1684 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1685 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1689 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1690 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1691 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1692 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1693 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1694 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1696 enum i40e_aq_link_speed {
1697 I40E_LINK_SPEED_UNKNOWN = 0,
1698 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1699 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1700 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1701 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1702 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT),
1703 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT),
1706 struct i40e_aqc_module_desc {
1714 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1716 struct i40e_aq_get_phy_abilities_resp {
1717 __le32 phy_type; /* bitmap using the above enum for offsets */
1718 u8 link_speed; /* bitmap using the above enum bit patterns */
1720 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1721 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1722 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1723 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1724 #define I40E_AQ_PHY_AN_ENABLED 0x10
1725 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1726 __le16 eee_capability;
1727 #define I40E_AQ_EEE_100BASE_TX 0x0002
1728 #define I40E_AQ_EEE_1000BASE_T 0x0004
1729 #define I40E_AQ_EEE_10GBASE_T 0x0008
1730 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1731 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1732 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1735 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1739 u8 qualified_module_count;
1740 #define I40E_AQ_PHY_MAX_QMS 16
1741 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1744 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1746 /* Set PHY Config (direct 0x0601) */
1747 struct i40e_aq_set_phy_config { /* same bits as above in all */
1751 /* bits 0-2 use the values from get_phy_abilities_resp */
1752 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1753 #define I40E_AQ_PHY_ENABLE_AN 0x10
1754 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1755 __le16 eee_capability;
1761 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1763 /* Set MAC Config command data structure (direct 0x0603) */
1764 struct i40e_aq_set_mac_config {
1765 __le16 max_frame_size;
1767 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1768 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1769 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1770 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1771 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1772 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1773 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1774 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1775 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1776 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1777 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1778 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1779 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1780 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1781 u8 tx_timer_priority; /* bitmap */
1782 __le16 tx_timer_value;
1783 __le16 fc_refresh_threshold;
1787 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1789 /* Restart Auto-Negotiation (direct 0x605) */
1790 struct i40e_aqc_set_link_restart_an {
1792 #define I40E_AQ_PHY_RESTART_AN 0x02
1793 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1797 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1799 /* Get Link Status cmd & response data structure (direct 0x0607) */
1800 struct i40e_aqc_get_link_status {
1801 __le16 command_flags; /* only field set on command */
1802 #define I40E_AQ_LSE_MASK 0x3
1803 #define I40E_AQ_LSE_NOP 0x0
1804 #define I40E_AQ_LSE_DISABLE 0x2
1805 #define I40E_AQ_LSE_ENABLE 0x3
1806 /* only response uses this flag */
1807 #define I40E_AQ_LSE_IS_ENABLED 0x1
1808 u8 phy_type; /* i40e_aq_phy_type */
1809 u8 link_speed; /* i40e_aq_link_speed */
1811 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1812 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1813 #define I40E_AQ_LINK_FAULT 0x02
1814 #define I40E_AQ_LINK_FAULT_TX 0x04
1815 #define I40E_AQ_LINK_FAULT_RX 0x08
1816 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1817 #define I40E_AQ_LINK_UP_PORT 0x20
1818 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1819 #define I40E_AQ_SIGNAL_DETECT 0x80
1821 #define I40E_AQ_AN_COMPLETED 0x01
1822 #define I40E_AQ_LP_AN_ABILITY 0x02
1823 #define I40E_AQ_PD_FAULT 0x04
1824 #define I40E_AQ_FEC_EN 0x08
1825 #define I40E_AQ_PHY_LOW_POWER 0x10
1826 #define I40E_AQ_LINK_PAUSE_TX 0x20
1827 #define I40E_AQ_LINK_PAUSE_RX 0x40
1828 #define I40E_AQ_QUALIFIED_MODULE 0x80
1830 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1831 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1832 #define I40E_AQ_LINK_TX_SHIFT 0x02
1833 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1834 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1835 #define I40E_AQ_LINK_TX_DRAINED 0x01
1836 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1837 #define I40E_AQ_LINK_FORCED_40G 0x10
1838 /* 25G Error Codes */
1839 #define I40E_AQ_25G_NO_ERR 0X00
1840 #define I40E_AQ_25G_NOT_PRESENT 0X01
1841 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
1842 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
1843 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
1844 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
1845 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1846 __le16 max_frame_size;
1848 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1849 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1850 u8 external_power_ability;
1851 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
1852 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
1853 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
1854 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
1858 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1860 /* Set event mask command (direct 0x613) */
1861 struct i40e_aqc_set_phy_int_mask {
1864 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1865 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1866 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1867 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1868 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1869 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1870 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1871 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1872 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1876 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1878 /* Get Local AN advt register (direct 0x0614)
1879 * Set Local AN advt register (direct 0x0615)
1880 * Get Link Partner AN advt register (direct 0x0616)
1882 struct i40e_aqc_an_advt_reg {
1883 __le32 local_an_reg0;
1884 __le16 local_an_reg1;
1888 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1890 /* Set Loopback mode (0x0618) */
1891 struct i40e_aqc_set_lb_mode {
1893 #define I40E_AQ_LB_PHY_LOCAL 0x01
1894 #define I40E_AQ_LB_PHY_REMOTE 0x02
1895 #define I40E_AQ_LB_MAC_LOCAL 0x04
1899 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1901 /* Set PHY Debug command (0x0622) */
1902 struct i40e_aqc_set_phy_debug {
1904 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1905 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1906 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1907 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1908 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1909 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1910 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1911 /* Disable link manageability on a single port */
1912 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1913 /* Disable link manageability on all ports needs both bits 4 and 5 */
1914 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
1918 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1920 enum i40e_aq_phy_reg_type {
1921 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1922 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1923 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1926 /* Run PHY Activity (0x0626) */
1927 struct i40e_aqc_run_phy_activity {
1936 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1938 /* NVM Read command (indirect 0x0701)
1939 * NVM Erase commands (direct 0x0702)
1940 * NVM Update commands (indirect 0x0703)
1942 struct i40e_aqc_nvm_update {
1944 #define I40E_AQ_NVM_LAST_CMD 0x01
1945 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1953 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1955 /* NVM Config Read (indirect 0x0704) */
1956 struct i40e_aqc_nvm_config_read {
1958 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1959 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1960 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
1961 __le16 element_count;
1962 __le16 element_id; /* Feature/field ID */
1963 __le16 element_id_msw; /* MSWord of field ID */
1964 __le32 address_high;
1968 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1970 /* NVM Config Write (indirect 0x0705) */
1971 struct i40e_aqc_nvm_config_write {
1973 __le16 element_count;
1975 __le32 address_high;
1979 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1981 /* Used for 0x0704 as well as for 0x0705 commands */
1982 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1983 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
1984 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1985 #define I40E_AQ_ANVM_FEATURE 0
1986 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
1987 struct i40e_aqc_nvm_config_data_feature {
1989 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1990 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1991 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
1992 __le16 feature_options;
1993 __le16 feature_selection;
1996 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1998 struct i40e_aqc_nvm_config_data_immediate_field {
2001 __le16 field_options;
2005 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2007 /* OEM Post Update (indirect 0x0720)
2008 * no command data struct used
2010 struct i40e_aqc_nvm_oem_post_update {
2011 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2016 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2018 struct i40e_aqc_nvm_oem_post_update_buffer {
2025 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2027 /* Thermal Sensor (indirect 0x0721)
2028 * read or set thermal sensor configs and values
2029 * takes a sensor and command specific data buffer, not detailed here
2031 struct i40e_aqc_thermal_sensor {
2033 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2034 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2035 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2041 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2043 /* Send to PF command (indirect 0x0801) id is only used by PF
2044 * Send to VF command (indirect 0x0802) id is only used by PF
2045 * Send to Peer PF command (indirect 0x0803)
2047 struct i40e_aqc_pf_vf_message {
2054 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2056 /* Alternate structure */
2058 /* Direct write (direct 0x0900)
2059 * Direct read (direct 0x0902)
2061 struct i40e_aqc_alternate_write {
2068 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2070 /* Indirect write (indirect 0x0901)
2071 * Indirect read (indirect 0x0903)
2074 struct i40e_aqc_alternate_ind_write {
2081 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2083 /* Done alternate write (direct 0x0904)
2086 struct i40e_aqc_alternate_write_done {
2088 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2089 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2090 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2091 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2095 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2097 /* Set OEM mode (direct 0x0905) */
2098 struct i40e_aqc_alternate_set_mode {
2100 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2101 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2105 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2107 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2109 /* async events 0x10xx */
2111 /* Lan Queue Overflow Event (direct, 0x1001) */
2112 struct i40e_aqc_lan_overflow {
2113 __le32 prtdcb_rupto;
2118 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2120 /* Get LLDP MIB (indirect 0x0A00) */
2121 struct i40e_aqc_lldp_get_mib {
2124 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2125 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2126 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2127 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2128 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2129 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2130 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2131 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2132 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2133 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2134 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2142 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2144 /* Configure LLDP MIB Change Event (direct 0x0A01)
2145 * also used for the event (with type in the command field)
2147 struct i40e_aqc_lldp_update_mib {
2149 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2150 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2156 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2158 /* Add LLDP TLV (indirect 0x0A02)
2159 * Delete LLDP TLV (indirect 0x0A04)
2161 struct i40e_aqc_lldp_add_tlv {
2162 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2170 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2172 /* Update LLDP TLV (indirect 0x0A03) */
2173 struct i40e_aqc_lldp_update_tlv {
2174 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2183 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2185 /* Stop LLDP (direct 0x0A05) */
2186 struct i40e_aqc_lldp_stop {
2188 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2189 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2193 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2195 /* Start LLDP (direct 0x0A06) */
2197 struct i40e_aqc_lldp_start {
2199 #define I40E_AQ_LLDP_AGENT_START 0x1
2203 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2205 /* Get CEE DCBX Oper Config (0x0A07)
2206 * uses the generic descriptor struct
2207 * returns below as indirect response
2210 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2211 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2212 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2213 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2214 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2215 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2217 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2218 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2219 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2220 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2221 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2222 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2223 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2224 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2225 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2226 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2227 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2228 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2230 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2231 * word boundary layout issues, which the Linux compilers silently deal
2232 * with by adding padding, making the actual struct larger than designed.
2233 * However, the FW compiler for the NIC is less lenient and complains
2234 * about the struct. Hence, the struct defined here has an extra byte in
2235 * fields reserved3 and reserved4 to directly acknowledge that padding,
2236 * and the new length is used in the length check macro.
2238 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2246 __le16 oper_app_prio;
2251 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2253 struct i40e_aqc_get_cee_dcb_cfg_resp {
2258 __le16 oper_app_prio;
2263 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2265 /* Set Local LLDP MIB (indirect 0x0A08)
2266 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2268 struct i40e_aqc_lldp_set_local_mib {
2269 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2270 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2271 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2272 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2273 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2274 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2275 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2276 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2281 __le32 address_high;
2285 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2287 struct i40e_aqc_lldp_set_local_mib_resp {
2288 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
2293 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
2295 /* Stop/Start LLDP Agent (direct 0x0A09)
2296 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2298 struct i40e_aqc_lldp_stop_start_specific_agent {
2299 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2300 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2301 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2306 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2308 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2309 struct i40e_aqc_add_udp_tunnel {
2313 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2314 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2315 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2316 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2320 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2322 struct i40e_aqc_add_udp_tunnel_completion {
2324 u8 filter_entry_index;
2326 #define I40E_AQC_SINGLE_PF 0x0
2327 #define I40E_AQC_MULTIPLE_PFS 0x1
2332 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2334 /* remove UDP Tunnel command (0x0B01) */
2335 struct i40e_aqc_remove_udp_tunnel {
2337 u8 index; /* 0 to 15 */
2341 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2343 struct i40e_aqc_del_udp_tunnel_completion {
2345 u8 index; /* 0 to 15 */
2347 u8 total_filters_used;
2351 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2354 struct i40e_aqc_get_set_rss_key {
2355 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2356 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2357 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2358 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2365 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2367 struct i40e_aqc_get_set_rss_key_data {
2368 u8 standard_rss_key[0x28];
2369 u8 extended_hash_key[0xc];
2372 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2374 struct i40e_aqc_get_set_rss_lut {
2375 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2376 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2377 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2378 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2380 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2381 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2382 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2384 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2385 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2392 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2395 /* tunnel key structure 0x0B10 */
2397 struct i40e_aqc_tunnel_key_structure {
2400 u8 key1_len; /* 0 to 15 */
2401 u8 key2_len; /* 0 to 15 */
2403 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2404 /* response flags */
2405 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2406 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2407 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2408 u8 network_key_index;
2409 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2410 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2411 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2412 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2416 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2418 /* OEM mode commands (direct 0xFE0x) */
2419 struct i40e_aqc_oem_param_change {
2421 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2422 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2423 #define I40E_AQ_OEM_PARAM_MAC 2
2424 __le32 param_value1;
2425 __le16 param_value2;
2429 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2431 struct i40e_aqc_oem_state_change {
2433 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2434 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2438 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2440 /* Initialize OCSD (0xFE02, direct) */
2441 struct i40e_aqc_opc_oem_ocsd_initialize {
2444 __le32 ocsd_memory_block_addr_high;
2445 __le32 ocsd_memory_block_addr_low;
2446 __le32 requested_update_interval;
2449 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2451 /* Initialize OCBB (0xFE03, direct) */
2452 struct i40e_aqc_opc_oem_ocbb_initialize {
2455 __le32 ocbb_memory_block_addr_high;
2456 __le32 ocbb_memory_block_addr_low;
2460 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2462 /* debug commands */
2464 /* get device id (0xFF00) uses the generic structure */
2466 /* set test more (0xFF01, internal) */
2468 struct i40e_acq_set_test_mode {
2470 #define I40E_AQ_TEST_PARTIAL 0
2471 #define I40E_AQ_TEST_FULL 1
2472 #define I40E_AQ_TEST_NVM 2
2475 #define I40E_AQ_TEST_OPEN 0
2476 #define I40E_AQ_TEST_CLOSE 1
2477 #define I40E_AQ_TEST_INC 2
2479 __le32 address_high;
2483 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2485 /* Debug Read Register command (0xFF03)
2486 * Debug Write Register command (0xFF04)
2488 struct i40e_aqc_debug_reg_read_write {
2495 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2497 /* Scatter/gather Reg Read (indirect 0xFF05)
2498 * Scatter/gather Reg Write (indirect 0xFF06)
2501 /* i40e_aq_desc is used for the command */
2502 struct i40e_aqc_debug_reg_sg_element_data {
2507 /* Debug Modify register (direct 0xFF07) */
2508 struct i40e_aqc_debug_modify_reg {
2515 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2517 /* dump internal data (0xFF08, indirect) */
2519 #define I40E_AQ_CLUSTER_ID_AUX 0
2520 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2521 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2522 #define I40E_AQ_CLUSTER_ID_HMC 3
2523 #define I40E_AQ_CLUSTER_ID_MAC0 4
2524 #define I40E_AQ_CLUSTER_ID_MAC1 5
2525 #define I40E_AQ_CLUSTER_ID_MAC2 6
2526 #define I40E_AQ_CLUSTER_ID_MAC3 7
2527 #define I40E_AQ_CLUSTER_ID_DCB 8
2528 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2529 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2530 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2532 struct i40e_aqc_debug_dump_internals {
2537 __le32 address_high;
2541 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2543 struct i40e_aqc_debug_modify_internals {
2545 u8 cluster_specific_params[7];
2546 __le32 address_high;
2550 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2552 #endif /* _I40E_ADMINQ_CMD_H_ */