1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #ifndef _I40E_ADMINQ_CMD_H_
35 #define _I40E_ADMINQ_CMD_H_
37 /* This header file defines the i40e Admin Queue commands and is shared between
38 * i40e Firmware and Software.
40 * This file needs to comply with the Linux Kernel coding style.
43 #define I40E_FW_API_VERSION_MAJOR 0x0001
44 #define I40E_FW_API_VERSION_MINOR 0x0005
70 /* Flags sub-structure
71 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
72 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
75 /* command flags and offsets*/
76 #define I40E_AQ_FLAG_DD_SHIFT 0
77 #define I40E_AQ_FLAG_CMP_SHIFT 1
78 #define I40E_AQ_FLAG_ERR_SHIFT 2
79 #define I40E_AQ_FLAG_VFE_SHIFT 3
80 #define I40E_AQ_FLAG_LB_SHIFT 9
81 #define I40E_AQ_FLAG_RD_SHIFT 10
82 #define I40E_AQ_FLAG_VFC_SHIFT 11
83 #define I40E_AQ_FLAG_BUF_SHIFT 12
84 #define I40E_AQ_FLAG_SI_SHIFT 13
85 #define I40E_AQ_FLAG_EI_SHIFT 14
86 #define I40E_AQ_FLAG_FE_SHIFT 15
88 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
89 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
90 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
91 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
92 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
93 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
94 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
95 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
96 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
97 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
98 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
101 enum i40e_admin_queue_err {
102 I40E_AQ_RC_OK = 0, /* success */
103 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
104 I40E_AQ_RC_ENOENT = 2, /* No such element */
105 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
106 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
107 I40E_AQ_RC_EIO = 5, /* I/O error */
108 I40E_AQ_RC_ENXIO = 6, /* No such resource */
109 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
110 I40E_AQ_RC_EAGAIN = 8, /* Try again */
111 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
112 I40E_AQ_RC_EACCES = 10, /* Permission denied */
113 I40E_AQ_RC_EFAULT = 11, /* Bad address */
114 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
115 I40E_AQ_RC_EEXIST = 13, /* object already exists */
116 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
117 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
118 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
119 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
120 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
121 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
122 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
123 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
124 I40E_AQ_RC_EFBIG = 22, /* File too large */
127 /* Admin Queue command opcodes */
128 enum i40e_admin_queue_opc {
130 i40e_aqc_opc_get_version = 0x0001,
131 i40e_aqc_opc_driver_version = 0x0002,
132 i40e_aqc_opc_queue_shutdown = 0x0003,
133 i40e_aqc_opc_set_pf_context = 0x0004,
135 /* resource ownership */
136 i40e_aqc_opc_request_resource = 0x0008,
137 i40e_aqc_opc_release_resource = 0x0009,
139 i40e_aqc_opc_list_func_capabilities = 0x000A,
140 i40e_aqc_opc_list_dev_capabilities = 0x000B,
143 i40e_aqc_opc_set_proxy_config = 0x0104,
144 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
147 i40e_aqc_opc_mac_address_read = 0x0107,
148 i40e_aqc_opc_mac_address_write = 0x0108,
151 i40e_aqc_opc_clear_pxe_mode = 0x0110,
154 i40e_aqc_opc_set_wol_filter = 0x0120,
155 i40e_aqc_opc_get_wake_reason = 0x0121,
156 i40e_aqc_opc_clear_all_wol_filters = 0x025E,
158 /* internal switch commands */
159 i40e_aqc_opc_get_switch_config = 0x0200,
160 i40e_aqc_opc_add_statistics = 0x0201,
161 i40e_aqc_opc_remove_statistics = 0x0202,
162 i40e_aqc_opc_set_port_parameters = 0x0203,
163 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
164 i40e_aqc_opc_set_switch_config = 0x0205,
165 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
166 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
168 i40e_aqc_opc_add_vsi = 0x0210,
169 i40e_aqc_opc_update_vsi_parameters = 0x0211,
170 i40e_aqc_opc_get_vsi_parameters = 0x0212,
172 i40e_aqc_opc_add_pv = 0x0220,
173 i40e_aqc_opc_update_pv_parameters = 0x0221,
174 i40e_aqc_opc_get_pv_parameters = 0x0222,
176 i40e_aqc_opc_add_veb = 0x0230,
177 i40e_aqc_opc_update_veb_parameters = 0x0231,
178 i40e_aqc_opc_get_veb_parameters = 0x0232,
180 i40e_aqc_opc_delete_element = 0x0243,
182 i40e_aqc_opc_add_macvlan = 0x0250,
183 i40e_aqc_opc_remove_macvlan = 0x0251,
184 i40e_aqc_opc_add_vlan = 0x0252,
185 i40e_aqc_opc_remove_vlan = 0x0253,
186 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
187 i40e_aqc_opc_add_tag = 0x0255,
188 i40e_aqc_opc_remove_tag = 0x0256,
189 i40e_aqc_opc_add_multicast_etag = 0x0257,
190 i40e_aqc_opc_remove_multicast_etag = 0x0258,
191 i40e_aqc_opc_update_tag = 0x0259,
192 i40e_aqc_opc_add_control_packet_filter = 0x025A,
193 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
194 i40e_aqc_opc_add_cloud_filters = 0x025C,
195 i40e_aqc_opc_remove_cloud_filters = 0x025D,
196 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
198 i40e_aqc_opc_add_mirror_rule = 0x0260,
199 i40e_aqc_opc_delete_mirror_rule = 0x0261,
202 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
203 i40e_aqc_opc_dcb_updated = 0x0302,
206 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
207 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
208 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
209 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
210 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
211 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
213 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
214 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
215 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
216 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
217 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
218 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
219 i40e_aqc_opc_query_port_ets_config = 0x0419,
220 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
221 i40e_aqc_opc_suspend_port_tx = 0x041B,
222 i40e_aqc_opc_resume_port_tx = 0x041C,
223 i40e_aqc_opc_configure_partition_bw = 0x041D,
225 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
226 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
229 i40e_aqc_opc_get_phy_abilities = 0x0600,
230 i40e_aqc_opc_set_phy_config = 0x0601,
231 i40e_aqc_opc_set_mac_config = 0x0603,
232 i40e_aqc_opc_set_link_restart_an = 0x0605,
233 i40e_aqc_opc_get_link_status = 0x0607,
234 i40e_aqc_opc_set_phy_int_mask = 0x0613,
235 i40e_aqc_opc_get_local_advt_reg = 0x0614,
236 i40e_aqc_opc_set_local_advt_reg = 0x0615,
237 i40e_aqc_opc_get_partner_advt = 0x0616,
238 i40e_aqc_opc_set_lb_modes = 0x0618,
239 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
240 i40e_aqc_opc_set_phy_debug = 0x0622,
241 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
242 i40e_aqc_opc_run_phy_activity = 0x0626,
245 i40e_aqc_opc_nvm_read = 0x0701,
246 i40e_aqc_opc_nvm_erase = 0x0702,
247 i40e_aqc_opc_nvm_update = 0x0703,
248 i40e_aqc_opc_nvm_config_read = 0x0704,
249 i40e_aqc_opc_nvm_config_write = 0x0705,
250 i40e_aqc_opc_oem_post_update = 0x0720,
251 i40e_aqc_opc_thermal_sensor = 0x0721,
253 /* virtualization commands */
254 i40e_aqc_opc_send_msg_to_pf = 0x0801,
255 i40e_aqc_opc_send_msg_to_vf = 0x0802,
256 i40e_aqc_opc_send_msg_to_peer = 0x0803,
258 /* alternate structure */
259 i40e_aqc_opc_alternate_write = 0x0900,
260 i40e_aqc_opc_alternate_write_indirect = 0x0901,
261 i40e_aqc_opc_alternate_read = 0x0902,
262 i40e_aqc_opc_alternate_read_indirect = 0x0903,
263 i40e_aqc_opc_alternate_write_done = 0x0904,
264 i40e_aqc_opc_alternate_set_mode = 0x0905,
265 i40e_aqc_opc_alternate_clear_port = 0x0906,
268 i40e_aqc_opc_lldp_get_mib = 0x0A00,
269 i40e_aqc_opc_lldp_update_mib = 0x0A01,
270 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
271 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
272 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
273 i40e_aqc_opc_lldp_stop = 0x0A05,
274 i40e_aqc_opc_lldp_start = 0x0A06,
275 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
276 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
277 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
279 /* Tunnel commands */
280 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
281 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
282 i40e_aqc_opc_set_rss_key = 0x0B02,
283 i40e_aqc_opc_set_rss_lut = 0x0B03,
284 i40e_aqc_opc_get_rss_key = 0x0B04,
285 i40e_aqc_opc_get_rss_lut = 0x0B05,
288 i40e_aqc_opc_event_lan_overflow = 0x1001,
291 i40e_aqc_opc_oem_parameter_change = 0xFE00,
292 i40e_aqc_opc_oem_device_status_change = 0xFE01,
293 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
294 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
297 i40e_aqc_opc_debug_read_reg = 0xFF03,
298 i40e_aqc_opc_debug_write_reg = 0xFF04,
299 i40e_aqc_opc_debug_modify_reg = 0xFF07,
300 i40e_aqc_opc_debug_dump_internals = 0xFF08,
303 /* command structures and indirect data structures */
305 /* Structure naming conventions:
306 * - no suffix for direct command descriptor structures
307 * - _data for indirect sent data
308 * - _resp for indirect return data (data which is both will use _data)
309 * - _completion for direct return data
310 * - _element_ for repeated elements (may also be _data or _resp)
312 * Command structures are expected to overlay the params.raw member of the basic
313 * descriptor, and as such cannot exceed 16 bytes in length.
316 /* This macro is used to generate a compilation error if a structure
317 * is not exactly the correct length. It gives a divide by zero error if the
318 * structure is not of the correct size, otherwise it creates an enum that is
321 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
322 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
324 /* This macro is used extensively to ensure that command structures are 16
325 * bytes in length as they have to map to the raw array of that size.
327 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
329 /* internal (0x00XX) commands */
331 /* Get version (direct 0x0001) */
332 struct i40e_aqc_get_version {
341 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
343 /* Send driver version (indirect 0x0002) */
344 struct i40e_aqc_driver_version {
348 u8 driver_subbuild_ver;
354 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
356 /* Queue Shutdown (direct 0x0003) */
357 struct i40e_aqc_queue_shutdown {
358 __le32 driver_unloading;
359 #define I40E_AQ_DRIVER_UNLOADING 0x1
363 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
365 /* Set PF context (0x0004, direct) */
366 struct i40e_aqc_set_pf_context {
371 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
373 /* Request resource ownership (direct 0x0008)
374 * Release resource ownership (direct 0x0009)
376 #define I40E_AQ_RESOURCE_NVM 1
377 #define I40E_AQ_RESOURCE_SDP 2
378 #define I40E_AQ_RESOURCE_ACCESS_READ 1
379 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
380 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
381 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
383 struct i40e_aqc_request_resource {
387 __le32 resource_number;
391 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
393 /* Get function capabilities (indirect 0x000A)
394 * Get device capabilities (indirect 0x000B)
396 struct i40e_aqc_list_capabilites {
398 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
406 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
408 struct i40e_aqc_list_capabilities_element_resp {
420 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
421 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
422 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
423 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
424 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
425 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
426 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
427 #define I40E_AQ_CAP_ID_SRIOV 0x0012
428 #define I40E_AQ_CAP_ID_VF 0x0013
429 #define I40E_AQ_CAP_ID_VMDQ 0x0014
430 #define I40E_AQ_CAP_ID_8021QBG 0x0015
431 #define I40E_AQ_CAP_ID_8021QBR 0x0016
432 #define I40E_AQ_CAP_ID_VSI 0x0017
433 #define I40E_AQ_CAP_ID_DCB 0x0018
434 #define I40E_AQ_CAP_ID_FCOE 0x0021
435 #define I40E_AQ_CAP_ID_ISCSI 0x0022
436 #define I40E_AQ_CAP_ID_RSS 0x0040
437 #define I40E_AQ_CAP_ID_RXQ 0x0041
438 #define I40E_AQ_CAP_ID_TXQ 0x0042
439 #define I40E_AQ_CAP_ID_MSIX 0x0043
440 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
441 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
442 #define I40E_AQ_CAP_ID_1588 0x0046
443 #define I40E_AQ_CAP_ID_IWARP 0x0051
444 #define I40E_AQ_CAP_ID_LED 0x0061
445 #define I40E_AQ_CAP_ID_SDP 0x0062
446 #define I40E_AQ_CAP_ID_MDIO 0x0063
447 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
448 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
449 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
450 #define I40E_AQ_CAP_ID_CEM 0x00F2
452 /* Set CPPM Configuration (direct 0x0103) */
453 struct i40e_aqc_cppm_configuration {
454 __le16 command_flags;
455 #define I40E_AQ_CPPM_EN_LTRC 0x0800
456 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
457 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
458 #define I40E_AQ_CPPM_EN_HPTC 0x4000
459 #define I40E_AQ_CPPM_EN_DMARC 0x8000
468 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
470 /* Set ARP Proxy command / response (indirect 0x0104) */
471 struct i40e_aqc_arp_proxy_data {
472 __le16 command_flags;
473 #define I40E_AQ_ARP_INIT_IPV4 0x0800
474 #define I40E_AQ_ARP_UNSUP_CTL 0x1000
475 #define I40E_AQ_ARP_ENA 0x2000
476 #define I40E_AQ_ARP_ADD_IPV4 0x4000
477 #define I40E_AQ_ARP_DEL_IPV4 0x8000
479 __le32 enabled_offloads;
480 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
481 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
487 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
489 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
490 struct i40e_aqc_ns_proxy_data {
491 __le16 table_idx_mac_addr_0;
492 __le16 table_idx_mac_addr_1;
493 __le16 table_idx_ipv6_0;
494 __le16 table_idx_ipv6_1;
496 #define I40E_AQ_NS_PROXY_ADD_0 0x0001
497 #define I40E_AQ_NS_PROXY_DEL_0 0x0002
498 #define I40E_AQ_NS_PROXY_ADD_1 0x0004
499 #define I40E_AQ_NS_PROXY_DEL_1 0x0008
500 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
501 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
502 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
503 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
504 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
505 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
506 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
507 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
508 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
511 u8 local_mac_addr[6];
512 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
516 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
518 /* Manage LAA Command (0x0106) - obsolete */
519 struct i40e_aqc_mng_laa {
520 __le16 command_flags;
521 #define I40E_AQ_LAA_FLAG_WR 0x8000
528 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
530 /* Manage MAC Address Read Command (indirect 0x0107) */
531 struct i40e_aqc_mac_address_read {
532 __le16 command_flags;
533 #define I40E_AQC_LAN_ADDR_VALID 0x10
534 #define I40E_AQC_SAN_ADDR_VALID 0x20
535 #define I40E_AQC_PORT_ADDR_VALID 0x40
536 #define I40E_AQC_WOL_ADDR_VALID 0x80
537 #define I40E_AQC_MC_MAG_EN_VALID 0x100
538 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200
539 #define I40E_AQC_ADDR_VALID_MASK 0x3F0
545 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
547 struct i40e_aqc_mac_address_read_data {
554 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
556 /* Manage MAC Address Write Command (0x0108) */
557 struct i40e_aqc_mac_address_write {
558 __le16 command_flags;
559 #define I40E_AQC_MC_MAG_EN 0x0100
560 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
561 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
562 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
563 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
564 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
565 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
572 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
574 /* PXE commands (0x011x) */
576 /* Clear PXE Command and response (direct 0x0110) */
577 struct i40e_aqc_clear_pxe {
582 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
584 /* Set WoL Filter (0x0120) */
586 struct i40e_aqc_set_wol_filter {
588 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
589 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
590 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
591 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
593 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
594 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
595 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
597 #define I40E_AQC_SET_WOL_FILTER 0x8000
598 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
599 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000
600 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
601 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
603 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
604 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
610 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
612 struct i40e_aqc_set_wol_filter_data {
617 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
619 /* Get Wake Reason (0x0121) */
621 struct i40e_aqc_get_wake_reason_completion {
624 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
625 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
626 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
627 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
628 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
629 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
633 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
635 /* Switch configuration commands (0x02xx) */
637 /* Used by many indirect commands that only pass an seid and a buffer in the
640 struct i40e_aqc_switch_seid {
647 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
649 /* Get Switch Configuration command (indirect 0x0200)
650 * uses i40e_aqc_switch_seid for the descriptor
652 struct i40e_aqc_get_switch_config_header_resp {
658 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
660 struct i40e_aqc_switch_config_element_resp {
662 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
663 #define I40E_AQ_SW_ELEM_TYPE_PF 2
664 #define I40E_AQ_SW_ELEM_TYPE_VF 3
665 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
666 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
667 #define I40E_AQ_SW_ELEM_TYPE_PV 16
668 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
669 #define I40E_AQ_SW_ELEM_TYPE_PA 18
670 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
672 #define I40E_AQ_SW_ELEM_REV_1 1
675 __le16 downlink_seid;
678 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
679 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
680 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
685 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
687 /* Get Switch Configuration (indirect 0x0200)
688 * an array of elements are returned in the response buffer
689 * the first in the array is the header, remainder are elements
691 struct i40e_aqc_get_switch_config_resp {
692 struct i40e_aqc_get_switch_config_header_resp header;
693 struct i40e_aqc_switch_config_element_resp element[1];
696 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
698 /* Add Statistics (direct 0x0201)
699 * Remove Statistics (direct 0x0202)
701 struct i40e_aqc_add_remove_statistics {
708 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
710 /* Set Port Parameters command (direct 0x0203) */
711 struct i40e_aqc_set_port_parameters {
712 __le16 command_flags;
713 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
714 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
715 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
716 __le16 bad_frame_vsi;
717 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
718 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
719 __le16 default_seid; /* reserved for command */
723 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
725 /* Get Switch Resource Allocation (indirect 0x0204) */
726 struct i40e_aqc_get_switch_resource_alloc {
727 u8 num_entries; /* reserved for command */
733 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
735 /* expect an array of these structs in the response buffer */
736 struct i40e_aqc_switch_resource_alloc_element_resp {
738 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
739 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
740 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
741 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
742 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
743 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
744 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
745 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
746 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
747 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
748 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
749 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
750 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
751 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
752 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
753 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
754 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
755 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
756 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
761 __le16 total_unalloced;
765 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
767 /* Set Switch Configuration (direct 0x0205) */
768 struct i40e_aqc_set_switch_config {
770 /* flags used for both fields below */
771 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
772 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
777 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
779 /* Read Receive control registers (direct 0x0206)
780 * Write Receive control registers (direct 0x0207)
781 * used for accessing Rx control registers that can be
782 * slow and need special handling when under high Rx load
784 struct i40e_aqc_rx_ctl_reg_read_write {
791 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
793 /* Add VSI (indirect 0x0210)
794 * this indirect command uses struct i40e_aqc_vsi_properties_data
795 * as the indirect buffer (128 bytes)
797 * Update VSI (indirect 0x211)
798 * uses the same data structure as Add VSI
800 * Get VSI (indirect 0x0212)
801 * uses the same completion and data structure as Add VSI
803 struct i40e_aqc_add_get_update_vsi {
806 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
807 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
808 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
813 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
814 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
815 #define I40E_AQ_VSI_TYPE_VF 0x0
816 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
817 #define I40E_AQ_VSI_TYPE_PF 0x2
818 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
819 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
824 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
826 struct i40e_aqc_add_get_update_vsi_completion {
835 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
837 struct i40e_aqc_vsi_properties_data {
838 /* first 96 byte are written by SW */
839 __le16 valid_sections;
840 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
841 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
842 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
843 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
844 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
845 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
846 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
847 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
848 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
849 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
851 __le16 switch_id; /* 12bit id combined with flags below */
852 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
853 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
854 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
855 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
856 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
858 /* security section */
860 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
861 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
862 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
865 __le16 pvid; /* VLANS include priority bits */
868 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
869 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
870 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
871 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
872 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
873 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
874 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
875 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
876 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
877 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
878 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
879 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
880 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
881 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
882 u8 pvlan_reserved[3];
883 /* ingress egress up sections */
884 __le32 ingress_table; /* bitmap, 3 bits per up */
885 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
886 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
887 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
888 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
889 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
890 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
891 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
892 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
893 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
894 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
895 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
896 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
897 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
898 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
899 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
900 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
901 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
902 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
903 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
904 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
905 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
906 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
907 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
908 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
909 __le32 egress_table; /* same defines as for ingress table */
910 /* cascaded PV section */
913 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
914 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
915 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
916 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
917 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
918 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
919 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
920 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
921 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
923 /* queue mapping section */
924 __le16 mapping_flags;
925 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
926 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
927 __le16 queue_mapping[16];
928 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
929 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
930 __le16 tc_mapping[8];
931 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
932 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
933 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
934 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
935 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
936 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
937 /* queueing option section */
938 u8 queueing_opt_flags;
939 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
940 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
941 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
942 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
943 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
944 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
945 u8 queueing_opt_reserved[3];
946 /* scheduler section */
949 /* outer up section */
950 __le32 outer_up_table; /* same structure and defines as ingress tbl */
952 /* last 32 bytes are written by FW */
954 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
955 __le16 stat_counter_idx;
957 u8 resp_reserved[12];
960 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
962 /* Add Port Virtualizer (direct 0x0220)
963 * also used for update PV (direct 0x0221) but only flags are used
964 * (IS_CTRL_PORT only works on add PV)
966 struct i40e_aqc_add_update_pv {
967 __le16 command_flags;
968 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
969 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
970 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
971 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
973 __le16 connected_seid;
977 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
979 struct i40e_aqc_add_update_pv_completion {
980 /* reserved for update; for add also encodes error if rc == ENOSPC */
982 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
983 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
984 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
985 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
989 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
991 /* Get PV Params (direct 0x0222)
992 * uses i40e_aqc_switch_seid for the descriptor
995 struct i40e_aqc_get_pv_params_completion {
998 __le16 pv_flags; /* same flags as add_pv */
999 #define I40E_AQC_GET_PV_PV_TYPE 0x1
1000 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1001 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1003 __le16 default_port_seid;
1006 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1008 /* Add VEB (direct 0x0230) */
1009 struct i40e_aqc_add_veb {
1011 __le16 downlink_seid;
1013 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1014 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1015 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1016 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1017 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1018 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1019 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1020 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1025 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1027 struct i40e_aqc_add_veb_completion {
1030 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1032 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1033 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1034 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1035 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1036 __le16 statistic_index;
1041 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1043 /* Get VEB Parameters (direct 0x0232)
1044 * uses i40e_aqc_switch_seid for the descriptor
1046 struct i40e_aqc_get_veb_parameters_completion {
1049 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1050 __le16 statistic_index;
1056 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1058 /* Delete Element (direct 0x0243)
1059 * uses the generic i40e_aqc_switch_seid
1062 /* Add MAC-VLAN (indirect 0x0250) */
1064 /* used for the command for most vlan commands */
1065 struct i40e_aqc_macvlan {
1066 __le16 num_addresses;
1068 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1069 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1070 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1071 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1076 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1078 /* indirect data for command and response */
1079 struct i40e_aqc_add_macvlan_element_data {
1083 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1084 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1085 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1086 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1087 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1088 __le16 queue_number;
1089 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1090 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1091 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1092 /* response section */
1094 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1095 #define I40E_AQC_MM_HASH_MATCH 0x02
1096 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1100 struct i40e_aqc_add_remove_macvlan_completion {
1101 __le16 perfect_mac_used;
1102 __le16 perfect_mac_free;
1103 __le16 unicast_hash_free;
1104 __le16 multicast_hash_free;
1109 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1111 /* Remove MAC-VLAN (indirect 0x0251)
1112 * uses i40e_aqc_macvlan for the descriptor
1113 * data points to an array of num_addresses of elements
1116 struct i40e_aqc_remove_macvlan_element_data {
1120 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1121 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1122 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1123 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1127 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1128 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1129 u8 reply_reserved[3];
1132 /* Add VLAN (indirect 0x0252)
1133 * Remove VLAN (indirect 0x0253)
1134 * use the generic i40e_aqc_macvlan for the command
1136 struct i40e_aqc_add_remove_vlan_element_data {
1139 /* flags for add VLAN */
1140 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1141 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1142 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1143 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1144 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1145 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1146 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1147 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1148 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1149 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1150 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1151 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1152 /* flags for remove VLAN */
1153 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1156 /* flags for add VLAN */
1157 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1158 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1159 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1160 /* flags for remove VLAN */
1161 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1162 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1166 struct i40e_aqc_add_remove_vlan_completion {
1174 /* Set VSI Promiscuous Modes (direct 0x0254) */
1175 struct i40e_aqc_set_vsi_promiscuous_modes {
1176 __le16 promiscuous_flags;
1178 /* flags used for both fields above */
1179 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1180 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1181 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1182 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1183 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1184 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1186 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1188 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1189 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1193 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1195 /* Add S/E-tag command (direct 0x0255)
1196 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1198 struct i40e_aqc_add_tag {
1200 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1202 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1203 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1204 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1206 __le16 queue_number;
1210 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1212 struct i40e_aqc_add_remove_tag_completion {
1218 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1220 /* Remove S/E-tag command (direct 0x0256)
1221 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1223 struct i40e_aqc_remove_tag {
1225 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1226 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1227 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1232 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1234 /* Add multicast E-Tag (direct 0x0257)
1235 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1236 * and no external data
1238 struct i40e_aqc_add_remove_mcast_etag {
1241 u8 num_unicast_etags;
1243 __le32 addr_high; /* address of array of 2-byte s-tags */
1247 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1249 struct i40e_aqc_add_remove_mcast_etag_completion {
1251 __le16 mcast_etags_used;
1252 __le16 mcast_etags_free;
1258 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1260 /* Update S/E-Tag (direct 0x0259) */
1261 struct i40e_aqc_update_tag {
1263 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1264 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1265 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1271 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1273 struct i40e_aqc_update_tag_completion {
1279 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1281 /* Add Control Packet filter (direct 0x025A)
1282 * Remove Control Packet filter (direct 0x025B)
1283 * uses the i40e_aqc_add_oveb_cloud,
1284 * and the generic direct completion structure
1286 struct i40e_aqc_add_remove_control_packet_filter {
1290 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1291 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1292 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1293 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1294 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1296 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1297 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1298 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1303 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1305 struct i40e_aqc_add_remove_control_packet_filter_completion {
1306 __le16 mac_etype_used;
1308 __le16 mac_etype_free;
1313 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1315 /* Add Cloud filters (indirect 0x025C)
1316 * Remove Cloud filters (indirect 0x025D)
1317 * uses the i40e_aqc_add_remove_cloud_filters,
1318 * and the generic indirect completion structure
1320 struct i40e_aqc_add_remove_cloud_filters {
1324 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1325 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1326 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1332 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1334 struct i40e_aqc_add_remove_cloud_filters_element_data {
1348 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1349 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1350 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1351 /* 0x0000 reserved */
1352 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1353 /* 0x0002 reserved */
1354 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1355 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1356 /* 0x0005 reserved */
1357 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1358 /* 0x0007 reserved */
1359 /* 0x0008 reserved */
1360 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1361 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1362 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1363 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1365 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1366 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1367 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1368 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1369 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1371 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1372 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1373 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1374 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1375 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1376 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1377 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1378 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1380 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1381 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1382 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1386 __le16 queue_number;
1387 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1388 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1389 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1391 /* response section */
1392 u8 allocation_result;
1393 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1394 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1395 u8 response_reserved[7];
1398 struct i40e_aqc_remove_cloud_filters_completion {
1399 __le16 perfect_ovlan_used;
1400 __le16 perfect_ovlan_free;
1407 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1409 /* Add Mirror Rule (indirect or direct 0x0260)
1410 * Delete Mirror Rule (indirect or direct 0x0261)
1411 * note: some rule types (4,5) do not use an external buffer.
1412 * take care to set the flags correctly.
1414 struct i40e_aqc_add_delete_mirror_rule {
1417 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1418 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1419 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1420 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1421 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1422 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1423 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1424 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1426 __le16 destination; /* VSI for add, rule id for delete */
1427 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1431 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1433 struct i40e_aqc_add_delete_mirror_rule_completion {
1435 __le16 rule_id; /* only used on add */
1436 __le16 mirror_rules_used;
1437 __le16 mirror_rules_free;
1442 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1446 /* PFC Ignore (direct 0x0301)
1447 * the command and response use the same descriptor structure
1449 struct i40e_aqc_pfc_ignore {
1451 u8 command_flags; /* unused on response */
1452 #define I40E_AQC_PFC_IGNORE_SET 0x80
1453 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1457 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1459 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1460 * with no parameters
1463 /* TX scheduler 0x04xx */
1465 /* Almost all the indirect commands use
1466 * this generic struct to pass the SEID in param0
1468 struct i40e_aqc_tx_sched_ind {
1475 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1477 /* Several commands respond with a set of queue set handles */
1478 struct i40e_aqc_qs_handles_resp {
1479 __le16 qs_handles[8];
1482 /* Configure VSI BW limits (direct 0x0400) */
1483 struct i40e_aqc_configure_vsi_bw_limit {
1488 u8 max_credit; /* 0-3, limit = 2^max */
1492 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1494 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1495 * responds with i40e_aqc_qs_handles_resp
1497 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1500 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1502 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1503 __le16 tc_bw_max[2];
1507 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1509 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1510 * responds with i40e_aqc_qs_handles_resp
1512 struct i40e_aqc_configure_vsi_tc_bw_data {
1515 u8 tc_bw_credits[8];
1517 __le16 qs_handles[8];
1520 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1522 /* Query vsi bw configuration (indirect 0x0408) */
1523 struct i40e_aqc_query_vsi_bw_config_resp {
1525 u8 tc_suspended_bits;
1527 __le16 qs_handles[8];
1529 __le16 port_bw_limit;
1531 u8 max_bw; /* 0-3, limit = 2^max */
1535 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1537 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1538 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1541 u8 share_credits[8];
1544 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1545 __le16 tc_bw_max[2];
1548 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1550 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1551 struct i40e_aqc_configure_switching_comp_bw_limit {
1556 u8 max_bw; /* 0-3, limit = 2^max */
1560 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1562 /* Enable Physical Port ETS (indirect 0x0413)
1563 * Modify Physical Port ETS (indirect 0x0414)
1564 * Disable Physical Port ETS (indirect 0x0415)
1566 struct i40e_aqc_configure_switching_comp_ets_data {
1570 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1571 u8 tc_strict_priority_flags;
1573 u8 tc_bw_share_credits[8];
1577 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1579 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1580 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1583 __le16 tc_bw_credit[8];
1585 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1586 __le16 tc_bw_max[2];
1590 I40E_CHECK_STRUCT_LEN(0x40,
1591 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1593 /* Configure Switching Component Bandwidth Allocation per Tc
1596 struct i40e_aqc_configure_switching_comp_bw_config_data {
1599 u8 absolute_credits; /* bool */
1600 u8 tc_bw_share_credits[8];
1604 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1606 /* Query Switching Component Configuration (indirect 0x0418) */
1607 struct i40e_aqc_query_switching_comp_ets_config_resp {
1610 __le16 port_bw_limit;
1612 u8 tc_bw_max; /* 0-3, limit = 2^max */
1616 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1618 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1619 struct i40e_aqc_query_port_ets_config_resp {
1623 u8 tc_strict_priority_bits;
1625 u8 tc_bw_share_credits[8];
1626 __le16 tc_bw_limits[8];
1628 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1629 __le16 tc_bw_max[2];
1633 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1635 /* Query Switching Component Bandwidth Allocation per Traffic Type
1638 struct i40e_aqc_query_switching_comp_bw_config_resp {
1641 u8 absolute_credits_enable; /* bool */
1642 u8 tc_bw_share_credits[8];
1643 __le16 tc_bw_limits[8];
1645 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1646 __le16 tc_bw_max[2];
1649 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1651 /* Suspend/resume port TX traffic
1652 * (direct 0x041B and 0x041C) uses the generic SEID struct
1655 /* Configure partition BW
1658 struct i40e_aqc_configure_partition_bw_data {
1659 __le16 pf_valid_bits;
1660 u8 min_bw[16]; /* guaranteed bandwidth */
1661 u8 max_bw[16]; /* bandwidth limit */
1664 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1666 /* Get and set the active HMC resource profile and status.
1667 * (direct 0x0500) and (direct 0x0501)
1669 struct i40e_aq_get_set_hmc_resource_profile {
1675 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1677 enum i40e_aq_hmc_profile {
1678 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1679 I40E_HMC_PROFILE_DEFAULT = 1,
1680 I40E_HMC_PROFILE_FAVOR_VF = 2,
1681 I40E_HMC_PROFILE_EQUAL = 3,
1684 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1686 /* set in param0 for get phy abilities to report qualified modules */
1687 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1688 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1690 enum i40e_aq_phy_type {
1691 I40E_PHY_TYPE_SGMII = 0x0,
1692 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1693 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1694 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1695 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1696 I40E_PHY_TYPE_XAUI = 0x5,
1697 I40E_PHY_TYPE_XFI = 0x6,
1698 I40E_PHY_TYPE_SFI = 0x7,
1699 I40E_PHY_TYPE_XLAUI = 0x8,
1700 I40E_PHY_TYPE_XLPPI = 0x9,
1701 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1702 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1703 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1704 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1705 I40E_PHY_TYPE_100BASE_TX = 0x11,
1706 I40E_PHY_TYPE_1000BASE_T = 0x12,
1707 I40E_PHY_TYPE_10GBASE_T = 0x13,
1708 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1709 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1710 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1711 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1712 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1713 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1714 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1715 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1716 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1717 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1718 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1719 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1720 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1721 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1722 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1726 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1727 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1728 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1729 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1730 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1731 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1733 enum i40e_aq_link_speed {
1734 I40E_LINK_SPEED_UNKNOWN = 0,
1735 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1736 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1737 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1738 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1739 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT),
1740 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT),
1743 struct i40e_aqc_module_desc {
1751 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1753 struct i40e_aq_get_phy_abilities_resp {
1754 __le32 phy_type; /* bitmap using the above enum for offsets */
1755 u8 link_speed; /* bitmap using the above enum bit patterns */
1757 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1758 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1759 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1760 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1761 #define I40E_AQ_PHY_AN_ENABLED 0x10
1762 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1763 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
1764 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
1765 __le16 eee_capability;
1766 #define I40E_AQ_EEE_100BASE_TX 0x0002
1767 #define I40E_AQ_EEE_1000BASE_T 0x0004
1768 #define I40E_AQ_EEE_10GBASE_T 0x0008
1769 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1770 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1771 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1774 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1776 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01
1777 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02
1778 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1779 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1780 u8 fec_cfg_curr_mod_ext_info;
1781 #define I40E_AQ_ENABLE_FEC_KR 0x01
1782 #define I40E_AQ_ENABLE_FEC_RS 0x02
1783 #define I40E_AQ_REQUEST_FEC_KR 0x04
1784 #define I40E_AQ_REQUEST_FEC_RS 0x08
1785 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
1787 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
1788 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5
1793 u8 qualified_module_count;
1794 #define I40E_AQ_PHY_MAX_QMS 16
1795 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1798 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1800 /* Set PHY Config (direct 0x0601) */
1801 struct i40e_aq_set_phy_config { /* same bits as above in all */
1805 /* bits 0-2 use the values from get_phy_abilities_resp */
1806 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1807 #define I40E_AQ_PHY_ENABLE_AN 0x10
1808 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1809 __le16 eee_capability;
1814 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1815 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
1816 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
1817 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
1818 #define I40E_AQ_SET_FEC_AUTO BIT(4)
1819 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1820 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1824 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1826 /* Set MAC Config command data structure (direct 0x0603) */
1827 struct i40e_aq_set_mac_config {
1828 __le16 max_frame_size;
1830 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1831 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1832 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1833 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1834 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1835 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1836 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1837 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1838 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1839 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1840 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1841 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1842 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1843 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1844 u8 tx_timer_priority; /* bitmap */
1845 __le16 tx_timer_value;
1846 __le16 fc_refresh_threshold;
1850 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1852 /* Restart Auto-Negotiation (direct 0x605) */
1853 struct i40e_aqc_set_link_restart_an {
1855 #define I40E_AQ_PHY_RESTART_AN 0x02
1856 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1860 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1862 /* Get Link Status cmd & response data structure (direct 0x0607) */
1863 struct i40e_aqc_get_link_status {
1864 __le16 command_flags; /* only field set on command */
1865 #define I40E_AQ_LSE_MASK 0x3
1866 #define I40E_AQ_LSE_NOP 0x0
1867 #define I40E_AQ_LSE_DISABLE 0x2
1868 #define I40E_AQ_LSE_ENABLE 0x3
1869 /* only response uses this flag */
1870 #define I40E_AQ_LSE_IS_ENABLED 0x1
1871 u8 phy_type; /* i40e_aq_phy_type */
1872 u8 link_speed; /* i40e_aq_link_speed */
1874 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1875 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1876 #define I40E_AQ_LINK_FAULT 0x02
1877 #define I40E_AQ_LINK_FAULT_TX 0x04
1878 #define I40E_AQ_LINK_FAULT_RX 0x08
1879 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1880 #define I40E_AQ_LINK_UP_PORT 0x20
1881 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1882 #define I40E_AQ_SIGNAL_DETECT 0x80
1884 #define I40E_AQ_AN_COMPLETED 0x01
1885 #define I40E_AQ_LP_AN_ABILITY 0x02
1886 #define I40E_AQ_PD_FAULT 0x04
1887 #define I40E_AQ_FEC_EN 0x08
1888 #define I40E_AQ_PHY_LOW_POWER 0x10
1889 #define I40E_AQ_LINK_PAUSE_TX 0x20
1890 #define I40E_AQ_LINK_PAUSE_RX 0x40
1891 #define I40E_AQ_QUALIFIED_MODULE 0x80
1893 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1894 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1895 #define I40E_AQ_LINK_TX_SHIFT 0x02
1896 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1897 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1898 #define I40E_AQ_LINK_TX_DRAINED 0x01
1899 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1900 #define I40E_AQ_LINK_FORCED_40G 0x10
1901 /* 25G Error Codes */
1902 #define I40E_AQ_25G_NO_ERR 0X00
1903 #define I40E_AQ_25G_NOT_PRESENT 0X01
1904 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
1905 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
1906 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
1907 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
1908 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1909 __le16 max_frame_size;
1911 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
1912 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
1913 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1914 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1916 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
1917 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
1918 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
1919 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
1920 #define I40E_AQ_PWR_CLASS_MASK 0x03
1924 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1926 /* Set event mask command (direct 0x613) */
1927 struct i40e_aqc_set_phy_int_mask {
1930 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1931 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1932 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1933 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1934 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1935 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1936 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1937 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1938 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1942 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1944 /* Get Local AN advt register (direct 0x0614)
1945 * Set Local AN advt register (direct 0x0615)
1946 * Get Link Partner AN advt register (direct 0x0616)
1948 struct i40e_aqc_an_advt_reg {
1949 __le32 local_an_reg0;
1950 __le16 local_an_reg1;
1954 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1956 /* Set Loopback mode (0x0618) */
1957 struct i40e_aqc_set_lb_mode {
1959 #define I40E_AQ_LB_PHY_LOCAL 0x01
1960 #define I40E_AQ_LB_PHY_REMOTE 0x02
1961 #define I40E_AQ_LB_MAC_LOCAL 0x04
1965 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1967 /* Set PHY Debug command (0x0622) */
1968 struct i40e_aqc_set_phy_debug {
1970 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1971 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1972 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1973 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1974 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1975 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1976 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1977 /* Disable link manageability on a single port */
1978 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1979 /* Disable link manageability on all ports needs both bits 4 and 5 */
1980 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
1984 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1986 enum i40e_aq_phy_reg_type {
1987 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1988 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1989 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1992 /* Run PHY Activity (0x0626) */
1993 struct i40e_aqc_run_phy_activity {
2002 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
2004 /* NVM Read command (indirect 0x0701)
2005 * NVM Erase commands (direct 0x0702)
2006 * NVM Update commands (indirect 0x0703)
2008 struct i40e_aqc_nvm_update {
2010 #define I40E_AQ_NVM_LAST_CMD 0x01
2011 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2019 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2021 /* NVM Config Read (indirect 0x0704) */
2022 struct i40e_aqc_nvm_config_read {
2024 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2025 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2026 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2027 __le16 element_count;
2028 __le16 element_id; /* Feature/field ID */
2029 __le16 element_id_msw; /* MSWord of field ID */
2030 __le32 address_high;
2034 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2036 /* NVM Config Write (indirect 0x0705) */
2037 struct i40e_aqc_nvm_config_write {
2039 __le16 element_count;
2041 __le32 address_high;
2045 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2047 /* Used for 0x0704 as well as for 0x0705 commands */
2048 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2049 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2050 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2051 #define I40E_AQ_ANVM_FEATURE 0
2052 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
2053 struct i40e_aqc_nvm_config_data_feature {
2055 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2056 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2057 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2058 __le16 feature_options;
2059 __le16 feature_selection;
2062 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2064 struct i40e_aqc_nvm_config_data_immediate_field {
2067 __le16 field_options;
2071 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2073 /* OEM Post Update (indirect 0x0720)
2074 * no command data struct used
2076 struct i40e_aqc_nvm_oem_post_update {
2077 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2082 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2084 struct i40e_aqc_nvm_oem_post_update_buffer {
2091 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2093 /* Thermal Sensor (indirect 0x0721)
2094 * read or set thermal sensor configs and values
2095 * takes a sensor and command specific data buffer, not detailed here
2097 struct i40e_aqc_thermal_sensor {
2099 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2100 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2101 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2107 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2109 /* Send to PF command (indirect 0x0801) id is only used by PF
2110 * Send to VF command (indirect 0x0802) id is only used by PF
2111 * Send to Peer PF command (indirect 0x0803)
2113 struct i40e_aqc_pf_vf_message {
2120 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2122 /* Alternate structure */
2124 /* Direct write (direct 0x0900)
2125 * Direct read (direct 0x0902)
2127 struct i40e_aqc_alternate_write {
2134 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2136 /* Indirect write (indirect 0x0901)
2137 * Indirect read (indirect 0x0903)
2140 struct i40e_aqc_alternate_ind_write {
2147 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2149 /* Done alternate write (direct 0x0904)
2152 struct i40e_aqc_alternate_write_done {
2154 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2155 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2156 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2157 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2161 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2163 /* Set OEM mode (direct 0x0905) */
2164 struct i40e_aqc_alternate_set_mode {
2166 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2167 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2171 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2173 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2175 /* async events 0x10xx */
2177 /* Lan Queue Overflow Event (direct, 0x1001) */
2178 struct i40e_aqc_lan_overflow {
2179 __le32 prtdcb_rupto;
2184 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2186 /* Get LLDP MIB (indirect 0x0A00) */
2187 struct i40e_aqc_lldp_get_mib {
2190 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2191 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2192 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2193 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2194 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2195 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2196 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2197 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2198 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2199 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2200 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2208 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2210 /* Configure LLDP MIB Change Event (direct 0x0A01)
2211 * also used for the event (with type in the command field)
2213 struct i40e_aqc_lldp_update_mib {
2215 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2216 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2222 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2224 /* Add LLDP TLV (indirect 0x0A02)
2225 * Delete LLDP TLV (indirect 0x0A04)
2227 struct i40e_aqc_lldp_add_tlv {
2228 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2236 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2238 /* Update LLDP TLV (indirect 0x0A03) */
2239 struct i40e_aqc_lldp_update_tlv {
2240 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2249 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2251 /* Stop LLDP (direct 0x0A05) */
2252 struct i40e_aqc_lldp_stop {
2254 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2255 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2259 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2261 /* Start LLDP (direct 0x0A06) */
2263 struct i40e_aqc_lldp_start {
2265 #define I40E_AQ_LLDP_AGENT_START 0x1
2269 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2271 /* Get CEE DCBX Oper Config (0x0A07)
2272 * uses the generic descriptor struct
2273 * returns below as indirect response
2276 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2277 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2278 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2279 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2280 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2281 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2283 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2284 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2285 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2286 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2287 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2288 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2289 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2290 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2291 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2292 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2293 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2294 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2296 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2297 * word boundary layout issues, which the Linux compilers silently deal
2298 * with by adding padding, making the actual struct larger than designed.
2299 * However, the FW compiler for the NIC is less lenient and complains
2300 * about the struct. Hence, the struct defined here has an extra byte in
2301 * fields reserved3 and reserved4 to directly acknowledge that padding,
2302 * and the new length is used in the length check macro.
2304 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2312 __le16 oper_app_prio;
2317 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2319 struct i40e_aqc_get_cee_dcb_cfg_resp {
2324 __le16 oper_app_prio;
2329 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2331 /* Set Local LLDP MIB (indirect 0x0A08)
2332 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2334 struct i40e_aqc_lldp_set_local_mib {
2335 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2336 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2337 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2338 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2339 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2340 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2341 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2342 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2347 __le32 address_high;
2351 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2353 struct i40e_aqc_lldp_set_local_mib_resp {
2354 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
2359 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
2361 /* Stop/Start LLDP Agent (direct 0x0A09)
2362 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2364 struct i40e_aqc_lldp_stop_start_specific_agent {
2365 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2366 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2367 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2372 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2374 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2375 struct i40e_aqc_add_udp_tunnel {
2379 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2380 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2381 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2382 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2386 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2388 struct i40e_aqc_add_udp_tunnel_completion {
2390 u8 filter_entry_index;
2392 #define I40E_AQC_SINGLE_PF 0x0
2393 #define I40E_AQC_MULTIPLE_PFS 0x1
2398 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2400 /* remove UDP Tunnel command (0x0B01) */
2401 struct i40e_aqc_remove_udp_tunnel {
2403 u8 index; /* 0 to 15 */
2407 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2409 struct i40e_aqc_del_udp_tunnel_completion {
2411 u8 index; /* 0 to 15 */
2413 u8 total_filters_used;
2417 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2419 struct i40e_aqc_get_set_rss_key {
2420 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2421 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2422 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2423 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2430 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2432 struct i40e_aqc_get_set_rss_key_data {
2433 u8 standard_rss_key[0x28];
2434 u8 extended_hash_key[0xc];
2437 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2439 struct i40e_aqc_get_set_rss_lut {
2440 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2441 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2442 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2443 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2445 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2446 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2447 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2449 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2450 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2457 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2459 /* tunnel key structure 0x0B10 */
2461 struct i40e_aqc_tunnel_key_structure {
2464 u8 key1_len; /* 0 to 15 */
2465 u8 key2_len; /* 0 to 15 */
2467 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2468 /* response flags */
2469 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2470 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2471 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2472 u8 network_key_index;
2473 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2474 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2475 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2476 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2480 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2482 /* OEM mode commands (direct 0xFE0x) */
2483 struct i40e_aqc_oem_param_change {
2485 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2486 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2487 #define I40E_AQ_OEM_PARAM_MAC 2
2488 __le32 param_value1;
2489 __le16 param_value2;
2493 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2495 struct i40e_aqc_oem_state_change {
2497 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2498 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2502 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2504 /* Initialize OCSD (0xFE02, direct) */
2505 struct i40e_aqc_opc_oem_ocsd_initialize {
2508 __le32 ocsd_memory_block_addr_high;
2509 __le32 ocsd_memory_block_addr_low;
2510 __le32 requested_update_interval;
2513 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2515 /* Initialize OCBB (0xFE03, direct) */
2516 struct i40e_aqc_opc_oem_ocbb_initialize {
2519 __le32 ocbb_memory_block_addr_high;
2520 __le32 ocbb_memory_block_addr_low;
2524 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2526 /* debug commands */
2528 /* get device id (0xFF00) uses the generic structure */
2530 /* set test more (0xFF01, internal) */
2532 struct i40e_acq_set_test_mode {
2534 #define I40E_AQ_TEST_PARTIAL 0
2535 #define I40E_AQ_TEST_FULL 1
2536 #define I40E_AQ_TEST_NVM 2
2539 #define I40E_AQ_TEST_OPEN 0
2540 #define I40E_AQ_TEST_CLOSE 1
2541 #define I40E_AQ_TEST_INC 2
2543 __le32 address_high;
2547 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2549 /* Debug Read Register command (0xFF03)
2550 * Debug Write Register command (0xFF04)
2552 struct i40e_aqc_debug_reg_read_write {
2559 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2561 /* Scatter/gather Reg Read (indirect 0xFF05)
2562 * Scatter/gather Reg Write (indirect 0xFF06)
2565 /* i40e_aq_desc is used for the command */
2566 struct i40e_aqc_debug_reg_sg_element_data {
2571 /* Debug Modify register (direct 0xFF07) */
2572 struct i40e_aqc_debug_modify_reg {
2579 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2581 /* dump internal data (0xFF08, indirect) */
2583 #define I40E_AQ_CLUSTER_ID_AUX 0
2584 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2585 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2586 #define I40E_AQ_CLUSTER_ID_HMC 3
2587 #define I40E_AQ_CLUSTER_ID_MAC0 4
2588 #define I40E_AQ_CLUSTER_ID_MAC1 5
2589 #define I40E_AQ_CLUSTER_ID_MAC2 6
2590 #define I40E_AQ_CLUSTER_ID_MAC3 7
2591 #define I40E_AQ_CLUSTER_ID_DCB 8
2592 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2593 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2594 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2596 struct i40e_aqc_debug_dump_internals {
2601 __le32 address_high;
2605 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2607 struct i40e_aqc_debug_modify_internals {
2609 u8 cluster_specific_params[7];
2610 __le32 address_high;
2614 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2616 #endif /* _I40E_ADMINQ_CMD_H_ */