1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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32 ***************************************************************************/
34 #ifndef _I40E_ADMINQ_CMD_H_
35 #define _I40E_ADMINQ_CMD_H_
37 /* This header file defines the i40e Admin Queue commands and is shared between
38 * i40e Firmware and Software.
40 * This file needs to comply with the Linux Kernel coding style.
43 #define I40E_FW_API_VERSION_MAJOR 0x0001
44 #define I40E_FW_API_VERSION_MINOR_X722 0x0005
45 #define I40E_FW_API_VERSION_MINOR_X710 0x0007
47 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
48 I40E_FW_API_VERSION_MINOR_X710 : \
49 I40E_FW_API_VERSION_MINOR_X722)
51 /* API version 1.7 implements additional link and PHY-specific APIs */
52 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
78 /* Flags sub-structure
79 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
80 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
83 /* command flags and offsets*/
84 #define I40E_AQ_FLAG_DD_SHIFT 0
85 #define I40E_AQ_FLAG_CMP_SHIFT 1
86 #define I40E_AQ_FLAG_ERR_SHIFT 2
87 #define I40E_AQ_FLAG_VFE_SHIFT 3
88 #define I40E_AQ_FLAG_LB_SHIFT 9
89 #define I40E_AQ_FLAG_RD_SHIFT 10
90 #define I40E_AQ_FLAG_VFC_SHIFT 11
91 #define I40E_AQ_FLAG_BUF_SHIFT 12
92 #define I40E_AQ_FLAG_SI_SHIFT 13
93 #define I40E_AQ_FLAG_EI_SHIFT 14
94 #define I40E_AQ_FLAG_FE_SHIFT 15
96 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
97 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
98 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
99 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
100 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
101 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
102 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
103 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
104 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
105 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
106 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
109 enum i40e_admin_queue_err {
110 I40E_AQ_RC_OK = 0, /* success */
111 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
112 I40E_AQ_RC_ENOENT = 2, /* No such element */
113 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
114 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
115 I40E_AQ_RC_EIO = 5, /* I/O error */
116 I40E_AQ_RC_ENXIO = 6, /* No such resource */
117 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
118 I40E_AQ_RC_EAGAIN = 8, /* Try again */
119 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
120 I40E_AQ_RC_EACCES = 10, /* Permission denied */
121 I40E_AQ_RC_EFAULT = 11, /* Bad address */
122 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
123 I40E_AQ_RC_EEXIST = 13, /* object already exists */
124 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
125 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
126 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
127 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
128 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
129 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
130 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
131 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
132 I40E_AQ_RC_EFBIG = 22, /* File too large */
135 /* Admin Queue command opcodes */
136 enum i40e_admin_queue_opc {
138 i40e_aqc_opc_get_version = 0x0001,
139 i40e_aqc_opc_driver_version = 0x0002,
140 i40e_aqc_opc_queue_shutdown = 0x0003,
141 i40e_aqc_opc_set_pf_context = 0x0004,
143 /* resource ownership */
144 i40e_aqc_opc_request_resource = 0x0008,
145 i40e_aqc_opc_release_resource = 0x0009,
147 i40e_aqc_opc_list_func_capabilities = 0x000A,
148 i40e_aqc_opc_list_dev_capabilities = 0x000B,
151 i40e_aqc_opc_set_proxy_config = 0x0104,
152 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
155 i40e_aqc_opc_mac_address_read = 0x0107,
156 i40e_aqc_opc_mac_address_write = 0x0108,
159 i40e_aqc_opc_clear_pxe_mode = 0x0110,
162 i40e_aqc_opc_set_wol_filter = 0x0120,
163 i40e_aqc_opc_get_wake_reason = 0x0121,
164 i40e_aqc_opc_clear_all_wol_filters = 0x025E,
166 /* internal switch commands */
167 i40e_aqc_opc_get_switch_config = 0x0200,
168 i40e_aqc_opc_add_statistics = 0x0201,
169 i40e_aqc_opc_remove_statistics = 0x0202,
170 i40e_aqc_opc_set_port_parameters = 0x0203,
171 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
172 i40e_aqc_opc_set_switch_config = 0x0205,
173 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
174 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
176 i40e_aqc_opc_add_vsi = 0x0210,
177 i40e_aqc_opc_update_vsi_parameters = 0x0211,
178 i40e_aqc_opc_get_vsi_parameters = 0x0212,
180 i40e_aqc_opc_add_pv = 0x0220,
181 i40e_aqc_opc_update_pv_parameters = 0x0221,
182 i40e_aqc_opc_get_pv_parameters = 0x0222,
184 i40e_aqc_opc_add_veb = 0x0230,
185 i40e_aqc_opc_update_veb_parameters = 0x0231,
186 i40e_aqc_opc_get_veb_parameters = 0x0232,
188 i40e_aqc_opc_delete_element = 0x0243,
190 i40e_aqc_opc_add_macvlan = 0x0250,
191 i40e_aqc_opc_remove_macvlan = 0x0251,
192 i40e_aqc_opc_add_vlan = 0x0252,
193 i40e_aqc_opc_remove_vlan = 0x0253,
194 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
195 i40e_aqc_opc_add_tag = 0x0255,
196 i40e_aqc_opc_remove_tag = 0x0256,
197 i40e_aqc_opc_add_multicast_etag = 0x0257,
198 i40e_aqc_opc_remove_multicast_etag = 0x0258,
199 i40e_aqc_opc_update_tag = 0x0259,
200 i40e_aqc_opc_add_control_packet_filter = 0x025A,
201 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
202 i40e_aqc_opc_add_cloud_filters = 0x025C,
203 i40e_aqc_opc_remove_cloud_filters = 0x025D,
204 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
205 i40e_aqc_opc_replace_cloud_filters = 0x025F,
207 i40e_aqc_opc_add_mirror_rule = 0x0260,
208 i40e_aqc_opc_delete_mirror_rule = 0x0261,
210 /* Dynamic Device Personalization */
211 i40e_aqc_opc_write_personalization_profile = 0x0270,
212 i40e_aqc_opc_get_personalization_profile_list = 0x0271,
215 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
216 i40e_aqc_opc_dcb_updated = 0x0302,
217 i40e_aqc_opc_set_dcb_parameters = 0x0303,
220 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
221 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
222 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
223 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
224 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
225 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
227 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
228 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
229 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
230 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
231 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
232 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
233 i40e_aqc_opc_query_port_ets_config = 0x0419,
234 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
235 i40e_aqc_opc_suspend_port_tx = 0x041B,
236 i40e_aqc_opc_resume_port_tx = 0x041C,
237 i40e_aqc_opc_configure_partition_bw = 0x041D,
239 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
240 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
243 i40e_aqc_opc_get_phy_abilities = 0x0600,
244 i40e_aqc_opc_set_phy_config = 0x0601,
245 i40e_aqc_opc_set_mac_config = 0x0603,
246 i40e_aqc_opc_set_link_restart_an = 0x0605,
247 i40e_aqc_opc_get_link_status = 0x0607,
248 i40e_aqc_opc_set_phy_int_mask = 0x0613,
249 i40e_aqc_opc_get_local_advt_reg = 0x0614,
250 i40e_aqc_opc_set_local_advt_reg = 0x0615,
251 i40e_aqc_opc_get_partner_advt = 0x0616,
252 i40e_aqc_opc_set_lb_modes = 0x0618,
253 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
254 i40e_aqc_opc_set_phy_debug = 0x0622,
255 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
256 i40e_aqc_opc_run_phy_activity = 0x0626,
257 i40e_aqc_opc_set_phy_register = 0x0628,
258 i40e_aqc_opc_get_phy_register = 0x0629,
261 i40e_aqc_opc_nvm_read = 0x0701,
262 i40e_aqc_opc_nvm_erase = 0x0702,
263 i40e_aqc_opc_nvm_update = 0x0703,
264 i40e_aqc_opc_nvm_config_read = 0x0704,
265 i40e_aqc_opc_nvm_config_write = 0x0705,
266 i40e_aqc_opc_nvm_progress = 0x0706,
267 i40e_aqc_opc_oem_post_update = 0x0720,
268 i40e_aqc_opc_thermal_sensor = 0x0721,
270 /* virtualization commands */
271 i40e_aqc_opc_send_msg_to_pf = 0x0801,
272 i40e_aqc_opc_send_msg_to_vf = 0x0802,
273 i40e_aqc_opc_send_msg_to_peer = 0x0803,
275 /* alternate structure */
276 i40e_aqc_opc_alternate_write = 0x0900,
277 i40e_aqc_opc_alternate_write_indirect = 0x0901,
278 i40e_aqc_opc_alternate_read = 0x0902,
279 i40e_aqc_opc_alternate_read_indirect = 0x0903,
280 i40e_aqc_opc_alternate_write_done = 0x0904,
281 i40e_aqc_opc_alternate_set_mode = 0x0905,
282 i40e_aqc_opc_alternate_clear_port = 0x0906,
285 i40e_aqc_opc_lldp_get_mib = 0x0A00,
286 i40e_aqc_opc_lldp_update_mib = 0x0A01,
287 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
288 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
289 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
290 i40e_aqc_opc_lldp_stop = 0x0A05,
291 i40e_aqc_opc_lldp_start = 0x0A06,
292 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
293 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
294 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
296 /* Tunnel commands */
297 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
298 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
299 i40e_aqc_opc_set_rss_key = 0x0B02,
300 i40e_aqc_opc_set_rss_lut = 0x0B03,
301 i40e_aqc_opc_get_rss_key = 0x0B04,
302 i40e_aqc_opc_get_rss_lut = 0x0B05,
305 i40e_aqc_opc_event_lan_overflow = 0x1001,
308 i40e_aqc_opc_oem_parameter_change = 0xFE00,
309 i40e_aqc_opc_oem_device_status_change = 0xFE01,
310 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
311 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
314 i40e_aqc_opc_debug_read_reg = 0xFF03,
315 i40e_aqc_opc_debug_write_reg = 0xFF04,
316 i40e_aqc_opc_debug_modify_reg = 0xFF07,
317 i40e_aqc_opc_debug_dump_internals = 0xFF08,
320 /* command structures and indirect data structures */
322 /* Structure naming conventions:
323 * - no suffix for direct command descriptor structures
324 * - _data for indirect sent data
325 * - _resp for indirect return data (data which is both will use _data)
326 * - _completion for direct return data
327 * - _element_ for repeated elements (may also be _data or _resp)
329 * Command structures are expected to overlay the params.raw member of the basic
330 * descriptor, and as such cannot exceed 16 bytes in length.
333 /* This macro is used to generate a compilation error if a structure
334 * is not exactly the correct length. It gives a divide by zero error if the
335 * structure is not of the correct size, otherwise it creates an enum that is
338 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
339 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
341 /* This macro is used extensively to ensure that command structures are 16
342 * bytes in length as they have to map to the raw array of that size.
344 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
346 /* internal (0x00XX) commands */
348 /* Get version (direct 0x0001) */
349 struct i40e_aqc_get_version {
358 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
360 /* Send driver version (indirect 0x0002) */
361 struct i40e_aqc_driver_version {
365 u8 driver_subbuild_ver;
371 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
373 /* Queue Shutdown (direct 0x0003) */
374 struct i40e_aqc_queue_shutdown {
375 __le32 driver_unloading;
376 #define I40E_AQ_DRIVER_UNLOADING 0x1
380 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
382 /* Set PF context (0x0004, direct) */
383 struct i40e_aqc_set_pf_context {
388 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
390 /* Request resource ownership (direct 0x0008)
391 * Release resource ownership (direct 0x0009)
393 #define I40E_AQ_RESOURCE_NVM 1
394 #define I40E_AQ_RESOURCE_SDP 2
395 #define I40E_AQ_RESOURCE_ACCESS_READ 1
396 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
397 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
398 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
400 struct i40e_aqc_request_resource {
404 __le32 resource_number;
408 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
410 /* Get function capabilities (indirect 0x000A)
411 * Get device capabilities (indirect 0x000B)
413 struct i40e_aqc_list_capabilites {
415 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
423 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
425 struct i40e_aqc_list_capabilities_element_resp {
437 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
438 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
439 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
440 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
441 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
442 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
443 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
444 #define I40E_AQ_CAP_ID_SRIOV 0x0012
445 #define I40E_AQ_CAP_ID_VF 0x0013
446 #define I40E_AQ_CAP_ID_VMDQ 0x0014
447 #define I40E_AQ_CAP_ID_8021QBG 0x0015
448 #define I40E_AQ_CAP_ID_8021QBR 0x0016
449 #define I40E_AQ_CAP_ID_VSI 0x0017
450 #define I40E_AQ_CAP_ID_DCB 0x0018
451 #define I40E_AQ_CAP_ID_FCOE 0x0021
452 #define I40E_AQ_CAP_ID_ISCSI 0x0022
453 #define I40E_AQ_CAP_ID_RSS 0x0040
454 #define I40E_AQ_CAP_ID_RXQ 0x0041
455 #define I40E_AQ_CAP_ID_TXQ 0x0042
456 #define I40E_AQ_CAP_ID_MSIX 0x0043
457 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
458 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
459 #define I40E_AQ_CAP_ID_1588 0x0046
460 #define I40E_AQ_CAP_ID_IWARP 0x0051
461 #define I40E_AQ_CAP_ID_LED 0x0061
462 #define I40E_AQ_CAP_ID_SDP 0x0062
463 #define I40E_AQ_CAP_ID_MDIO 0x0063
464 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
465 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
466 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
467 #define I40E_AQ_CAP_ID_CEM 0x00F2
469 /* Set CPPM Configuration (direct 0x0103) */
470 struct i40e_aqc_cppm_configuration {
471 __le16 command_flags;
472 #define I40E_AQ_CPPM_EN_LTRC 0x0800
473 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
474 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
475 #define I40E_AQ_CPPM_EN_HPTC 0x4000
476 #define I40E_AQ_CPPM_EN_DMARC 0x8000
485 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
487 /* Set ARP Proxy command / response (indirect 0x0104) */
488 struct i40e_aqc_arp_proxy_data {
489 __le16 command_flags;
490 #define I40E_AQ_ARP_INIT_IPV4 0x0800
491 #define I40E_AQ_ARP_UNSUP_CTL 0x1000
492 #define I40E_AQ_ARP_ENA 0x2000
493 #define I40E_AQ_ARP_ADD_IPV4 0x4000
494 #define I40E_AQ_ARP_DEL_IPV4 0x8000
496 __le32 enabled_offloads;
497 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
498 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
504 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
506 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
507 struct i40e_aqc_ns_proxy_data {
508 __le16 table_idx_mac_addr_0;
509 __le16 table_idx_mac_addr_1;
510 __le16 table_idx_ipv6_0;
511 __le16 table_idx_ipv6_1;
513 #define I40E_AQ_NS_PROXY_ADD_0 0x0001
514 #define I40E_AQ_NS_PROXY_DEL_0 0x0002
515 #define I40E_AQ_NS_PROXY_ADD_1 0x0004
516 #define I40E_AQ_NS_PROXY_DEL_1 0x0008
517 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
518 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
519 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
520 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
521 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
522 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
523 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
524 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
525 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
528 u8 local_mac_addr[6];
529 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
533 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
535 /* Manage LAA Command (0x0106) - obsolete */
536 struct i40e_aqc_mng_laa {
537 __le16 command_flags;
538 #define I40E_AQ_LAA_FLAG_WR 0x8000
545 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
547 /* Manage MAC Address Read Command (indirect 0x0107) */
548 struct i40e_aqc_mac_address_read {
549 __le16 command_flags;
550 #define I40E_AQC_LAN_ADDR_VALID 0x10
551 #define I40E_AQC_SAN_ADDR_VALID 0x20
552 #define I40E_AQC_PORT_ADDR_VALID 0x40
553 #define I40E_AQC_WOL_ADDR_VALID 0x80
554 #define I40E_AQC_MC_MAG_EN_VALID 0x100
555 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200
556 #define I40E_AQC_ADDR_VALID_MASK 0x3F0
562 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
564 struct i40e_aqc_mac_address_read_data {
571 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
573 /* Manage MAC Address Write Command (0x0108) */
574 struct i40e_aqc_mac_address_write {
575 __le16 command_flags;
576 #define I40E_AQC_MC_MAG_EN 0x0100
577 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
578 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
579 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
580 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
581 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
582 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
589 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
591 /* PXE commands (0x011x) */
593 /* Clear PXE Command and response (direct 0x0110) */
594 struct i40e_aqc_clear_pxe {
599 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
601 /* Set WoL Filter (0x0120) */
603 struct i40e_aqc_set_wol_filter {
605 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
606 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
607 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
608 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
610 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
611 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
612 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
614 #define I40E_AQC_SET_WOL_FILTER 0x8000
615 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
616 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000
617 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
618 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
620 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
621 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
627 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
629 struct i40e_aqc_set_wol_filter_data {
634 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
636 /* Get Wake Reason (0x0121) */
638 struct i40e_aqc_get_wake_reason_completion {
641 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
642 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
643 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
644 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
645 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
646 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
650 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
652 /* Switch configuration commands (0x02xx) */
654 /* Used by many indirect commands that only pass an seid and a buffer in the
657 struct i40e_aqc_switch_seid {
664 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
666 /* Get Switch Configuration command (indirect 0x0200)
667 * uses i40e_aqc_switch_seid for the descriptor
669 struct i40e_aqc_get_switch_config_header_resp {
675 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
677 struct i40e_aqc_switch_config_element_resp {
679 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
680 #define I40E_AQ_SW_ELEM_TYPE_PF 2
681 #define I40E_AQ_SW_ELEM_TYPE_VF 3
682 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
683 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
684 #define I40E_AQ_SW_ELEM_TYPE_PV 16
685 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
686 #define I40E_AQ_SW_ELEM_TYPE_PA 18
687 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
689 #define I40E_AQ_SW_ELEM_REV_1 1
692 __le16 downlink_seid;
695 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
696 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
697 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
702 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
704 /* Get Switch Configuration (indirect 0x0200)
705 * an array of elements are returned in the response buffer
706 * the first in the array is the header, remainder are elements
708 struct i40e_aqc_get_switch_config_resp {
709 struct i40e_aqc_get_switch_config_header_resp header;
710 struct i40e_aqc_switch_config_element_resp element[1];
713 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
715 /* Add Statistics (direct 0x0201)
716 * Remove Statistics (direct 0x0202)
718 struct i40e_aqc_add_remove_statistics {
725 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
727 /* Set Port Parameters command (direct 0x0203) */
728 struct i40e_aqc_set_port_parameters {
729 __le16 command_flags;
730 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
731 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
732 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
733 __le16 bad_frame_vsi;
734 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
735 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
736 __le16 default_seid; /* reserved for command */
740 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
742 /* Get Switch Resource Allocation (indirect 0x0204) */
743 struct i40e_aqc_get_switch_resource_alloc {
744 u8 num_entries; /* reserved for command */
750 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
752 /* expect an array of these structs in the response buffer */
753 struct i40e_aqc_switch_resource_alloc_element_resp {
755 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
756 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
757 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
758 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
759 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
760 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
761 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
762 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
763 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
764 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
765 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
766 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
767 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
768 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
769 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
770 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
771 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
772 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
773 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
778 __le16 total_unalloced;
782 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
784 /* Set Switch Configuration (direct 0x0205) */
785 struct i40e_aqc_set_switch_config {
787 /* flags used for both fields below */
788 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
789 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
790 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004
792 /* The ethertype in switch_tag is dropped on ingress and used
793 * internally by the switch. Set this to zero for the default
794 * of 0x88a8 (802.1ad). Should be zero for firmware API
795 * versions lower than 1.7.
798 /* The ethertypes in first_tag and second_tag are used to
799 * match the outer and inner VLAN tags (respectively) when HW
800 * double VLAN tagging is enabled via the set port parameters
801 * AQ command. Otherwise these are both ignored. Set them to
802 * zero for their defaults of 0x8100 (802.1Q). Should be zero
803 * for firmware API versions lower than 1.7.
810 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
812 /* Read Receive control registers (direct 0x0206)
813 * Write Receive control registers (direct 0x0207)
814 * used for accessing Rx control registers that can be
815 * slow and need special handling when under high Rx load
817 struct i40e_aqc_rx_ctl_reg_read_write {
824 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
826 /* Add VSI (indirect 0x0210)
827 * this indirect command uses struct i40e_aqc_vsi_properties_data
828 * as the indirect buffer (128 bytes)
830 * Update VSI (indirect 0x211)
831 * uses the same data structure as Add VSI
833 * Get VSI (indirect 0x0212)
834 * uses the same completion and data structure as Add VSI
836 struct i40e_aqc_add_get_update_vsi {
839 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
840 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
841 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
846 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
847 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
848 #define I40E_AQ_VSI_TYPE_VF 0x0
849 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
850 #define I40E_AQ_VSI_TYPE_PF 0x2
851 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
852 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
857 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
859 struct i40e_aqc_add_get_update_vsi_completion {
868 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
870 struct i40e_aqc_vsi_properties_data {
871 /* first 96 byte are written by SW */
872 __le16 valid_sections;
873 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
874 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
875 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
876 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
877 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
878 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
879 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
880 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
881 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
882 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
884 __le16 switch_id; /* 12bit id combined with flags below */
885 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
886 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
887 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
888 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
889 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
891 /* security section */
893 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
894 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
895 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
898 __le16 pvid; /* VLANS include priority bits */
901 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
902 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
903 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
904 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
905 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
906 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
907 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
908 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
909 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
910 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
911 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
912 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
913 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
914 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
915 u8 pvlan_reserved[3];
916 /* ingress egress up sections */
917 __le32 ingress_table; /* bitmap, 3 bits per up */
918 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
919 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
920 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
921 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
922 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
923 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
924 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
925 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
926 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
927 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
928 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
929 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
930 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
931 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
932 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
933 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
934 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
935 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
936 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
937 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
938 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
939 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
940 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
941 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
942 __le32 egress_table; /* same defines as for ingress table */
943 /* cascaded PV section */
946 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
947 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
948 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
949 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
950 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
951 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
952 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
953 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
954 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
956 /* queue mapping section */
957 __le16 mapping_flags;
958 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
959 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
960 __le16 queue_mapping[16];
961 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
962 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
963 __le16 tc_mapping[8];
964 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
965 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
966 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
967 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
968 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
969 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
970 /* queueing option section */
971 u8 queueing_opt_flags;
972 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
973 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
974 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
975 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
976 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
977 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
978 u8 queueing_opt_reserved[3];
979 /* scheduler section */
982 /* outer up section */
983 __le32 outer_up_table; /* same structure and defines as ingress tbl */
985 /* last 32 bytes are written by FW */
987 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
988 __le16 stat_counter_idx;
990 u8 resp_reserved[12];
993 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
995 /* Add Port Virtualizer (direct 0x0220)
996 * also used for update PV (direct 0x0221) but only flags are used
997 * (IS_CTRL_PORT only works on add PV)
999 struct i40e_aqc_add_update_pv {
1000 __le16 command_flags;
1001 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
1002 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
1003 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
1004 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
1006 __le16 connected_seid;
1010 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
1012 struct i40e_aqc_add_update_pv_completion {
1013 /* reserved for update; for add also encodes error if rc == ENOSPC */
1015 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
1016 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
1017 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
1018 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
1022 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
1024 /* Get PV Params (direct 0x0222)
1025 * uses i40e_aqc_switch_seid for the descriptor
1028 struct i40e_aqc_get_pv_params_completion {
1030 __le16 default_stag;
1031 __le16 pv_flags; /* same flags as add_pv */
1032 #define I40E_AQC_GET_PV_PV_TYPE 0x1
1033 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1034 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1036 __le16 default_port_seid;
1039 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1041 /* Add VEB (direct 0x0230) */
1042 struct i40e_aqc_add_veb {
1044 __le16 downlink_seid;
1046 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1047 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1048 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1049 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1050 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1051 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1052 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1053 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1058 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1060 struct i40e_aqc_add_veb_completion {
1063 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1065 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1066 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1067 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1068 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1069 __le16 statistic_index;
1074 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1076 /* Get VEB Parameters (direct 0x0232)
1077 * uses i40e_aqc_switch_seid for the descriptor
1079 struct i40e_aqc_get_veb_parameters_completion {
1082 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1083 __le16 statistic_index;
1089 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1091 /* Delete Element (direct 0x0243)
1092 * uses the generic i40e_aqc_switch_seid
1095 /* Add MAC-VLAN (indirect 0x0250) */
1097 /* used for the command for most vlan commands */
1098 struct i40e_aqc_macvlan {
1099 __le16 num_addresses;
1101 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1102 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1103 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1104 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1109 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1111 /* indirect data for command and response */
1112 struct i40e_aqc_add_macvlan_element_data {
1116 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1117 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1118 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1119 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1120 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1121 __le16 queue_number;
1122 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1123 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1124 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1125 /* response section */
1127 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1128 #define I40E_AQC_MM_HASH_MATCH 0x02
1129 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1133 struct i40e_aqc_add_remove_macvlan_completion {
1134 __le16 perfect_mac_used;
1135 __le16 perfect_mac_free;
1136 __le16 unicast_hash_free;
1137 __le16 multicast_hash_free;
1142 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1144 /* Remove MAC-VLAN (indirect 0x0251)
1145 * uses i40e_aqc_macvlan for the descriptor
1146 * data points to an array of num_addresses of elements
1149 struct i40e_aqc_remove_macvlan_element_data {
1153 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1154 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1155 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1156 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1160 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1161 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1162 u8 reply_reserved[3];
1165 /* Add VLAN (indirect 0x0252)
1166 * Remove VLAN (indirect 0x0253)
1167 * use the generic i40e_aqc_macvlan for the command
1169 struct i40e_aqc_add_remove_vlan_element_data {
1172 /* flags for add VLAN */
1173 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1174 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1175 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1176 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1177 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1178 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1179 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1180 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1181 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1182 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1183 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1184 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1185 /* flags for remove VLAN */
1186 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1189 /* flags for add VLAN */
1190 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1191 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1192 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1193 /* flags for remove VLAN */
1194 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1195 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1199 struct i40e_aqc_add_remove_vlan_completion {
1207 /* Set VSI Promiscuous Modes (direct 0x0254) */
1208 struct i40e_aqc_set_vsi_promiscuous_modes {
1209 __le16 promiscuous_flags;
1211 /* flags used for both fields above */
1212 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1213 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1214 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1215 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1216 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1217 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1219 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1221 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1222 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1226 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1228 /* Add S/E-tag command (direct 0x0255)
1229 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1231 struct i40e_aqc_add_tag {
1233 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1235 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1236 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1237 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1239 __le16 queue_number;
1243 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1245 struct i40e_aqc_add_remove_tag_completion {
1251 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1253 /* Remove S/E-tag command (direct 0x0256)
1254 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1256 struct i40e_aqc_remove_tag {
1258 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1259 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1260 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1265 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1267 /* Add multicast E-Tag (direct 0x0257)
1268 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1269 * and no external data
1271 struct i40e_aqc_add_remove_mcast_etag {
1274 u8 num_unicast_etags;
1276 __le32 addr_high; /* address of array of 2-byte s-tags */
1280 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1282 struct i40e_aqc_add_remove_mcast_etag_completion {
1284 __le16 mcast_etags_used;
1285 __le16 mcast_etags_free;
1291 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1293 /* Update S/E-Tag (direct 0x0259) */
1294 struct i40e_aqc_update_tag {
1296 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1297 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1298 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1304 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1306 struct i40e_aqc_update_tag_completion {
1312 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1314 /* Add Control Packet filter (direct 0x025A)
1315 * Remove Control Packet filter (direct 0x025B)
1316 * uses the i40e_aqc_add_oveb_cloud,
1317 * and the generic direct completion structure
1319 struct i40e_aqc_add_remove_control_packet_filter {
1323 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1324 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1325 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1326 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1327 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1329 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1330 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1331 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1336 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1338 struct i40e_aqc_add_remove_control_packet_filter_completion {
1339 __le16 mac_etype_used;
1341 __le16 mac_etype_free;
1346 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1348 /* Add Cloud filters (indirect 0x025C)
1349 * Remove Cloud filters (indirect 0x025D)
1350 * uses the i40e_aqc_add_remove_cloud_filters,
1351 * and the generic indirect completion structure
1353 struct i40e_aqc_add_remove_cloud_filters {
1357 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1358 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1359 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1361 #define I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1
1367 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1369 struct i40e_aqc_add_remove_cloud_filters_element_data {
1383 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1384 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1385 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1386 /* 0x0000 reserved */
1387 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1388 /* 0x0002 reserved */
1389 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1390 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1391 /* 0x0005 reserved */
1392 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1393 /* 0x0007 reserved */
1394 /* 0x0008 reserved */
1395 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1396 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1397 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1398 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1399 /* 0x0010 to 0x0017 is for custom filters */
1401 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1402 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1403 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1404 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1405 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1407 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1408 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1409 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1410 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1411 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1412 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1413 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1414 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1416 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1417 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1418 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1422 __le16 queue_number;
1423 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1424 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1425 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1427 /* response section */
1428 u8 allocation_result;
1429 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1430 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1431 u8 response_reserved[7];
1434 /* i40e_aqc_add_rm_cloud_filt_elem_ext is used when
1435 * I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set. refer to
1438 struct i40e_aqc_add_rm_cloud_filt_elem_ext {
1439 struct i40e_aqc_add_remove_cloud_filters_element_data element;
1440 u16 general_fields[32];
1441 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
1442 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
1443 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
1444 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
1445 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
1446 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
1447 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
1448 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
1449 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
1450 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
1451 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
1452 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
1453 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
1454 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
1455 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
1456 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1457 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
1458 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
1459 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
1460 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
1461 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
1462 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
1463 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
1464 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
1465 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
1466 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
1467 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
1468 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
1469 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
1470 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
1471 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
1474 struct i40e_aqc_remove_cloud_filters_completion {
1475 __le16 perfect_ovlan_used;
1476 __le16 perfect_ovlan_free;
1483 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1485 /* Replace filter Command 0x025F
1486 * uses the i40e_aqc_replace_cloud_filters,
1487 * and the generic indirect completion structure
1489 struct i40e_filter_data {
1494 struct i40e_aqc_replace_cloud_filters_cmd {
1496 #define I40E_AQC_REPLACE_L1_FILTER 0x0
1497 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1
1498 #define I40E_AQC_GET_CLOUD_FILTERS 0x2
1499 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4
1500 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8
1509 struct i40e_aqc_replace_cloud_filters_cmd_buf {
1511 /* Filter type INPUT codes*/
1512 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3
1513 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL)
1515 /* Field Vector offsets */
1516 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0
1517 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6
1518 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7
1519 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8
1520 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9
1521 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10
1522 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11
1523 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12
1525 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14
1527 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15
1529 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37
1530 struct i40e_filter_data filters[8];
1533 /* Add Mirror Rule (indirect or direct 0x0260)
1534 * Delete Mirror Rule (indirect or direct 0x0261)
1535 * note: some rule types (4,5) do not use an external buffer.
1536 * take care to set the flags correctly.
1538 struct i40e_aqc_add_delete_mirror_rule {
1541 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1542 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1543 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1544 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1545 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1546 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1547 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1548 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1550 __le16 destination; /* VSI for add, rule id for delete */
1551 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1555 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1557 struct i40e_aqc_add_delete_mirror_rule_completion {
1559 __le16 rule_id; /* only used on add */
1560 __le16 mirror_rules_used;
1561 __le16 mirror_rules_free;
1566 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1568 /* Dynamic Device Personalization */
1569 struct i40e_aqc_write_personalization_profile {
1572 __le32 profile_track_id;
1577 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1579 struct i40e_aqc_write_ddp_resp {
1580 __le32 error_offset;
1586 struct i40e_aqc_get_applied_profiles {
1588 #define I40E_AQC_GET_DDP_GET_CONF 0x1
1589 #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2
1596 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1600 /* PFC Ignore (direct 0x0301)
1601 * the command and response use the same descriptor structure
1603 struct i40e_aqc_pfc_ignore {
1605 u8 command_flags; /* unused on response */
1606 #define I40E_AQC_PFC_IGNORE_SET 0x80
1607 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1611 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1613 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1614 * with no parameters
1617 /* TX scheduler 0x04xx */
1619 /* Almost all the indirect commands use
1620 * this generic struct to pass the SEID in param0
1622 struct i40e_aqc_tx_sched_ind {
1629 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1631 /* Several commands respond with a set of queue set handles */
1632 struct i40e_aqc_qs_handles_resp {
1633 __le16 qs_handles[8];
1636 /* Configure VSI BW limits (direct 0x0400) */
1637 struct i40e_aqc_configure_vsi_bw_limit {
1642 u8 max_credit; /* 0-3, limit = 2^max */
1646 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1648 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1649 * responds with i40e_aqc_qs_handles_resp
1651 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1654 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1656 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1657 __le16 tc_bw_max[2];
1661 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1663 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1664 * responds with i40e_aqc_qs_handles_resp
1666 struct i40e_aqc_configure_vsi_tc_bw_data {
1669 u8 tc_bw_credits[8];
1671 __le16 qs_handles[8];
1674 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1676 /* Query vsi bw configuration (indirect 0x0408) */
1677 struct i40e_aqc_query_vsi_bw_config_resp {
1679 u8 tc_suspended_bits;
1681 __le16 qs_handles[8];
1683 __le16 port_bw_limit;
1685 u8 max_bw; /* 0-3, limit = 2^max */
1689 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1691 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1692 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1695 u8 share_credits[8];
1698 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1699 __le16 tc_bw_max[2];
1702 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1704 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1705 struct i40e_aqc_configure_switching_comp_bw_limit {
1710 u8 max_bw; /* 0-3, limit = 2^max */
1714 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1716 /* Enable Physical Port ETS (indirect 0x0413)
1717 * Modify Physical Port ETS (indirect 0x0414)
1718 * Disable Physical Port ETS (indirect 0x0415)
1720 struct i40e_aqc_configure_switching_comp_ets_data {
1724 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1725 u8 tc_strict_priority_flags;
1727 u8 tc_bw_share_credits[8];
1731 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1733 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1734 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1737 __le16 tc_bw_credit[8];
1739 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1740 __le16 tc_bw_max[2];
1744 I40E_CHECK_STRUCT_LEN(0x40,
1745 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1747 /* Configure Switching Component Bandwidth Allocation per Tc
1750 struct i40e_aqc_configure_switching_comp_bw_config_data {
1753 u8 absolute_credits; /* bool */
1754 u8 tc_bw_share_credits[8];
1758 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1760 /* Query Switching Component Configuration (indirect 0x0418) */
1761 struct i40e_aqc_query_switching_comp_ets_config_resp {
1764 __le16 port_bw_limit;
1766 u8 tc_bw_max; /* 0-3, limit = 2^max */
1770 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1772 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1773 struct i40e_aqc_query_port_ets_config_resp {
1777 u8 tc_strict_priority_bits;
1779 u8 tc_bw_share_credits[8];
1780 __le16 tc_bw_limits[8];
1782 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1783 __le16 tc_bw_max[2];
1787 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1789 /* Query Switching Component Bandwidth Allocation per Traffic Type
1792 struct i40e_aqc_query_switching_comp_bw_config_resp {
1795 u8 absolute_credits_enable; /* bool */
1796 u8 tc_bw_share_credits[8];
1797 __le16 tc_bw_limits[8];
1799 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1800 __le16 tc_bw_max[2];
1803 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1805 /* Suspend/resume port TX traffic
1806 * (direct 0x041B and 0x041C) uses the generic SEID struct
1809 /* Configure partition BW
1812 struct i40e_aqc_configure_partition_bw_data {
1813 __le16 pf_valid_bits;
1814 u8 min_bw[16]; /* guaranteed bandwidth */
1815 u8 max_bw[16]; /* bandwidth limit */
1818 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1820 /* Get and set the active HMC resource profile and status.
1821 * (direct 0x0500) and (direct 0x0501)
1823 struct i40e_aq_get_set_hmc_resource_profile {
1829 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1831 enum i40e_aq_hmc_profile {
1832 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1833 I40E_HMC_PROFILE_DEFAULT = 1,
1834 I40E_HMC_PROFILE_FAVOR_VF = 2,
1835 I40E_HMC_PROFILE_EQUAL = 3,
1838 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1840 /* set in param0 for get phy abilities to report qualified modules */
1841 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1842 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1844 enum i40e_aq_phy_type {
1845 I40E_PHY_TYPE_SGMII = 0x0,
1846 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1847 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1848 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1849 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1850 I40E_PHY_TYPE_XAUI = 0x5,
1851 I40E_PHY_TYPE_XFI = 0x6,
1852 I40E_PHY_TYPE_SFI = 0x7,
1853 I40E_PHY_TYPE_XLAUI = 0x8,
1854 I40E_PHY_TYPE_XLPPI = 0x9,
1855 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1856 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1857 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1858 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1859 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1860 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1861 I40E_PHY_TYPE_100BASE_TX = 0x11,
1862 I40E_PHY_TYPE_1000BASE_T = 0x12,
1863 I40E_PHY_TYPE_10GBASE_T = 0x13,
1864 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1865 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1866 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1867 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1868 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1869 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1870 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1871 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1872 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1873 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1874 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1875 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1876 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1877 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1878 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1879 I40E_PHY_TYPE_25GBASE_AOC = 0x23,
1880 I40E_PHY_TYPE_25GBASE_ACC = 0x24,
1882 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1883 I40E_PHY_TYPE_EMPTY = 0xFE,
1884 I40E_PHY_TYPE_DEFAULT = 0xFF,
1887 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1888 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1889 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1890 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1891 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1892 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1894 enum i40e_aq_link_speed {
1895 I40E_LINK_SPEED_UNKNOWN = 0,
1896 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1897 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1898 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1899 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1900 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT),
1901 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT),
1904 struct i40e_aqc_module_desc {
1912 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1914 struct i40e_aq_get_phy_abilities_resp {
1915 __le32 phy_type; /* bitmap using the above enum for offsets */
1916 u8 link_speed; /* bitmap using the above enum bit patterns */
1918 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1919 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1920 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1921 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1922 #define I40E_AQ_PHY_AN_ENABLED 0x10
1923 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1924 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
1925 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
1926 __le16 eee_capability;
1927 #define I40E_AQ_EEE_100BASE_TX 0x0002
1928 #define I40E_AQ_EEE_1000BASE_T 0x0004
1929 #define I40E_AQ_EEE_10GBASE_T 0x0008
1930 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1931 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1932 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1935 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1937 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01
1938 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02
1939 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1940 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1941 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10
1942 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20
1943 u8 fec_cfg_curr_mod_ext_info;
1944 #define I40E_AQ_ENABLE_FEC_KR 0x01
1945 #define I40E_AQ_ENABLE_FEC_RS 0x02
1946 #define I40E_AQ_REQUEST_FEC_KR 0x04
1947 #define I40E_AQ_REQUEST_FEC_RS 0x08
1948 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
1950 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
1951 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5
1956 u8 qualified_module_count;
1957 #define I40E_AQ_PHY_MAX_QMS 16
1958 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1961 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1963 /* Set PHY Config (direct 0x0601) */
1964 struct i40e_aq_set_phy_config { /* same bits as above in all */
1968 /* bits 0-2 use the values from get_phy_abilities_resp */
1969 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1970 #define I40E_AQ_PHY_ENABLE_AN 0x10
1971 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1972 __le16 eee_capability;
1977 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1978 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
1979 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
1980 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
1981 #define I40E_AQ_SET_FEC_AUTO BIT(4)
1982 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1983 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1987 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1989 /* Set MAC Config command data structure (direct 0x0603) */
1990 struct i40e_aq_set_mac_config {
1991 __le16 max_frame_size;
1993 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1994 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1995 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1996 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1997 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1998 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1999 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
2000 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
2001 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
2002 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
2003 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
2004 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
2005 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
2006 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
2007 u8 tx_timer_priority; /* bitmap */
2008 __le16 tx_timer_value;
2009 __le16 fc_refresh_threshold;
2013 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
2015 /* Restart Auto-Negotiation (direct 0x605) */
2016 struct i40e_aqc_set_link_restart_an {
2018 #define I40E_AQ_PHY_RESTART_AN 0x02
2019 #define I40E_AQ_PHY_LINK_ENABLE 0x04
2023 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
2025 /* Get Link Status cmd & response data structure (direct 0x0607) */
2026 struct i40e_aqc_get_link_status {
2027 __le16 command_flags; /* only field set on command */
2028 #define I40E_AQ_LSE_MASK 0x3
2029 #define I40E_AQ_LSE_NOP 0x0
2030 #define I40E_AQ_LSE_DISABLE 0x2
2031 #define I40E_AQ_LSE_ENABLE 0x3
2032 /* only response uses this flag */
2033 #define I40E_AQ_LSE_IS_ENABLED 0x1
2034 u8 phy_type; /* i40e_aq_phy_type */
2035 u8 link_speed; /* i40e_aq_link_speed */
2037 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
2038 #define I40E_AQ_LINK_UP_FUNCTION 0x01
2039 #define I40E_AQ_LINK_FAULT 0x02
2040 #define I40E_AQ_LINK_FAULT_TX 0x04
2041 #define I40E_AQ_LINK_FAULT_RX 0x08
2042 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
2043 #define I40E_AQ_LINK_UP_PORT 0x20
2044 #define I40E_AQ_MEDIA_AVAILABLE 0x40
2045 #define I40E_AQ_SIGNAL_DETECT 0x80
2047 #define I40E_AQ_AN_COMPLETED 0x01
2048 #define I40E_AQ_LP_AN_ABILITY 0x02
2049 #define I40E_AQ_PD_FAULT 0x04
2050 #define I40E_AQ_FEC_EN 0x08
2051 #define I40E_AQ_PHY_LOW_POWER 0x10
2052 #define I40E_AQ_LINK_PAUSE_TX 0x20
2053 #define I40E_AQ_LINK_PAUSE_RX 0x40
2054 #define I40E_AQ_QUALIFIED_MODULE 0x80
2056 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
2057 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
2058 #define I40E_AQ_LINK_TX_SHIFT 0x02
2059 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
2060 #define I40E_AQ_LINK_TX_ACTIVE 0x00
2061 #define I40E_AQ_LINK_TX_DRAINED 0x01
2062 #define I40E_AQ_LINK_TX_FLUSHED 0x03
2063 #define I40E_AQ_LINK_FORCED_40G 0x10
2064 /* 25G Error Codes */
2065 #define I40E_AQ_25G_NO_ERR 0X00
2066 #define I40E_AQ_25G_NOT_PRESENT 0X01
2067 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
2068 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
2069 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
2070 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
2071 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
2072 /* Since firmware API 1.7 loopback field keeps power class info as well */
2073 #define I40E_AQ_LOOPBACK_MASK 0x07
2074 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6
2075 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)
2076 __le16 max_frame_size;
2078 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
2079 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
2080 #define I40E_AQ_CONFIG_CRC_ENA 0x04
2081 #define I40E_AQ_CONFIG_PACING_MASK 0x78
2085 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
2086 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
2087 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
2088 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
2089 #define I40E_AQ_PWR_CLASS_MASK 0x03
2099 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
2101 /* Set event mask command (direct 0x613) */
2102 struct i40e_aqc_set_phy_int_mask {
2105 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
2106 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
2107 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
2108 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
2109 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
2110 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
2111 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
2112 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
2113 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
2117 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
2119 /* Get Local AN advt register (direct 0x0614)
2120 * Set Local AN advt register (direct 0x0615)
2121 * Get Link Partner AN advt register (direct 0x0616)
2123 struct i40e_aqc_an_advt_reg {
2124 __le32 local_an_reg0;
2125 __le16 local_an_reg1;
2129 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
2131 /* Set Loopback mode (0x0618) */
2132 struct i40e_aqc_set_lb_mode {
2134 #define I40E_AQ_LB_PHY_LOCAL 0x01
2135 #define I40E_AQ_LB_PHY_REMOTE 0x02
2136 #define I40E_AQ_LB_MAC_LOCAL 0x04
2140 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
2142 /* Set PHY Debug command (0x0622) */
2143 struct i40e_aqc_set_phy_debug {
2145 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
2146 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
2147 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
2148 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2149 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
2150 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
2151 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
2152 /* Disable link manageability on a single port */
2153 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
2154 /* Disable link manageability on all ports needs both bits 4 and 5 */
2155 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
2159 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
2161 enum i40e_aq_phy_reg_type {
2162 I40E_AQC_PHY_REG_INTERNAL = 0x1,
2163 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
2164 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2167 /* Run PHY Activity (0x0626) */
2168 struct i40e_aqc_run_phy_activity {
2177 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
2179 /* Set PHY Register command (0x0628) */
2180 /* Get PHY Register command (0x0629) */
2181 struct i40e_aqc_phy_register_access {
2183 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0
2184 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
2185 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
2193 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
2195 /* NVM Read command (indirect 0x0701)
2196 * NVM Erase commands (direct 0x0702)
2197 * NVM Update commands (indirect 0x0703)
2199 struct i40e_aqc_nvm_update {
2201 #define I40E_AQ_NVM_LAST_CMD 0x01
2202 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2203 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
2204 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03
2205 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
2206 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
2214 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2216 /* NVM Config Read (indirect 0x0704) */
2217 struct i40e_aqc_nvm_config_read {
2219 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2220 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2221 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2222 __le16 element_count;
2223 __le16 element_id; /* Feature/field ID */
2224 __le16 element_id_msw; /* MSWord of field ID */
2225 __le32 address_high;
2229 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2231 /* NVM Config Write (indirect 0x0705) */
2232 struct i40e_aqc_nvm_config_write {
2234 __le16 element_count;
2236 __le32 address_high;
2240 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2242 /* Used for 0x0704 as well as for 0x0705 commands */
2243 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2244 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2245 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2246 #define I40E_AQ_ANVM_FEATURE 0
2247 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
2248 struct i40e_aqc_nvm_config_data_feature {
2250 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2251 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2252 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2253 __le16 feature_options;
2254 __le16 feature_selection;
2257 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2259 struct i40e_aqc_nvm_config_data_immediate_field {
2262 __le16 field_options;
2266 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2268 /* OEM Post Update (indirect 0x0720)
2269 * no command data struct used
2271 struct i40e_aqc_nvm_oem_post_update {
2272 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2277 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2279 struct i40e_aqc_nvm_oem_post_update_buffer {
2286 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2288 /* Thermal Sensor (indirect 0x0721)
2289 * read or set thermal sensor configs and values
2290 * takes a sensor and command specific data buffer, not detailed here
2292 struct i40e_aqc_thermal_sensor {
2294 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2295 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2296 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2302 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2304 /* Send to PF command (indirect 0x0801) id is only used by PF
2305 * Send to VF command (indirect 0x0802) id is only used by PF
2306 * Send to Peer PF command (indirect 0x0803)
2308 struct i40e_aqc_pf_vf_message {
2315 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2317 /* Alternate structure */
2319 /* Direct write (direct 0x0900)
2320 * Direct read (direct 0x0902)
2322 struct i40e_aqc_alternate_write {
2329 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2331 /* Indirect write (indirect 0x0901)
2332 * Indirect read (indirect 0x0903)
2335 struct i40e_aqc_alternate_ind_write {
2342 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2344 /* Done alternate write (direct 0x0904)
2347 struct i40e_aqc_alternate_write_done {
2349 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2350 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2351 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2352 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2356 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2358 /* Set OEM mode (direct 0x0905) */
2359 struct i40e_aqc_alternate_set_mode {
2361 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2362 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2366 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2368 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2370 /* async events 0x10xx */
2372 /* Lan Queue Overflow Event (direct, 0x1001) */
2373 struct i40e_aqc_lan_overflow {
2374 __le32 prtdcb_rupto;
2379 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2381 /* Get LLDP MIB (indirect 0x0A00) */
2382 struct i40e_aqc_lldp_get_mib {
2385 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2386 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2387 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2388 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2389 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2390 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2391 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2392 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2393 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2394 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2395 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2403 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2405 /* Configure LLDP MIB Change Event (direct 0x0A01)
2406 * also used for the event (with type in the command field)
2408 struct i40e_aqc_lldp_update_mib {
2410 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2411 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2417 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2419 /* Add LLDP TLV (indirect 0x0A02)
2420 * Delete LLDP TLV (indirect 0x0A04)
2422 struct i40e_aqc_lldp_add_tlv {
2423 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2431 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2433 /* Update LLDP TLV (indirect 0x0A03) */
2434 struct i40e_aqc_lldp_update_tlv {
2435 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2444 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2446 /* Stop LLDP (direct 0x0A05) */
2447 struct i40e_aqc_lldp_stop {
2449 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2450 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2454 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2456 /* Start LLDP (direct 0x0A06) */
2458 struct i40e_aqc_lldp_start {
2460 #define I40E_AQ_LLDP_AGENT_START 0x1
2464 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2466 /* Set DCB (direct 0x0303) */
2467 struct i40e_aqc_set_dcb_parameters {
2469 #define I40E_AQ_DCB_SET_AGENT 0x1
2470 #define I40E_DCB_VALID 0x1
2475 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2477 /* Get CEE DCBX Oper Config (0x0A07)
2478 * uses the generic descriptor struct
2479 * returns below as indirect response
2482 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2483 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2484 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2485 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2486 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2487 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2489 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2490 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2491 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2492 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2493 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2494 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2495 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2496 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2497 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2498 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2499 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2500 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2502 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2503 * word boundary layout issues, which the Linux compilers silently deal
2504 * with by adding padding, making the actual struct larger than designed.
2505 * However, the FW compiler for the NIC is less lenient and complains
2506 * about the struct. Hence, the struct defined here has an extra byte in
2507 * fields reserved3 and reserved4 to directly acknowledge that padding,
2508 * and the new length is used in the length check macro.
2510 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2518 __le16 oper_app_prio;
2523 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2525 struct i40e_aqc_get_cee_dcb_cfg_resp {
2530 __le16 oper_app_prio;
2535 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2537 /* Set Local LLDP MIB (indirect 0x0A08)
2538 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2540 struct i40e_aqc_lldp_set_local_mib {
2541 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2542 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2543 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2544 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2545 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2546 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2547 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2548 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2553 __le32 address_high;
2557 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2559 struct i40e_aqc_lldp_set_local_mib_resp {
2560 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
2565 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
2567 /* Stop/Start LLDP Agent (direct 0x0A09)
2568 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2570 struct i40e_aqc_lldp_stop_start_specific_agent {
2571 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2572 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2573 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2578 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2580 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2581 struct i40e_aqc_add_udp_tunnel {
2585 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2586 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2587 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2588 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2592 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2594 struct i40e_aqc_add_udp_tunnel_completion {
2596 u8 filter_entry_index;
2598 #define I40E_AQC_SINGLE_PF 0x0
2599 #define I40E_AQC_MULTIPLE_PFS 0x1
2604 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2606 /* remove UDP Tunnel command (0x0B01) */
2607 struct i40e_aqc_remove_udp_tunnel {
2609 u8 index; /* 0 to 15 */
2613 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2615 struct i40e_aqc_del_udp_tunnel_completion {
2617 u8 index; /* 0 to 15 */
2619 u8 total_filters_used;
2623 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2625 struct i40e_aqc_get_set_rss_key {
2626 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2627 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2628 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2629 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2636 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2638 struct i40e_aqc_get_set_rss_key_data {
2639 u8 standard_rss_key[0x28];
2640 u8 extended_hash_key[0xc];
2643 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2645 struct i40e_aqc_get_set_rss_lut {
2646 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2647 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2648 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2649 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2651 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2652 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2653 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2655 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2656 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2663 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2665 /* tunnel key structure 0x0B10 */
2667 struct i40e_aqc_tunnel_key_structure {
2670 u8 key1_len; /* 0 to 15 */
2671 u8 key2_len; /* 0 to 15 */
2673 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2674 /* response flags */
2675 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2676 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2677 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2678 u8 network_key_index;
2679 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2680 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2681 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2682 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2686 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2688 /* OEM mode commands (direct 0xFE0x) */
2689 struct i40e_aqc_oem_param_change {
2691 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2692 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2693 #define I40E_AQ_OEM_PARAM_MAC 2
2694 __le32 param_value1;
2695 __le16 param_value2;
2699 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2701 struct i40e_aqc_oem_state_change {
2703 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2704 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2708 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2710 /* Initialize OCSD (0xFE02, direct) */
2711 struct i40e_aqc_opc_oem_ocsd_initialize {
2714 __le32 ocsd_memory_block_addr_high;
2715 __le32 ocsd_memory_block_addr_low;
2716 __le32 requested_update_interval;
2719 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2721 /* Initialize OCBB (0xFE03, direct) */
2722 struct i40e_aqc_opc_oem_ocbb_initialize {
2725 __le32 ocbb_memory_block_addr_high;
2726 __le32 ocbb_memory_block_addr_low;
2730 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2732 /* debug commands */
2734 /* get device id (0xFF00) uses the generic structure */
2736 /* set test more (0xFF01, internal) */
2738 struct i40e_acq_set_test_mode {
2740 #define I40E_AQ_TEST_PARTIAL 0
2741 #define I40E_AQ_TEST_FULL 1
2742 #define I40E_AQ_TEST_NVM 2
2745 #define I40E_AQ_TEST_OPEN 0
2746 #define I40E_AQ_TEST_CLOSE 1
2747 #define I40E_AQ_TEST_INC 2
2749 __le32 address_high;
2753 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2755 /* Debug Read Register command (0xFF03)
2756 * Debug Write Register command (0xFF04)
2758 struct i40e_aqc_debug_reg_read_write {
2765 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2767 /* Scatter/gather Reg Read (indirect 0xFF05)
2768 * Scatter/gather Reg Write (indirect 0xFF06)
2771 /* i40e_aq_desc is used for the command */
2772 struct i40e_aqc_debug_reg_sg_element_data {
2777 /* Debug Modify register (direct 0xFF07) */
2778 struct i40e_aqc_debug_modify_reg {
2785 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2787 /* dump internal data (0xFF08, indirect) */
2789 #define I40E_AQ_CLUSTER_ID_AUX 0
2790 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2791 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2792 #define I40E_AQ_CLUSTER_ID_HMC 3
2793 #define I40E_AQ_CLUSTER_ID_MAC0 4
2794 #define I40E_AQ_CLUSTER_ID_MAC1 5
2795 #define I40E_AQ_CLUSTER_ID_MAC2 6
2796 #define I40E_AQ_CLUSTER_ID_MAC3 7
2797 #define I40E_AQ_CLUSTER_ID_DCB 8
2798 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2799 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2800 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2802 struct i40e_aqc_debug_dump_internals {
2807 __le32 address_high;
2811 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2813 struct i40e_aqc_debug_modify_internals {
2815 u8 cluster_specific_params[7];
2816 __le32 address_high;
2820 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2822 #endif /* _I40E_ADMINQ_CMD_H_ */