1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ***************************************************************************/
34 #ifndef _I40E_ADMINQ_CMD_H_
35 #define _I40E_ADMINQ_CMD_H_
37 /* This header file defines the i40e Admin Queue commands and is shared between
38 * i40e Firmware and Software.
40 * This file needs to comply with the Linux Kernel coding style.
43 #define I40E_FW_API_VERSION_MAJOR 0x0001
44 #define I40E_FW_API_VERSION_MINOR 0x0005
70 /* Flags sub-structure
71 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
72 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
75 /* command flags and offsets*/
76 #define I40E_AQ_FLAG_DD_SHIFT 0
77 #define I40E_AQ_FLAG_CMP_SHIFT 1
78 #define I40E_AQ_FLAG_ERR_SHIFT 2
79 #define I40E_AQ_FLAG_VFE_SHIFT 3
80 #define I40E_AQ_FLAG_LB_SHIFT 9
81 #define I40E_AQ_FLAG_RD_SHIFT 10
82 #define I40E_AQ_FLAG_VFC_SHIFT 11
83 #define I40E_AQ_FLAG_BUF_SHIFT 12
84 #define I40E_AQ_FLAG_SI_SHIFT 13
85 #define I40E_AQ_FLAG_EI_SHIFT 14
86 #define I40E_AQ_FLAG_FE_SHIFT 15
88 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
89 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
90 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
91 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
92 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
93 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
94 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
95 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
96 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
97 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
98 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
101 enum i40e_admin_queue_err {
102 I40E_AQ_RC_OK = 0, /* success */
103 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
104 I40E_AQ_RC_ENOENT = 2, /* No such element */
105 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
106 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
107 I40E_AQ_RC_EIO = 5, /* I/O error */
108 I40E_AQ_RC_ENXIO = 6, /* No such resource */
109 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
110 I40E_AQ_RC_EAGAIN = 8, /* Try again */
111 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
112 I40E_AQ_RC_EACCES = 10, /* Permission denied */
113 I40E_AQ_RC_EFAULT = 11, /* Bad address */
114 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
115 I40E_AQ_RC_EEXIST = 13, /* object already exists */
116 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
117 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
118 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
119 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
120 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
121 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
122 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
123 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
124 I40E_AQ_RC_EFBIG = 22, /* File too large */
127 /* Admin Queue command opcodes */
128 enum i40e_admin_queue_opc {
130 i40e_aqc_opc_get_version = 0x0001,
131 i40e_aqc_opc_driver_version = 0x0002,
132 i40e_aqc_opc_queue_shutdown = 0x0003,
133 i40e_aqc_opc_set_pf_context = 0x0004,
135 /* resource ownership */
136 i40e_aqc_opc_request_resource = 0x0008,
137 i40e_aqc_opc_release_resource = 0x0009,
139 i40e_aqc_opc_list_func_capabilities = 0x000A,
140 i40e_aqc_opc_list_dev_capabilities = 0x000B,
144 i40e_aqc_opc_set_proxy_config = 0x0104,
145 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
149 i40e_aqc_opc_mac_address_read = 0x0107,
150 i40e_aqc_opc_mac_address_write = 0x0108,
153 i40e_aqc_opc_clear_pxe_mode = 0x0110,
157 i40e_aqc_opc_set_wol_filter = 0x0120,
158 i40e_aqc_opc_get_wake_reason = 0x0121,
161 /* internal switch commands */
162 i40e_aqc_opc_get_switch_config = 0x0200,
163 i40e_aqc_opc_add_statistics = 0x0201,
164 i40e_aqc_opc_remove_statistics = 0x0202,
165 i40e_aqc_opc_set_port_parameters = 0x0203,
166 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
167 i40e_aqc_opc_set_switch_config = 0x0205,
168 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
169 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
171 i40e_aqc_opc_add_vsi = 0x0210,
172 i40e_aqc_opc_update_vsi_parameters = 0x0211,
173 i40e_aqc_opc_get_vsi_parameters = 0x0212,
175 i40e_aqc_opc_add_pv = 0x0220,
176 i40e_aqc_opc_update_pv_parameters = 0x0221,
177 i40e_aqc_opc_get_pv_parameters = 0x0222,
179 i40e_aqc_opc_add_veb = 0x0230,
180 i40e_aqc_opc_update_veb_parameters = 0x0231,
181 i40e_aqc_opc_get_veb_parameters = 0x0232,
183 i40e_aqc_opc_delete_element = 0x0243,
185 i40e_aqc_opc_add_macvlan = 0x0250,
186 i40e_aqc_opc_remove_macvlan = 0x0251,
187 i40e_aqc_opc_add_vlan = 0x0252,
188 i40e_aqc_opc_remove_vlan = 0x0253,
189 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
190 i40e_aqc_opc_add_tag = 0x0255,
191 i40e_aqc_opc_remove_tag = 0x0256,
192 i40e_aqc_opc_add_multicast_etag = 0x0257,
193 i40e_aqc_opc_remove_multicast_etag = 0x0258,
194 i40e_aqc_opc_update_tag = 0x0259,
195 i40e_aqc_opc_add_control_packet_filter = 0x025A,
196 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
197 i40e_aqc_opc_add_cloud_filters = 0x025C,
198 i40e_aqc_opc_remove_cloud_filters = 0x025D,
199 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
201 i40e_aqc_opc_add_mirror_rule = 0x0260,
202 i40e_aqc_opc_delete_mirror_rule = 0x0261,
205 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
206 i40e_aqc_opc_dcb_updated = 0x0302,
209 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
210 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
211 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
212 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
213 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
214 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
216 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
217 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
218 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
219 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
220 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
221 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
222 i40e_aqc_opc_query_port_ets_config = 0x0419,
223 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
224 i40e_aqc_opc_suspend_port_tx = 0x041B,
225 i40e_aqc_opc_resume_port_tx = 0x041C,
226 i40e_aqc_opc_configure_partition_bw = 0x041D,
228 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
229 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
232 i40e_aqc_opc_get_phy_abilities = 0x0600,
233 i40e_aqc_opc_set_phy_config = 0x0601,
234 i40e_aqc_opc_set_mac_config = 0x0603,
235 i40e_aqc_opc_set_link_restart_an = 0x0605,
236 i40e_aqc_opc_get_link_status = 0x0607,
237 i40e_aqc_opc_set_phy_int_mask = 0x0613,
238 i40e_aqc_opc_get_local_advt_reg = 0x0614,
239 i40e_aqc_opc_set_local_advt_reg = 0x0615,
240 i40e_aqc_opc_get_partner_advt = 0x0616,
241 i40e_aqc_opc_set_lb_modes = 0x0618,
242 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
243 i40e_aqc_opc_set_phy_debug = 0x0622,
244 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
245 i40e_aqc_opc_run_phy_activity = 0x0626,
248 i40e_aqc_opc_nvm_read = 0x0701,
249 i40e_aqc_opc_nvm_erase = 0x0702,
250 i40e_aqc_opc_nvm_update = 0x0703,
251 i40e_aqc_opc_nvm_config_read = 0x0704,
252 i40e_aqc_opc_nvm_config_write = 0x0705,
253 i40e_aqc_opc_oem_post_update = 0x0720,
254 i40e_aqc_opc_thermal_sensor = 0x0721,
256 /* virtualization commands */
257 i40e_aqc_opc_send_msg_to_pf = 0x0801,
258 i40e_aqc_opc_send_msg_to_vf = 0x0802,
259 i40e_aqc_opc_send_msg_to_peer = 0x0803,
261 /* alternate structure */
262 i40e_aqc_opc_alternate_write = 0x0900,
263 i40e_aqc_opc_alternate_write_indirect = 0x0901,
264 i40e_aqc_opc_alternate_read = 0x0902,
265 i40e_aqc_opc_alternate_read_indirect = 0x0903,
266 i40e_aqc_opc_alternate_write_done = 0x0904,
267 i40e_aqc_opc_alternate_set_mode = 0x0905,
268 i40e_aqc_opc_alternate_clear_port = 0x0906,
271 i40e_aqc_opc_lldp_get_mib = 0x0A00,
272 i40e_aqc_opc_lldp_update_mib = 0x0A01,
273 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
274 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
275 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
276 i40e_aqc_opc_lldp_stop = 0x0A05,
277 i40e_aqc_opc_lldp_start = 0x0A06,
278 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
279 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
280 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
282 /* Tunnel commands */
283 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
284 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
286 i40e_aqc_opc_set_rss_key = 0x0B02,
287 i40e_aqc_opc_set_rss_lut = 0x0B03,
288 i40e_aqc_opc_get_rss_key = 0x0B04,
289 i40e_aqc_opc_get_rss_lut = 0x0B05,
293 i40e_aqc_opc_event_lan_overflow = 0x1001,
296 i40e_aqc_opc_oem_parameter_change = 0xFE00,
297 i40e_aqc_opc_oem_device_status_change = 0xFE01,
298 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
299 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
302 i40e_aqc_opc_debug_read_reg = 0xFF03,
303 i40e_aqc_opc_debug_write_reg = 0xFF04,
304 i40e_aqc_opc_debug_modify_reg = 0xFF07,
305 i40e_aqc_opc_debug_dump_internals = 0xFF08,
308 /* command structures and indirect data structures */
310 /* Structure naming conventions:
311 * - no suffix for direct command descriptor structures
312 * - _data for indirect sent data
313 * - _resp for indirect return data (data which is both will use _data)
314 * - _completion for direct return data
315 * - _element_ for repeated elements (may also be _data or _resp)
317 * Command structures are expected to overlay the params.raw member of the basic
318 * descriptor, and as such cannot exceed 16 bytes in length.
321 /* This macro is used to generate a compilation error if a structure
322 * is not exactly the correct length. It gives a divide by zero error if the
323 * structure is not of the correct size, otherwise it creates an enum that is
326 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
327 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
329 /* This macro is used extensively to ensure that command structures are 16
330 * bytes in length as they have to map to the raw array of that size.
332 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
334 /* internal (0x00XX) commands */
336 /* Get version (direct 0x0001) */
337 struct i40e_aqc_get_version {
346 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
348 /* Send driver version (indirect 0x0002) */
349 struct i40e_aqc_driver_version {
353 u8 driver_subbuild_ver;
359 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
361 /* Queue Shutdown (direct 0x0003) */
362 struct i40e_aqc_queue_shutdown {
363 __le32 driver_unloading;
364 #define I40E_AQ_DRIVER_UNLOADING 0x1
368 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
370 /* Set PF context (0x0004, direct) */
371 struct i40e_aqc_set_pf_context {
376 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
378 /* Request resource ownership (direct 0x0008)
379 * Release resource ownership (direct 0x0009)
381 #define I40E_AQ_RESOURCE_NVM 1
382 #define I40E_AQ_RESOURCE_SDP 2
383 #define I40E_AQ_RESOURCE_ACCESS_READ 1
384 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
385 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
386 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
388 struct i40e_aqc_request_resource {
392 __le32 resource_number;
396 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
398 /* Get function capabilities (indirect 0x000A)
399 * Get device capabilities (indirect 0x000B)
401 struct i40e_aqc_list_capabilites {
403 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
411 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
413 struct i40e_aqc_list_capabilities_element_resp {
425 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
426 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
427 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
428 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
429 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
430 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
431 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
432 #define I40E_AQ_CAP_ID_SRIOV 0x0012
433 #define I40E_AQ_CAP_ID_VF 0x0013
434 #define I40E_AQ_CAP_ID_VMDQ 0x0014
435 #define I40E_AQ_CAP_ID_8021QBG 0x0015
436 #define I40E_AQ_CAP_ID_8021QBR 0x0016
437 #define I40E_AQ_CAP_ID_VSI 0x0017
438 #define I40E_AQ_CAP_ID_DCB 0x0018
439 #define I40E_AQ_CAP_ID_FCOE 0x0021
440 #define I40E_AQ_CAP_ID_ISCSI 0x0022
441 #define I40E_AQ_CAP_ID_RSS 0x0040
442 #define I40E_AQ_CAP_ID_RXQ 0x0041
443 #define I40E_AQ_CAP_ID_TXQ 0x0042
444 #define I40E_AQ_CAP_ID_MSIX 0x0043
445 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
446 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
447 #define I40E_AQ_CAP_ID_1588 0x0046
448 #define I40E_AQ_CAP_ID_IWARP 0x0051
449 #define I40E_AQ_CAP_ID_LED 0x0061
450 #define I40E_AQ_CAP_ID_SDP 0x0062
451 #define I40E_AQ_CAP_ID_MDIO 0x0063
452 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
453 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
454 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
455 #define I40E_AQ_CAP_ID_CEM 0x00F2
457 /* Set CPPM Configuration (direct 0x0103) */
458 struct i40e_aqc_cppm_configuration {
459 __le16 command_flags;
460 #define I40E_AQ_CPPM_EN_LTRC 0x0800
461 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
462 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
463 #define I40E_AQ_CPPM_EN_HPTC 0x4000
464 #define I40E_AQ_CPPM_EN_DMARC 0x8000
473 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
475 /* Set ARP Proxy command / response (indirect 0x0104) */
476 struct i40e_aqc_arp_proxy_data {
477 __le16 command_flags;
478 #define I40E_AQ_ARP_INIT_IPV4 0x0008
479 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
480 #define I40E_AQ_ARP_ENA 0x0020
481 #define I40E_AQ_ARP_ADD_IPV4 0x0040
482 #define I40E_AQ_ARP_DEL_IPV4 0x0080
490 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
492 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
493 struct i40e_aqc_ns_proxy_data {
494 __le16 table_idx_mac_addr_0;
495 __le16 table_idx_mac_addr_1;
496 __le16 table_idx_ipv6_0;
497 __le16 table_idx_ipv6_1;
499 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
500 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
501 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
502 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
503 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
504 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
505 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
506 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
507 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
508 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
509 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
512 u8 local_mac_addr[6];
513 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
517 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
519 /* Manage LAA Command (0x0106) - obsolete */
520 struct i40e_aqc_mng_laa {
521 __le16 command_flags;
522 #define I40E_AQ_LAA_FLAG_WR 0x8000
529 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
531 /* Manage MAC Address Read Command (indirect 0x0107) */
532 struct i40e_aqc_mac_address_read {
533 __le16 command_flags;
534 #define I40E_AQC_LAN_ADDR_VALID 0x10
535 #define I40E_AQC_SAN_ADDR_VALID 0x20
536 #define I40E_AQC_PORT_ADDR_VALID 0x40
537 #define I40E_AQC_WOL_ADDR_VALID 0x80
538 #define I40E_AQC_MC_MAG_EN_VALID 0x100
539 #define I40E_AQC_ADDR_VALID_MASK 0x1F0
545 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
547 struct i40e_aqc_mac_address_read_data {
554 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
556 /* Manage MAC Address Write Command (0x0108) */
557 struct i40e_aqc_mac_address_write {
558 __le16 command_flags;
559 #define I40E_AQC_MC_MAG_EN 0x0100
560 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
561 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
562 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
563 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
564 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
571 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
573 /* PXE commands (0x011x) */
575 /* Clear PXE Command and response (direct 0x0110) */
576 struct i40e_aqc_clear_pxe {
581 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
584 /* Set WoL Filter (0x0120) */
586 struct i40e_aqc_set_wol_filter {
588 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
589 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
590 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
591 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
593 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
594 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
595 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
597 #define I40E_AQC_SET_WOL_FILTER 0x8000
598 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
599 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
600 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
602 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
603 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
609 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
611 struct i40e_aqc_set_wol_filter_data {
616 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
618 /* Get Wake Reason (0x0121) */
620 struct i40e_aqc_get_wake_reason_completion {
623 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
624 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
625 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
626 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
627 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
628 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
632 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
634 #endif /* X722_SUPPORT */
635 /* Switch configuration commands (0x02xx) */
637 /* Used by many indirect commands that only pass an seid and a buffer in the
640 struct i40e_aqc_switch_seid {
647 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
649 /* Get Switch Configuration command (indirect 0x0200)
650 * uses i40e_aqc_switch_seid for the descriptor
652 struct i40e_aqc_get_switch_config_header_resp {
658 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
660 struct i40e_aqc_switch_config_element_resp {
662 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
663 #define I40E_AQ_SW_ELEM_TYPE_PF 2
664 #define I40E_AQ_SW_ELEM_TYPE_VF 3
665 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
666 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
667 #define I40E_AQ_SW_ELEM_TYPE_PV 16
668 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
669 #define I40E_AQ_SW_ELEM_TYPE_PA 18
670 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
672 #define I40E_AQ_SW_ELEM_REV_1 1
675 __le16 downlink_seid;
678 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
679 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
680 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
685 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
687 /* Get Switch Configuration (indirect 0x0200)
688 * an array of elements are returned in the response buffer
689 * the first in the array is the header, remainder are elements
691 struct i40e_aqc_get_switch_config_resp {
692 struct i40e_aqc_get_switch_config_header_resp header;
693 struct i40e_aqc_switch_config_element_resp element[1];
696 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
698 /* Add Statistics (direct 0x0201)
699 * Remove Statistics (direct 0x0202)
701 struct i40e_aqc_add_remove_statistics {
708 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
710 /* Set Port Parameters command (direct 0x0203) */
711 struct i40e_aqc_set_port_parameters {
712 __le16 command_flags;
713 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
714 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
715 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
716 __le16 bad_frame_vsi;
717 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
718 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
719 __le16 default_seid; /* reserved for command */
723 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
725 /* Get Switch Resource Allocation (indirect 0x0204) */
726 struct i40e_aqc_get_switch_resource_alloc {
727 u8 num_entries; /* reserved for command */
733 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
735 /* expect an array of these structs in the response buffer */
736 struct i40e_aqc_switch_resource_alloc_element_resp {
738 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
739 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
740 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
741 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
742 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
743 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
744 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
745 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
746 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
747 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
748 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
749 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
750 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
751 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
752 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
753 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
754 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
755 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
756 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
761 __le16 total_unalloced;
765 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
767 /* Set Switch Configuration (direct 0x0205) */
768 struct i40e_aqc_set_switch_config {
770 /* flags used for both fields below */
771 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
772 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
777 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
779 /* Read Receive control registers (direct 0x0206)
780 * Write Receive control registers (direct 0x0207)
781 * used for accessing Rx control registers that can be
782 * slow and need special handling when under high Rx load
784 struct i40e_aqc_rx_ctl_reg_read_write {
791 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
793 /* Add VSI (indirect 0x0210)
794 * this indirect command uses struct i40e_aqc_vsi_properties_data
795 * as the indirect buffer (128 bytes)
797 * Update VSI (indirect 0x211)
798 * uses the same data structure as Add VSI
800 * Get VSI (indirect 0x0212)
801 * uses the same completion and data structure as Add VSI
803 struct i40e_aqc_add_get_update_vsi {
806 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
807 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
808 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
813 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
814 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
815 #define I40E_AQ_VSI_TYPE_VF 0x0
816 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
817 #define I40E_AQ_VSI_TYPE_PF 0x2
818 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
819 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
824 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
826 struct i40e_aqc_add_get_update_vsi_completion {
835 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
837 struct i40e_aqc_vsi_properties_data {
838 /* first 96 byte are written by SW */
839 __le16 valid_sections;
840 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
841 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
842 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
843 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
844 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
845 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
846 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
847 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
848 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
849 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
851 __le16 switch_id; /* 12bit id combined with flags below */
852 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
853 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
854 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
855 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
856 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
858 /* security section */
860 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
861 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
862 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
865 __le16 pvid; /* VLANS include priority bits */
868 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
869 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
870 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
871 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
872 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
873 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
874 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
875 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
876 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
877 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
878 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
879 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
880 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
881 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
882 u8 pvlan_reserved[3];
883 /* ingress egress up sections */
884 __le32 ingress_table; /* bitmap, 3 bits per up */
885 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
886 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
887 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
888 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
889 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
890 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
891 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
892 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
893 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
894 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
895 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
896 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
897 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
898 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
899 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
900 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
901 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
902 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
903 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
904 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
905 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
906 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
907 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
908 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
909 __le32 egress_table; /* same defines as for ingress table */
910 /* cascaded PV section */
913 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
914 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
915 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
916 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
917 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
918 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
919 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
920 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
921 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
923 /* queue mapping section */
924 __le16 mapping_flags;
925 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
926 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
927 __le16 queue_mapping[16];
928 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
929 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
930 __le16 tc_mapping[8];
931 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
932 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
933 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
934 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
935 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
936 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
937 /* queueing option section */
938 u8 queueing_opt_flags;
940 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
941 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
943 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
944 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
946 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
947 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
949 u8 queueing_opt_reserved[3];
950 /* scheduler section */
953 /* outer up section */
954 __le32 outer_up_table; /* same structure and defines as ingress tbl */
956 /* last 32 bytes are written by FW */
958 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
959 __le16 stat_counter_idx;
961 u8 resp_reserved[12];
964 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
966 /* Add Port Virtualizer (direct 0x0220)
967 * also used for update PV (direct 0x0221) but only flags are used
968 * (IS_CTRL_PORT only works on add PV)
970 struct i40e_aqc_add_update_pv {
971 __le16 command_flags;
972 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
973 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
974 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
975 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
977 __le16 connected_seid;
981 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
983 struct i40e_aqc_add_update_pv_completion {
984 /* reserved for update; for add also encodes error if rc == ENOSPC */
986 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
987 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
988 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
989 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
993 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
995 /* Get PV Params (direct 0x0222)
996 * uses i40e_aqc_switch_seid for the descriptor
999 struct i40e_aqc_get_pv_params_completion {
1001 __le16 default_stag;
1002 __le16 pv_flags; /* same flags as add_pv */
1003 #define I40E_AQC_GET_PV_PV_TYPE 0x1
1004 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1005 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1007 __le16 default_port_seid;
1010 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1012 /* Add VEB (direct 0x0230) */
1013 struct i40e_aqc_add_veb {
1015 __le16 downlink_seid;
1017 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1018 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1019 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1020 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1021 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1022 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1023 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1024 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1029 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1031 struct i40e_aqc_add_veb_completion {
1034 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1036 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1037 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1038 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1039 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1040 __le16 statistic_index;
1045 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1047 /* Get VEB Parameters (direct 0x0232)
1048 * uses i40e_aqc_switch_seid for the descriptor
1050 struct i40e_aqc_get_veb_parameters_completion {
1053 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1054 __le16 statistic_index;
1060 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1062 /* Delete Element (direct 0x0243)
1063 * uses the generic i40e_aqc_switch_seid
1066 /* Add MAC-VLAN (indirect 0x0250) */
1068 /* used for the command for most vlan commands */
1069 struct i40e_aqc_macvlan {
1070 __le16 num_addresses;
1072 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1073 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1074 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1075 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1080 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1082 /* indirect data for command and response */
1083 struct i40e_aqc_add_macvlan_element_data {
1087 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1088 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1089 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1090 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1091 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1092 __le16 queue_number;
1093 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1094 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1095 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1096 /* response section */
1098 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1099 #define I40E_AQC_MM_HASH_MATCH 0x02
1100 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1104 struct i40e_aqc_add_remove_macvlan_completion {
1105 __le16 perfect_mac_used;
1106 __le16 perfect_mac_free;
1107 __le16 unicast_hash_free;
1108 __le16 multicast_hash_free;
1113 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1115 /* Remove MAC-VLAN (indirect 0x0251)
1116 * uses i40e_aqc_macvlan for the descriptor
1117 * data points to an array of num_addresses of elements
1120 struct i40e_aqc_remove_macvlan_element_data {
1124 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1125 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1126 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1127 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1131 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1132 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1133 u8 reply_reserved[3];
1136 /* Add VLAN (indirect 0x0252)
1137 * Remove VLAN (indirect 0x0253)
1138 * use the generic i40e_aqc_macvlan for the command
1140 struct i40e_aqc_add_remove_vlan_element_data {
1143 /* flags for add VLAN */
1144 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1145 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1146 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1147 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1148 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1149 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1150 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1151 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1152 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1153 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1154 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1155 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1156 /* flags for remove VLAN */
1157 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1160 /* flags for add VLAN */
1161 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1162 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1163 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1164 /* flags for remove VLAN */
1165 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1166 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1170 struct i40e_aqc_add_remove_vlan_completion {
1178 /* Set VSI Promiscuous Modes (direct 0x0254) */
1179 struct i40e_aqc_set_vsi_promiscuous_modes {
1180 __le16 promiscuous_flags;
1182 /* flags used for both fields above */
1183 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1184 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1185 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1186 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1187 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1188 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1190 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1192 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1193 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1197 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1199 /* Add S/E-tag command (direct 0x0255)
1200 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1202 struct i40e_aqc_add_tag {
1204 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1206 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1207 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1208 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1210 __le16 queue_number;
1214 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1216 struct i40e_aqc_add_remove_tag_completion {
1222 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1224 /* Remove S/E-tag command (direct 0x0256)
1225 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1227 struct i40e_aqc_remove_tag {
1229 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1230 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1231 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1236 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1238 /* Add multicast E-Tag (direct 0x0257)
1239 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1240 * and no external data
1242 struct i40e_aqc_add_remove_mcast_etag {
1245 u8 num_unicast_etags;
1247 __le32 addr_high; /* address of array of 2-byte s-tags */
1251 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1253 struct i40e_aqc_add_remove_mcast_etag_completion {
1255 __le16 mcast_etags_used;
1256 __le16 mcast_etags_free;
1262 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1264 /* Update S/E-Tag (direct 0x0259) */
1265 struct i40e_aqc_update_tag {
1267 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1268 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1269 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1275 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1277 struct i40e_aqc_update_tag_completion {
1283 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1285 /* Add Control Packet filter (direct 0x025A)
1286 * Remove Control Packet filter (direct 0x025B)
1287 * uses the i40e_aqc_add_oveb_cloud,
1288 * and the generic direct completion structure
1290 struct i40e_aqc_add_remove_control_packet_filter {
1294 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1295 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1296 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1297 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1298 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1300 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1301 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1302 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1307 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1309 struct i40e_aqc_add_remove_control_packet_filter_completion {
1310 __le16 mac_etype_used;
1312 __le16 mac_etype_free;
1317 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1319 /* Add Cloud filters (indirect 0x025C)
1320 * Remove Cloud filters (indirect 0x025D)
1321 * uses the i40e_aqc_add_remove_cloud_filters,
1322 * and the generic indirect completion structure
1324 struct i40e_aqc_add_remove_cloud_filters {
1328 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1329 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1330 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1336 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1338 struct i40e_aqc_add_remove_cloud_filters_element_data {
1352 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1353 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1354 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1355 /* 0x0000 reserved */
1356 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1357 /* 0x0002 reserved */
1358 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1359 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1360 /* 0x0005 reserved */
1361 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1362 /* 0x0007 reserved */
1363 /* 0x0008 reserved */
1364 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1365 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1366 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1367 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1369 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1370 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1371 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1372 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1373 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1375 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1376 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1377 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1378 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1379 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1380 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1381 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1382 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1384 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1385 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1386 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1390 __le16 queue_number;
1391 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1392 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1393 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1395 /* response section */
1396 u8 allocation_result;
1397 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1398 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1399 u8 response_reserved[7];
1402 struct i40e_aqc_remove_cloud_filters_completion {
1403 __le16 perfect_ovlan_used;
1404 __le16 perfect_ovlan_free;
1411 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1413 /* Add Mirror Rule (indirect or direct 0x0260)
1414 * Delete Mirror Rule (indirect or direct 0x0261)
1415 * note: some rule types (4,5) do not use an external buffer.
1416 * take care to set the flags correctly.
1418 struct i40e_aqc_add_delete_mirror_rule {
1421 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1422 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1423 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1424 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1425 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1426 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1427 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1428 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1430 __le16 destination; /* VSI for add, rule id for delete */
1431 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1435 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1437 struct i40e_aqc_add_delete_mirror_rule_completion {
1439 __le16 rule_id; /* only used on add */
1440 __le16 mirror_rules_used;
1441 __le16 mirror_rules_free;
1446 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1450 /* PFC Ignore (direct 0x0301)
1451 * the command and response use the same descriptor structure
1453 struct i40e_aqc_pfc_ignore {
1455 u8 command_flags; /* unused on response */
1456 #define I40E_AQC_PFC_IGNORE_SET 0x80
1457 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1461 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1463 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1464 * with no parameters
1467 /* TX scheduler 0x04xx */
1469 /* Almost all the indirect commands use
1470 * this generic struct to pass the SEID in param0
1472 struct i40e_aqc_tx_sched_ind {
1479 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1481 /* Several commands respond with a set of queue set handles */
1482 struct i40e_aqc_qs_handles_resp {
1483 __le16 qs_handles[8];
1486 /* Configure VSI BW limits (direct 0x0400) */
1487 struct i40e_aqc_configure_vsi_bw_limit {
1492 u8 max_credit; /* 0-3, limit = 2^max */
1496 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1498 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1499 * responds with i40e_aqc_qs_handles_resp
1501 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1504 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1506 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1507 __le16 tc_bw_max[2];
1511 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1513 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1514 * responds with i40e_aqc_qs_handles_resp
1516 struct i40e_aqc_configure_vsi_tc_bw_data {
1519 u8 tc_bw_credits[8];
1521 __le16 qs_handles[8];
1524 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1526 /* Query vsi bw configuration (indirect 0x0408) */
1527 struct i40e_aqc_query_vsi_bw_config_resp {
1529 u8 tc_suspended_bits;
1531 __le16 qs_handles[8];
1533 __le16 port_bw_limit;
1535 u8 max_bw; /* 0-3, limit = 2^max */
1539 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1541 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1542 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1545 u8 share_credits[8];
1548 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1549 __le16 tc_bw_max[2];
1552 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1554 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1555 struct i40e_aqc_configure_switching_comp_bw_limit {
1560 u8 max_bw; /* 0-3, limit = 2^max */
1564 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1566 /* Enable Physical Port ETS (indirect 0x0413)
1567 * Modify Physical Port ETS (indirect 0x0414)
1568 * Disable Physical Port ETS (indirect 0x0415)
1570 struct i40e_aqc_configure_switching_comp_ets_data {
1574 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1575 u8 tc_strict_priority_flags;
1577 u8 tc_bw_share_credits[8];
1581 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1583 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1584 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1587 __le16 tc_bw_credit[8];
1589 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1590 __le16 tc_bw_max[2];
1594 I40E_CHECK_STRUCT_LEN(0x40,
1595 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1597 /* Configure Switching Component Bandwidth Allocation per Tc
1600 struct i40e_aqc_configure_switching_comp_bw_config_data {
1603 u8 absolute_credits; /* bool */
1604 u8 tc_bw_share_credits[8];
1608 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1610 /* Query Switching Component Configuration (indirect 0x0418) */
1611 struct i40e_aqc_query_switching_comp_ets_config_resp {
1614 __le16 port_bw_limit;
1616 u8 tc_bw_max; /* 0-3, limit = 2^max */
1620 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1622 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1623 struct i40e_aqc_query_port_ets_config_resp {
1627 u8 tc_strict_priority_bits;
1629 u8 tc_bw_share_credits[8];
1630 __le16 tc_bw_limits[8];
1632 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1633 __le16 tc_bw_max[2];
1637 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1639 /* Query Switching Component Bandwidth Allocation per Traffic Type
1642 struct i40e_aqc_query_switching_comp_bw_config_resp {
1645 u8 absolute_credits_enable; /* bool */
1646 u8 tc_bw_share_credits[8];
1647 __le16 tc_bw_limits[8];
1649 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1650 __le16 tc_bw_max[2];
1653 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1655 /* Suspend/resume port TX traffic
1656 * (direct 0x041B and 0x041C) uses the generic SEID struct
1659 /* Configure partition BW
1662 struct i40e_aqc_configure_partition_bw_data {
1663 __le16 pf_valid_bits;
1664 u8 min_bw[16]; /* guaranteed bandwidth */
1665 u8 max_bw[16]; /* bandwidth limit */
1668 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1670 /* Get and set the active HMC resource profile and status.
1671 * (direct 0x0500) and (direct 0x0501)
1673 struct i40e_aq_get_set_hmc_resource_profile {
1679 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1681 enum i40e_aq_hmc_profile {
1682 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1683 I40E_HMC_PROFILE_DEFAULT = 1,
1684 I40E_HMC_PROFILE_FAVOR_VF = 2,
1685 I40E_HMC_PROFILE_EQUAL = 3,
1688 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1690 /* set in param0 for get phy abilities to report qualified modules */
1691 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1692 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1694 enum i40e_aq_phy_type {
1695 I40E_PHY_TYPE_SGMII = 0x0,
1696 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1697 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1698 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1699 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1700 I40E_PHY_TYPE_XAUI = 0x5,
1701 I40E_PHY_TYPE_XFI = 0x6,
1702 I40E_PHY_TYPE_SFI = 0x7,
1703 I40E_PHY_TYPE_XLAUI = 0x8,
1704 I40E_PHY_TYPE_XLPPI = 0x9,
1705 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1706 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1707 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1708 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1709 I40E_PHY_TYPE_100BASE_TX = 0x11,
1710 I40E_PHY_TYPE_1000BASE_T = 0x12,
1711 I40E_PHY_TYPE_10GBASE_T = 0x13,
1712 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1713 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1714 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1715 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1716 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1717 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1718 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1719 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1720 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1721 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1722 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1723 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1724 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1725 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1726 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1730 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1731 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1732 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1733 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1734 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1735 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1737 enum i40e_aq_link_speed {
1738 I40E_LINK_SPEED_UNKNOWN = 0,
1739 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1740 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1741 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1742 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1743 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT),
1744 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT),
1747 struct i40e_aqc_module_desc {
1755 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1757 struct i40e_aq_get_phy_abilities_resp {
1758 __le32 phy_type; /* bitmap using the above enum for offsets */
1759 u8 link_speed; /* bitmap using the above enum bit patterns */
1761 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1762 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1763 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1764 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1765 #define I40E_AQ_PHY_AN_ENABLED 0x10
1766 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1767 __le16 eee_capability;
1768 #define I40E_AQ_EEE_100BASE_TX 0x0002
1769 #define I40E_AQ_EEE_1000BASE_T 0x0004
1770 #define I40E_AQ_EEE_10GBASE_T 0x0008
1771 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1772 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1773 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1776 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1778 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1779 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1780 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1781 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1786 u8 qualified_module_count;
1787 #define I40E_AQ_PHY_MAX_QMS 16
1788 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1791 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1793 /* Set PHY Config (direct 0x0601) */
1794 struct i40e_aq_set_phy_config { /* same bits as above in all */
1798 /* bits 0-2 use the values from get_phy_abilities_resp */
1799 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1800 #define I40E_AQ_PHY_ENABLE_AN 0x10
1801 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1802 __le16 eee_capability;
1806 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1807 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1808 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1809 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1813 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1815 /* Set MAC Config command data structure (direct 0x0603) */
1816 struct i40e_aq_set_mac_config {
1817 __le16 max_frame_size;
1819 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1820 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1821 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1822 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1823 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1824 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1825 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1826 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1827 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1828 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1829 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1830 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1831 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1832 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1833 u8 tx_timer_priority; /* bitmap */
1834 __le16 tx_timer_value;
1835 __le16 fc_refresh_threshold;
1839 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1841 /* Restart Auto-Negotiation (direct 0x605) */
1842 struct i40e_aqc_set_link_restart_an {
1844 #define I40E_AQ_PHY_RESTART_AN 0x02
1845 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1849 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1851 /* Get Link Status cmd & response data structure (direct 0x0607) */
1852 struct i40e_aqc_get_link_status {
1853 __le16 command_flags; /* only field set on command */
1854 #define I40E_AQ_LSE_MASK 0x3
1855 #define I40E_AQ_LSE_NOP 0x0
1856 #define I40E_AQ_LSE_DISABLE 0x2
1857 #define I40E_AQ_LSE_ENABLE 0x3
1858 /* only response uses this flag */
1859 #define I40E_AQ_LSE_IS_ENABLED 0x1
1860 u8 phy_type; /* i40e_aq_phy_type */
1861 u8 link_speed; /* i40e_aq_link_speed */
1863 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1864 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1865 #define I40E_AQ_LINK_FAULT 0x02
1866 #define I40E_AQ_LINK_FAULT_TX 0x04
1867 #define I40E_AQ_LINK_FAULT_RX 0x08
1868 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1869 #define I40E_AQ_LINK_UP_PORT 0x20
1870 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1871 #define I40E_AQ_SIGNAL_DETECT 0x80
1873 #define I40E_AQ_AN_COMPLETED 0x01
1874 #define I40E_AQ_LP_AN_ABILITY 0x02
1875 #define I40E_AQ_PD_FAULT 0x04
1876 #define I40E_AQ_FEC_EN 0x08
1877 #define I40E_AQ_PHY_LOW_POWER 0x10
1878 #define I40E_AQ_LINK_PAUSE_TX 0x20
1879 #define I40E_AQ_LINK_PAUSE_RX 0x40
1880 #define I40E_AQ_QUALIFIED_MODULE 0x80
1882 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1883 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1884 #define I40E_AQ_LINK_TX_SHIFT 0x02
1885 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1886 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1887 #define I40E_AQ_LINK_TX_DRAINED 0x01
1888 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1889 #define I40E_AQ_LINK_FORCED_40G 0x10
1890 /* 25G Error Codes */
1891 #define I40E_AQ_25G_NO_ERR 0X00
1892 #define I40E_AQ_25G_NOT_PRESENT 0X01
1893 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
1894 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
1895 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
1896 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
1897 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1898 __le16 max_frame_size;
1900 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1901 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1903 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
1904 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
1905 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
1906 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
1907 #define I40E_AQ_PWR_CLASS_MASK 0x03
1911 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1913 /* Set event mask command (direct 0x613) */
1914 struct i40e_aqc_set_phy_int_mask {
1917 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1918 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1919 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1920 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1921 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1922 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1923 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1924 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1925 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1929 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1931 /* Get Local AN advt register (direct 0x0614)
1932 * Set Local AN advt register (direct 0x0615)
1933 * Get Link Partner AN advt register (direct 0x0616)
1935 struct i40e_aqc_an_advt_reg {
1936 __le32 local_an_reg0;
1937 __le16 local_an_reg1;
1941 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1943 /* Set Loopback mode (0x0618) */
1944 struct i40e_aqc_set_lb_mode {
1946 #define I40E_AQ_LB_PHY_LOCAL 0x01
1947 #define I40E_AQ_LB_PHY_REMOTE 0x02
1948 #define I40E_AQ_LB_MAC_LOCAL 0x04
1952 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1954 /* Set PHY Debug command (0x0622) */
1955 struct i40e_aqc_set_phy_debug {
1957 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1958 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1959 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1960 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1961 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1962 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1963 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1964 /* Disable link manageability on a single port */
1965 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1966 /* Disable link manageability on all ports needs both bits 4 and 5 */
1967 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
1971 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1973 enum i40e_aq_phy_reg_type {
1974 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1975 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1976 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1979 /* Run PHY Activity (0x0626) */
1980 struct i40e_aqc_run_phy_activity {
1989 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1991 /* NVM Read command (indirect 0x0701)
1992 * NVM Erase commands (direct 0x0702)
1993 * NVM Update commands (indirect 0x0703)
1995 struct i40e_aqc_nvm_update {
1997 #define I40E_AQ_NVM_LAST_CMD 0x01
1998 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2006 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2008 /* NVM Config Read (indirect 0x0704) */
2009 struct i40e_aqc_nvm_config_read {
2011 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2012 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2013 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2014 __le16 element_count;
2015 __le16 element_id; /* Feature/field ID */
2016 __le16 element_id_msw; /* MSWord of field ID */
2017 __le32 address_high;
2021 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2023 /* NVM Config Write (indirect 0x0705) */
2024 struct i40e_aqc_nvm_config_write {
2026 __le16 element_count;
2028 __le32 address_high;
2032 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2034 /* Used for 0x0704 as well as for 0x0705 commands */
2035 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2036 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2037 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2038 #define I40E_AQ_ANVM_FEATURE 0
2039 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
2040 struct i40e_aqc_nvm_config_data_feature {
2042 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2043 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2044 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2045 __le16 feature_options;
2046 __le16 feature_selection;
2049 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2051 struct i40e_aqc_nvm_config_data_immediate_field {
2054 __le16 field_options;
2058 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2060 /* OEM Post Update (indirect 0x0720)
2061 * no command data struct used
2063 struct i40e_aqc_nvm_oem_post_update {
2064 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2069 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2071 struct i40e_aqc_nvm_oem_post_update_buffer {
2078 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2080 /* Thermal Sensor (indirect 0x0721)
2081 * read or set thermal sensor configs and values
2082 * takes a sensor and command specific data buffer, not detailed here
2084 struct i40e_aqc_thermal_sensor {
2086 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2087 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2088 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2094 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2096 /* Send to PF command (indirect 0x0801) id is only used by PF
2097 * Send to VF command (indirect 0x0802) id is only used by PF
2098 * Send to Peer PF command (indirect 0x0803)
2100 struct i40e_aqc_pf_vf_message {
2107 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2109 /* Alternate structure */
2111 /* Direct write (direct 0x0900)
2112 * Direct read (direct 0x0902)
2114 struct i40e_aqc_alternate_write {
2121 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2123 /* Indirect write (indirect 0x0901)
2124 * Indirect read (indirect 0x0903)
2127 struct i40e_aqc_alternate_ind_write {
2134 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2136 /* Done alternate write (direct 0x0904)
2139 struct i40e_aqc_alternate_write_done {
2141 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2142 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2143 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2144 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2148 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2150 /* Set OEM mode (direct 0x0905) */
2151 struct i40e_aqc_alternate_set_mode {
2153 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2154 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2158 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2160 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2162 /* async events 0x10xx */
2164 /* Lan Queue Overflow Event (direct, 0x1001) */
2165 struct i40e_aqc_lan_overflow {
2166 __le32 prtdcb_rupto;
2171 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2173 /* Get LLDP MIB (indirect 0x0A00) */
2174 struct i40e_aqc_lldp_get_mib {
2177 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2178 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2179 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2180 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2181 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2182 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2183 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2184 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2185 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2186 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2187 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2195 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2197 /* Configure LLDP MIB Change Event (direct 0x0A01)
2198 * also used for the event (with type in the command field)
2200 struct i40e_aqc_lldp_update_mib {
2202 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2203 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2209 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2211 /* Add LLDP TLV (indirect 0x0A02)
2212 * Delete LLDP TLV (indirect 0x0A04)
2214 struct i40e_aqc_lldp_add_tlv {
2215 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2223 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2225 /* Update LLDP TLV (indirect 0x0A03) */
2226 struct i40e_aqc_lldp_update_tlv {
2227 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2236 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2238 /* Stop LLDP (direct 0x0A05) */
2239 struct i40e_aqc_lldp_stop {
2241 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2242 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2246 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2248 /* Start LLDP (direct 0x0A06) */
2250 struct i40e_aqc_lldp_start {
2252 #define I40E_AQ_LLDP_AGENT_START 0x1
2256 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2258 /* Get CEE DCBX Oper Config (0x0A07)
2259 * uses the generic descriptor struct
2260 * returns below as indirect response
2263 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2264 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2265 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2266 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2267 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2268 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2270 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2271 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2272 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2273 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2274 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2275 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2276 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2277 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2278 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2279 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2280 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2281 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2283 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2284 * word boundary layout issues, which the Linux compilers silently deal
2285 * with by adding padding, making the actual struct larger than designed.
2286 * However, the FW compiler for the NIC is less lenient and complains
2287 * about the struct. Hence, the struct defined here has an extra byte in
2288 * fields reserved3 and reserved4 to directly acknowledge that padding,
2289 * and the new length is used in the length check macro.
2291 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2299 __le16 oper_app_prio;
2304 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2306 struct i40e_aqc_get_cee_dcb_cfg_resp {
2311 __le16 oper_app_prio;
2316 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2318 /* Set Local LLDP MIB (indirect 0x0A08)
2319 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2321 struct i40e_aqc_lldp_set_local_mib {
2322 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2323 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2324 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2325 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2326 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2327 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2328 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2329 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2334 __le32 address_high;
2338 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2340 struct i40e_aqc_lldp_set_local_mib_resp {
2341 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
2346 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
2348 /* Stop/Start LLDP Agent (direct 0x0A09)
2349 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2351 struct i40e_aqc_lldp_stop_start_specific_agent {
2352 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2353 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2354 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2359 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2361 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2362 struct i40e_aqc_add_udp_tunnel {
2366 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2367 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2368 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2369 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2373 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2375 struct i40e_aqc_add_udp_tunnel_completion {
2377 u8 filter_entry_index;
2379 #define I40E_AQC_SINGLE_PF 0x0
2380 #define I40E_AQC_MULTIPLE_PFS 0x1
2385 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2387 /* remove UDP Tunnel command (0x0B01) */
2388 struct i40e_aqc_remove_udp_tunnel {
2390 u8 index; /* 0 to 15 */
2394 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2396 struct i40e_aqc_del_udp_tunnel_completion {
2398 u8 index; /* 0 to 15 */
2400 u8 total_filters_used;
2404 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2407 struct i40e_aqc_get_set_rss_key {
2408 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2409 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2410 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2411 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2418 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2420 struct i40e_aqc_get_set_rss_key_data {
2421 u8 standard_rss_key[0x28];
2422 u8 extended_hash_key[0xc];
2425 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2427 struct i40e_aqc_get_set_rss_lut {
2428 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2429 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2430 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2431 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2433 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2434 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2435 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2437 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2438 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2445 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2448 /* tunnel key structure 0x0B10 */
2450 struct i40e_aqc_tunnel_key_structure {
2453 u8 key1_len; /* 0 to 15 */
2454 u8 key2_len; /* 0 to 15 */
2456 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2457 /* response flags */
2458 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2459 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2460 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2461 u8 network_key_index;
2462 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2463 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2464 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2465 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2469 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2471 /* OEM mode commands (direct 0xFE0x) */
2472 struct i40e_aqc_oem_param_change {
2474 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2475 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2476 #define I40E_AQ_OEM_PARAM_MAC 2
2477 __le32 param_value1;
2478 __le16 param_value2;
2482 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2484 struct i40e_aqc_oem_state_change {
2486 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2487 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2491 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2493 /* Initialize OCSD (0xFE02, direct) */
2494 struct i40e_aqc_opc_oem_ocsd_initialize {
2497 __le32 ocsd_memory_block_addr_high;
2498 __le32 ocsd_memory_block_addr_low;
2499 __le32 requested_update_interval;
2502 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2504 /* Initialize OCBB (0xFE03, direct) */
2505 struct i40e_aqc_opc_oem_ocbb_initialize {
2508 __le32 ocbb_memory_block_addr_high;
2509 __le32 ocbb_memory_block_addr_low;
2513 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2515 /* debug commands */
2517 /* get device id (0xFF00) uses the generic structure */
2519 /* set test more (0xFF01, internal) */
2521 struct i40e_acq_set_test_mode {
2523 #define I40E_AQ_TEST_PARTIAL 0
2524 #define I40E_AQ_TEST_FULL 1
2525 #define I40E_AQ_TEST_NVM 2
2528 #define I40E_AQ_TEST_OPEN 0
2529 #define I40E_AQ_TEST_CLOSE 1
2530 #define I40E_AQ_TEST_INC 2
2532 __le32 address_high;
2536 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2538 /* Debug Read Register command (0xFF03)
2539 * Debug Write Register command (0xFF04)
2541 struct i40e_aqc_debug_reg_read_write {
2548 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2550 /* Scatter/gather Reg Read (indirect 0xFF05)
2551 * Scatter/gather Reg Write (indirect 0xFF06)
2554 /* i40e_aq_desc is used for the command */
2555 struct i40e_aqc_debug_reg_sg_element_data {
2560 /* Debug Modify register (direct 0xFF07) */
2561 struct i40e_aqc_debug_modify_reg {
2568 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2570 /* dump internal data (0xFF08, indirect) */
2572 #define I40E_AQ_CLUSTER_ID_AUX 0
2573 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2574 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2575 #define I40E_AQ_CLUSTER_ID_HMC 3
2576 #define I40E_AQ_CLUSTER_ID_MAC0 4
2577 #define I40E_AQ_CLUSTER_ID_MAC1 5
2578 #define I40E_AQ_CLUSTER_ID_MAC2 6
2579 #define I40E_AQ_CLUSTER_ID_MAC3 7
2580 #define I40E_AQ_CLUSTER_ID_DCB 8
2581 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2582 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2583 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2585 struct i40e_aqc_debug_dump_internals {
2590 __le32 address_high;
2594 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2596 struct i40e_aqc_debug_modify_internals {
2598 u8 cluster_specific_params[7];
2599 __le32 address_high;
2603 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2605 #endif /* _I40E_ADMINQ_CMD_H_ */