1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ***************************************************************************/
34 #ifndef _I40E_ADMINQ_CMD_H_
35 #define _I40E_ADMINQ_CMD_H_
37 /* This header file defines the i40e Admin Queue commands and is shared between
38 * i40e Firmware and Software.
40 * This file needs to comply with the Linux Kernel coding style.
43 #define I40E_FW_API_VERSION_MAJOR 0x0001
44 #define I40E_FW_API_VERSION_MINOR 0x0004
70 /* Flags sub-structure
71 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
72 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
75 /* command flags and offsets*/
76 #define I40E_AQ_FLAG_DD_SHIFT 0
77 #define I40E_AQ_FLAG_CMP_SHIFT 1
78 #define I40E_AQ_FLAG_ERR_SHIFT 2
79 #define I40E_AQ_FLAG_VFE_SHIFT 3
80 #define I40E_AQ_FLAG_LB_SHIFT 9
81 #define I40E_AQ_FLAG_RD_SHIFT 10
82 #define I40E_AQ_FLAG_VFC_SHIFT 11
83 #define I40E_AQ_FLAG_BUF_SHIFT 12
84 #define I40E_AQ_FLAG_SI_SHIFT 13
85 #define I40E_AQ_FLAG_EI_SHIFT 14
86 #define I40E_AQ_FLAG_FE_SHIFT 15
88 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
89 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
90 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
91 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
92 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
93 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
94 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
95 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
96 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
97 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
98 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
101 enum i40e_admin_queue_err {
102 I40E_AQ_RC_OK = 0, /* success */
103 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
104 I40E_AQ_RC_ENOENT = 2, /* No such element */
105 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
106 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
107 I40E_AQ_RC_EIO = 5, /* I/O error */
108 I40E_AQ_RC_ENXIO = 6, /* No such resource */
109 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
110 I40E_AQ_RC_EAGAIN = 8, /* Try again */
111 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
112 I40E_AQ_RC_EACCES = 10, /* Permission denied */
113 I40E_AQ_RC_EFAULT = 11, /* Bad address */
114 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
115 I40E_AQ_RC_EEXIST = 13, /* object already exists */
116 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
117 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
118 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
119 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
120 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
121 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
122 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
123 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
124 I40E_AQ_RC_EFBIG = 22, /* File too large */
127 /* Admin Queue command opcodes */
128 enum i40e_admin_queue_opc {
130 i40e_aqc_opc_get_version = 0x0001,
131 i40e_aqc_opc_driver_version = 0x0002,
132 i40e_aqc_opc_queue_shutdown = 0x0003,
133 i40e_aqc_opc_set_pf_context = 0x0004,
135 /* resource ownership */
136 i40e_aqc_opc_request_resource = 0x0008,
137 i40e_aqc_opc_release_resource = 0x0009,
139 i40e_aqc_opc_list_func_capabilities = 0x000A,
140 i40e_aqc_opc_list_dev_capabilities = 0x000B,
144 i40e_aqc_opc_set_proxy_config = 0x0104,
145 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
149 i40e_aqc_opc_mac_address_read = 0x0107,
150 i40e_aqc_opc_mac_address_write = 0x0108,
153 i40e_aqc_opc_clear_pxe_mode = 0x0110,
157 i40e_aqc_opc_set_wol_filter = 0x0120,
158 i40e_aqc_opc_get_wake_reason = 0x0121,
161 /* internal switch commands */
162 i40e_aqc_opc_get_switch_config = 0x0200,
163 i40e_aqc_opc_add_statistics = 0x0201,
164 i40e_aqc_opc_remove_statistics = 0x0202,
165 i40e_aqc_opc_set_port_parameters = 0x0203,
166 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
168 i40e_aqc_opc_add_vsi = 0x0210,
169 i40e_aqc_opc_update_vsi_parameters = 0x0211,
170 i40e_aqc_opc_get_vsi_parameters = 0x0212,
172 i40e_aqc_opc_add_pv = 0x0220,
173 i40e_aqc_opc_update_pv_parameters = 0x0221,
174 i40e_aqc_opc_get_pv_parameters = 0x0222,
176 i40e_aqc_opc_add_veb = 0x0230,
177 i40e_aqc_opc_update_veb_parameters = 0x0231,
178 i40e_aqc_opc_get_veb_parameters = 0x0232,
180 i40e_aqc_opc_delete_element = 0x0243,
182 i40e_aqc_opc_add_macvlan = 0x0250,
183 i40e_aqc_opc_remove_macvlan = 0x0251,
184 i40e_aqc_opc_add_vlan = 0x0252,
185 i40e_aqc_opc_remove_vlan = 0x0253,
186 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
187 i40e_aqc_opc_add_tag = 0x0255,
188 i40e_aqc_opc_remove_tag = 0x0256,
189 i40e_aqc_opc_add_multicast_etag = 0x0257,
190 i40e_aqc_opc_remove_multicast_etag = 0x0258,
191 i40e_aqc_opc_update_tag = 0x0259,
192 i40e_aqc_opc_add_control_packet_filter = 0x025A,
193 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
194 i40e_aqc_opc_add_cloud_filters = 0x025C,
195 i40e_aqc_opc_remove_cloud_filters = 0x025D,
197 i40e_aqc_opc_add_mirror_rule = 0x0260,
198 i40e_aqc_opc_delete_mirror_rule = 0x0261,
201 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
202 i40e_aqc_opc_dcb_updated = 0x0302,
205 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
206 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
207 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
208 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
209 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
210 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
212 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
213 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
214 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
215 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
216 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
217 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
218 i40e_aqc_opc_query_port_ets_config = 0x0419,
219 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
220 i40e_aqc_opc_suspend_port_tx = 0x041B,
221 i40e_aqc_opc_resume_port_tx = 0x041C,
222 i40e_aqc_opc_configure_partition_bw = 0x041D,
225 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
226 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
229 i40e_aqc_opc_get_phy_abilities = 0x0600,
230 i40e_aqc_opc_set_phy_config = 0x0601,
231 i40e_aqc_opc_set_mac_config = 0x0603,
232 i40e_aqc_opc_set_link_restart_an = 0x0605,
233 i40e_aqc_opc_get_link_status = 0x0607,
234 i40e_aqc_opc_set_phy_int_mask = 0x0613,
235 i40e_aqc_opc_get_local_advt_reg = 0x0614,
236 i40e_aqc_opc_set_local_advt_reg = 0x0615,
237 i40e_aqc_opc_get_partner_advt = 0x0616,
238 i40e_aqc_opc_set_lb_modes = 0x0618,
239 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
240 i40e_aqc_opc_set_phy_debug = 0x0622,
241 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
244 i40e_aqc_opc_nvm_read = 0x0701,
245 i40e_aqc_opc_nvm_erase = 0x0702,
246 i40e_aqc_opc_nvm_update = 0x0703,
247 i40e_aqc_opc_nvm_config_read = 0x0704,
248 i40e_aqc_opc_nvm_config_write = 0x0705,
249 i40e_aqc_opc_oem_post_update = 0x0720,
251 /* virtualization commands */
252 i40e_aqc_opc_send_msg_to_pf = 0x0801,
253 i40e_aqc_opc_send_msg_to_vf = 0x0802,
254 i40e_aqc_opc_send_msg_to_peer = 0x0803,
256 /* alternate structure */
257 i40e_aqc_opc_alternate_write = 0x0900,
258 i40e_aqc_opc_alternate_write_indirect = 0x0901,
259 i40e_aqc_opc_alternate_read = 0x0902,
260 i40e_aqc_opc_alternate_read_indirect = 0x0903,
261 i40e_aqc_opc_alternate_write_done = 0x0904,
262 i40e_aqc_opc_alternate_set_mode = 0x0905,
263 i40e_aqc_opc_alternate_clear_port = 0x0906,
266 i40e_aqc_opc_lldp_get_mib = 0x0A00,
267 i40e_aqc_opc_lldp_update_mib = 0x0A01,
268 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
269 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
270 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
271 i40e_aqc_opc_lldp_stop = 0x0A05,
272 i40e_aqc_opc_lldp_start = 0x0A06,
273 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
274 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
275 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
277 /* Tunnel commands */
278 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
279 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
281 i40e_aqc_opc_set_rss_key = 0x0B02,
282 i40e_aqc_opc_set_rss_lut = 0x0B03,
283 i40e_aqc_opc_get_rss_key = 0x0B04,
284 i40e_aqc_opc_get_rss_lut = 0x0B05,
288 i40e_aqc_opc_event_lan_overflow = 0x1001,
291 i40e_aqc_opc_oem_parameter_change = 0xFE00,
292 i40e_aqc_opc_oem_device_status_change = 0xFE01,
293 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
294 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
297 i40e_aqc_opc_debug_read_reg = 0xFF03,
298 i40e_aqc_opc_debug_write_reg = 0xFF04,
299 i40e_aqc_opc_debug_modify_reg = 0xFF07,
300 i40e_aqc_opc_debug_dump_internals = 0xFF08,
303 /* command structures and indirect data structures */
305 /* Structure naming conventions:
306 * - no suffix for direct command descriptor structures
307 * - _data for indirect sent data
308 * - _resp for indirect return data (data which is both will use _data)
309 * - _completion for direct return data
310 * - _element_ for repeated elements (may also be _data or _resp)
312 * Command structures are expected to overlay the params.raw member of the basic
313 * descriptor, and as such cannot exceed 16 bytes in length.
316 /* This macro is used to generate a compilation error if a structure
317 * is not exactly the correct length. It gives a divide by zero error if the
318 * structure is not of the correct size, otherwise it creates an enum that is
321 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
322 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
324 /* This macro is used extensively to ensure that command structures are 16
325 * bytes in length as they have to map to the raw array of that size.
327 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
329 /* internal (0x00XX) commands */
331 /* Get version (direct 0x0001) */
332 struct i40e_aqc_get_version {
341 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
343 /* Send driver version (indirect 0x0002) */
344 struct i40e_aqc_driver_version {
348 u8 driver_subbuild_ver;
354 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
356 /* Queue Shutdown (direct 0x0003) */
357 struct i40e_aqc_queue_shutdown {
358 __le32 driver_unloading;
359 #define I40E_AQ_DRIVER_UNLOADING 0x1
363 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
365 /* Set PF context (0x0004, direct) */
366 struct i40e_aqc_set_pf_context {
371 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
373 /* Request resource ownership (direct 0x0008)
374 * Release resource ownership (direct 0x0009)
376 #define I40E_AQ_RESOURCE_NVM 1
377 #define I40E_AQ_RESOURCE_SDP 2
378 #define I40E_AQ_RESOURCE_ACCESS_READ 1
379 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
380 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
381 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
383 struct i40e_aqc_request_resource {
387 __le32 resource_number;
391 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
393 /* Get function capabilities (indirect 0x000A)
394 * Get device capabilities (indirect 0x000B)
396 struct i40e_aqc_list_capabilites {
398 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
406 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
408 struct i40e_aqc_list_capabilities_element_resp {
420 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
421 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
422 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
423 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
424 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
425 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
426 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
427 #define I40E_AQ_CAP_ID_SRIOV 0x0012
428 #define I40E_AQ_CAP_ID_VF 0x0013
429 #define I40E_AQ_CAP_ID_VMDQ 0x0014
430 #define I40E_AQ_CAP_ID_8021QBG 0x0015
431 #define I40E_AQ_CAP_ID_8021QBR 0x0016
432 #define I40E_AQ_CAP_ID_VSI 0x0017
433 #define I40E_AQ_CAP_ID_DCB 0x0018
434 #define I40E_AQ_CAP_ID_FCOE 0x0021
435 #define I40E_AQ_CAP_ID_ISCSI 0x0022
436 #define I40E_AQ_CAP_ID_RSS 0x0040
437 #define I40E_AQ_CAP_ID_RXQ 0x0041
438 #define I40E_AQ_CAP_ID_TXQ 0x0042
439 #define I40E_AQ_CAP_ID_MSIX 0x0043
440 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
441 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
442 #define I40E_AQ_CAP_ID_1588 0x0046
443 #define I40E_AQ_CAP_ID_IWARP 0x0051
444 #define I40E_AQ_CAP_ID_LED 0x0061
445 #define I40E_AQ_CAP_ID_SDP 0x0062
446 #define I40E_AQ_CAP_ID_MDIO 0x0063
447 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
448 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
449 #define I40E_AQ_CAP_ID_CEM 0x00F2
451 /* Set CPPM Configuration (direct 0x0103) */
452 struct i40e_aqc_cppm_configuration {
453 __le16 command_flags;
454 #define I40E_AQ_CPPM_EN_LTRC 0x0800
455 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
456 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
457 #define I40E_AQ_CPPM_EN_HPTC 0x4000
458 #define I40E_AQ_CPPM_EN_DMARC 0x8000
467 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
469 /* Set ARP Proxy command / response (indirect 0x0104) */
470 struct i40e_aqc_arp_proxy_data {
471 __le16 command_flags;
472 #define I40E_AQ_ARP_INIT_IPV4 0x0008
473 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
474 #define I40E_AQ_ARP_ENA 0x0020
475 #define I40E_AQ_ARP_ADD_IPV4 0x0040
476 #define I40E_AQ_ARP_DEL_IPV4 0x0080
484 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
486 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
487 struct i40e_aqc_ns_proxy_data {
488 __le16 table_idx_mac_addr_0;
489 __le16 table_idx_mac_addr_1;
490 __le16 table_idx_ipv6_0;
491 __le16 table_idx_ipv6_1;
493 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
494 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
495 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
496 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
497 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
498 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
499 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
500 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
501 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
502 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
503 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
506 u8 local_mac_addr[6];
507 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
511 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
513 /* Manage LAA Command (0x0106) - obsolete */
514 struct i40e_aqc_mng_laa {
515 __le16 command_flags;
516 #define I40E_AQ_LAA_FLAG_WR 0x8000
523 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
525 /* Manage MAC Address Read Command (indirect 0x0107) */
526 struct i40e_aqc_mac_address_read {
527 __le16 command_flags;
528 #define I40E_AQC_LAN_ADDR_VALID 0x10
529 #define I40E_AQC_SAN_ADDR_VALID 0x20
530 #define I40E_AQC_PORT_ADDR_VALID 0x40
531 #define I40E_AQC_WOL_ADDR_VALID 0x80
532 #define I40E_AQC_MC_MAG_EN_VALID 0x100
533 #define I40E_AQC_ADDR_VALID_MASK 0x1F0
539 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
541 struct i40e_aqc_mac_address_read_data {
548 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
550 /* Manage MAC Address Write Command (0x0108) */
551 struct i40e_aqc_mac_address_write {
552 __le16 command_flags;
553 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
554 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
555 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
556 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
557 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
564 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
566 /* PXE commands (0x011x) */
568 /* Clear PXE Command and response (direct 0x0110) */
569 struct i40e_aqc_clear_pxe {
574 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
577 /* Set WoL Filter (0x0120) */
579 struct i40e_aqc_set_wol_filter {
581 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
583 #define I40E_AQC_SET_WOL_FILTER 0x8000
584 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
586 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
587 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
593 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
595 /* Get Wake Reason (0x0121) */
597 struct i40e_aqc_get_wake_reason_completion {
603 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
605 struct i40e_aqc_set_wol_filter_data {
610 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
612 #endif /* X722_SUPPORT */
613 /* Switch configuration commands (0x02xx) */
615 /* Used by many indirect commands that only pass an seid and a buffer in the
618 struct i40e_aqc_switch_seid {
625 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
627 /* Get Switch Configuration command (indirect 0x0200)
628 * uses i40e_aqc_switch_seid for the descriptor
630 struct i40e_aqc_get_switch_config_header_resp {
636 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
638 struct i40e_aqc_switch_config_element_resp {
640 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
641 #define I40E_AQ_SW_ELEM_TYPE_PF 2
642 #define I40E_AQ_SW_ELEM_TYPE_VF 3
643 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
644 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
645 #define I40E_AQ_SW_ELEM_TYPE_PV 16
646 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
647 #define I40E_AQ_SW_ELEM_TYPE_PA 18
648 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
650 #define I40E_AQ_SW_ELEM_REV_1 1
653 __le16 downlink_seid;
656 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
657 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
658 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
663 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
665 /* Get Switch Configuration (indirect 0x0200)
666 * an array of elements are returned in the response buffer
667 * the first in the array is the header, remainder are elements
669 struct i40e_aqc_get_switch_config_resp {
670 struct i40e_aqc_get_switch_config_header_resp header;
671 struct i40e_aqc_switch_config_element_resp element[1];
674 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
676 /* Add Statistics (direct 0x0201)
677 * Remove Statistics (direct 0x0202)
679 struct i40e_aqc_add_remove_statistics {
686 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
688 /* Set Port Parameters command (direct 0x0203) */
689 struct i40e_aqc_set_port_parameters {
690 __le16 command_flags;
691 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
692 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
693 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
694 __le16 bad_frame_vsi;
695 __le16 default_seid; /* reserved for command */
699 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
701 /* Get Switch Resource Allocation (indirect 0x0204) */
702 struct i40e_aqc_get_switch_resource_alloc {
703 u8 num_entries; /* reserved for command */
709 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
711 /* expect an array of these structs in the response buffer */
712 struct i40e_aqc_switch_resource_alloc_element_resp {
714 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
715 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
716 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
717 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
718 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
719 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
720 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
721 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
722 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
723 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
724 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
725 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
726 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
727 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
728 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
729 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
730 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
731 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
732 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
737 __le16 total_unalloced;
741 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
743 /* Add VSI (indirect 0x0210)
744 * this indirect command uses struct i40e_aqc_vsi_properties_data
745 * as the indirect buffer (128 bytes)
747 * Update VSI (indirect 0x211)
748 * uses the same data structure as Add VSI
750 * Get VSI (indirect 0x0212)
751 * uses the same completion and data structure as Add VSI
753 struct i40e_aqc_add_get_update_vsi {
756 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
757 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
758 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
763 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
764 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
765 #define I40E_AQ_VSI_TYPE_VF 0x0
766 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
767 #define I40E_AQ_VSI_TYPE_PF 0x2
768 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
769 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
774 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
776 struct i40e_aqc_add_get_update_vsi_completion {
785 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
787 struct i40e_aqc_vsi_properties_data {
788 /* first 96 byte are written by SW */
789 __le16 valid_sections;
790 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
791 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
792 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
793 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
794 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
795 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
796 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
797 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
798 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
799 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
801 __le16 switch_id; /* 12bit id combined with flags below */
802 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
803 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
804 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
805 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
806 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
808 /* security section */
810 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
811 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
812 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
815 __le16 pvid; /* VLANS include priority bits */
818 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
819 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
820 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
821 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
822 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
823 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
824 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
825 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
826 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
827 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
828 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
829 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
830 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
831 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
832 u8 pvlan_reserved[3];
833 /* ingress egress up sections */
834 __le32 ingress_table; /* bitmap, 3 bits per up */
835 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
836 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
837 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
838 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
839 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
840 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
841 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
842 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
843 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
844 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
845 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
846 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
847 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
848 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
849 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
850 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
851 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
852 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
853 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
854 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
855 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
856 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
857 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
858 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
859 __le32 egress_table; /* same defines as for ingress table */
860 /* cascaded PV section */
863 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
864 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
865 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
866 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
867 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
868 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
869 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
870 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
871 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
873 /* queue mapping section */
874 __le16 mapping_flags;
875 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
876 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
877 __le16 queue_mapping[16];
878 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
879 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
880 __le16 tc_mapping[8];
881 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
882 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
883 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
884 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
885 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
886 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
887 /* queueing option section */
888 u8 queueing_opt_flags;
889 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
890 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
892 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
893 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
895 u8 queueing_opt_reserved[3];
896 /* scheduler section */
899 /* outer up section */
900 __le32 outer_up_table; /* same structure and defines as ingress table */
902 /* last 32 bytes are written by FW */
904 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
905 __le16 stat_counter_idx;
907 u8 resp_reserved[12];
910 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
912 /* Add Port Virtualizer (direct 0x0220)
913 * also used for update PV (direct 0x0221) but only flags are used
914 * (IS_CTRL_PORT only works on add PV)
916 struct i40e_aqc_add_update_pv {
917 __le16 command_flags;
918 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
919 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
920 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
921 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
923 __le16 connected_seid;
927 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
929 struct i40e_aqc_add_update_pv_completion {
930 /* reserved for update; for add also encodes error if rc == ENOSPC */
932 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
933 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
934 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
935 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
939 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
941 /* Get PV Params (direct 0x0222)
942 * uses i40e_aqc_switch_seid for the descriptor
945 struct i40e_aqc_get_pv_params_completion {
948 __le16 pv_flags; /* same flags as add_pv */
949 #define I40E_AQC_GET_PV_PV_TYPE 0x1
950 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
951 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
953 __le16 default_port_seid;
956 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
958 /* Add VEB (direct 0x0230) */
959 struct i40e_aqc_add_veb {
961 __le16 downlink_seid;
963 #define I40E_AQC_ADD_VEB_FLOATING 0x1
964 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
965 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
966 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
967 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
968 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
969 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
974 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
976 struct i40e_aqc_add_veb_completion {
979 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
981 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
982 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
983 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
984 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
985 __le16 statistic_index;
990 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
992 /* Get VEB Parameters (direct 0x0232)
993 * uses i40e_aqc_switch_seid for the descriptor
995 struct i40e_aqc_get_veb_parameters_completion {
998 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
999 __le16 statistic_index;
1005 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1007 /* Delete Element (direct 0x0243)
1008 * uses the generic i40e_aqc_switch_seid
1011 /* Add MAC-VLAN (indirect 0x0250) */
1013 /* used for the command for most vlan commands */
1014 struct i40e_aqc_macvlan {
1015 __le16 num_addresses;
1017 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1018 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1019 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1020 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1025 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1027 /* indirect data for command and response */
1028 struct i40e_aqc_add_macvlan_element_data {
1032 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1033 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1034 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1035 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1036 __le16 queue_number;
1037 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1038 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1039 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1040 /* response section */
1042 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1043 #define I40E_AQC_MM_HASH_MATCH 0x02
1044 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1048 struct i40e_aqc_add_remove_macvlan_completion {
1049 __le16 perfect_mac_used;
1050 __le16 perfect_mac_free;
1051 __le16 unicast_hash_free;
1052 __le16 multicast_hash_free;
1057 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1059 /* Remove MAC-VLAN (indirect 0x0251)
1060 * uses i40e_aqc_macvlan for the descriptor
1061 * data points to an array of num_addresses of elements
1064 struct i40e_aqc_remove_macvlan_element_data {
1068 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1069 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1070 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1071 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1075 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1076 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1077 u8 reply_reserved[3];
1080 /* Add VLAN (indirect 0x0252)
1081 * Remove VLAN (indirect 0x0253)
1082 * use the generic i40e_aqc_macvlan for the command
1084 struct i40e_aqc_add_remove_vlan_element_data {
1087 /* flags for add VLAN */
1088 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1089 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1090 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1091 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1092 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1093 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1094 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1095 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1096 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1097 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1098 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1099 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1100 /* flags for remove VLAN */
1101 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1104 /* flags for add VLAN */
1105 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1106 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1107 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1108 /* flags for remove VLAN */
1109 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1110 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1114 struct i40e_aqc_add_remove_vlan_completion {
1122 /* Set VSI Promiscuous Modes (direct 0x0254) */
1123 struct i40e_aqc_set_vsi_promiscuous_modes {
1124 __le16 promiscuous_flags;
1126 /* flags used for both fields above */
1127 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1128 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1129 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1130 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1131 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1133 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1135 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1136 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1140 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1142 /* Add S/E-tag command (direct 0x0255)
1143 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1145 struct i40e_aqc_add_tag {
1147 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1149 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1150 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1151 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1153 __le16 queue_number;
1157 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1159 struct i40e_aqc_add_remove_tag_completion {
1165 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1167 /* Remove S/E-tag command (direct 0x0256)
1168 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1170 struct i40e_aqc_remove_tag {
1172 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1173 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1174 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1179 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1181 /* Add multicast E-Tag (direct 0x0257)
1182 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1183 * and no external data
1185 struct i40e_aqc_add_remove_mcast_etag {
1188 u8 num_unicast_etags;
1190 __le32 addr_high; /* address of array of 2-byte s-tags */
1194 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1196 struct i40e_aqc_add_remove_mcast_etag_completion {
1198 __le16 mcast_etags_used;
1199 __le16 mcast_etags_free;
1205 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1207 /* Update S/E-Tag (direct 0x0259) */
1208 struct i40e_aqc_update_tag {
1210 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1211 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1212 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1218 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1220 struct i40e_aqc_update_tag_completion {
1226 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1228 /* Add Control Packet filter (direct 0x025A)
1229 * Remove Control Packet filter (direct 0x025B)
1230 * uses the i40e_aqc_add_oveb_cloud,
1231 * and the generic direct completion structure
1233 struct i40e_aqc_add_remove_control_packet_filter {
1237 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1238 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1239 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1240 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1241 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1243 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1244 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1245 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1250 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1252 struct i40e_aqc_add_remove_control_packet_filter_completion {
1253 __le16 mac_etype_used;
1255 __le16 mac_etype_free;
1260 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1262 /* Add Cloud filters (indirect 0x025C)
1263 * Remove Cloud filters (indirect 0x025D)
1264 * uses the i40e_aqc_add_remove_cloud_filters,
1265 * and the generic indirect completion structure
1267 struct i40e_aqc_add_remove_cloud_filters {
1271 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1272 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1273 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1279 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1281 struct i40e_aqc_add_remove_cloud_filters_element_data {
1295 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1296 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1297 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1298 /* 0x0000 reserved */
1299 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1300 /* 0x0002 reserved */
1301 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1302 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1303 /* 0x0005 reserved */
1304 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1305 /* 0x0007 reserved */
1306 /* 0x0008 reserved */
1307 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1308 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1309 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1310 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1312 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1313 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1314 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1315 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1316 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1318 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1319 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1320 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0
1321 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1322 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2
1323 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1327 __le16 queue_number;
1328 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1329 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1330 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1332 /* response section */
1333 u8 allocation_result;
1334 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1335 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1336 u8 response_reserved[7];
1339 struct i40e_aqc_remove_cloud_filters_completion {
1340 __le16 perfect_ovlan_used;
1341 __le16 perfect_ovlan_free;
1348 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1350 /* Add Mirror Rule (indirect or direct 0x0260)
1351 * Delete Mirror Rule (indirect or direct 0x0261)
1352 * note: some rule types (4,5) do not use an external buffer.
1353 * take care to set the flags correctly.
1355 struct i40e_aqc_add_delete_mirror_rule {
1358 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1359 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1360 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1361 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1362 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1363 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1364 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1365 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1367 __le16 destination; /* VSI for add, rule id for delete */
1368 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1372 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1374 struct i40e_aqc_add_delete_mirror_rule_completion {
1376 __le16 rule_id; /* only used on add */
1377 __le16 mirror_rules_used;
1378 __le16 mirror_rules_free;
1383 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1387 /* PFC Ignore (direct 0x0301)
1388 * the command and response use the same descriptor structure
1390 struct i40e_aqc_pfc_ignore {
1392 u8 command_flags; /* unused on response */
1393 #define I40E_AQC_PFC_IGNORE_SET 0x80
1394 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1398 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1400 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1401 * with no parameters
1404 /* TX scheduler 0x04xx */
1406 /* Almost all the indirect commands use
1407 * this generic struct to pass the SEID in param0
1409 struct i40e_aqc_tx_sched_ind {
1416 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1418 /* Several commands respond with a set of queue set handles */
1419 struct i40e_aqc_qs_handles_resp {
1420 __le16 qs_handles[8];
1423 /* Configure VSI BW limits (direct 0x0400) */
1424 struct i40e_aqc_configure_vsi_bw_limit {
1429 u8 max_credit; /* 0-3, limit = 2^max */
1433 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1435 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1436 * responds with i40e_aqc_qs_handles_resp
1438 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1441 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1443 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1444 __le16 tc_bw_max[2];
1448 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1450 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1451 * responds with i40e_aqc_qs_handles_resp
1453 struct i40e_aqc_configure_vsi_tc_bw_data {
1456 u8 tc_bw_credits[8];
1458 __le16 qs_handles[8];
1461 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1463 /* Query vsi bw configuration (indirect 0x0408) */
1464 struct i40e_aqc_query_vsi_bw_config_resp {
1466 u8 tc_suspended_bits;
1468 __le16 qs_handles[8];
1470 __le16 port_bw_limit;
1472 u8 max_bw; /* 0-3, limit = 2^max */
1476 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1478 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1479 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1482 u8 share_credits[8];
1485 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1486 __le16 tc_bw_max[2];
1489 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1491 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1492 struct i40e_aqc_configure_switching_comp_bw_limit {
1497 u8 max_bw; /* 0-3, limit = 2^max */
1501 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1503 /* Enable Physical Port ETS (indirect 0x0413)
1504 * Modify Physical Port ETS (indirect 0x0414)
1505 * Disable Physical Port ETS (indirect 0x0415)
1507 struct i40e_aqc_configure_switching_comp_ets_data {
1511 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1512 u8 tc_strict_priority_flags;
1514 u8 tc_bw_share_credits[8];
1518 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1520 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1521 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1524 __le16 tc_bw_credit[8];
1526 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1527 __le16 tc_bw_max[2];
1531 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1533 /* Configure Switching Component Bandwidth Allocation per Tc
1536 struct i40e_aqc_configure_switching_comp_bw_config_data {
1539 u8 absolute_credits; /* bool */
1540 u8 tc_bw_share_credits[8];
1544 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1546 /* Query Switching Component Configuration (indirect 0x0418) */
1547 struct i40e_aqc_query_switching_comp_ets_config_resp {
1550 __le16 port_bw_limit;
1552 u8 tc_bw_max; /* 0-3, limit = 2^max */
1556 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1558 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1559 struct i40e_aqc_query_port_ets_config_resp {
1563 u8 tc_strict_priority_bits;
1565 u8 tc_bw_share_credits[8];
1566 __le16 tc_bw_limits[8];
1568 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1569 __le16 tc_bw_max[2];
1573 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1575 /* Query Switching Component Bandwidth Allocation per Traffic Type
1578 struct i40e_aqc_query_switching_comp_bw_config_resp {
1581 u8 absolute_credits_enable; /* bool */
1582 u8 tc_bw_share_credits[8];
1583 __le16 tc_bw_limits[8];
1585 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1586 __le16 tc_bw_max[2];
1589 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1591 /* Suspend/resume port TX traffic
1592 * (direct 0x041B and 0x041C) uses the generic SEID struct
1595 /* Configure partition BW
1598 struct i40e_aqc_configure_partition_bw_data {
1599 __le16 pf_valid_bits;
1600 u8 min_bw[16]; /* guaranteed bandwidth */
1601 u8 max_bw[16]; /* bandwidth limit */
1604 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1606 /* Get and set the active HMC resource profile and status.
1607 * (direct 0x0500) and (direct 0x0501)
1609 struct i40e_aq_get_set_hmc_resource_profile {
1615 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1617 enum i40e_aq_hmc_profile {
1618 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1619 I40E_HMC_PROFILE_DEFAULT = 1,
1620 I40E_HMC_PROFILE_FAVOR_VF = 2,
1621 I40E_HMC_PROFILE_EQUAL = 3,
1624 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1625 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1627 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1629 /* set in param0 for get phy abilities to report qualified modules */
1630 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1631 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1633 enum i40e_aq_phy_type {
1634 I40E_PHY_TYPE_SGMII = 0x0,
1635 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1636 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1637 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1638 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1639 I40E_PHY_TYPE_XAUI = 0x5,
1640 I40E_PHY_TYPE_XFI = 0x6,
1641 I40E_PHY_TYPE_SFI = 0x7,
1642 I40E_PHY_TYPE_XLAUI = 0x8,
1643 I40E_PHY_TYPE_XLPPI = 0x9,
1644 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1645 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1646 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1647 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1648 I40E_PHY_TYPE_100BASE_TX = 0x11,
1649 I40E_PHY_TYPE_1000BASE_T = 0x12,
1650 I40E_PHY_TYPE_10GBASE_T = 0x13,
1651 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1652 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1653 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1654 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1655 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1656 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1657 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1658 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1659 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1660 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1661 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1665 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1666 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1667 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1668 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1669 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1671 enum i40e_aq_link_speed {
1672 I40E_LINK_SPEED_UNKNOWN = 0,
1673 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1674 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1675 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1676 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1677 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1680 struct i40e_aqc_module_desc {
1688 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1690 struct i40e_aq_get_phy_abilities_resp {
1691 __le32 phy_type; /* bitmap using the above enum for offsets */
1692 u8 link_speed; /* bitmap using the above enum bit patterns */
1694 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1695 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1696 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1697 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1698 #define I40E_AQ_PHY_AN_ENABLED 0x10
1699 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1700 __le16 eee_capability;
1701 #define I40E_AQ_EEE_100BASE_TX 0x0002
1702 #define I40E_AQ_EEE_1000BASE_T 0x0004
1703 #define I40E_AQ_EEE_10GBASE_T 0x0008
1704 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1705 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1706 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1709 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1713 u8 qualified_module_count;
1714 #define I40E_AQ_PHY_MAX_QMS 16
1715 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1718 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1720 /* Set PHY Config (direct 0x0601) */
1721 struct i40e_aq_set_phy_config { /* same bits as above in all */
1725 /* bits 0-2 use the values from get_phy_abilities_resp */
1726 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1727 #define I40E_AQ_PHY_ENABLE_AN 0x10
1728 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1729 __le16 eee_capability;
1735 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1737 /* Set MAC Config command data structure (direct 0x0603) */
1738 struct i40e_aq_set_mac_config {
1739 __le16 max_frame_size;
1741 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1742 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1743 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1744 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1745 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1746 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1747 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1748 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1749 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1750 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1751 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1752 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1753 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1754 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1755 u8 tx_timer_priority; /* bitmap */
1756 __le16 tx_timer_value;
1757 __le16 fc_refresh_threshold;
1761 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1763 /* Restart Auto-Negotiation (direct 0x605) */
1764 struct i40e_aqc_set_link_restart_an {
1766 #define I40E_AQ_PHY_RESTART_AN 0x02
1767 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1771 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1773 /* Get Link Status cmd & response data structure (direct 0x0607) */
1774 struct i40e_aqc_get_link_status {
1775 __le16 command_flags; /* only field set on command */
1776 #define I40E_AQ_LSE_MASK 0x3
1777 #define I40E_AQ_LSE_NOP 0x0
1778 #define I40E_AQ_LSE_DISABLE 0x2
1779 #define I40E_AQ_LSE_ENABLE 0x3
1780 /* only response uses this flag */
1781 #define I40E_AQ_LSE_IS_ENABLED 0x1
1782 u8 phy_type; /* i40e_aq_phy_type */
1783 u8 link_speed; /* i40e_aq_link_speed */
1785 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1786 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1787 #define I40E_AQ_LINK_FAULT 0x02
1788 #define I40E_AQ_LINK_FAULT_TX 0x04
1789 #define I40E_AQ_LINK_FAULT_RX 0x08
1790 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1791 #define I40E_AQ_LINK_UP_PORT 0x20
1792 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1793 #define I40E_AQ_SIGNAL_DETECT 0x80
1795 #define I40E_AQ_AN_COMPLETED 0x01
1796 #define I40E_AQ_LP_AN_ABILITY 0x02
1797 #define I40E_AQ_PD_FAULT 0x04
1798 #define I40E_AQ_FEC_EN 0x08
1799 #define I40E_AQ_PHY_LOW_POWER 0x10
1800 #define I40E_AQ_LINK_PAUSE_TX 0x20
1801 #define I40E_AQ_LINK_PAUSE_RX 0x40
1802 #define I40E_AQ_QUALIFIED_MODULE 0x80
1804 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1805 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1806 #define I40E_AQ_LINK_TX_SHIFT 0x02
1807 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1808 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1809 #define I40E_AQ_LINK_TX_DRAINED 0x01
1810 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1811 #define I40E_AQ_LINK_FORCED_40G 0x10
1812 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1813 __le16 max_frame_size;
1815 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1816 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1820 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1822 /* Set event mask command (direct 0x613) */
1823 struct i40e_aqc_set_phy_int_mask {
1826 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1827 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1828 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1829 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1830 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1831 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1832 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1833 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1834 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1838 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1840 /* Get Local AN advt register (direct 0x0614)
1841 * Set Local AN advt register (direct 0x0615)
1842 * Get Link Partner AN advt register (direct 0x0616)
1844 struct i40e_aqc_an_advt_reg {
1845 __le32 local_an_reg0;
1846 __le16 local_an_reg1;
1850 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1852 /* Set Loopback mode (0x0618) */
1853 struct i40e_aqc_set_lb_mode {
1855 #define I40E_AQ_LB_PHY_LOCAL 0x01
1856 #define I40E_AQ_LB_PHY_REMOTE 0x02
1857 #define I40E_AQ_LB_MAC_LOCAL 0x04
1861 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1863 /* Set PHY Debug command (0x0622) */
1864 struct i40e_aqc_set_phy_debug {
1866 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1867 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1868 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1869 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1870 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1871 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1872 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1873 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1877 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1879 enum i40e_aq_phy_reg_type {
1880 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1881 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1882 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1885 /* NVM Read command (indirect 0x0701)
1886 * NVM Erase commands (direct 0x0702)
1887 * NVM Update commands (indirect 0x0703)
1889 struct i40e_aqc_nvm_update {
1891 #define I40E_AQ_NVM_LAST_CMD 0x01
1892 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1900 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1902 /* NVM Config Read (indirect 0x0704) */
1903 struct i40e_aqc_nvm_config_read {
1905 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1906 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1907 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
1908 __le16 element_count;
1909 __le16 element_id; /* Feature/field ID */
1910 __le16 element_id_msw; /* MSWord of field ID */
1911 __le32 address_high;
1915 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1917 /* NVM Config Write (indirect 0x0705) */
1918 struct i40e_aqc_nvm_config_write {
1920 __le16 element_count;
1922 __le32 address_high;
1926 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1928 /* Used for 0x0704 as well as for 0x0705 commands */
1929 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1930 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1931 #define I40E_AQ_ANVM_FEATURE 0
1932 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
1933 struct i40e_aqc_nvm_config_data_feature {
1935 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1936 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1937 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
1938 __le16 feature_options;
1939 __le16 feature_selection;
1942 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1944 struct i40e_aqc_nvm_config_data_immediate_field {
1947 __le16 field_options;
1951 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1953 /* OEM Post Update (indirect 0x0720)
1954 * no command data struct used
1956 struct i40e_aqc_nvm_oem_post_update {
1957 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
1962 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1964 struct i40e_aqc_nvm_oem_post_update_buffer {
1971 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1973 /* Send to PF command (indirect 0x0801) id is only used by PF
1974 * Send to VF command (indirect 0x0802) id is only used by PF
1975 * Send to Peer PF command (indirect 0x0803)
1977 struct i40e_aqc_pf_vf_message {
1984 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1986 /* Alternate structure */
1988 /* Direct write (direct 0x0900)
1989 * Direct read (direct 0x0902)
1991 struct i40e_aqc_alternate_write {
1998 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2000 /* Indirect write (indirect 0x0901)
2001 * Indirect read (indirect 0x0903)
2004 struct i40e_aqc_alternate_ind_write {
2011 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2013 /* Done alternate write (direct 0x0904)
2016 struct i40e_aqc_alternate_write_done {
2018 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2019 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2020 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2021 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2025 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2027 /* Set OEM mode (direct 0x0905) */
2028 struct i40e_aqc_alternate_set_mode {
2030 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2031 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2035 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2037 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2039 /* async events 0x10xx */
2041 /* Lan Queue Overflow Event (direct, 0x1001) */
2042 struct i40e_aqc_lan_overflow {
2043 __le32 prtdcb_rupto;
2048 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2050 /* Get LLDP MIB (indirect 0x0A00) */
2051 struct i40e_aqc_lldp_get_mib {
2054 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2055 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2056 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2057 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2058 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2059 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2060 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2061 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2062 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2063 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2064 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2072 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2074 /* Configure LLDP MIB Change Event (direct 0x0A01)
2075 * also used for the event (with type in the command field)
2077 struct i40e_aqc_lldp_update_mib {
2079 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2080 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2086 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2088 /* Add LLDP TLV (indirect 0x0A02)
2089 * Delete LLDP TLV (indirect 0x0A04)
2091 struct i40e_aqc_lldp_add_tlv {
2092 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2100 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2102 /* Update LLDP TLV (indirect 0x0A03) */
2103 struct i40e_aqc_lldp_update_tlv {
2104 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2113 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2115 /* Stop LLDP (direct 0x0A05) */
2116 struct i40e_aqc_lldp_stop {
2118 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2119 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2123 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2125 /* Start LLDP (direct 0x0A06) */
2127 struct i40e_aqc_lldp_start {
2129 #define I40E_AQ_LLDP_AGENT_START 0x1
2133 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2135 /* Get CEE DCBX Oper Config (0x0A07)
2136 * uses the generic descriptor struct
2137 * returns below as indirect response
2140 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2141 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2142 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2143 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2144 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2145 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2147 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2148 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2149 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2150 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2151 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2152 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2153 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2154 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2155 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2156 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2157 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2158 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2160 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2161 * word boundary layout issues, which the Linux compilers silently deal
2162 * with by adding padding, making the actual struct larger than designed.
2163 * However, the FW compiler for the NIC is less lenient and complains
2164 * about the struct. Hence, the struct defined here has an extra byte in
2165 * fields reserved3 and reserved4 to directly acknowledge that padding,
2166 * and the new length is used in the length check macro.
2168 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2176 __le16 oper_app_prio;
2181 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2183 struct i40e_aqc_get_cee_dcb_cfg_resp {
2188 __le16 oper_app_prio;
2193 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2195 /* Set Local LLDP MIB (indirect 0x0A08)
2196 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2198 struct i40e_aqc_lldp_set_local_mib {
2199 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2200 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2201 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2202 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2203 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2204 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2205 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2206 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2211 __le32 address_high;
2215 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2217 /* Stop/Start LLDP Agent (direct 0x0A09)
2218 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2220 struct i40e_aqc_lldp_stop_start_specific_agent {
2221 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2222 #define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2227 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2229 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2230 struct i40e_aqc_add_udp_tunnel {
2234 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2235 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2236 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2240 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2242 struct i40e_aqc_add_udp_tunnel_completion {
2244 u8 filter_entry_index;
2246 #define I40E_AQC_SINGLE_PF 0x0
2247 #define I40E_AQC_MULTIPLE_PFS 0x1
2252 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2254 /* remove UDP Tunnel command (0x0B01) */
2255 struct i40e_aqc_remove_udp_tunnel {
2257 u8 index; /* 0 to 15 */
2261 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2263 struct i40e_aqc_del_udp_tunnel_completion {
2265 u8 index; /* 0 to 15 */
2267 u8 total_filters_used;
2271 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2274 struct i40e_aqc_get_set_rss_key {
2275 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2276 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2277 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2278 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2285 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2287 struct i40e_aqc_get_set_rss_key_data {
2288 u8 standard_rss_key[0x28];
2289 u8 extended_hash_key[0xc];
2292 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2294 struct i40e_aqc_get_set_rss_lut {
2295 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2296 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2297 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2298 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2300 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2301 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2302 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2304 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2305 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2312 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2315 /* tunnel key structure 0x0B10 */
2317 struct i40e_aqc_tunnel_key_structure {
2320 u8 key1_len; /* 0 to 15 */
2321 u8 key2_len; /* 0 to 15 */
2323 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2324 /* response flags */
2325 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2326 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2327 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2328 u8 network_key_index;
2329 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2330 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2331 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2332 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2336 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2338 /* OEM mode commands (direct 0xFE0x) */
2339 struct i40e_aqc_oem_param_change {
2341 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2342 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2343 #define I40E_AQ_OEM_PARAM_MAC 2
2344 __le32 param_value1;
2345 __le16 param_value2;
2349 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2351 struct i40e_aqc_oem_state_change {
2353 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2354 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2358 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2360 /* Initialize OCSD (0xFE02, direct) */
2361 struct i40e_aqc_opc_oem_ocsd_initialize {
2364 __le32 ocsd_memory_block_addr_high;
2365 __le32 ocsd_memory_block_addr_low;
2366 __le32 requested_update_interval;
2369 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2371 /* Initialize OCBB (0xFE03, direct) */
2372 struct i40e_aqc_opc_oem_ocbb_initialize {
2375 __le32 ocbb_memory_block_addr_high;
2376 __le32 ocbb_memory_block_addr_low;
2380 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2382 /* debug commands */
2384 /* get device id (0xFF00) uses the generic structure */
2386 /* set test more (0xFF01, internal) */
2388 struct i40e_acq_set_test_mode {
2390 #define I40E_AQ_TEST_PARTIAL 0
2391 #define I40E_AQ_TEST_FULL 1
2392 #define I40E_AQ_TEST_NVM 2
2395 #define I40E_AQ_TEST_OPEN 0
2396 #define I40E_AQ_TEST_CLOSE 1
2397 #define I40E_AQ_TEST_INC 2
2399 __le32 address_high;
2403 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2405 /* Debug Read Register command (0xFF03)
2406 * Debug Write Register command (0xFF04)
2408 struct i40e_aqc_debug_reg_read_write {
2415 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2417 /* Scatter/gather Reg Read (indirect 0xFF05)
2418 * Scatter/gather Reg Write (indirect 0xFF06)
2421 /* i40e_aq_desc is used for the command */
2422 struct i40e_aqc_debug_reg_sg_element_data {
2427 /* Debug Modify register (direct 0xFF07) */
2428 struct i40e_aqc_debug_modify_reg {
2435 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2437 /* dump internal data (0xFF08, indirect) */
2439 #define I40E_AQ_CLUSTER_ID_AUX 0
2440 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2441 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2442 #define I40E_AQ_CLUSTER_ID_HMC 3
2443 #define I40E_AQ_CLUSTER_ID_MAC0 4
2444 #define I40E_AQ_CLUSTER_ID_MAC1 5
2445 #define I40E_AQ_CLUSTER_ID_MAC2 6
2446 #define I40E_AQ_CLUSTER_ID_MAC3 7
2447 #define I40E_AQ_CLUSTER_ID_DCB 8
2448 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2449 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2450 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2452 struct i40e_aqc_debug_dump_internals {
2457 __le32 address_high;
2461 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2463 struct i40e_aqc_debug_modify_internals {
2465 u8 cluster_specific_params[7];
2466 __le32 address_high;
2470 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2472 #endif /* _I40E_ADMINQ_CMD_H_ */