1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #ifndef _I40E_ADMINQ_CMD_H_
35 #define _I40E_ADMINQ_CMD_H_
37 /* This header file defines the i40e Admin Queue commands and is shared between
38 * i40e Firmware and Software.
40 * This file needs to comply with the Linux Kernel coding style.
43 #define I40E_FW_API_VERSION_MAJOR 0x0001
44 #define I40E_FW_API_VERSION_MINOR 0x0004
70 /* Flags sub-structure
71 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
72 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
75 /* command flags and offsets*/
76 #define I40E_AQ_FLAG_DD_SHIFT 0
77 #define I40E_AQ_FLAG_CMP_SHIFT 1
78 #define I40E_AQ_FLAG_ERR_SHIFT 2
79 #define I40E_AQ_FLAG_VFE_SHIFT 3
80 #define I40E_AQ_FLAG_LB_SHIFT 9
81 #define I40E_AQ_FLAG_RD_SHIFT 10
82 #define I40E_AQ_FLAG_VFC_SHIFT 11
83 #define I40E_AQ_FLAG_BUF_SHIFT 12
84 #define I40E_AQ_FLAG_SI_SHIFT 13
85 #define I40E_AQ_FLAG_EI_SHIFT 14
86 #define I40E_AQ_FLAG_FE_SHIFT 15
88 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
89 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
90 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
91 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
92 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
93 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
94 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
95 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
96 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
97 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
98 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
101 enum i40e_admin_queue_err {
102 I40E_AQ_RC_OK = 0, /* success */
103 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
104 I40E_AQ_RC_ENOENT = 2, /* No such element */
105 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
106 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
107 I40E_AQ_RC_EIO = 5, /* I/O error */
108 I40E_AQ_RC_ENXIO = 6, /* No such resource */
109 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
110 I40E_AQ_RC_EAGAIN = 8, /* Try again */
111 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
112 I40E_AQ_RC_EACCES = 10, /* Permission denied */
113 I40E_AQ_RC_EFAULT = 11, /* Bad address */
114 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
115 I40E_AQ_RC_EEXIST = 13, /* object already exists */
116 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
117 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
118 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
119 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
120 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
121 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
122 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
123 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
124 I40E_AQ_RC_EFBIG = 22, /* File too large */
127 /* Admin Queue command opcodes */
128 enum i40e_admin_queue_opc {
130 i40e_aqc_opc_get_version = 0x0001,
131 i40e_aqc_opc_driver_version = 0x0002,
132 i40e_aqc_opc_queue_shutdown = 0x0003,
133 i40e_aqc_opc_set_pf_context = 0x0004,
135 /* resource ownership */
136 i40e_aqc_opc_request_resource = 0x0008,
137 i40e_aqc_opc_release_resource = 0x0009,
139 i40e_aqc_opc_list_func_capabilities = 0x000A,
140 i40e_aqc_opc_list_dev_capabilities = 0x000B,
143 i40e_aqc_opc_mac_address_read = 0x0107,
144 i40e_aqc_opc_mac_address_write = 0x0108,
147 i40e_aqc_opc_clear_pxe_mode = 0x0110,
149 /* internal switch commands */
150 i40e_aqc_opc_get_switch_config = 0x0200,
151 i40e_aqc_opc_add_statistics = 0x0201,
152 i40e_aqc_opc_remove_statistics = 0x0202,
153 i40e_aqc_opc_set_port_parameters = 0x0203,
154 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
156 i40e_aqc_opc_add_vsi = 0x0210,
157 i40e_aqc_opc_update_vsi_parameters = 0x0211,
158 i40e_aqc_opc_get_vsi_parameters = 0x0212,
160 i40e_aqc_opc_add_pv = 0x0220,
161 i40e_aqc_opc_update_pv_parameters = 0x0221,
162 i40e_aqc_opc_get_pv_parameters = 0x0222,
164 i40e_aqc_opc_add_veb = 0x0230,
165 i40e_aqc_opc_update_veb_parameters = 0x0231,
166 i40e_aqc_opc_get_veb_parameters = 0x0232,
168 i40e_aqc_opc_delete_element = 0x0243,
170 i40e_aqc_opc_add_macvlan = 0x0250,
171 i40e_aqc_opc_remove_macvlan = 0x0251,
172 i40e_aqc_opc_add_vlan = 0x0252,
173 i40e_aqc_opc_remove_vlan = 0x0253,
174 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
175 i40e_aqc_opc_add_tag = 0x0255,
176 i40e_aqc_opc_remove_tag = 0x0256,
177 i40e_aqc_opc_add_multicast_etag = 0x0257,
178 i40e_aqc_opc_remove_multicast_etag = 0x0258,
179 i40e_aqc_opc_update_tag = 0x0259,
180 i40e_aqc_opc_add_control_packet_filter = 0x025A,
181 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
182 i40e_aqc_opc_add_cloud_filters = 0x025C,
183 i40e_aqc_opc_remove_cloud_filters = 0x025D,
185 i40e_aqc_opc_add_mirror_rule = 0x0260,
186 i40e_aqc_opc_delete_mirror_rule = 0x0261,
189 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
190 i40e_aqc_opc_dcb_updated = 0x0302,
193 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
194 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
195 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
196 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
197 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
198 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
200 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
201 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
202 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
203 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
204 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
205 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
206 i40e_aqc_opc_query_port_ets_config = 0x0419,
207 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
208 i40e_aqc_opc_suspend_port_tx = 0x041B,
209 i40e_aqc_opc_resume_port_tx = 0x041C,
210 i40e_aqc_opc_configure_partition_bw = 0x041D,
213 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
214 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
217 i40e_aqc_opc_get_phy_abilities = 0x0600,
218 i40e_aqc_opc_set_phy_config = 0x0601,
219 i40e_aqc_opc_set_mac_config = 0x0603,
220 i40e_aqc_opc_set_link_restart_an = 0x0605,
221 i40e_aqc_opc_get_link_status = 0x0607,
222 i40e_aqc_opc_set_phy_int_mask = 0x0613,
223 i40e_aqc_opc_get_local_advt_reg = 0x0614,
224 i40e_aqc_opc_set_local_advt_reg = 0x0615,
225 i40e_aqc_opc_get_partner_advt = 0x0616,
226 i40e_aqc_opc_set_lb_modes = 0x0618,
227 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
228 i40e_aqc_opc_set_phy_debug = 0x0622,
229 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
232 i40e_aqc_opc_nvm_read = 0x0701,
233 i40e_aqc_opc_nvm_erase = 0x0702,
234 i40e_aqc_opc_nvm_update = 0x0703,
235 i40e_aqc_opc_nvm_config_read = 0x0704,
236 i40e_aqc_opc_nvm_config_write = 0x0705,
238 /* virtualization commands */
239 i40e_aqc_opc_send_msg_to_pf = 0x0801,
240 i40e_aqc_opc_send_msg_to_vf = 0x0802,
241 i40e_aqc_opc_send_msg_to_peer = 0x0803,
243 /* alternate structure */
244 i40e_aqc_opc_alternate_write = 0x0900,
245 i40e_aqc_opc_alternate_write_indirect = 0x0901,
246 i40e_aqc_opc_alternate_read = 0x0902,
247 i40e_aqc_opc_alternate_read_indirect = 0x0903,
248 i40e_aqc_opc_alternate_write_done = 0x0904,
249 i40e_aqc_opc_alternate_set_mode = 0x0905,
250 i40e_aqc_opc_alternate_clear_port = 0x0906,
253 i40e_aqc_opc_lldp_get_mib = 0x0A00,
254 i40e_aqc_opc_lldp_update_mib = 0x0A01,
255 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
256 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
257 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
258 i40e_aqc_opc_lldp_stop = 0x0A05,
259 i40e_aqc_opc_lldp_start = 0x0A06,
260 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
261 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
262 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
264 /* Tunnel commands */
265 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
266 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
269 i40e_aqc_opc_event_lan_overflow = 0x1001,
272 i40e_aqc_opc_oem_parameter_change = 0xFE00,
273 i40e_aqc_opc_oem_device_status_change = 0xFE01,
274 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
275 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
278 i40e_aqc_opc_debug_read_reg = 0xFF03,
279 i40e_aqc_opc_debug_write_reg = 0xFF04,
280 i40e_aqc_opc_debug_modify_reg = 0xFF07,
281 i40e_aqc_opc_debug_dump_internals = 0xFF08,
284 /* command structures and indirect data structures */
286 /* Structure naming conventions:
287 * - no suffix for direct command descriptor structures
288 * - _data for indirect sent data
289 * - _resp for indirect return data (data which is both will use _data)
290 * - _completion for direct return data
291 * - _element_ for repeated elements (may also be _data or _resp)
293 * Command structures are expected to overlay the params.raw member of the basic
294 * descriptor, and as such cannot exceed 16 bytes in length.
297 /* This macro is used to generate a compilation error if a structure
298 * is not exactly the correct length. It gives a divide by zero error if the
299 * structure is not of the correct size, otherwise it creates an enum that is
302 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
303 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
305 /* This macro is used extensively to ensure that command structures are 16
306 * bytes in length as they have to map to the raw array of that size.
308 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
310 /* internal (0x00XX) commands */
312 /* Get version (direct 0x0001) */
313 struct i40e_aqc_get_version {
322 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
324 /* Send driver version (indirect 0x0002) */
325 struct i40e_aqc_driver_version {
329 u8 driver_subbuild_ver;
335 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
337 /* Queue Shutdown (direct 0x0003) */
338 struct i40e_aqc_queue_shutdown {
339 __le32 driver_unloading;
340 #define I40E_AQ_DRIVER_UNLOADING 0x1
344 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
346 /* Set PF context (0x0004, direct) */
347 struct i40e_aqc_set_pf_context {
352 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
354 /* Request resource ownership (direct 0x0008)
355 * Release resource ownership (direct 0x0009)
357 #define I40E_AQ_RESOURCE_NVM 1
358 #define I40E_AQ_RESOURCE_SDP 2
359 #define I40E_AQ_RESOURCE_ACCESS_READ 1
360 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
361 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
362 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
364 struct i40e_aqc_request_resource {
368 __le32 resource_number;
372 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
374 /* Get function capabilities (indirect 0x000A)
375 * Get device capabilities (indirect 0x000B)
377 struct i40e_aqc_list_capabilites {
379 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
387 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
389 struct i40e_aqc_list_capabilities_element_resp {
401 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
402 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
403 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
404 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
405 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
406 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
407 #define I40E_AQ_CAP_ID_SRIOV 0x0012
408 #define I40E_AQ_CAP_ID_VF 0x0013
409 #define I40E_AQ_CAP_ID_VMDQ 0x0014
410 #define I40E_AQ_CAP_ID_8021QBG 0x0015
411 #define I40E_AQ_CAP_ID_8021QBR 0x0016
412 #define I40E_AQ_CAP_ID_VSI 0x0017
413 #define I40E_AQ_CAP_ID_DCB 0x0018
414 #define I40E_AQ_CAP_ID_FCOE 0x0021
415 #define I40E_AQ_CAP_ID_ISCSI 0x0022
416 #define I40E_AQ_CAP_ID_RSS 0x0040
417 #define I40E_AQ_CAP_ID_RXQ 0x0041
418 #define I40E_AQ_CAP_ID_TXQ 0x0042
419 #define I40E_AQ_CAP_ID_MSIX 0x0043
420 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
421 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
422 #define I40E_AQ_CAP_ID_1588 0x0046
423 #define I40E_AQ_CAP_ID_IWARP 0x0051
424 #define I40E_AQ_CAP_ID_LED 0x0061
425 #define I40E_AQ_CAP_ID_SDP 0x0062
426 #define I40E_AQ_CAP_ID_MDIO 0x0063
427 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
428 #define I40E_AQ_CAP_ID_CEM 0x00F2
430 /* Set CPPM Configuration (direct 0x0103) */
431 struct i40e_aqc_cppm_configuration {
432 __le16 command_flags;
433 #define I40E_AQ_CPPM_EN_LTRC 0x0800
434 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
435 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
436 #define I40E_AQ_CPPM_EN_HPTC 0x4000
437 #define I40E_AQ_CPPM_EN_DMARC 0x8000
446 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
448 /* Set ARP Proxy command / response (indirect 0x0104) */
449 struct i40e_aqc_arp_proxy_data {
450 __le16 command_flags;
451 #define I40E_AQ_ARP_INIT_IPV4 0x0008
452 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
453 #define I40E_AQ_ARP_ENA 0x0020
454 #define I40E_AQ_ARP_ADD_IPV4 0x0040
455 #define I40E_AQ_ARP_DEL_IPV4 0x0080
463 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
465 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
466 struct i40e_aqc_ns_proxy_data {
467 __le16 table_idx_mac_addr_0;
468 __le16 table_idx_mac_addr_1;
469 __le16 table_idx_ipv6_0;
470 __le16 table_idx_ipv6_1;
472 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
473 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
474 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
475 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
476 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
477 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
478 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
479 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
480 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
481 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
482 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
485 u8 local_mac_addr[6];
486 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
490 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
492 /* Manage LAA Command (0x0106) - obsolete */
493 struct i40e_aqc_mng_laa {
494 __le16 command_flags;
495 #define I40E_AQ_LAA_FLAG_WR 0x8000
502 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
504 /* Manage MAC Address Read Command (indirect 0x0107) */
505 struct i40e_aqc_mac_address_read {
506 __le16 command_flags;
507 #define I40E_AQC_LAN_ADDR_VALID 0x10
508 #define I40E_AQC_SAN_ADDR_VALID 0x20
509 #define I40E_AQC_PORT_ADDR_VALID 0x40
510 #define I40E_AQC_WOL_ADDR_VALID 0x80
511 #define I40E_AQC_MC_MAG_EN_VALID 0x100
512 #define I40E_AQC_ADDR_VALID_MASK 0x1F0
518 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
520 struct i40e_aqc_mac_address_read_data {
527 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
529 /* Manage MAC Address Write Command (0x0108) */
530 struct i40e_aqc_mac_address_write {
531 __le16 command_flags;
532 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
533 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
534 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
535 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
536 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
543 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
545 /* PXE commands (0x011x) */
547 /* Clear PXE Command and response (direct 0x0110) */
548 struct i40e_aqc_clear_pxe {
553 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
555 /* Switch configuration commands (0x02xx) */
557 /* Used by many indirect commands that only pass an seid and a buffer in the
560 struct i40e_aqc_switch_seid {
567 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
569 /* Get Switch Configuration command (indirect 0x0200)
570 * uses i40e_aqc_switch_seid for the descriptor
572 struct i40e_aqc_get_switch_config_header_resp {
578 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
580 struct i40e_aqc_switch_config_element_resp {
582 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
583 #define I40E_AQ_SW_ELEM_TYPE_PF 2
584 #define I40E_AQ_SW_ELEM_TYPE_VF 3
585 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
586 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
587 #define I40E_AQ_SW_ELEM_TYPE_PV 16
588 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
589 #define I40E_AQ_SW_ELEM_TYPE_PA 18
590 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
592 #define I40E_AQ_SW_ELEM_REV_1 1
595 __le16 downlink_seid;
598 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
599 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
600 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
605 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
607 /* Get Switch Configuration (indirect 0x0200)
608 * an array of elements are returned in the response buffer
609 * the first in the array is the header, remainder are elements
611 struct i40e_aqc_get_switch_config_resp {
612 struct i40e_aqc_get_switch_config_header_resp header;
613 struct i40e_aqc_switch_config_element_resp element[1];
616 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
618 /* Add Statistics (direct 0x0201)
619 * Remove Statistics (direct 0x0202)
621 struct i40e_aqc_add_remove_statistics {
628 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
630 /* Set Port Parameters command (direct 0x0203) */
631 struct i40e_aqc_set_port_parameters {
632 __le16 command_flags;
633 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
634 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
635 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
636 __le16 bad_frame_vsi;
637 __le16 default_seid; /* reserved for command */
641 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
643 /* Get Switch Resource Allocation (indirect 0x0204) */
644 struct i40e_aqc_get_switch_resource_alloc {
645 u8 num_entries; /* reserved for command */
651 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
653 /* expect an array of these structs in the response buffer */
654 struct i40e_aqc_switch_resource_alloc_element_resp {
656 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
657 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
658 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
659 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
660 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
661 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
662 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
663 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
664 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
665 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
666 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
667 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
668 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
669 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
670 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
671 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
672 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
673 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
674 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
679 __le16 total_unalloced;
683 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
685 /* Add VSI (indirect 0x0210)
686 * this indirect command uses struct i40e_aqc_vsi_properties_data
687 * as the indirect buffer (128 bytes)
689 * Update VSI (indirect 0x211)
690 * uses the same data structure as Add VSI
692 * Get VSI (indirect 0x0212)
693 * uses the same completion and data structure as Add VSI
695 struct i40e_aqc_add_get_update_vsi {
698 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
699 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
700 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
705 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
706 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
707 #define I40E_AQ_VSI_TYPE_VF 0x0
708 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
709 #define I40E_AQ_VSI_TYPE_PF 0x2
710 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
711 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
716 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
718 struct i40e_aqc_add_get_update_vsi_completion {
727 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
729 struct i40e_aqc_vsi_properties_data {
730 /* first 96 byte are written by SW */
731 __le16 valid_sections;
732 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
733 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
734 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
735 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
736 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
737 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
738 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
739 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
740 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
741 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
743 __le16 switch_id; /* 12bit id combined with flags below */
744 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
745 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
746 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
747 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
748 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
750 /* security section */
752 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
753 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
754 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
757 __le16 pvid; /* VLANS include priority bits */
760 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
761 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
762 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
763 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
764 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
765 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
766 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
767 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
768 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
769 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
770 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
771 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
772 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
773 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
774 u8 pvlan_reserved[3];
775 /* ingress egress up sections */
776 __le32 ingress_table; /* bitmap, 3 bits per up */
777 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
778 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
779 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
780 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
781 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
782 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
783 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
784 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
785 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
786 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
787 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
788 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
789 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
790 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
791 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
792 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
793 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
794 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
795 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
796 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
797 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
798 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
799 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
800 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
801 __le32 egress_table; /* same defines as for ingress table */
802 /* cascaded PV section */
805 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
806 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
807 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
808 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
809 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
810 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
811 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
812 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
813 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
815 /* queue mapping section */
816 __le16 mapping_flags;
817 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
818 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
819 __le16 queue_mapping[16];
820 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
821 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
822 __le16 tc_mapping[8];
823 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
824 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
825 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
826 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
827 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
828 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
829 /* queueing option section */
830 u8 queueing_opt_flags;
831 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
832 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
833 u8 queueing_opt_reserved[3];
834 /* scheduler section */
837 /* outer up section */
838 __le32 outer_up_table; /* same structure and defines as ingress table */
840 /* last 32 bytes are written by FW */
842 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
843 __le16 stat_counter_idx;
845 u8 resp_reserved[12];
848 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
850 /* Add Port Virtualizer (direct 0x0220)
851 * also used for update PV (direct 0x0221) but only flags are used
852 * (IS_CTRL_PORT only works on add PV)
854 struct i40e_aqc_add_update_pv {
855 __le16 command_flags;
856 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
857 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
858 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
859 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
861 __le16 connected_seid;
865 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
867 struct i40e_aqc_add_update_pv_completion {
868 /* reserved for update; for add also encodes error if rc == ENOSPC */
870 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
871 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
872 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
873 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
877 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
879 /* Get PV Params (direct 0x0222)
880 * uses i40e_aqc_switch_seid for the descriptor
883 struct i40e_aqc_get_pv_params_completion {
886 __le16 pv_flags; /* same flags as add_pv */
887 #define I40E_AQC_GET_PV_PV_TYPE 0x1
888 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
889 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
891 __le16 default_port_seid;
894 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
896 /* Add VEB (direct 0x0230) */
897 struct i40e_aqc_add_veb {
899 __le16 downlink_seid;
901 #define I40E_AQC_ADD_VEB_FLOATING 0x1
902 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
903 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
904 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
905 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
906 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
907 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
912 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
914 struct i40e_aqc_add_veb_completion {
917 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
919 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
920 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
921 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
922 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
923 __le16 statistic_index;
928 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
930 /* Get VEB Parameters (direct 0x0232)
931 * uses i40e_aqc_switch_seid for the descriptor
933 struct i40e_aqc_get_veb_parameters_completion {
936 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
937 __le16 statistic_index;
943 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
945 /* Delete Element (direct 0x0243)
946 * uses the generic i40e_aqc_switch_seid
949 /* Add MAC-VLAN (indirect 0x0250) */
951 /* used for the command for most vlan commands */
952 struct i40e_aqc_macvlan {
953 __le16 num_addresses;
955 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
956 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
957 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
958 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
963 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
965 /* indirect data for command and response */
966 struct i40e_aqc_add_macvlan_element_data {
970 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
971 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
972 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
973 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
975 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
976 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
977 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
978 /* response section */
980 #define I40E_AQC_MM_PERFECT_MATCH 0x01
981 #define I40E_AQC_MM_HASH_MATCH 0x02
982 #define I40E_AQC_MM_ERR_NO_RES 0xFF
986 struct i40e_aqc_add_remove_macvlan_completion {
987 __le16 perfect_mac_used;
988 __le16 perfect_mac_free;
989 __le16 unicast_hash_free;
990 __le16 multicast_hash_free;
995 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
997 /* Remove MAC-VLAN (indirect 0x0251)
998 * uses i40e_aqc_macvlan for the descriptor
999 * data points to an array of num_addresses of elements
1002 struct i40e_aqc_remove_macvlan_element_data {
1006 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1007 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1008 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1009 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1013 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1014 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1015 u8 reply_reserved[3];
1018 /* Add VLAN (indirect 0x0252)
1019 * Remove VLAN (indirect 0x0253)
1020 * use the generic i40e_aqc_macvlan for the command
1022 struct i40e_aqc_add_remove_vlan_element_data {
1025 /* flags for add VLAN */
1026 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1027 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1028 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1029 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1030 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1031 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1032 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1033 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1034 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1035 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1036 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1037 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1038 /* flags for remove VLAN */
1039 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1042 /* flags for add VLAN */
1043 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1044 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1045 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1046 /* flags for remove VLAN */
1047 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1048 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1052 struct i40e_aqc_add_remove_vlan_completion {
1060 /* Set VSI Promiscuous Modes (direct 0x0254) */
1061 struct i40e_aqc_set_vsi_promiscuous_modes {
1062 __le16 promiscuous_flags;
1064 /* flags used for both fields above */
1065 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1066 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1067 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1068 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1069 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1071 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1073 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1074 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1078 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1080 /* Add S/E-tag command (direct 0x0255)
1081 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1083 struct i40e_aqc_add_tag {
1085 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1087 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1088 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1089 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1091 __le16 queue_number;
1095 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1097 struct i40e_aqc_add_remove_tag_completion {
1103 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1105 /* Remove S/E-tag command (direct 0x0256)
1106 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1108 struct i40e_aqc_remove_tag {
1110 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1111 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1112 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1117 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1119 /* Add multicast E-Tag (direct 0x0257)
1120 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1121 * and no external data
1123 struct i40e_aqc_add_remove_mcast_etag {
1126 u8 num_unicast_etags;
1128 __le32 addr_high; /* address of array of 2-byte s-tags */
1132 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1134 struct i40e_aqc_add_remove_mcast_etag_completion {
1136 __le16 mcast_etags_used;
1137 __le16 mcast_etags_free;
1143 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1145 /* Update S/E-Tag (direct 0x0259) */
1146 struct i40e_aqc_update_tag {
1148 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1149 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1150 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1156 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1158 struct i40e_aqc_update_tag_completion {
1164 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1166 /* Add Control Packet filter (direct 0x025A)
1167 * Remove Control Packet filter (direct 0x025B)
1168 * uses the i40e_aqc_add_oveb_cloud,
1169 * and the generic direct completion structure
1171 struct i40e_aqc_add_remove_control_packet_filter {
1175 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1176 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1177 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1178 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1179 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1181 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1182 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1183 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1188 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1190 struct i40e_aqc_add_remove_control_packet_filter_completion {
1191 __le16 mac_etype_used;
1193 __le16 mac_etype_free;
1198 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1200 /* Add Cloud filters (indirect 0x025C)
1201 * Remove Cloud filters (indirect 0x025D)
1202 * uses the i40e_aqc_add_remove_cloud_filters,
1203 * and the generic indirect completion structure
1205 struct i40e_aqc_add_remove_cloud_filters {
1209 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1210 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1211 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1217 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1219 struct i40e_aqc_add_remove_cloud_filters_element_data {
1233 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1234 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1235 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1236 /* 0x0000 reserved */
1237 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1238 /* 0x0002 reserved */
1239 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1240 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1241 /* 0x0005 reserved */
1242 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1243 /* 0x0007 reserved */
1244 /* 0x0008 reserved */
1245 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1246 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1247 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1248 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1250 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1251 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1252 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1253 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1254 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1256 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1257 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1258 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0
1259 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1260 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2
1261 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1265 __le16 queue_number;
1266 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1267 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1268 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1270 /* response section */
1271 u8 allocation_result;
1272 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1273 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1274 u8 response_reserved[7];
1277 struct i40e_aqc_remove_cloud_filters_completion {
1278 __le16 perfect_ovlan_used;
1279 __le16 perfect_ovlan_free;
1286 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1288 /* Add Mirror Rule (indirect or direct 0x0260)
1289 * Delete Mirror Rule (indirect or direct 0x0261)
1290 * note: some rule types (4,5) do not use an external buffer.
1291 * take care to set the flags correctly.
1293 struct i40e_aqc_add_delete_mirror_rule {
1296 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1297 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1298 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1299 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1300 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1301 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1302 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1303 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1305 __le16 destination; /* VSI for add, rule id for delete */
1306 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1310 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1312 struct i40e_aqc_add_delete_mirror_rule_completion {
1314 __le16 rule_id; /* only used on add */
1315 __le16 mirror_rules_used;
1316 __le16 mirror_rules_free;
1321 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1325 /* PFC Ignore (direct 0x0301)
1326 * the command and response use the same descriptor structure
1328 struct i40e_aqc_pfc_ignore {
1330 u8 command_flags; /* unused on response */
1331 #define I40E_AQC_PFC_IGNORE_SET 0x80
1332 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1336 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1338 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1339 * with no parameters
1342 /* TX scheduler 0x04xx */
1344 /* Almost all the indirect commands use
1345 * this generic struct to pass the SEID in param0
1347 struct i40e_aqc_tx_sched_ind {
1354 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1356 /* Several commands respond with a set of queue set handles */
1357 struct i40e_aqc_qs_handles_resp {
1358 __le16 qs_handles[8];
1361 /* Configure VSI BW limits (direct 0x0400) */
1362 struct i40e_aqc_configure_vsi_bw_limit {
1367 u8 max_credit; /* 0-3, limit = 2^max */
1371 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1373 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1374 * responds with i40e_aqc_qs_handles_resp
1376 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1379 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1381 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1382 __le16 tc_bw_max[2];
1386 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1388 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1389 * responds with i40e_aqc_qs_handles_resp
1391 struct i40e_aqc_configure_vsi_tc_bw_data {
1394 u8 tc_bw_credits[8];
1396 __le16 qs_handles[8];
1399 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1401 /* Query vsi bw configuration (indirect 0x0408) */
1402 struct i40e_aqc_query_vsi_bw_config_resp {
1404 u8 tc_suspended_bits;
1406 __le16 qs_handles[8];
1408 __le16 port_bw_limit;
1410 u8 max_bw; /* 0-3, limit = 2^max */
1414 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1416 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1417 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1420 u8 share_credits[8];
1423 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1424 __le16 tc_bw_max[2];
1427 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1429 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1430 struct i40e_aqc_configure_switching_comp_bw_limit {
1435 u8 max_bw; /* 0-3, limit = 2^max */
1439 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1441 /* Enable Physical Port ETS (indirect 0x0413)
1442 * Modify Physical Port ETS (indirect 0x0414)
1443 * Disable Physical Port ETS (indirect 0x0415)
1445 struct i40e_aqc_configure_switching_comp_ets_data {
1449 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1450 u8 tc_strict_priority_flags;
1452 u8 tc_bw_share_credits[8];
1456 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1458 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1459 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1462 __le16 tc_bw_credit[8];
1464 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1465 __le16 tc_bw_max[2];
1469 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1471 /* Configure Switching Component Bandwidth Allocation per Tc
1474 struct i40e_aqc_configure_switching_comp_bw_config_data {
1477 u8 absolute_credits; /* bool */
1478 u8 tc_bw_share_credits[8];
1482 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1484 /* Query Switching Component Configuration (indirect 0x0418) */
1485 struct i40e_aqc_query_switching_comp_ets_config_resp {
1488 __le16 port_bw_limit;
1490 u8 tc_bw_max; /* 0-3, limit = 2^max */
1494 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1496 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1497 struct i40e_aqc_query_port_ets_config_resp {
1501 u8 tc_strict_priority_bits;
1503 u8 tc_bw_share_credits[8];
1504 __le16 tc_bw_limits[8];
1506 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1507 __le16 tc_bw_max[2];
1511 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1513 /* Query Switching Component Bandwidth Allocation per Traffic Type
1516 struct i40e_aqc_query_switching_comp_bw_config_resp {
1519 u8 absolute_credits_enable; /* bool */
1520 u8 tc_bw_share_credits[8];
1521 __le16 tc_bw_limits[8];
1523 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1524 __le16 tc_bw_max[2];
1527 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1529 /* Suspend/resume port TX traffic
1530 * (direct 0x041B and 0x041C) uses the generic SEID struct
1533 /* Configure partition BW
1536 struct i40e_aqc_configure_partition_bw_data {
1537 __le16 pf_valid_bits;
1538 u8 min_bw[16]; /* guaranteed bandwidth */
1539 u8 max_bw[16]; /* bandwidth limit */
1542 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1544 /* Get and set the active HMC resource profile and status.
1545 * (direct 0x0500) and (direct 0x0501)
1547 struct i40e_aq_get_set_hmc_resource_profile {
1553 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1555 enum i40e_aq_hmc_profile {
1556 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1557 I40E_HMC_PROFILE_DEFAULT = 1,
1558 I40E_HMC_PROFILE_FAVOR_VF = 2,
1559 I40E_HMC_PROFILE_EQUAL = 3,
1562 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1563 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1565 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1567 /* set in param0 for get phy abilities to report qualified modules */
1568 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1569 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1571 enum i40e_aq_phy_type {
1572 I40E_PHY_TYPE_SGMII = 0x0,
1573 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1574 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1575 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1576 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1577 I40E_PHY_TYPE_XAUI = 0x5,
1578 I40E_PHY_TYPE_XFI = 0x6,
1579 I40E_PHY_TYPE_SFI = 0x7,
1580 I40E_PHY_TYPE_XLAUI = 0x8,
1581 I40E_PHY_TYPE_XLPPI = 0x9,
1582 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1583 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1584 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1585 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1586 I40E_PHY_TYPE_100BASE_TX = 0x11,
1587 I40E_PHY_TYPE_1000BASE_T = 0x12,
1588 I40E_PHY_TYPE_10GBASE_T = 0x13,
1589 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1590 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1591 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1592 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1593 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1594 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1595 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1596 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1597 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1598 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1599 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1603 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1604 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1605 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1606 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1607 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1609 enum i40e_aq_link_speed {
1610 I40E_LINK_SPEED_UNKNOWN = 0,
1611 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1612 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1613 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1614 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1615 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1618 struct i40e_aqc_module_desc {
1626 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1628 struct i40e_aq_get_phy_abilities_resp {
1629 __le32 phy_type; /* bitmap using the above enum for offsets */
1630 u8 link_speed; /* bitmap using the above enum bit patterns */
1632 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1633 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1634 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1635 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1636 #define I40E_AQ_PHY_AN_ENABLED 0x10
1637 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1638 __le16 eee_capability;
1639 #define I40E_AQ_EEE_100BASE_TX 0x0002
1640 #define I40E_AQ_EEE_1000BASE_T 0x0004
1641 #define I40E_AQ_EEE_10GBASE_T 0x0008
1642 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1643 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1644 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1647 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1651 u8 qualified_module_count;
1652 #define I40E_AQ_PHY_MAX_QMS 16
1653 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1656 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1658 /* Set PHY Config (direct 0x0601) */
1659 struct i40e_aq_set_phy_config { /* same bits as above in all */
1663 /* bits 0-2 use the values from get_phy_abilities_resp */
1664 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1665 #define I40E_AQ_PHY_ENABLE_AN 0x10
1666 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1667 __le16 eee_capability;
1673 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1675 /* Set MAC Config command data structure (direct 0x0603) */
1676 struct i40e_aq_set_mac_config {
1677 __le16 max_frame_size;
1679 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1680 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1681 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1682 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1683 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1684 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1685 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1686 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1687 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1688 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1689 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1690 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1691 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1692 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1693 u8 tx_timer_priority; /* bitmap */
1694 __le16 tx_timer_value;
1695 __le16 fc_refresh_threshold;
1699 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1701 /* Restart Auto-Negotiation (direct 0x605) */
1702 struct i40e_aqc_set_link_restart_an {
1704 #define I40E_AQ_PHY_RESTART_AN 0x02
1705 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1709 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1711 /* Get Link Status cmd & response data structure (direct 0x0607) */
1712 struct i40e_aqc_get_link_status {
1713 __le16 command_flags; /* only field set on command */
1714 #define I40E_AQ_LSE_MASK 0x3
1715 #define I40E_AQ_LSE_NOP 0x0
1716 #define I40E_AQ_LSE_DISABLE 0x2
1717 #define I40E_AQ_LSE_ENABLE 0x3
1718 /* only response uses this flag */
1719 #define I40E_AQ_LSE_IS_ENABLED 0x1
1720 u8 phy_type; /* i40e_aq_phy_type */
1721 u8 link_speed; /* i40e_aq_link_speed */
1723 #define I40E_AQ_LINK_UP 0x01
1724 #define I40E_AQ_LINK_FAULT 0x02
1725 #define I40E_AQ_LINK_FAULT_TX 0x04
1726 #define I40E_AQ_LINK_FAULT_RX 0x08
1727 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1728 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1729 #define I40E_AQ_SIGNAL_DETECT 0x80
1731 #define I40E_AQ_AN_COMPLETED 0x01
1732 #define I40E_AQ_LP_AN_ABILITY 0x02
1733 #define I40E_AQ_PD_FAULT 0x04
1734 #define I40E_AQ_FEC_EN 0x08
1735 #define I40E_AQ_PHY_LOW_POWER 0x10
1736 #define I40E_AQ_LINK_PAUSE_TX 0x20
1737 #define I40E_AQ_LINK_PAUSE_RX 0x40
1738 #define I40E_AQ_QUALIFIED_MODULE 0x80
1740 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1741 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1742 #define I40E_AQ_LINK_TX_SHIFT 0x02
1743 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1744 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1745 #define I40E_AQ_LINK_TX_DRAINED 0x01
1746 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1747 #define I40E_AQ_LINK_FORCED_40G 0x10
1748 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1749 __le16 max_frame_size;
1751 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1752 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1756 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1758 /* Set event mask command (direct 0x613) */
1759 struct i40e_aqc_set_phy_int_mask {
1762 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1763 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1764 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1765 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1766 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1767 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1768 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1769 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1770 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1774 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1776 /* Get Local AN advt register (direct 0x0614)
1777 * Set Local AN advt register (direct 0x0615)
1778 * Get Link Partner AN advt register (direct 0x0616)
1780 struct i40e_aqc_an_advt_reg {
1781 __le32 local_an_reg0;
1782 __le16 local_an_reg1;
1786 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1788 /* Set Loopback mode (0x0618) */
1789 struct i40e_aqc_set_lb_mode {
1791 #define I40E_AQ_LB_PHY_LOCAL 0x01
1792 #define I40E_AQ_LB_PHY_REMOTE 0x02
1793 #define I40E_AQ_LB_MAC_LOCAL 0x04
1797 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1799 /* Set PHY Debug command (0x0622) */
1800 struct i40e_aqc_set_phy_debug {
1802 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1803 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1804 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1805 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1806 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1807 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1808 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1809 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1813 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1815 enum i40e_aq_phy_reg_type {
1816 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1817 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1818 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1821 /* NVM Read command (indirect 0x0701)
1822 * NVM Erase commands (direct 0x0702)
1823 * NVM Update commands (indirect 0x0703)
1825 struct i40e_aqc_nvm_update {
1827 #define I40E_AQ_NVM_LAST_CMD 0x01
1828 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1836 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1838 /* NVM Config Read (indirect 0x0704) */
1839 struct i40e_aqc_nvm_config_read {
1841 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1842 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1843 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
1844 __le16 element_count;
1845 __le16 element_id; /* Feature/field ID */
1846 __le16 element_id_msw; /* MSWord of field ID */
1847 __le32 address_high;
1851 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1853 /* NVM Config Write (indirect 0x0705) */
1854 struct i40e_aqc_nvm_config_write {
1856 __le16 element_count;
1858 __le32 address_high;
1862 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1864 /* Used for 0x0704 as well as for 0x0705 commands */
1865 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1866 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1867 #define I40E_AQ_ANVM_FEATURE 0
1868 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
1869 struct i40e_aqc_nvm_config_data_feature {
1871 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1872 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1873 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
1874 __le16 feature_options;
1875 __le16 feature_selection;
1878 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1880 struct i40e_aqc_nvm_config_data_immediate_field {
1883 __le16 field_options;
1887 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1889 /* Send to PF command (indirect 0x0801) id is only used by PF
1890 * Send to VF command (indirect 0x0802) id is only used by PF
1891 * Send to Peer PF command (indirect 0x0803)
1893 struct i40e_aqc_pf_vf_message {
1900 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1902 /* Alternate structure */
1904 /* Direct write (direct 0x0900)
1905 * Direct read (direct 0x0902)
1907 struct i40e_aqc_alternate_write {
1914 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1916 /* Indirect write (indirect 0x0901)
1917 * Indirect read (indirect 0x0903)
1920 struct i40e_aqc_alternate_ind_write {
1927 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1929 /* Done alternate write (direct 0x0904)
1932 struct i40e_aqc_alternate_write_done {
1934 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1935 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1936 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1937 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
1941 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1943 /* Set OEM mode (direct 0x0905) */
1944 struct i40e_aqc_alternate_set_mode {
1946 #define I40E_AQ_ALTERNATE_MODE_NONE 0
1947 #define I40E_AQ_ALTERNATE_MODE_OEM 1
1951 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1953 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1955 /* async events 0x10xx */
1957 /* Lan Queue Overflow Event (direct, 0x1001) */
1958 struct i40e_aqc_lan_overflow {
1959 __le32 prtdcb_rupto;
1964 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1966 /* Get LLDP MIB (indirect 0x0A00) */
1967 struct i40e_aqc_lldp_get_mib {
1970 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1971 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
1972 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
1973 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
1974 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
1975 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
1976 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
1977 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
1978 #define I40E_AQ_LLDP_TX_SHIFT 0x4
1979 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
1980 /* TX pause flags use I40E_AQ_LINK_TX_* above */
1988 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
1990 /* Configure LLDP MIB Change Event (direct 0x0A01)
1991 * also used for the event (with type in the command field)
1993 struct i40e_aqc_lldp_update_mib {
1995 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1996 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2002 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2004 /* Add LLDP TLV (indirect 0x0A02)
2005 * Delete LLDP TLV (indirect 0x0A04)
2007 struct i40e_aqc_lldp_add_tlv {
2008 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2016 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2018 /* Update LLDP TLV (indirect 0x0A03) */
2019 struct i40e_aqc_lldp_update_tlv {
2020 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2029 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2031 /* Stop LLDP (direct 0x0A05) */
2032 struct i40e_aqc_lldp_stop {
2034 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2035 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2039 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2041 /* Start LLDP (direct 0x0A06) */
2043 struct i40e_aqc_lldp_start {
2045 #define I40E_AQ_LLDP_AGENT_START 0x1
2049 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2051 /* Get CEE DCBX Oper Config (0x0A07)
2052 * uses the generic descriptor struct
2053 * returns below as indirect response
2056 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2057 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2058 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2059 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2060 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2061 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2062 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2063 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2064 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2065 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2066 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2067 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2068 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2069 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2070 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2071 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2072 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2073 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2075 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2083 __le16 oper_app_prio;
2088 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2090 struct i40e_aqc_get_cee_dcb_cfg_resp {
2095 __le16 oper_app_prio;
2100 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2102 /* Set Local LLDP MIB (indirect 0x0A08)
2103 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2105 struct i40e_aqc_lldp_set_local_mib {
2106 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2107 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2112 __le32 address_high;
2116 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2118 /* Stop/Start LLDP Agent (direct 0x0A09)
2119 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2121 struct i40e_aqc_lldp_stop_start_specific_agent {
2122 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2123 #define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2128 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2130 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2131 struct i40e_aqc_add_udp_tunnel {
2135 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2136 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2137 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2141 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2143 struct i40e_aqc_add_udp_tunnel_completion {
2145 u8 filter_entry_index;
2147 #define I40E_AQC_SINGLE_PF 0x0
2148 #define I40E_AQC_MULTIPLE_PFS 0x1
2153 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2155 /* remove UDP Tunnel command (0x0B01) */
2156 struct i40e_aqc_remove_udp_tunnel {
2158 u8 index; /* 0 to 15 */
2162 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2164 struct i40e_aqc_del_udp_tunnel_completion {
2166 u8 index; /* 0 to 15 */
2168 u8 total_filters_used;
2172 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2174 /* tunnel key structure 0x0B10 */
2176 struct i40e_aqc_tunnel_key_structure {
2179 u8 key1_len; /* 0 to 15 */
2180 u8 key2_len; /* 0 to 15 */
2182 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2183 /* response flags */
2184 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2185 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2186 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2187 u8 network_key_index;
2188 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2189 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2190 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2191 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2195 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2197 /* OEM mode commands (direct 0xFE0x) */
2198 struct i40e_aqc_oem_param_change {
2200 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2201 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2202 #define I40E_AQ_OEM_PARAM_MAC 2
2203 __le32 param_value1;
2204 __le16 param_value2;
2208 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2210 struct i40e_aqc_oem_state_change {
2212 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2213 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2217 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2219 /* Initialize OCSD (0xFE02, direct) */
2220 struct i40e_aqc_opc_oem_ocsd_initialize {
2223 __le32 ocsd_memory_block_addr_high;
2224 __le32 ocsd_memory_block_addr_low;
2225 __le32 requested_update_interval;
2228 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2230 /* Initialize OCBB (0xFE03, direct) */
2231 struct i40e_aqc_opc_oem_ocbb_initialize {
2234 __le32 ocbb_memory_block_addr_high;
2235 __le32 ocbb_memory_block_addr_low;
2239 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2241 /* debug commands */
2243 /* get device id (0xFF00) uses the generic structure */
2245 /* set test more (0xFF01, internal) */
2247 struct i40e_acq_set_test_mode {
2249 #define I40E_AQ_TEST_PARTIAL 0
2250 #define I40E_AQ_TEST_FULL 1
2251 #define I40E_AQ_TEST_NVM 2
2254 #define I40E_AQ_TEST_OPEN 0
2255 #define I40E_AQ_TEST_CLOSE 1
2256 #define I40E_AQ_TEST_INC 2
2258 __le32 address_high;
2262 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2264 /* Debug Read Register command (0xFF03)
2265 * Debug Write Register command (0xFF04)
2267 struct i40e_aqc_debug_reg_read_write {
2274 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2276 /* Scatter/gather Reg Read (indirect 0xFF05)
2277 * Scatter/gather Reg Write (indirect 0xFF06)
2280 /* i40e_aq_desc is used for the command */
2281 struct i40e_aqc_debug_reg_sg_element_data {
2286 /* Debug Modify register (direct 0xFF07) */
2287 struct i40e_aqc_debug_modify_reg {
2294 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2296 /* dump internal data (0xFF08, indirect) */
2298 #define I40E_AQ_CLUSTER_ID_AUX 0
2299 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2300 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2301 #define I40E_AQ_CLUSTER_ID_HMC 3
2302 #define I40E_AQ_CLUSTER_ID_MAC0 4
2303 #define I40E_AQ_CLUSTER_ID_MAC1 5
2304 #define I40E_AQ_CLUSTER_ID_MAC2 6
2305 #define I40E_AQ_CLUSTER_ID_MAC3 7
2306 #define I40E_AQ_CLUSTER_ID_DCB 8
2307 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2308 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2309 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2311 struct i40e_aqc_debug_dump_internals {
2316 __le32 address_high;
2320 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2322 struct i40e_aqc_debug_modify_internals {
2324 u8 cluster_specific_params[7];
2325 __le32 address_high;
2329 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);