1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
5 #ifndef _I40E_ADMINQ_CMD_H_
6 #define _I40E_ADMINQ_CMD_H_
8 /* This header file defines the i40e Admin Queue commands and is shared between
9 * i40e Firmware and Software.
11 * This file needs to comply with the Linux Kernel coding style.
14 #define I40E_FW_API_VERSION_MAJOR 0x0001
15 #define I40E_FW_API_VERSION_MINOR_X722 0x0006
16 #define I40E_FW_API_VERSION_MINOR_X710 0x0007
18 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
19 I40E_FW_API_VERSION_MINOR_X710 : \
20 I40E_FW_API_VERSION_MINOR_X722)
22 /* API version 1.7 implements additional link and PHY-specific APIs */
23 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
24 /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */
25 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
51 /* Flags sub-structure
52 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
53 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
56 /* command flags and offsets*/
57 #define I40E_AQ_FLAG_DD_SHIFT 0
58 #define I40E_AQ_FLAG_CMP_SHIFT 1
59 #define I40E_AQ_FLAG_ERR_SHIFT 2
60 #define I40E_AQ_FLAG_VFE_SHIFT 3
61 #define I40E_AQ_FLAG_LB_SHIFT 9
62 #define I40E_AQ_FLAG_RD_SHIFT 10
63 #define I40E_AQ_FLAG_VFC_SHIFT 11
64 #define I40E_AQ_FLAG_BUF_SHIFT 12
65 #define I40E_AQ_FLAG_SI_SHIFT 13
66 #define I40E_AQ_FLAG_EI_SHIFT 14
67 #define I40E_AQ_FLAG_FE_SHIFT 15
69 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
70 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
71 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
72 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
73 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
74 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
75 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
76 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
77 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
78 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
79 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
82 enum i40e_admin_queue_err {
83 I40E_AQ_RC_OK = 0, /* success */
84 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
85 I40E_AQ_RC_ENOENT = 2, /* No such element */
86 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
87 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
88 I40E_AQ_RC_EIO = 5, /* I/O error */
89 I40E_AQ_RC_ENXIO = 6, /* No such resource */
90 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
91 I40E_AQ_RC_EAGAIN = 8, /* Try again */
92 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
93 I40E_AQ_RC_EACCES = 10, /* Permission denied */
94 I40E_AQ_RC_EFAULT = 11, /* Bad address */
95 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
96 I40E_AQ_RC_EEXIST = 13, /* object already exists */
97 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
98 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
99 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
100 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
101 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
102 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
103 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
104 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
105 I40E_AQ_RC_EFBIG = 22, /* File too large */
108 /* Admin Queue command opcodes */
109 enum i40e_admin_queue_opc {
111 i40e_aqc_opc_get_version = 0x0001,
112 i40e_aqc_opc_driver_version = 0x0002,
113 i40e_aqc_opc_queue_shutdown = 0x0003,
114 i40e_aqc_opc_set_pf_context = 0x0004,
116 /* resource ownership */
117 i40e_aqc_opc_request_resource = 0x0008,
118 i40e_aqc_opc_release_resource = 0x0009,
120 i40e_aqc_opc_list_func_capabilities = 0x000A,
121 i40e_aqc_opc_list_dev_capabilities = 0x000B,
124 i40e_aqc_opc_set_proxy_config = 0x0104,
125 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
128 i40e_aqc_opc_mac_address_read = 0x0107,
129 i40e_aqc_opc_mac_address_write = 0x0108,
132 i40e_aqc_opc_clear_pxe_mode = 0x0110,
135 i40e_aqc_opc_set_wol_filter = 0x0120,
136 i40e_aqc_opc_get_wake_reason = 0x0121,
137 i40e_aqc_opc_clear_all_wol_filters = 0x025E,
139 /* internal switch commands */
140 i40e_aqc_opc_get_switch_config = 0x0200,
141 i40e_aqc_opc_add_statistics = 0x0201,
142 i40e_aqc_opc_remove_statistics = 0x0202,
143 i40e_aqc_opc_set_port_parameters = 0x0203,
144 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
145 i40e_aqc_opc_set_switch_config = 0x0205,
146 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
147 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
149 i40e_aqc_opc_add_vsi = 0x0210,
150 i40e_aqc_opc_update_vsi_parameters = 0x0211,
151 i40e_aqc_opc_get_vsi_parameters = 0x0212,
153 i40e_aqc_opc_add_pv = 0x0220,
154 i40e_aqc_opc_update_pv_parameters = 0x0221,
155 i40e_aqc_opc_get_pv_parameters = 0x0222,
157 i40e_aqc_opc_add_veb = 0x0230,
158 i40e_aqc_opc_update_veb_parameters = 0x0231,
159 i40e_aqc_opc_get_veb_parameters = 0x0232,
161 i40e_aqc_opc_delete_element = 0x0243,
163 i40e_aqc_opc_add_macvlan = 0x0250,
164 i40e_aqc_opc_remove_macvlan = 0x0251,
165 i40e_aqc_opc_add_vlan = 0x0252,
166 i40e_aqc_opc_remove_vlan = 0x0253,
167 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
168 i40e_aqc_opc_add_tag = 0x0255,
169 i40e_aqc_opc_remove_tag = 0x0256,
170 i40e_aqc_opc_add_multicast_etag = 0x0257,
171 i40e_aqc_opc_remove_multicast_etag = 0x0258,
172 i40e_aqc_opc_update_tag = 0x0259,
173 i40e_aqc_opc_add_control_packet_filter = 0x025A,
174 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
175 i40e_aqc_opc_add_cloud_filters = 0x025C,
176 i40e_aqc_opc_remove_cloud_filters = 0x025D,
177 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
178 i40e_aqc_opc_replace_cloud_filters = 0x025F,
180 i40e_aqc_opc_add_mirror_rule = 0x0260,
181 i40e_aqc_opc_delete_mirror_rule = 0x0261,
183 /* Dynamic Device Personalization */
184 i40e_aqc_opc_write_personalization_profile = 0x0270,
185 i40e_aqc_opc_get_personalization_profile_list = 0x0271,
188 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
189 i40e_aqc_opc_dcb_updated = 0x0302,
190 i40e_aqc_opc_set_dcb_parameters = 0x0303,
193 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
194 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
195 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
196 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
197 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
198 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
200 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
201 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
202 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
203 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
204 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
205 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
206 i40e_aqc_opc_query_port_ets_config = 0x0419,
207 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
208 i40e_aqc_opc_suspend_port_tx = 0x041B,
209 i40e_aqc_opc_resume_port_tx = 0x041C,
210 i40e_aqc_opc_configure_partition_bw = 0x041D,
212 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
213 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
216 i40e_aqc_opc_get_phy_abilities = 0x0600,
217 i40e_aqc_opc_set_phy_config = 0x0601,
218 i40e_aqc_opc_set_mac_config = 0x0603,
219 i40e_aqc_opc_set_link_restart_an = 0x0605,
220 i40e_aqc_opc_get_link_status = 0x0607,
221 i40e_aqc_opc_set_phy_int_mask = 0x0613,
222 i40e_aqc_opc_get_local_advt_reg = 0x0614,
223 i40e_aqc_opc_set_local_advt_reg = 0x0615,
224 i40e_aqc_opc_get_partner_advt = 0x0616,
225 i40e_aqc_opc_set_lb_modes = 0x0618,
226 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
227 i40e_aqc_opc_set_phy_debug = 0x0622,
228 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
229 i40e_aqc_opc_run_phy_activity = 0x0626,
230 i40e_aqc_opc_set_phy_register = 0x0628,
231 i40e_aqc_opc_get_phy_register = 0x0629,
234 i40e_aqc_opc_nvm_read = 0x0701,
235 i40e_aqc_opc_nvm_erase = 0x0702,
236 i40e_aqc_opc_nvm_update = 0x0703,
237 i40e_aqc_opc_nvm_config_read = 0x0704,
238 i40e_aqc_opc_nvm_config_write = 0x0705,
239 i40e_aqc_opc_nvm_progress = 0x0706,
240 i40e_aqc_opc_oem_post_update = 0x0720,
241 i40e_aqc_opc_thermal_sensor = 0x0721,
243 /* virtualization commands */
244 i40e_aqc_opc_send_msg_to_pf = 0x0801,
245 i40e_aqc_opc_send_msg_to_vf = 0x0802,
246 i40e_aqc_opc_send_msg_to_peer = 0x0803,
248 /* alternate structure */
249 i40e_aqc_opc_alternate_write = 0x0900,
250 i40e_aqc_opc_alternate_write_indirect = 0x0901,
251 i40e_aqc_opc_alternate_read = 0x0902,
252 i40e_aqc_opc_alternate_read_indirect = 0x0903,
253 i40e_aqc_opc_alternate_write_done = 0x0904,
254 i40e_aqc_opc_alternate_set_mode = 0x0905,
255 i40e_aqc_opc_alternate_clear_port = 0x0906,
258 i40e_aqc_opc_lldp_get_mib = 0x0A00,
259 i40e_aqc_opc_lldp_update_mib = 0x0A01,
260 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
261 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
262 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
263 i40e_aqc_opc_lldp_stop = 0x0A05,
264 i40e_aqc_opc_lldp_start = 0x0A06,
265 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
266 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
267 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
269 /* Tunnel commands */
270 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
271 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
272 i40e_aqc_opc_set_rss_key = 0x0B02,
273 i40e_aqc_opc_set_rss_lut = 0x0B03,
274 i40e_aqc_opc_get_rss_key = 0x0B04,
275 i40e_aqc_opc_get_rss_lut = 0x0B05,
278 i40e_aqc_opc_event_lan_overflow = 0x1001,
281 i40e_aqc_opc_oem_parameter_change = 0xFE00,
282 i40e_aqc_opc_oem_device_status_change = 0xFE01,
283 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
284 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
287 i40e_aqc_opc_debug_read_reg = 0xFF03,
288 i40e_aqc_opc_debug_write_reg = 0xFF04,
289 i40e_aqc_opc_debug_modify_reg = 0xFF07,
290 i40e_aqc_opc_debug_dump_internals = 0xFF08,
293 /* command structures and indirect data structures */
295 /* Structure naming conventions:
296 * - no suffix for direct command descriptor structures
297 * - _data for indirect sent data
298 * - _resp for indirect return data (data which is both will use _data)
299 * - _completion for direct return data
300 * - _element_ for repeated elements (may also be _data or _resp)
302 * Command structures are expected to overlay the params.raw member of the basic
303 * descriptor, and as such cannot exceed 16 bytes in length.
306 /* This macro is used to generate a compilation error if a structure
307 * is not exactly the correct length. It gives a divide by zero error if the
308 * structure is not of the correct size, otherwise it creates an enum that is
311 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
312 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
314 /* This macro is used extensively to ensure that command structures are 16
315 * bytes in length as they have to map to the raw array of that size.
317 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
319 /* internal (0x00XX) commands */
321 /* Get version (direct 0x0001) */
322 struct i40e_aqc_get_version {
331 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
333 /* Send driver version (indirect 0x0002) */
334 struct i40e_aqc_driver_version {
338 u8 driver_subbuild_ver;
344 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
346 /* Queue Shutdown (direct 0x0003) */
347 struct i40e_aqc_queue_shutdown {
348 __le32 driver_unloading;
349 #define I40E_AQ_DRIVER_UNLOADING 0x1
353 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
355 /* Set PF context (0x0004, direct) */
356 struct i40e_aqc_set_pf_context {
361 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
363 /* Request resource ownership (direct 0x0008)
364 * Release resource ownership (direct 0x0009)
366 #define I40E_AQ_RESOURCE_NVM 1
367 #define I40E_AQ_RESOURCE_SDP 2
368 #define I40E_AQ_RESOURCE_ACCESS_READ 1
369 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
370 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
371 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
373 struct i40e_aqc_request_resource {
377 __le32 resource_number;
381 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
383 /* Get function capabilities (indirect 0x000A)
384 * Get device capabilities (indirect 0x000B)
386 struct i40e_aqc_list_capabilites {
388 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
396 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
398 struct i40e_aqc_list_capabilities_element_resp {
410 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
411 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
412 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
413 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
414 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
415 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
416 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
417 #define I40E_AQ_CAP_ID_SRIOV 0x0012
418 #define I40E_AQ_CAP_ID_VF 0x0013
419 #define I40E_AQ_CAP_ID_VMDQ 0x0014
420 #define I40E_AQ_CAP_ID_8021QBG 0x0015
421 #define I40E_AQ_CAP_ID_8021QBR 0x0016
422 #define I40E_AQ_CAP_ID_VSI 0x0017
423 #define I40E_AQ_CAP_ID_DCB 0x0018
424 #define I40E_AQ_CAP_ID_FCOE 0x0021
425 #define I40E_AQ_CAP_ID_ISCSI 0x0022
426 #define I40E_AQ_CAP_ID_RSS 0x0040
427 #define I40E_AQ_CAP_ID_RXQ 0x0041
428 #define I40E_AQ_CAP_ID_TXQ 0x0042
429 #define I40E_AQ_CAP_ID_MSIX 0x0043
430 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
431 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
432 #define I40E_AQ_CAP_ID_1588 0x0046
433 #define I40E_AQ_CAP_ID_IWARP 0x0051
434 #define I40E_AQ_CAP_ID_LED 0x0061
435 #define I40E_AQ_CAP_ID_SDP 0x0062
436 #define I40E_AQ_CAP_ID_MDIO 0x0063
437 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
438 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
439 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
440 #define I40E_AQ_CAP_ID_CEM 0x00F2
442 /* Set CPPM Configuration (direct 0x0103) */
443 struct i40e_aqc_cppm_configuration {
444 __le16 command_flags;
445 #define I40E_AQ_CPPM_EN_LTRC 0x0800
446 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
447 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
448 #define I40E_AQ_CPPM_EN_HPTC 0x4000
449 #define I40E_AQ_CPPM_EN_DMARC 0x8000
458 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
460 /* Set ARP Proxy command / response (indirect 0x0104) */
461 struct i40e_aqc_arp_proxy_data {
462 __le16 command_flags;
463 #define I40E_AQ_ARP_INIT_IPV4 0x0800
464 #define I40E_AQ_ARP_UNSUP_CTL 0x1000
465 #define I40E_AQ_ARP_ENA 0x2000
466 #define I40E_AQ_ARP_ADD_IPV4 0x4000
467 #define I40E_AQ_ARP_DEL_IPV4 0x8000
469 __le32 enabled_offloads;
470 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
471 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
477 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
479 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
480 struct i40e_aqc_ns_proxy_data {
481 __le16 table_idx_mac_addr_0;
482 __le16 table_idx_mac_addr_1;
483 __le16 table_idx_ipv6_0;
484 __le16 table_idx_ipv6_1;
486 #define I40E_AQ_NS_PROXY_ADD_0 0x0001
487 #define I40E_AQ_NS_PROXY_DEL_0 0x0002
488 #define I40E_AQ_NS_PROXY_ADD_1 0x0004
489 #define I40E_AQ_NS_PROXY_DEL_1 0x0008
490 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
491 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
492 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
493 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
494 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
495 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
496 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
497 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
498 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
501 u8 local_mac_addr[6];
502 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
506 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
508 /* Manage LAA Command (0x0106) - obsolete */
509 struct i40e_aqc_mng_laa {
510 __le16 command_flags;
511 #define I40E_AQ_LAA_FLAG_WR 0x8000
518 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
520 /* Manage MAC Address Read Command (indirect 0x0107) */
521 struct i40e_aqc_mac_address_read {
522 __le16 command_flags;
523 #define I40E_AQC_LAN_ADDR_VALID 0x10
524 #define I40E_AQC_SAN_ADDR_VALID 0x20
525 #define I40E_AQC_PORT_ADDR_VALID 0x40
526 #define I40E_AQC_WOL_ADDR_VALID 0x80
527 #define I40E_AQC_MC_MAG_EN_VALID 0x100
528 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200
529 #define I40E_AQC_ADDR_VALID_MASK 0x3F0
535 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
537 struct i40e_aqc_mac_address_read_data {
544 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
546 /* Manage MAC Address Write Command (0x0108) */
547 struct i40e_aqc_mac_address_write {
548 __le16 command_flags;
549 #define I40E_AQC_MC_MAG_EN 0x0100
550 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
551 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
552 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
553 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
554 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
555 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
562 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
564 /* PXE commands (0x011x) */
566 /* Clear PXE Command and response (direct 0x0110) */
567 struct i40e_aqc_clear_pxe {
572 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
574 /* Set WoL Filter (0x0120) */
576 struct i40e_aqc_set_wol_filter {
578 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
579 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
580 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
581 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
583 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
584 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
585 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
587 #define I40E_AQC_SET_WOL_FILTER 0x8000
588 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
589 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000
590 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
591 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
593 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
594 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
600 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
602 struct i40e_aqc_set_wol_filter_data {
607 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
609 /* Get Wake Reason (0x0121) */
611 struct i40e_aqc_get_wake_reason_completion {
614 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
615 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
616 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
617 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
618 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
619 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
623 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
625 /* Switch configuration commands (0x02xx) */
627 /* Used by many indirect commands that only pass an seid and a buffer in the
630 struct i40e_aqc_switch_seid {
637 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
639 /* Get Switch Configuration command (indirect 0x0200)
640 * uses i40e_aqc_switch_seid for the descriptor
642 struct i40e_aqc_get_switch_config_header_resp {
648 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
650 struct i40e_aqc_switch_config_element_resp {
652 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
653 #define I40E_AQ_SW_ELEM_TYPE_PF 2
654 #define I40E_AQ_SW_ELEM_TYPE_VF 3
655 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
656 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
657 #define I40E_AQ_SW_ELEM_TYPE_PV 16
658 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
659 #define I40E_AQ_SW_ELEM_TYPE_PA 18
660 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
662 #define I40E_AQ_SW_ELEM_REV_1 1
665 __le16 downlink_seid;
668 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
669 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
670 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
675 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
677 /* Get Switch Configuration (indirect 0x0200)
678 * an array of elements are returned in the response buffer
679 * the first in the array is the header, remainder are elements
681 struct i40e_aqc_get_switch_config_resp {
682 struct i40e_aqc_get_switch_config_header_resp header;
683 struct i40e_aqc_switch_config_element_resp element[1];
686 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
688 /* Add Statistics (direct 0x0201)
689 * Remove Statistics (direct 0x0202)
691 struct i40e_aqc_add_remove_statistics {
698 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
700 /* Set Port Parameters command (direct 0x0203) */
701 struct i40e_aqc_set_port_parameters {
702 __le16 command_flags;
703 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
704 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
705 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
706 __le16 bad_frame_vsi;
707 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
708 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
709 __le16 default_seid; /* reserved for command */
713 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
715 /* Get Switch Resource Allocation (indirect 0x0204) */
716 struct i40e_aqc_get_switch_resource_alloc {
717 u8 num_entries; /* reserved for command */
723 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
725 /* expect an array of these structs in the response buffer */
726 struct i40e_aqc_switch_resource_alloc_element_resp {
728 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
729 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
730 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
731 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
732 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
733 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
734 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
735 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
736 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
737 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
738 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
739 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
740 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
741 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
742 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
743 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
744 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
745 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
746 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
751 __le16 total_unalloced;
755 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
757 /* Set Switch Configuration (direct 0x0205) */
758 struct i40e_aqc_set_switch_config {
760 /* flags used for both fields below */
761 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
762 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
763 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004
765 /* The ethertype in switch_tag is dropped on ingress and used
766 * internally by the switch. Set this to zero for the default
767 * of 0x88a8 (802.1ad). Should be zero for firmware API
768 * versions lower than 1.7.
771 /* The ethertypes in first_tag and second_tag are used to
772 * match the outer and inner VLAN tags (respectively) when HW
773 * double VLAN tagging is enabled via the set port parameters
774 * AQ command. Otherwise these are both ignored. Set them to
775 * zero for their defaults of 0x8100 (802.1Q). Should be zero
776 * for firmware API versions lower than 1.7.
780 /* Next byte is split into following:
781 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0
782 * Bit 6 : 0 : Destination Port, 1: source port
787 * 3: Both TCP and UDP
790 * 1: L4 port only mode
791 * 2: non-tunneled mode
794 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80
796 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40
798 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00
799 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10
800 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20
801 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30
803 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00
804 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01
805 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02
806 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03
811 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
813 /* Read Receive control registers (direct 0x0206)
814 * Write Receive control registers (direct 0x0207)
815 * used for accessing Rx control registers that can be
816 * slow and need special handling when under high Rx load
818 struct i40e_aqc_rx_ctl_reg_read_write {
825 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
827 /* Add VSI (indirect 0x0210)
828 * this indirect command uses struct i40e_aqc_vsi_properties_data
829 * as the indirect buffer (128 bytes)
831 * Update VSI (indirect 0x211)
832 * uses the same data structure as Add VSI
834 * Get VSI (indirect 0x0212)
835 * uses the same completion and data structure as Add VSI
837 struct i40e_aqc_add_get_update_vsi {
840 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
841 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
842 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
847 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
848 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
849 #define I40E_AQ_VSI_TYPE_VF 0x0
850 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
851 #define I40E_AQ_VSI_TYPE_PF 0x2
852 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
853 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
858 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
860 struct i40e_aqc_add_get_update_vsi_completion {
869 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
871 struct i40e_aqc_vsi_properties_data {
872 /* first 96 byte are written by SW */
873 __le16 valid_sections;
874 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
875 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
876 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
877 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
878 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
879 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
880 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
881 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
882 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
883 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
885 __le16 switch_id; /* 12bit id combined with flags below */
886 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
887 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
888 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
889 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
890 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
892 /* security section */
894 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
895 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
896 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
899 __le16 pvid; /* VLANS include priority bits */
902 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
903 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
904 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
905 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
906 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
907 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
908 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
909 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
910 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
911 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
912 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
913 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
914 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
915 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
916 u8 pvlan_reserved[3];
917 /* ingress egress up sections */
918 __le32 ingress_table; /* bitmap, 3 bits per up */
919 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
920 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
921 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
922 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
923 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
924 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
925 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
926 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
927 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
928 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
929 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
930 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
931 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
932 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
933 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
934 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
935 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
936 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
937 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
938 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
939 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
940 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
941 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
942 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
943 __le32 egress_table; /* same defines as for ingress table */
944 /* cascaded PV section */
947 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
948 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
949 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
950 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
951 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
952 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
953 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
954 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
955 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
957 /* queue mapping section */
958 __le16 mapping_flags;
959 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
960 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
961 __le16 queue_mapping[16];
962 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
963 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
964 __le16 tc_mapping[8];
965 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
966 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
967 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
968 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
969 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
970 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
971 /* queueing option section */
972 u8 queueing_opt_flags;
973 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
974 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
975 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
976 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
977 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
978 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
979 u8 queueing_opt_reserved[3];
980 /* scheduler section */
983 /* outer up section */
984 __le32 outer_up_table; /* same structure and defines as ingress tbl */
986 /* last 32 bytes are written by FW */
988 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
989 __le16 stat_counter_idx;
991 u8 resp_reserved[12];
994 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
996 /* Add Port Virtualizer (direct 0x0220)
997 * also used for update PV (direct 0x0221) but only flags are used
998 * (IS_CTRL_PORT only works on add PV)
1000 struct i40e_aqc_add_update_pv {
1001 __le16 command_flags;
1002 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
1003 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
1004 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
1005 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
1007 __le16 connected_seid;
1011 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
1013 struct i40e_aqc_add_update_pv_completion {
1014 /* reserved for update; for add also encodes error if rc == ENOSPC */
1016 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
1017 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
1018 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
1019 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
1023 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
1025 /* Get PV Params (direct 0x0222)
1026 * uses i40e_aqc_switch_seid for the descriptor
1029 struct i40e_aqc_get_pv_params_completion {
1031 __le16 default_stag;
1032 __le16 pv_flags; /* same flags as add_pv */
1033 #define I40E_AQC_GET_PV_PV_TYPE 0x1
1034 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1035 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1037 __le16 default_port_seid;
1040 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1042 /* Add VEB (direct 0x0230) */
1043 struct i40e_aqc_add_veb {
1045 __le16 downlink_seid;
1047 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1048 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1049 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1050 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1051 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1052 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1053 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1054 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1059 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1061 struct i40e_aqc_add_veb_completion {
1064 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1066 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1067 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1068 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1069 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1070 __le16 statistic_index;
1075 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1077 /* Get VEB Parameters (direct 0x0232)
1078 * uses i40e_aqc_switch_seid for the descriptor
1080 struct i40e_aqc_get_veb_parameters_completion {
1083 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1084 __le16 statistic_index;
1090 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1092 /* Delete Element (direct 0x0243)
1093 * uses the generic i40e_aqc_switch_seid
1096 /* Add MAC-VLAN (indirect 0x0250) */
1098 /* used for the command for most vlan commands */
1099 struct i40e_aqc_macvlan {
1100 __le16 num_addresses;
1102 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1103 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1104 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1105 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1110 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1112 /* indirect data for command and response */
1113 struct i40e_aqc_add_macvlan_element_data {
1117 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1118 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1119 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1120 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1121 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1122 __le16 queue_number;
1123 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1124 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1125 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1126 /* response section */
1128 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1129 #define I40E_AQC_MM_HASH_MATCH 0x02
1130 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1134 struct i40e_aqc_add_remove_macvlan_completion {
1135 __le16 perfect_mac_used;
1136 __le16 perfect_mac_free;
1137 __le16 unicast_hash_free;
1138 __le16 multicast_hash_free;
1143 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1145 /* Remove MAC-VLAN (indirect 0x0251)
1146 * uses i40e_aqc_macvlan for the descriptor
1147 * data points to an array of num_addresses of elements
1150 struct i40e_aqc_remove_macvlan_element_data {
1154 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1155 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1156 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1157 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1161 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1162 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1163 u8 reply_reserved[3];
1166 /* Add VLAN (indirect 0x0252)
1167 * Remove VLAN (indirect 0x0253)
1168 * use the generic i40e_aqc_macvlan for the command
1170 struct i40e_aqc_add_remove_vlan_element_data {
1173 /* flags for add VLAN */
1174 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1175 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1176 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1177 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1178 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1179 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1180 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1181 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1182 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1183 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1184 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1185 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1186 /* flags for remove VLAN */
1187 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1190 /* flags for add VLAN */
1191 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1192 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1193 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1194 /* flags for remove VLAN */
1195 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1196 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1200 struct i40e_aqc_add_remove_vlan_completion {
1208 /* Set VSI Promiscuous Modes (direct 0x0254) */
1209 struct i40e_aqc_set_vsi_promiscuous_modes {
1210 __le16 promiscuous_flags;
1212 /* flags used for both fields above */
1213 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1214 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1215 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1216 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1217 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1218 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1220 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1222 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1223 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1227 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1229 /* Add S/E-tag command (direct 0x0255)
1230 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1232 struct i40e_aqc_add_tag {
1234 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1236 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1237 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1238 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1240 __le16 queue_number;
1244 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1246 struct i40e_aqc_add_remove_tag_completion {
1252 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1254 /* Remove S/E-tag command (direct 0x0256)
1255 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1257 struct i40e_aqc_remove_tag {
1259 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1260 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1261 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1266 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1268 /* Add multicast E-Tag (direct 0x0257)
1269 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1270 * and no external data
1272 struct i40e_aqc_add_remove_mcast_etag {
1275 u8 num_unicast_etags;
1277 __le32 addr_high; /* address of array of 2-byte s-tags */
1281 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1283 struct i40e_aqc_add_remove_mcast_etag_completion {
1285 __le16 mcast_etags_used;
1286 __le16 mcast_etags_free;
1292 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1294 /* Update S/E-Tag (direct 0x0259) */
1295 struct i40e_aqc_update_tag {
1297 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1298 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1299 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1305 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1307 struct i40e_aqc_update_tag_completion {
1313 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1315 /* Add Control Packet filter (direct 0x025A)
1316 * Remove Control Packet filter (direct 0x025B)
1317 * uses the i40e_aqc_add_oveb_cloud,
1318 * and the generic direct completion structure
1320 struct i40e_aqc_add_remove_control_packet_filter {
1324 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1325 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1326 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1327 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1328 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1330 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1331 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1332 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1337 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1339 struct i40e_aqc_add_remove_control_packet_filter_completion {
1340 __le16 mac_etype_used;
1342 __le16 mac_etype_free;
1347 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1349 /* Add Cloud filters (indirect 0x025C)
1350 * Remove Cloud filters (indirect 0x025D)
1351 * uses the i40e_aqc_add_remove_cloud_filters,
1352 * and the generic indirect completion structure
1354 struct i40e_aqc_add_remove_cloud_filters {
1358 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1359 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1360 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1362 #define I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1
1363 #define I40E_AQC_ADD_CLOUD_CMD_BB 1
1369 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1371 struct i40e_aqc_cloud_filters_element_data {
1388 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1389 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1390 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1391 /* 0x0000 reserved */
1392 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1393 /* 0x0002 reserved */
1394 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1395 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1396 /* 0x0005 reserved */
1397 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1398 /* 0x0007 reserved */
1399 /* 0x0008 reserved */
1400 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1401 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1402 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1403 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1404 /* 0x0010 to 0x0017 is for custom filters */
1405 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */
1406 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */
1407 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */
1409 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1410 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1411 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1412 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1413 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1415 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1416 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1417 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1418 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1419 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1420 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1421 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1422 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1424 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1425 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1426 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1430 __le16 queue_number;
1431 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1432 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1433 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1435 /* response section */
1436 u8 allocation_result;
1437 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1438 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1439 u8 response_reserved[7];
1442 /* i40e_aqc_add_rm_cloud_filt_elem_ext is used when
1443 * I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set.
1445 struct i40e_aqc_add_rm_cloud_filt_elem_ext {
1446 struct i40e_aqc_cloud_filters_element_data element;
1447 u16 general_fields[32];
1448 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
1449 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
1450 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
1451 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
1452 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
1453 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
1454 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
1455 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
1456 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
1457 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
1458 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
1459 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
1460 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
1461 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
1462 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
1463 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1464 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
1465 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
1466 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
1467 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
1468 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
1469 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
1470 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
1471 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
1472 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
1473 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
1474 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
1475 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
1476 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
1477 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
1478 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
1481 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1483 /* i40e_aqc_cloud_filters_element_bb is used when
1484 * I40E_AQC_CLOUD_CMD_BB flag is set.
1486 struct i40e_aqc_cloud_filters_element_bb {
1487 struct i40e_aqc_cloud_filters_element_data element;
1488 u16 general_fields[32];
1489 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
1490 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
1491 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
1492 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
1493 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
1494 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
1495 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
1496 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
1497 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
1498 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
1499 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
1500 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
1501 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
1502 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
1503 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
1504 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1505 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
1506 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
1507 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
1508 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
1509 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
1510 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
1511 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
1512 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
1513 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
1514 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
1515 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
1516 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
1517 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
1518 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
1519 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
1522 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1524 struct i40e_aqc_remove_cloud_filters_completion {
1525 __le16 perfect_ovlan_used;
1526 __le16 perfect_ovlan_free;
1533 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1535 /* Replace filter Command 0x025F
1536 * uses the i40e_aqc_replace_cloud_filters,
1537 * and the generic indirect completion structure
1539 struct i40e_filter_data {
1544 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);
1546 struct i40e_aqc_replace_cloud_filters_cmd {
1548 #define I40E_AQC_REPLACE_L1_FILTER 0x0
1549 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1
1550 #define I40E_AQC_GET_CLOUD_FILTERS 0x2
1551 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4
1552 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8
1562 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);
1564 struct i40e_aqc_replace_cloud_filters_cmd_buf {
1566 /* Filter type INPUT codes*/
1567 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3
1568 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL)
1570 /* Field Vector offsets */
1571 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0
1572 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6
1573 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7
1574 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8
1575 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9
1576 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10
1577 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11
1578 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12
1580 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14
1582 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15
1584 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37
1585 struct i40e_filter_data filters[8];
1588 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1590 /* Add Mirror Rule (indirect or direct 0x0260)
1591 * Delete Mirror Rule (indirect or direct 0x0261)
1592 * note: some rule types (4,5) do not use an external buffer.
1593 * take care to set the flags correctly.
1595 struct i40e_aqc_add_delete_mirror_rule {
1598 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1599 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1600 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1601 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1602 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1603 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1604 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1605 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1607 __le16 destination; /* VSI for add, rule id for delete */
1608 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1612 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1614 struct i40e_aqc_add_delete_mirror_rule_completion {
1616 __le16 rule_id; /* only used on add */
1617 __le16 mirror_rules_used;
1618 __le16 mirror_rules_free;
1623 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1625 /* Dynamic Device Personalization */
1626 struct i40e_aqc_write_personalization_profile {
1629 __le32 profile_track_id;
1634 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1636 struct i40e_aqc_write_ddp_resp {
1637 __le32 error_offset;
1643 struct i40e_aqc_get_applied_profiles {
1645 #define I40E_AQC_GET_DDP_GET_CONF 0x1
1646 #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2
1653 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1657 /* PFC Ignore (direct 0x0301)
1658 * the command and response use the same descriptor structure
1660 struct i40e_aqc_pfc_ignore {
1662 u8 command_flags; /* unused on response */
1663 #define I40E_AQC_PFC_IGNORE_SET 0x80
1664 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1668 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1670 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1671 * with no parameters
1674 /* TX scheduler 0x04xx */
1676 /* Almost all the indirect commands use
1677 * this generic struct to pass the SEID in param0
1679 struct i40e_aqc_tx_sched_ind {
1686 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1688 /* Several commands respond with a set of queue set handles */
1689 struct i40e_aqc_qs_handles_resp {
1690 __le16 qs_handles[8];
1693 /* Configure VSI BW limits (direct 0x0400) */
1694 struct i40e_aqc_configure_vsi_bw_limit {
1699 u8 max_credit; /* 0-3, limit = 2^max */
1703 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1705 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1706 * responds with i40e_aqc_qs_handles_resp
1708 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1711 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1713 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1714 __le16 tc_bw_max[2];
1718 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1720 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1721 * responds with i40e_aqc_qs_handles_resp
1723 struct i40e_aqc_configure_vsi_tc_bw_data {
1726 u8 tc_bw_credits[8];
1728 __le16 qs_handles[8];
1731 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1733 /* Query vsi bw configuration (indirect 0x0408) */
1734 struct i40e_aqc_query_vsi_bw_config_resp {
1736 u8 tc_suspended_bits;
1738 __le16 qs_handles[8];
1740 __le16 port_bw_limit;
1742 u8 max_bw; /* 0-3, limit = 2^max */
1746 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1748 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1749 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1752 u8 share_credits[8];
1755 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1756 __le16 tc_bw_max[2];
1759 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1761 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1762 struct i40e_aqc_configure_switching_comp_bw_limit {
1767 u8 max_bw; /* 0-3, limit = 2^max */
1771 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1773 /* Enable Physical Port ETS (indirect 0x0413)
1774 * Modify Physical Port ETS (indirect 0x0414)
1775 * Disable Physical Port ETS (indirect 0x0415)
1777 struct i40e_aqc_configure_switching_comp_ets_data {
1781 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1782 u8 tc_strict_priority_flags;
1784 u8 tc_bw_share_credits[8];
1788 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1790 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1791 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1794 __le16 tc_bw_credit[8];
1796 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1797 __le16 tc_bw_max[2];
1801 I40E_CHECK_STRUCT_LEN(0x40,
1802 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1804 /* Configure Switching Component Bandwidth Allocation per Tc
1807 struct i40e_aqc_configure_switching_comp_bw_config_data {
1810 u8 absolute_credits; /* bool */
1811 u8 tc_bw_share_credits[8];
1815 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1817 /* Query Switching Component Configuration (indirect 0x0418) */
1818 struct i40e_aqc_query_switching_comp_ets_config_resp {
1821 __le16 port_bw_limit;
1823 u8 tc_bw_max; /* 0-3, limit = 2^max */
1827 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1829 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1830 struct i40e_aqc_query_port_ets_config_resp {
1834 u8 tc_strict_priority_bits;
1836 u8 tc_bw_share_credits[8];
1837 __le16 tc_bw_limits[8];
1839 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1840 __le16 tc_bw_max[2];
1844 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1846 /* Query Switching Component Bandwidth Allocation per Traffic Type
1849 struct i40e_aqc_query_switching_comp_bw_config_resp {
1852 u8 absolute_credits_enable; /* bool */
1853 u8 tc_bw_share_credits[8];
1854 __le16 tc_bw_limits[8];
1856 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1857 __le16 tc_bw_max[2];
1860 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1862 /* Suspend/resume port TX traffic
1863 * (direct 0x041B and 0x041C) uses the generic SEID struct
1866 /* Configure partition BW
1869 struct i40e_aqc_configure_partition_bw_data {
1870 __le16 pf_valid_bits;
1871 u8 min_bw[16]; /* guaranteed bandwidth */
1872 u8 max_bw[16]; /* bandwidth limit */
1875 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1877 /* Get and set the active HMC resource profile and status.
1878 * (direct 0x0500) and (direct 0x0501)
1880 struct i40e_aq_get_set_hmc_resource_profile {
1886 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1888 enum i40e_aq_hmc_profile {
1889 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1890 I40E_HMC_PROFILE_DEFAULT = 1,
1891 I40E_HMC_PROFILE_FAVOR_VF = 2,
1892 I40E_HMC_PROFILE_EQUAL = 3,
1895 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1897 /* set in param0 for get phy abilities to report qualified modules */
1898 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1899 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1901 enum i40e_aq_phy_type {
1902 I40E_PHY_TYPE_SGMII = 0x0,
1903 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1904 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1905 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1906 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1907 I40E_PHY_TYPE_XAUI = 0x5,
1908 I40E_PHY_TYPE_XFI = 0x6,
1909 I40E_PHY_TYPE_SFI = 0x7,
1910 I40E_PHY_TYPE_XLAUI = 0x8,
1911 I40E_PHY_TYPE_XLPPI = 0x9,
1912 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1913 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1914 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1915 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1916 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1917 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1918 I40E_PHY_TYPE_100BASE_TX = 0x11,
1919 I40E_PHY_TYPE_1000BASE_T = 0x12,
1920 I40E_PHY_TYPE_10GBASE_T = 0x13,
1921 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1922 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1923 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1924 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1925 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1926 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1927 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1928 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1929 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1930 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1931 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1932 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1933 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1934 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1935 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1936 I40E_PHY_TYPE_25GBASE_AOC = 0x23,
1937 I40E_PHY_TYPE_25GBASE_ACC = 0x24,
1938 I40E_PHY_TYPE_2_5GBASE_T = 0x30,
1939 I40E_PHY_TYPE_5GBASE_T = 0x31,
1941 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1942 I40E_PHY_TYPE_EMPTY = 0xFE,
1943 I40E_PHY_TYPE_DEFAULT = 0xFF,
1946 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
1947 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
1948 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
1949 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1950 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
1951 BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1952 BIT_ULL(I40E_PHY_TYPE_XFI) | \
1953 BIT_ULL(I40E_PHY_TYPE_SFI) | \
1954 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1955 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1956 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
1957 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
1958 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
1959 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
1960 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
1961 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
1962 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1963 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1964 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1965 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
1966 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
1967 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
1968 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
1969 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
1970 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
1971 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
1972 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
1973 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
1974 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
1975 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
1976 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
1977 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
1978 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
1979 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
1980 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
1981 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
1982 BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
1983 BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
1985 #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0
1986 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1987 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1988 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1989 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1990 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1991 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1992 #define I40E_LINK_SPEED_5GB_SHIFT 0x7
1994 enum i40e_aq_link_speed {
1995 I40E_LINK_SPEED_UNKNOWN = 0,
1996 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1997 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1998 I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT),
1999 I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT),
2000 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
2001 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
2002 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT),
2003 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT),
2006 struct i40e_aqc_module_desc {
2014 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
2016 struct i40e_aq_get_phy_abilities_resp {
2017 __le32 phy_type; /* bitmap using the above enum for offsets */
2018 u8 link_speed; /* bitmap using the above enum bit patterns */
2020 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
2021 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
2022 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
2023 #define I40E_AQ_PHY_LINK_ENABLED 0x08
2024 #define I40E_AQ_PHY_AN_ENABLED 0x10
2025 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
2026 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
2027 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
2028 __le16 eee_capability;
2029 #define I40E_AQ_EEE_100BASE_TX 0x0002
2030 #define I40E_AQ_EEE_1000BASE_T 0x0004
2031 #define I40E_AQ_EEE_10GBASE_T 0x0008
2032 #define I40E_AQ_EEE_1000BASE_KX 0x0010
2033 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
2034 #define I40E_AQ_EEE_10GBASE_KR 0x0040
2037 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
2039 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01
2040 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02
2041 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
2042 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
2043 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10
2044 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20
2045 #define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40
2046 #define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80
2047 u8 fec_cfg_curr_mod_ext_info;
2048 #define I40E_AQ_ENABLE_FEC_KR 0x01
2049 #define I40E_AQ_ENABLE_FEC_RS 0x02
2050 #define I40E_AQ_REQUEST_FEC_KR 0x04
2051 #define I40E_AQ_REQUEST_FEC_RS 0x08
2052 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
2054 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
2055 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5
2060 u8 qualified_module_count;
2061 #define I40E_AQ_PHY_MAX_QMS 16
2062 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
2065 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
2067 /* Set PHY Config (direct 0x0601) */
2068 struct i40e_aq_set_phy_config { /* same bits as above in all */
2072 /* bits 0-2 use the values from get_phy_abilities_resp */
2073 #define I40E_AQ_PHY_ENABLE_LINK 0x08
2074 #define I40E_AQ_PHY_ENABLE_AN 0x10
2075 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
2076 __le16 eee_capability;
2081 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
2082 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
2083 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
2084 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
2085 #define I40E_AQ_SET_FEC_AUTO BIT(4)
2086 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
2087 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
2091 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
2093 /* Set MAC Config command data structure (direct 0x0603) */
2094 struct i40e_aq_set_mac_config {
2095 __le16 max_frame_size;
2097 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
2098 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
2099 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
2100 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
2101 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
2102 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
2103 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
2104 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
2105 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
2106 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
2107 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
2108 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
2109 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
2110 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
2111 u8 tx_timer_priority; /* bitmap */
2112 __le16 tx_timer_value;
2113 __le16 fc_refresh_threshold;
2117 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
2119 /* Restart Auto-Negotiation (direct 0x605) */
2120 struct i40e_aqc_set_link_restart_an {
2122 #define I40E_AQ_PHY_RESTART_AN 0x02
2123 #define I40E_AQ_PHY_LINK_ENABLE 0x04
2127 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
2129 /* Get Link Status cmd & response data structure (direct 0x0607) */
2130 struct i40e_aqc_get_link_status {
2131 __le16 command_flags; /* only field set on command */
2132 #define I40E_AQ_LSE_MASK 0x3
2133 #define I40E_AQ_LSE_NOP 0x0
2134 #define I40E_AQ_LSE_DISABLE 0x2
2135 #define I40E_AQ_LSE_ENABLE 0x3
2136 /* only response uses this flag */
2137 #define I40E_AQ_LSE_IS_ENABLED 0x1
2138 u8 phy_type; /* i40e_aq_phy_type */
2139 u8 link_speed; /* i40e_aq_link_speed */
2141 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
2142 #define I40E_AQ_LINK_UP_FUNCTION 0x01
2143 #define I40E_AQ_LINK_FAULT 0x02
2144 #define I40E_AQ_LINK_FAULT_TX 0x04
2145 #define I40E_AQ_LINK_FAULT_RX 0x08
2146 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
2147 #define I40E_AQ_LINK_UP_PORT 0x20
2148 #define I40E_AQ_MEDIA_AVAILABLE 0x40
2149 #define I40E_AQ_SIGNAL_DETECT 0x80
2151 #define I40E_AQ_AN_COMPLETED 0x01
2152 #define I40E_AQ_LP_AN_ABILITY 0x02
2153 #define I40E_AQ_PD_FAULT 0x04
2154 #define I40E_AQ_FEC_EN 0x08
2155 #define I40E_AQ_PHY_LOW_POWER 0x10
2156 #define I40E_AQ_LINK_PAUSE_TX 0x20
2157 #define I40E_AQ_LINK_PAUSE_RX 0x40
2158 #define I40E_AQ_QUALIFIED_MODULE 0x80
2160 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
2161 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
2162 #define I40E_AQ_LINK_TX_SHIFT 0x02
2163 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
2164 #define I40E_AQ_LINK_TX_ACTIVE 0x00
2165 #define I40E_AQ_LINK_TX_DRAINED 0x01
2166 #define I40E_AQ_LINK_TX_FLUSHED 0x03
2167 #define I40E_AQ_LINK_FORCED_40G 0x10
2168 /* 25G Error Codes */
2169 #define I40E_AQ_25G_NO_ERR 0X00
2170 #define I40E_AQ_25G_NOT_PRESENT 0X01
2171 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
2172 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
2173 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
2174 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
2175 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
2176 /* Since firmware API 1.7 loopback field keeps power class info as well */
2177 #define I40E_AQ_LOOPBACK_MASK 0x07
2178 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6
2179 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)
2180 __le16 max_frame_size;
2182 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
2183 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
2184 #define I40E_AQ_CONFIG_CRC_ENA 0x04
2185 #define I40E_AQ_CONFIG_PACING_MASK 0x78
2189 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
2190 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
2191 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
2192 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
2193 #define I40E_AQ_PWR_CLASS_MASK 0x03
2203 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
2205 /* Set event mask command (direct 0x613) */
2206 struct i40e_aqc_set_phy_int_mask {
2209 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
2210 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
2211 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
2212 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
2213 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
2214 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
2215 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
2216 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
2217 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
2221 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
2223 /* Get Local AN advt register (direct 0x0614)
2224 * Set Local AN advt register (direct 0x0615)
2225 * Get Link Partner AN advt register (direct 0x0616)
2227 struct i40e_aqc_an_advt_reg {
2228 __le32 local_an_reg0;
2229 __le16 local_an_reg1;
2233 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
2235 /* Set Loopback mode (0x0618) */
2236 struct i40e_aqc_set_lb_mode {
2238 #define I40E_AQ_LB_PHY_LOCAL 0x01
2239 #define I40E_AQ_LB_PHY_REMOTE 0x02
2240 #define I40E_AQ_LB_MAC_LOCAL 0x04
2244 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
2246 /* Set PHY Debug command (0x0622) */
2247 struct i40e_aqc_set_phy_debug {
2249 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
2250 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
2251 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
2252 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2253 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
2254 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
2255 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
2256 /* Disable link manageability on a single port */
2257 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
2258 /* Disable link manageability on all ports needs both bits 4 and 5 */
2259 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
2263 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
2265 enum i40e_aq_phy_reg_type {
2266 I40E_AQC_PHY_REG_INTERNAL = 0x1,
2267 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
2268 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2271 /* Run PHY Activity (0x0626) */
2272 struct i40e_aqc_run_phy_activity {
2281 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
2283 /* Set PHY Register command (0x0628) */
2284 /* Get PHY Register command (0x0629) */
2285 struct i40e_aqc_phy_register_access {
2287 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0
2288 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
2289 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
2292 #define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 1
2299 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
2301 /* NVM Read command (indirect 0x0701)
2302 * NVM Erase commands (direct 0x0702)
2303 * NVM Update commands (indirect 0x0703)
2305 struct i40e_aqc_nvm_update {
2307 #define I40E_AQ_NVM_LAST_CMD 0x01
2308 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20
2309 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40
2310 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2311 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
2312 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03
2313 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
2314 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
2322 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2324 /* NVM Config Read (indirect 0x0704) */
2325 struct i40e_aqc_nvm_config_read {
2327 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2328 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2329 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2330 __le16 element_count;
2331 __le16 element_id; /* Feature/field ID */
2332 __le16 element_id_msw; /* MSWord of field ID */
2333 __le32 address_high;
2337 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2339 /* NVM Config Write (indirect 0x0705) */
2340 struct i40e_aqc_nvm_config_write {
2342 __le16 element_count;
2344 __le32 address_high;
2348 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2350 /* Used for 0x0704 as well as for 0x0705 commands */
2351 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2352 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2353 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2354 #define I40E_AQ_ANVM_FEATURE 0
2355 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
2356 struct i40e_aqc_nvm_config_data_feature {
2358 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2359 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2360 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2361 __le16 feature_options;
2362 __le16 feature_selection;
2365 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2367 struct i40e_aqc_nvm_config_data_immediate_field {
2370 __le16 field_options;
2374 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2376 /* OEM Post Update (indirect 0x0720)
2377 * no command data struct used
2379 struct i40e_aqc_nvm_oem_post_update {
2380 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2385 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2387 struct i40e_aqc_nvm_oem_post_update_buffer {
2394 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2396 /* Thermal Sensor (indirect 0x0721)
2397 * read or set thermal sensor configs and values
2398 * takes a sensor and command specific data buffer, not detailed here
2400 struct i40e_aqc_thermal_sensor {
2402 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2403 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2404 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2410 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2412 /* Send to PF command (indirect 0x0801) id is only used by PF
2413 * Send to VF command (indirect 0x0802) id is only used by PF
2414 * Send to Peer PF command (indirect 0x0803)
2416 struct i40e_aqc_pf_vf_message {
2423 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2425 /* Alternate structure */
2427 /* Direct write (direct 0x0900)
2428 * Direct read (direct 0x0902)
2430 struct i40e_aqc_alternate_write {
2437 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2439 /* Indirect write (indirect 0x0901)
2440 * Indirect read (indirect 0x0903)
2443 struct i40e_aqc_alternate_ind_write {
2450 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2452 /* Done alternate write (direct 0x0904)
2455 struct i40e_aqc_alternate_write_done {
2457 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2458 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2459 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2460 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2464 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2466 /* Set OEM mode (direct 0x0905) */
2467 struct i40e_aqc_alternate_set_mode {
2469 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2470 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2474 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2476 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2478 /* async events 0x10xx */
2480 /* Lan Queue Overflow Event (direct, 0x1001) */
2481 struct i40e_aqc_lan_overflow {
2482 __le32 prtdcb_rupto;
2487 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2489 /* Get LLDP MIB (indirect 0x0A00) */
2490 struct i40e_aqc_lldp_get_mib {
2493 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2494 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2495 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2496 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2497 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2498 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2499 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2500 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2501 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2502 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2503 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2511 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2513 /* Configure LLDP MIB Change Event (direct 0x0A01)
2514 * also used for the event (with type in the command field)
2516 struct i40e_aqc_lldp_update_mib {
2518 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2519 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2525 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2527 /* Add LLDP TLV (indirect 0x0A02)
2528 * Delete LLDP TLV (indirect 0x0A04)
2530 struct i40e_aqc_lldp_add_tlv {
2531 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2539 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2541 /* Update LLDP TLV (indirect 0x0A03) */
2542 struct i40e_aqc_lldp_update_tlv {
2543 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2552 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2554 /* Stop LLDP (direct 0x0A05) */
2555 struct i40e_aqc_lldp_stop {
2557 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2558 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2562 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2564 /* Start LLDP (direct 0x0A06) */
2566 struct i40e_aqc_lldp_start {
2568 #define I40E_AQ_LLDP_AGENT_START 0x1
2572 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2574 /* Set DCB (direct 0x0303) */
2575 struct i40e_aqc_set_dcb_parameters {
2577 #define I40E_AQ_DCB_SET_AGENT 0x1
2578 #define I40E_DCB_VALID 0x1
2583 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2585 /* Get CEE DCBX Oper Config (0x0A07)
2586 * uses the generic descriptor struct
2587 * returns below as indirect response
2590 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2591 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2592 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2593 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2594 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2595 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2597 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2598 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2599 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2600 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2601 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2602 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2603 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2604 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2605 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2606 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2607 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2608 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2610 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2611 * word boundary layout issues, which the Linux compilers silently deal
2612 * with by adding padding, making the actual struct larger than designed.
2613 * However, the FW compiler for the NIC is less lenient and complains
2614 * about the struct. Hence, the struct defined here has an extra byte in
2615 * fields reserved3 and reserved4 to directly acknowledge that padding,
2616 * and the new length is used in the length check macro.
2618 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2626 __le16 oper_app_prio;
2631 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2633 struct i40e_aqc_get_cee_dcb_cfg_resp {
2638 __le16 oper_app_prio;
2643 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2645 /* Set Local LLDP MIB (indirect 0x0A08)
2646 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2648 struct i40e_aqc_lldp_set_local_mib {
2649 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2650 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2651 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2652 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2653 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2654 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2655 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2656 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2661 __le32 address_high;
2665 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2667 struct i40e_aqc_lldp_set_local_mib_resp {
2668 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
2673 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
2675 /* Stop/Start LLDP Agent (direct 0x0A09)
2676 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2678 struct i40e_aqc_lldp_stop_start_specific_agent {
2679 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2680 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2681 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2686 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2688 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2689 struct i40e_aqc_add_udp_tunnel {
2693 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2694 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2695 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2696 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2700 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2702 struct i40e_aqc_add_udp_tunnel_completion {
2704 u8 filter_entry_index;
2706 #define I40E_AQC_SINGLE_PF 0x0
2707 #define I40E_AQC_MULTIPLE_PFS 0x1
2712 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2714 /* remove UDP Tunnel command (0x0B01) */
2715 struct i40e_aqc_remove_udp_tunnel {
2717 u8 index; /* 0 to 15 */
2721 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2723 struct i40e_aqc_del_udp_tunnel_completion {
2725 u8 index; /* 0 to 15 */
2727 u8 total_filters_used;
2731 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2733 struct i40e_aqc_get_set_rss_key {
2734 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2735 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2736 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2737 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2744 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2746 struct i40e_aqc_get_set_rss_key_data {
2747 u8 standard_rss_key[0x28];
2748 u8 extended_hash_key[0xc];
2751 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2753 struct i40e_aqc_get_set_rss_lut {
2754 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2755 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2756 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2757 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2759 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2760 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2761 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2763 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2764 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2771 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2773 /* tunnel key structure 0x0B10 */
2775 struct i40e_aqc_tunnel_key_structure {
2778 u8 key1_len; /* 0 to 15 */
2779 u8 key2_len; /* 0 to 15 */
2781 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2782 /* response flags */
2783 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2784 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2785 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2786 u8 network_key_index;
2787 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2788 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2789 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2790 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2794 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2796 /* OEM mode commands (direct 0xFE0x) */
2797 struct i40e_aqc_oem_param_change {
2799 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2800 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2801 #define I40E_AQ_OEM_PARAM_MAC 2
2802 __le32 param_value1;
2803 __le16 param_value2;
2807 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2809 struct i40e_aqc_oem_state_change {
2811 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2812 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2816 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2818 /* Initialize OCSD (0xFE02, direct) */
2819 struct i40e_aqc_opc_oem_ocsd_initialize {
2822 __le32 ocsd_memory_block_addr_high;
2823 __le32 ocsd_memory_block_addr_low;
2824 __le32 requested_update_interval;
2827 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2829 /* Initialize OCBB (0xFE03, direct) */
2830 struct i40e_aqc_opc_oem_ocbb_initialize {
2833 __le32 ocbb_memory_block_addr_high;
2834 __le32 ocbb_memory_block_addr_low;
2838 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2840 /* debug commands */
2842 /* get device id (0xFF00) uses the generic structure */
2844 /* set test more (0xFF01, internal) */
2846 struct i40e_acq_set_test_mode {
2848 #define I40E_AQ_TEST_PARTIAL 0
2849 #define I40E_AQ_TEST_FULL 1
2850 #define I40E_AQ_TEST_NVM 2
2853 #define I40E_AQ_TEST_OPEN 0
2854 #define I40E_AQ_TEST_CLOSE 1
2855 #define I40E_AQ_TEST_INC 2
2857 __le32 address_high;
2861 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2863 /* Debug Read Register command (0xFF03)
2864 * Debug Write Register command (0xFF04)
2866 struct i40e_aqc_debug_reg_read_write {
2873 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2875 /* Scatter/gather Reg Read (indirect 0xFF05)
2876 * Scatter/gather Reg Write (indirect 0xFF06)
2879 /* i40e_aq_desc is used for the command */
2880 struct i40e_aqc_debug_reg_sg_element_data {
2885 /* Debug Modify register (direct 0xFF07) */
2886 struct i40e_aqc_debug_modify_reg {
2893 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2895 /* dump internal data (0xFF08, indirect) */
2897 #define I40E_AQ_CLUSTER_ID_AUX 0
2898 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2899 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2900 #define I40E_AQ_CLUSTER_ID_HMC 3
2901 #define I40E_AQ_CLUSTER_ID_MAC0 4
2902 #define I40E_AQ_CLUSTER_ID_MAC1 5
2903 #define I40E_AQ_CLUSTER_ID_MAC2 6
2904 #define I40E_AQ_CLUSTER_ID_MAC3 7
2905 #define I40E_AQ_CLUSTER_ID_DCB 8
2906 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2907 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2908 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2910 struct i40e_aqc_debug_dump_internals {
2915 __le32 address_high;
2919 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2921 struct i40e_aqc_debug_modify_internals {
2923 u8 cluster_specific_params[7];
2924 __le32 address_high;
2928 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2930 #endif /* _I40E_ADMINQ_CMD_H_ */